1/*
2 * initcp0.S
3 *
4 *  Created on: Jan 12, 2011
5 *  Author: MIPS TECHNOLOGIES, INC
6 *  Common CP0 register initializations
7*/
8/*
9Unpublished work (c) MIPS Technologies, Inc.  All rights reserved.  Unpublished rights reserved
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11
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46*/
47#include <boot.h>
48#include <regdef.h>
49#include <m32c0.h>
50
51	.set	noreorder           // Don't allow the assembler to reorder instructions.
52	.set	noat                // Don't allow the assembler to use r1(at) for synthetic instr.
53/**************************************************************************************
54**************************************************************************************/
55LEAF(init_cp0)
56	// Initialize Status
57	// RAMHACK: Use RAM (Status.BEV == 0) exception vectors.
58	// li	    v1, 0x00400404		// (M_StatusIM | M_StatusERL | M_StatusBEV)
59    	li	    v1, 0x00000404      // (M_StatusIM | M_StatusERL)
60	mtc0	v1, C0_STATUS		// write C0_Status
61
62	// Initialize Watch registers if implemented.
63	mfc0	v0, C0_CONFIG1		// read C0_Config1
64	ext	    v1, v0, 3, 1		// extract bit 3 WR (Watch registers implemented)
65	beq 	v1, zero, done_wr
66	li    	v1, 0x7				// (M_WatchHiI | M_WatchHiR | M_WatchHiW)
67
68	// Clear Watch Status bits and disable watch exceptions
69	mtc0	v1, C0_WATCHHI		// write C0_WatchHi0
70	mfc0	v0, C0_WATCHHI		// read C0_WatchHi0
71	bgez 	v0, done_wr			// Check for bit 31 (sign bit) for more Watch registers
72	mtc0	zero, C0_WATCHLO	// write C0_WatchLo0
73
74	mtc0	v1, C0_WATCHHI, 1	// write C0_WatchHi1
75	mfc0	v0, C0_WATCHHI, 1	// read C0_WatchHi1
76	bgez 	v0, done_wr			// Check for bit 31 (sign bit) for more Watch registers
77	mtc0	zero, C0_WATCHLO, 1	// write C0_WatchLo1
78
79	mtc0	v1, C0_WATCHHI, 2	// write C0_WatchHi2
80	mfc0	v0, C0_WATCHHI, 2	// read C0_WatchHi2
81	bgez 	v0, done_wr			// Check for bit 31 (sign bit) for more Watch registers
82	mtc0	zero, C0_WATCHLO, 2	// write C0_WatchLo2
83
84	mtc0	v1, C0_WATCHHI, 3	// write C0_WatchHi3
85	mfc0	v0, C0_WATCHHI, 3	// read C0_WatchHi3
86	bgez 	v0, done_wr			// Check for bit 31 (sign bit) for more Watch registers
87	mtc0	zero, C0_WATCHLO, 3	// write C0_WatchLo3
88
89	mtc0	v1, C0_WATCHHI, 4	// write C0_WatchHi4
90	mfc0	v0, C0_WATCHHI, 4	// read C0_WatchHi4
91	bgez 	v0, done_wr			// Check for bit 31 (sign bit) for more Watch registers
92	mtc0	zero, C0_WATCHLO, 4	// write C0_WatchLo4
93
94	mtc0	v1, C0_WATCHHI, 5	// write C0_WatchHi5
95	mfc0	v0, C0_WATCHHI, 5	// read C0_WatchHi5
96	bgez 	v0, done_wr			// Check for bit 31 (sign bit) for more Watch registers
97	mtc0	zero, C0_WATCHLO, 5	// write C0_WatchLo5
98
99	mtc0	v1, C0_WATCHHI, 6	// write C0_WatchHi6
100	mfc0	v0, C0_WATCHHI, 6	// read C0_WatchHi6
101	bgez 	v0, done_wr			// Check for bit 31 (sign bit) for more Watch registers
102	mtc0	zero, C0_WATCHLO, 6	// write C0_WatchLo6
103
104	mtc0	v1, C0_WATCHHI, 7	// write C0_WatchHi7
105	mtc0	zero, C0_WATCHLO, 7	// write C0_WatchLo7
106
107done_wr:
108
109	// Clear WP bit to avoid watch exception upon user code entry, IV, and software interrupts.
110	// RAMHACK: Use vectored interrupts (Cause.IV) to isolate them from other exceptions.
111	lui     v1, 0x0080              // Cause.IV = 1
112	mtc0	v1, C0_CAUSE		// write C0_Cause: Init AFTER init of CP0 WatchHi/Lo registers.
113
114	// Clear timer interrupt. (Count was cleared at the reset vector to allow timing boot.)
115	mtc0	zero, C0_COMPARE	// write C0_Compare
116
117    jr      ra
118	nop
119END(init_cp0)
120