1/* 2 * init_CoreFPGA5mem.S 3 * 4 * Created on: Jun 4, 2012 5 * Author: chrisr 6 */ 7/* 8Unpublished work (c) MIPS Technologies, Inc. All rights reserved. Unpublished rights reserved 9under the copyright laws of the United States of America and other countries. 10 11This code is confidential and proprietary to MIPS Technologies, Inc. ("MIPS Technologies") and 12may be disclosed only as permitted in writing by MIPS Technologies or an authorized third party. 13Any copying, reproducing, modifying, use or disclosure of this code (in whole or in part) that is 14not expressly permitted in writing by MIPS Technologies or an authorized third party is strictly 15prohibited. At a minimum, this code is protected under trade secret, unfair competition, and 16copyright laws. Violations thereof may result in criminal penalties and fines. 17 18MIPS Technologies reserves the right to change this code to improve function, design or 19otherwise. MIPS Technologies does not assume any liability arising out of the application or use 20of this code, or of any error or omission in such code. Any warranties, whether express, statutory, 21implied or otherwise, including but not limited to the implied warranties of merchantability or 22fitness for a particular purpose, are excluded. Except as expressly provided in any written license 23agreement from MIPS Technologies or an authorized third party, the furnishing of this code does 24not give recipient any license to any intellectual property rights, including any patent rights, that 25cover this code. 26 27This code shall not be exported, reexported, transferred, or released, directly or indirectly, in 28violation of the law of any country or international law, regulation, treaty, Executive Order, 29statute, amendments or supplements thereto. Should a conflict arise regarding the export, 30reexport, transfer, or release of this code, the laws of the United States of America shall be 31the governing law. 32 33This code may only be disclosed to the United States government ("Government"), or to 34Government users, with prior written consent from MIPS Technologies or an authorized third 35party. This code constitutes one or more of the following: commercial computer software, 36commercial computer software documentation or other commercial items. If the user of this 37code, or any related documentation of any kind, including related technical data or manuals, is an 38agency, department, or other entity of the Government, the use, duplication, reproduction, release, 39modification, disclosure, or transfer of this code, or any related documentation of any kind, is 40restricted in accordance with Federal Acquisition Regulation 12.212 for civilian agencies and 41Defense Federal Acquisition Regulation Supplement 227.7202 for military agencies. The use of 42this code by the Government is further restricted in accordance with the terms of the license 43agreement(s) and/or applicable contract terms and conditions covering this code from MIPS 44Technologies or an authorized third party. 45*/ 46#include <regdef.h> 47#include <boot.h> 48 49 .set noreorder # Don't allow the assembler to reorder instructions. 50 51/************************************************************************************** 52Wait for the controller to startup. Then its good to go! 53**************************************************************************************/ 54LEAF(init_CoreFPGA6_mem) 55 56 /* Wait for MIG to init */ 57 la a0, 0xbbc00004 581: 59/* RAMHACK: The read of Xilinx DRAM controller reg while executig from DRAM causing bad fetch? 60 lw a2, 0(a0) 61 andi a2, 0x1 62 beqz a2, 1b 63 nop 64*/ 65 jr ra 66 nop 67 68END(init_CoreFPGA6_mem) 69 70
