1/*
2 * copy_c2_ram.S
3 *
4 *  Created on: Jan 12, 2011
5 *  Author: MIPS TECHNOLOGIES, INC
6 *  Copy code and data to ram then clear BSS
7*/
8/*
9Unpublished work (c) MIPS Technologies, Inc.  All rights reserved.  Unpublished rights reserved
10under the copyright laws of the United States of America and other countries.
11
12This code is confidential and proprietary to MIPS Technologies, Inc. ("MIPS Technologies") and
13may be disclosed only as permitted in writing by MIPS Technologies or an authorized third party.
14Any copying, reproducing, modifying, use or disclosure of this code (in whole or in part) that is
15not expressly permitted in writing by MIPS Technologies or an authorized third party is strictly
16prohibited. At a minimum, this code is protected under trade secret, unfair competition, and
17copyright laws. Violations thereof may result in criminal penalties and fines.
18
19MIPS Technologies reserves the right to change this code to improve function, design or
20otherwise. MIPS Technologies does not assume any liability arising out of the application or use
21of this code, or of any error or omission in such code.  Any warranties, whether express, statutory,
22implied or otherwise, including but not limited to the implied warranties of merchantability or
23fitness for a particular purpose, are excluded.  Except as expressly provided in any written license
24agreement from MIPS Technologies or an authorized third party, the furnishing of this code does
25not give recipient any license to any intellectual property rights, including any patent rights, that
26cover this code.
27
28This code shall not be exported, reexported, transferred, or released, directly or indirectly, in
29violation of the law of any country or international law, regulation, treaty, Executive Order,
30statute, amendments or supplements thereto.  Should a conflict arise regarding the export,
31reexport, transfer, or release of this code, the laws of the United States of America shall be
32the governing law.
33
34This code may only be disclosed to the United States government ("Government"), or to
35Government users, with prior written consent from MIPS Technologies or an authorized third
36party.  This code constitutes one or more of the following: commercial computer software,
37commercial computer software documentation or other commercial items.  If the user of this
38code, or any related documentation of any kind, including related technical data or manuals, is an
39agency, department, or other entity of the Government, the use, duplication, reproduction, release,
40modification, disclosure, or transfer of this code, or any related documentation of any kind, is
41restricted in accordance with Federal Acquisition Regulation 12.212 for civilian agencies and
42Defense Federal Acquisition Regulation Supplement 227.7202 for military agencies.  The use of
43this code by the Government is further restricted in accordance with the terms of the license
44agreement(s) and/or applicable contract terms and conditions covering this code from MIPS
45Technologies or an authorized third party.
46*/
47#include <regdef.h>
48#include <boot.h>
49
50#define s1_all_ones     s1   /* at Will hold 0xffffffff to simplify bit insertion of 1's. */
51#define a0_temp_data    a0   /* a0 data to be moved */
52#define a1_temp_addr    a1   /* from address */
53#define a2_temp_dest    a2   /* to address */
54#define a3_temp_mark    a3   /* ending address */
55
56
57	.set	noreorder           # Don't allow the assembler to reorder instructions.
58	.set	noat                # Don't allow the assembler to use r1(at) for synthetic instr.
59
60/**************************************************************************************
61**************************************************************************************/
62LEAF(copy_c2_ram)
63
64	li      s1_all_ones, 0xffffffff
65
66/* RAMHACK: Link addr == load addr. No copy of code from ROM to RAM required.
67    // Copy code and read-only/initialized data from FLASH to (uncached) RAM.
68    la      a1_temp_addr, _zap1
69    ins     a1_temp_addr, s1_all_ones, 29, 1
70    la      a2_temp_dest, _ftext_ram
71    ins     a2_temp_dest, s1_all_ones, 29, 1
72    la      a3_temp_mark, _edata_ram
73    ins     a3_temp_mark, s1_all_ones, 29, 1
74    beq     a2_temp_dest, a3_temp_mark, zero_bss
75    nop
76next_ram_word:
77    lw      a0_temp_data, 0(a1_temp_addr)
78    sw      a0_temp_data, 0(a2_temp_dest)
79    addiu   a2_temp_dest, 4
80    bne     a3_temp_mark, a2_temp_dest, next_ram_word
81    addiu   a1_temp_addr, 4
82*/
83
84// RAMHACK: Zero sbss in addition to bss.
85zero_sbss:
86    la      a1_temp_addr, _start_sbss
87    ins     a1_temp_addr, s1_all_ones, 29, 1
88    la      a3_temp_mark, _end_sbss
89    ins     a3_temp_mark, s1_all_ones, 29, 1
90    beq     a1_temp_addr, a3_temp_mark, zero_bss
91    nop
92next_sbss_word:
93    sw      zero, 0(a1_temp_addr)
94    addiu   a1_temp_addr, 4
95    bne     a1_temp_addr, a3_temp_mark, next_sbss_word
96    nop
97
98zero_bss:
99    la      a1_temp_addr, _start_bss
100    ins     a1_temp_addr, s1_all_ones, 29, 1
101    la      a3_temp_mark, _end_bss
102    ins     a3_temp_mark, s1_all_ones, 29, 1
103    beq     a1_temp_addr, a3_temp_mark, copy_c2_ram_done
104    nop
105next_bss_word:
106    sw      zero, 0(a1_temp_addr)
107    addiu   a1_temp_addr, 4
108    bne     a1_temp_addr, a3_temp_mark, next_bss_word
109    nop
110
111copy_c2_ram_done:
112    jr      ra
113    nop
114END(copy_c2_ram)
115
116