1 /**************************************************************************/
2 /* */
3 /* Copyright (c) Microsoft Corporation. All rights reserved. */
4 /* */
5 /* This software is licensed under the Microsoft Software License */
6 /* Terms for Microsoft Azure RTOS. Full text of the license can be */
7 /* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
8 /* and in the root directory of this software. */
9 /* */
10 /**************************************************************************/
11
12
13 /**************************************************************************/
14 /**************************************************************************/
15 /** */
16 /** USBX Component */
17 /** */
18 /** EHCI Controller Driver */
19 /** */
20 /**************************************************************************/
21 /**************************************************************************/
22
23
24 /* Include necessary system files. */
25
26 #define UX_SOURCE_CODE
27
28 #include "ux_api.h"
29 #include "ux_hcd_ehci.h"
30 #include "ux_host_stack.h"
31
32
33 /**************************************************************************/
34 /* */
35 /* FUNCTION RELEASE */
36 /* */
37 /* _ux_hcd_ehci_request_interrupt_transfer PORTABLE C */
38 /* 6.1 */
39 /* AUTHOR */
40 /* */
41 /* Chaoqiong Xiao, Microsoft Corporation */
42 /* */
43 /* DESCRIPTION */
44 /* */
45 /* This function performs an interrupt transfer request. An interrupt */
46 /* transfer can only be as large as the MaxpacketField in the */
47 /* endpoint descriptor. This was verified at the upper layer and does */
48 /* not need to be reverified here. */
49 /* */
50 /* INPUT */
51 /* */
52 /* hcd_ehci Pointer to EHCI controller */
53 /* transfer_request Pointer to transfer request */
54 /* */
55 /* OUTPUT */
56 /* */
57 /* Completion Status */
58 /* */
59 /* CALLS */
60 /* */
61 /* _ux_hcd_ehci_request_transfer_add Add transfer to ED */
62 /* */
63 /* CALLED BY */
64 /* */
65 /* EHCI Controller Driver */
66 /* */
67 /* RELEASE HISTORY */
68 /* */
69 /* DATE NAME DESCRIPTION */
70 /* */
71 /* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */
72 /* 09-30-2020 Chaoqiong Xiao Modified comment(s), */
73 /* resulting in version 6.1 */
74 /* */
75 /**************************************************************************/
_ux_hcd_ehci_request_interrupt_transfer(UX_HCD_EHCI * hcd_ehci,UX_TRANSFER * transfer_request)76 UINT _ux_hcd_ehci_request_interrupt_transfer(UX_HCD_EHCI *hcd_ehci, UX_TRANSFER *transfer_request)
77 {
78
79 UX_ENDPOINT *endpoint;
80 UX_EHCI_ED *ed;
81 ULONG pid;
82 ULONG td_component;
83 UINT status;
84
85
86 /* Get the pointer to the endpoint. */
87 endpoint = (UX_ENDPOINT *) transfer_request -> ux_transfer_request_endpoint;
88
89 /* Now get the physical ED attached to this endpoint. */
90 ed = endpoint -> ux_endpoint_ed;
91
92 /* The overlay parameters should be reset now. */
93 ed -> ux_ehci_ed_current_td = UX_NULL;
94 ed -> ux_ehci_ed_queue_element = (UX_EHCI_TD *) UX_EHCI_TD_T;
95 ed -> ux_ehci_ed_alternate_td = (UX_EHCI_TD *) UX_EHCI_QH_T;
96 ed -> ux_ehci_ed_state &= UX_EHCI_QH_TOGGLE;
97 ed -> ux_ehci_ed_bp0 = UX_NULL;
98 ed -> ux_ehci_ed_bp1 = UX_NULL;
99 ed -> ux_ehci_ed_bp2 = UX_NULL;
100 ed -> ux_ehci_ed_bp3 = UX_NULL;
101 ed -> ux_ehci_ed_bp4 = UX_NULL;
102
103 /* Get the correct PID for this transfer. */
104 if ((transfer_request -> ux_transfer_request_type & UX_REQUEST_DIRECTION) == UX_REQUEST_IN)
105 pid = UX_EHCI_PID_IN;
106 else
107 pid = UX_EHCI_PID_OUT;
108
109 /* Add this transfer request to the ED. */
110 status = _ux_hcd_ehci_request_transfer_add(hcd_ehci, ed, 0, pid, 0,
111 transfer_request -> ux_transfer_request_data_pointer,
112 transfer_request -> ux_transfer_request_requested_length,
113 transfer_request);
114
115 /* Ensure we got the TD allocated properly. */
116 if (status == UX_SUCCESS)
117 {
118
119 /* Set the IOC bit in the last TD. */
120 ed -> ux_ehci_ed_last_td -> ux_ehci_td_control |= UX_EHCI_TD_IOC;
121
122 /* Ensure the IOC bit is set before activating the TD. This is necessary
123 for some processors that perform writes out of order as an optimization. */
124 UX_DATA_MEMORY_BARRIER
125
126 /* Activate the first TD linked to the ED. */
127 td_component = (ULONG) ed -> ux_ehci_ed_queue_element;
128 td_component &= ~UX_EHCI_TD_T;
129 ed -> ux_ehci_ed_queue_element = (UX_EHCI_TD *) td_component;
130
131 }
132
133 /* Return completion status. */
134 return(status);
135 }
136
137
