1;;-------------------------------------------------------------------------
2;; Declarations of SFR registers and bits, interrupt/exception vectors,
3;; interrupt control registers, memory map information, and additional
4;; configurations for a generic (non-existent) RISC-V device.
5;;
6;; This declaration file can be used by all flavors of the IAR C-SPY
7;; Debugger for RISC-V (simulator and emulators).
8;;
9;; Copyright 2019 IAR Systems AB.
10;;-------------------------------------------------------------------------
11
12
13;;-------------------------------------------------------------------------
14;; SFR declaration file
15;;
16;; Syntax: File = Filename
17;;
18;;   Filename   Name of SFR declaration file
19;;-------------------------------------------------------------------------
20
21;; CSR
22#include weak "csr.sfr"
23
24[SfrInclude]
25File = ioriscv.sfr
26
27
28;;-------------------------------------------------------------------------
29;; Memory information
30;;
31;; Syntax: Memory[NN] = Name Zone StartAdr EndAdr AccType
32;;
33;;   NN         Optional counter
34;;   Name       Name of address space (legal characters: A-Z, a-z, 0-9, _)
35;;   Zone       Must be Memory
36;;   StartAdr   Start address of memory address space
37;;   EndAdr     End address of memory address space
38;;   AccType    Type of access, read-only (R) or read-write (RW)
39;;              (W - noncached) for SFR areas and areas that are shared,
40;;              implemented as different core-specific physical memories
41;;              in a multicore device.
42;;
43;; Used to define named memory address spaces within the 'Memory' zone.
44;;
45;;-------------------------------------------------------------------------
46;;       Name            Zone      StartAdr      EndAdr        AccType
47;;-------------------------------------------------------------------------
48
49[Memory]
50Memory = Peripherals     Memory    0x02000000    0x1FFFFFFF    W
51Memory = Flash           Memory    0x20000000    0x3FFFFFFF    R
52Memory = RAM             Memory    0x80000000    0x8003FFFF    RW
53
54TrustedRanges = true
55
56;;-------------------------------------------------------------------------
57;; Device file
58;;
59;; Syntax: File = Filename
60;;
61;;   Filename   Name of device file
62;;-------------------------------------------------------------------------
63
64[DeviceFile]
65File = <Undefined>
66
67
68;;-------------------------------------------------------------------------
69;; Device information
70;;
71;; Syntax: Item = Value
72;;
73;;   Item    Name of item
74;;   Value   Value of item
75;;-------------------------------------------------------------------------
76
77[DeviceInfo]
78DataFlash = YES
79FlashSize = 0032
80FlashType = CS Fixed2
81StartAddress = 0x02000000
82EndAddress = 0x80003FFF
83BusSize = 00
84IDCodeBitLength = 128
85CodeFlashIDCode = NO
86DataFlashIDCode = NO
87CoreNumbers = 1
88
89;;-------------------------------------------------------------------------
90;; Interrupt declarations
91;;
92;; Syntax: InterruptNN = Id Vector Type
93;;
94;;   NN          Counter
95;;   Id          Unique Interrupt 'name'
96;;   Vector      Exception Code
97;;   Controller  SiFive1
98;;   Core        Core Number
99;;   Enable      Enable bit
100;;   Pending     Pending bit
101;;   Priority    Priority level
102;;   UserLvl     (M)achine/(S)upervisor/(U)ser
103;;   Trap        '0' exception
104;;               '1' interrupt
105;;   Maskable    '0' Non Maskable
106;;               '1' Maskable
107;;-------------------------------------------------------------------------
108[InterruptList]
109Interrupt7 = TIMER  0x07  SiFive1  0x00  mie.mtie  mip.mtip  0x00  M  0x01  0x00
110
111;;-------------------------------------------------------------------------
112;; End of file
113;;-------------------------------------------------------------------------
114