1 /**************************************************************************/ 2 /* */ 3 /* Copyright (c) Microsoft Corporation. All rights reserved. */ 4 /* */ 5 /* This software is licensed under the Microsoft Software License */ 6 /* Terms for Microsoft Azure RTOS. Full text of the license can be */ 7 /* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ 8 /* and in the root directory of this software. */ 9 /* */ 10 /**************************************************************************/ 11 12 13 /**************************************************************************/ 14 /**************************************************************************/ 15 /** */ 16 /** USBX Component */ 17 /** */ 18 /** EHCI Controller */ 19 /** */ 20 /**************************************************************************/ 21 /**************************************************************************/ 22 23 24 /**************************************************************************/ 25 /* */ 26 /* COMPONENT DEFINITION RELEASE */ 27 /* */ 28 /* ux_hcd_ehci.h PORTABLE C */ 29 /* 6.1.8 */ 30 /* AUTHOR */ 31 /* */ 32 /* Chaoqiong Xiao, Microsoft Corporation */ 33 /* */ 34 /* DESCRIPTION */ 35 /* */ 36 /* This file contains all the header and extern functions used by the */ 37 /* USBX host EHCI Controller. */ 38 /* */ 39 /* RELEASE HISTORY */ 40 /* */ 41 /* DATE NAME DESCRIPTION */ 42 /* */ 43 /* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ 44 /* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ 45 /* used UX prefix to refer to */ 46 /* TX symbols instead of using */ 47 /* them directly, */ 48 /* resulting in version 6.1 */ 49 /* 11-09-2020 Chaoqiong Xiao Modified comment(s), */ 50 /* used unsigned defines, */ 51 /* named unions and structs, */ 52 /* resulting in version 6.1.2 */ 53 /* 08-02-2021 Chaoqiong Xiao Modified comment(s), */ 54 /* fixed spelling error, */ 55 /* added extern "C" keyword */ 56 /* for compatibility with C++, */ 57 /* resulting in version 6.1.8 */ 58 /* */ 59 /**************************************************************************/ 60 61 #ifndef UX_HCD_EHCI_H 62 #define UX_HCD_EHCI_H 63 64 /* Determine if a C++ compiler is being used. If so, ensure that standard 65 C is used to process the API information. */ 66 67 #ifdef __cplusplus 68 69 /* Yes, C++ compiler is present. Use standard C. */ 70 extern "C" { 71 72 #endif 73 74 75 /* Possible defined EHCI HCD extensions. */ 76 77 /* Extension for peripheral host mode select (function like). */ 78 /* #define UX_HCD_EHCI_EXT_USB_HOST_MODE_ENABLE(hcd_ehci) */ 79 80 /* Extension for embedded TT (UX_TRUE/UX_FALSE). */ 81 /* #define UX_HCD_EHCI_EXT_EMBEDDED_TT_SUPPORT */ 82 83 /* Extension for phy high speed mode select (function like). */ 84 /* #define UX_HCD_EHCI_EXT_USBPHY_HIGHSPEED_MODE_SET(hcd_ehci, on_off) */ 85 86 /* Define EHCI generic definitions. */ 87 88 #define UX_EHCI_CONTROLLER 2 89 #define UX_EHCI_MAX_PAYLOAD 16384 90 #define UX_EHCI_FRAME_DELAY 4 91 #define UX_EHCI_PAGE_SIZE 4096 92 #define UX_EHCI_PAGE_ALIGN 0xfffff000 93 94 95 /* Define EHCI host controller capability registers. */ 96 97 #define EHCI_HCCR_CAP_LENGTH 0x00 98 #define EHCI_HCCR_HCS_PARAMS 0x01 99 #define EHCI_HCCR_HCC_PARAMS 0x02 100 #define EHCI_HCCR_HCSP_PORT_ROUTE 0x03 101 102 103 /* Define EHCI host controller registers. */ 104 105 #define EHCI_HCOR_USB_COMMAND (hcd_ehci -> ux_hcd_ehci_hcor + 0x00) 106 #define EHCI_HCOR_USB_STATUS (hcd_ehci -> ux_hcd_ehci_hcor + 0x01) 107 #define EHCI_HCOR_USB_INTERRUPT (hcd_ehci -> ux_hcd_ehci_hcor + 0x02) 108 #define EHCI_HCOR_FRAME_INDEX (hcd_ehci -> ux_hcd_ehci_hcor + 0x03) 109 #define EHCI_HCOR_FRAME_LIST_BASE_ADDRESS (hcd_ehci -> ux_hcd_ehci_hcor + 0x05) 110 #define EHCI_HCOR_ASYNCH_LIST_ADDRESS (hcd_ehci -> ux_hcd_ehci_hcor + 0x06) 111 #define EHCI_HCOR_CONFIG_FLAG (hcd_ehci -> ux_hcd_ehci_hcor + 0x10) 112 #define EHCI_HCOR_PORT_SC (hcd_ehci -> ux_hcd_ehci_hcor + 0x11) 113 114 115 /* Define EHCI IO control register values. */ 116 117 #define EHCI_HC_IO_RS 0x00000001u 118 #define EHCI_HC_IO_HCRESET 0x00000002u 119 #define EHCI_HC_IO_PSE 0x00000010u 120 #define EHCI_HC_IO_ASE 0x00000020u 121 #define EHCI_HC_IO_IAAD 0x00000040u 122 #define EHCI_HC_IO_ITC 0x00010000u 123 #define EHCI_HC_IO_FRAME_SIZE_1024 0x00000000u 124 #define EHCI_HC_IO_FRAME_SIZE_512 0x00000004u 125 #define EHCI_HC_IO_FRAME_SIZE_256 0x00000008u 126 #define EHCI_HC_IO_FRAME_SIZE_128 0x0000000Cu 127 #define EHCI_HC_IO_FRAME_SIZE_64 0x00008000u 128 #define EHCI_HC_IO_FRAME_SIZE_32 0x00008004u 129 130 /* The number if entries in the periodic tree can be changed to save space IF and only IF the PFLF flag in the HCCPARAMS register 131 allows it. Setting values less than 1024 in controllers without the ability to change the Frame List Size leads to a EHCI crash. */ 132 133 #ifndef UX_EHCI_FRAME_LIST_ENTRIES 134 #define UX_EHCI_FRAME_LIST_ENTRIES 1024 135 #endif 136 #define UX_EHCI_FRAME_LIST_MASK EHCI_HC_IO_FRAME_SIZE_1024 137 138 /* Define EHCI HCOR status register. */ 139 140 #define EHCI_HC_STS_USB_INT 0x00000001u 141 #define EHCI_HC_STS_USB_ERR_INT 0x00000002u 142 #define EHCI_HC_STS_PCD 0x00000004u 143 #define EHCI_HC_STS_FLR 0x00000008u 144 #define EHCI_HC_STS_HSE 0x00000010u 145 #define EHCI_HC_STS_IAA 0x00000020u 146 #define EHCI_HC_STS_HC_HALTED 0x00001000u 147 #define EHCI_HC_STS_RECLAMATION 0x00002000u 148 #define EHCI_HC_STS_PSS 0x00004000u 149 #define EHCI_HC_STS_ASS 0x00008000u 150 151 #define EHCI_HC_INTERRUPT_ENABLE_NORMAL (EHCI_HC_STS_USB_INT|EHCI_HC_STS_USB_ERR_INT|EHCI_HC_STS_PCD|EHCI_HC_STS_HSE|EHCI_HC_STS_IAA) 152 153 154 /* Define EHCI HCOR root HUB command/status. */ 155 156 #define EHCI_HC_RH_PPC 0x00000010u 157 #define EHCI_HC_RH_PSM 0x00000100u 158 #define EHCI_HC_RH_NPS 0x00000200u 159 #define EHCI_HC_RH_DT 0x00000400u 160 #define EHCI_HC_RH_OCPM 0x00000800u 161 #define EHCI_HC_RH_NOCP 0x00001000u 162 163 #define EHCI_HC_PS_CCS 0x00000001u 164 #define EHCI_HC_PS_CSC 0x00000002u 165 #define EHCI_HC_PS_PE 0x00000004u 166 #define EHCI_HC_PS_PEC 0x00000008u 167 #define EHCI_HC_PS_OCA 0x00000010u 168 #define EHCI_HC_PS_OCC 0x00000020u 169 #define EHCI_HC_PS_FPR 0x00000040u 170 #define EHCI_HC_PS_SUSPEND 0x00000080u 171 #define EHCI_HC_PS_PR 0x00000100u 172 #define EHCI_HC_PS_PP 0x00001000u 173 #define EHCI_HC_PS_SPEED_MASK 0x00000c00u 174 #define EHCI_HC_PS_SPEED_LOW 0x00000400u 175 #define EHCI_HC_PS_PO 0x00002000u 176 #define EHCI_HC_PS_EMBEDDED_TT_SPEED_MASK 0x0c000000u 177 #define EHCI_HC_PS_EMBEDDED_TT_SPEED_FULL 0x00000000u 178 #define EHCI_HC_PS_EMBEDDED_TT_SPEED_LOW 0x04000000u 179 #define EHCI_HC_PS_EMBEDDED_TT_SPEED_HIGH 0x08000000u 180 181 #define EHCI_HC_RH_POWER_STABLE_DELAY 25 182 #define EHCI_HC_RH_RESET_DELAY 50 183 #define EHCI_HC_RH_RESET_SETTLE_DELAY 5 184 185 186 /* Define EHCI interrupt status register definitions. */ 187 188 #define EHCI_HC_INT_IE 0x00000001u 189 #define EHCI_HC_INT_EIE 0x00000002u 190 #define EHCI_HC_INT_PCIE 0x00000004u 191 #define EHCI_HC_INT_FLRE 0x00000008u 192 #define EHCI_HC_INT_HSER 0x00000010u 193 #define EHCI_HC_INT_IAAE 0x00000020u 194 195 196 /* Define EHCI frame interval definition. */ 197 198 #define EHCI_HC_FM_INTERVAL_CLEAR 0x8000ffff 199 #define EHCI_HC_FM_INTERVAL_SET 0x27780000 200 201 202 /* Define EHCI static definition. */ 203 204 #define UX_EHCI_AVAILABLE_BANDWIDTH 6000 205 #define UX_EHCI_STOP 0 206 #define UX_EHCI_START 1 207 #define UX_EHCI_ROUTE_TO_LOCAL_HC 1 208 #define UX_EHCI_INIT_DELAY 1000 209 #define UX_EHCI_RESET_RETRY 1000 210 #define UX_EHCI_RESET_DELAY 100 211 #define UX_EHCI_PORT_RESET_RETRY 10 212 #define UX_EHCI_PORT_RESET_DELAY 50 213 214 215 /* Define EHCI initialization values. */ 216 217 #define UX_EHCI_COMMAND_STATUS_RESET 0 218 #define UX_EHCI_INIT_RESET_DELAY 10 219 220 221 /* Define EHCI completion code errors. */ 222 223 #define UX_EHCI_NO_ERROR 0x00 224 #define UX_EHCI_ERROR_CRC 0x01 225 #define UX_EHCI_ERROR_BIT_STUFFING 0x02 226 #define UX_EHCI_ERROR_DATA_TOGGLE 0x03 227 #define UX_EHCI_ERROR_STALL 0x04 228 #define UX_EHCI_ERROR_DEVICE_NOT_RESPONDING 0x05 229 #define UX_EHCI_ERROR_PID_FAILURE 0x06 230 #define UX_EHCI_ERROR_DATA_OVERRUN 0x08 231 #define UX_EHCI_ERROR_DATA_UNDERRUN 0x09 232 #define UX_EHCI_ERROR_BUFFER_OVERRUN 0x0c 233 #define UX_EHCI_ERROR_BUFFER_UNDERRUN 0x0d 234 #define UX_EHCI_ERROR_NOT_ACCESSED 0x0f 235 #define UX_EHCI_ERROR_NAK 0x10 236 #define UX_EHCI_ERROR_BABBLE 0x11 237 238 /* EHCI general descriptor type (Link Pointer). */ 239 240 #define UX_EHCI_LP_MASK (0xFFFFFFE0u) /* 32-byte align. */ 241 242 #define UX_EHCI_TYP_MASK (0x3u<<1) 243 #define UX_EHCI_TYP_ITD (0x0u<<1) 244 #define UX_EHCI_TYP_QH (0x1u<<1) 245 #define UX_EHCI_TYP_SITD (0x2u<<1) 246 #define UX_EHCI_TYP_FSTN (0x3u<<1) 247 248 #define UX_EHCI_T (0x1u<<0) 249 250 /* EHCI general descriptor type (Capabilities). */ 251 252 #define UX_EHCI_ENDPT_MASK (0xFu<<8) 253 #define UX_EHCI_ENDPT_SHIFT (8) 254 255 #define UX_EHCI_DEVICE_ADDRESS_MASK (0x3Fu<<0) 256 257 #define UX_EHCI_CMASK_MASK (0xFFu<<8) 258 #define UX_EHCI_CMASK_0 (0x01u<<8) 259 #define UX_EHCI_CMASK_1 (0x02u<<8) 260 #define UX_EHCI_CMASK_2 (0x04u<<8) 261 #define UX_EHCI_CMASK_3 (0x08u<<8) 262 #define UX_EHCI_CMASK_4 (0x10u<<8) 263 #define UX_EHCI_CMASK_5 (0x20u<<8) 264 #define UX_EHCI_CMASK_6 (0x40u<<8) 265 #define UX_EHCI_CMASK_7 (0x80u<<8) 266 #define UX_EHCI_CMASK_ISOOUT_ANY (0x00u<<8) 267 #define UX_EHCI_CMASK_INT_Y0 (0x1Cu<<8) 268 #define UX_EHCI_CMASK_INT_Y1 (0x31u<<8) 269 #define UX_EHCI_CMASK_INT_Y2 (0x70u<<8) 270 #define UX_EHCI_CMASK_INT_Y3 (0xE0u<<8) 271 #define UX_EHCI_CMASK_INT_Y4 (0xC1u<<8) 272 #define UX_EHCI_CMASK_INT_Y5 (0x81u<<8) 273 #define UX_EHCI_CMASK_INT_Y7 (0x07u<<8) 274 #define UX_EHCI_CMASK_ISOIN_C1 (0x01u<<8) 275 #define UX_EHCI_CMASK_ISOIN_C2 (0x03u<<8) 276 #define UX_EHCI_CMASK_ISOIN_C3 (0x07u<<8) 277 #define UX_EHCI_CMASK_ISOIN_C4 (0x0Fu<<8) 278 #define UX_EHCI_CMASK_ISOIN_C5 (0x1Fu<<8) 279 #define UX_EHCI_CMASK_ISOIN_C6 (0x3Fu<<8) 280 281 #define UX_EHCI_SMASK_MASK (0xFFu<<0) 282 #define UX_EHCI_SMASK_0 (0x01u<<0) 283 #define UX_EHCI_SMASK_1 (0x02u<<0) 284 #define UX_EHCI_SMASK_2 (0x04u<<0) 285 #define UX_EHCI_SMASK_3 (0x08u<<0) 286 #define UX_EHCI_SMASK_4 (0x10u<<0) 287 #define UX_EHCI_SMASK_5 (0x20u<<0) 288 #define UX_EHCI_SMASK_6 (0x40u<<0) 289 #define UX_EHCI_SMASK_7 (0x80u<<0) 290 #define UX_EHCI_SMASK_INTERVAL_1 (0xFFu<<0) 291 #define UX_EHCI_SMASK_INTERVAL_2 (0x55u<<0) 292 #define UX_EHCI_SMASK_INTERVAL_3 (0x11u<<0) 293 #define UX_EHCI_SMASK_INTERVAL_4 (0x01u<<0) 294 295 296 /* EHCI general descriptor type (Buffer pointer page part). */ 297 298 #define UX_EHCI_BP_MASK (0xFFFFF000u) /* 4K align. */ 299 300 /* Define EHCI pointers. */ 301 302 typedef union UX_EHCI_POINTER_UNION { 303 ULONG value; 304 VOID *void_ptr; 305 UCHAR *u8_ptr; 306 USHORT *u16_ptr; 307 ULONG *u32_ptr; 308 } UX_EHCI_POINTER; 309 310 typedef union UX_EHCI_LINK_POINTER_UNION { 311 ULONG value; 312 VOID *void_ptr; 313 UCHAR *u8_ptr; 314 USHORT *u16_ptr; 315 ULONG *u32_ptr; 316 struct UX_EHCI_ED_STRUCT *qh_ptr; 317 struct UX_EHCI_ED_STRUCT *ed_ptr; 318 struct UX_EHCI_TD_STRUCT *td_ptr; 319 struct UX_EHCI_HSISO_TD_STRUCT *itd_ptr; 320 struct UX_EHCI_FSISO_TD_STRUCT *sitd_ptr; 321 } UX_EHCI_LINK_POINTER; 322 323 typedef union UX_EHCI_PERIODIC_LINK_POINTER_UNION { 324 ULONG value; 325 VOID *void_ptr; 326 UCHAR *u8_ptr; 327 USHORT *u16_ptr; 328 ULONG *u32_ptr; 329 struct UX_EHCI_ED_STRUCT *qh_ptr; 330 struct UX_EHCI_ED_STRUCT *ed_ptr; 331 struct UX_EHCI_HSISO_TD_STRUCT *itd_ptr; 332 struct UX_EHCI_FSISO_TD_STRUCT *sitd_ptr; 333 } UX_EHCI_PERIODIC_LINK_POINTER; 334 335 336 /* Define the EHCI structure. */ 337 338 typedef struct UX_HCD_EHCI_STRUCT 339 { 340 341 struct UX_HCD_STRUCT 342 *ux_hcd_ehci_hcd_owner; 343 ULONG ux_hcd_ehci_hcor; 344 struct UX_EHCI_ED_STRUCT 345 **ux_hcd_ehci_frame_list; 346 ULONG *ux_hcd_ehci_base; 347 UINT ux_hcd_ehci_nb_root_hubs; 348 struct UX_EHCI_TD_STRUCT 349 *ux_hcd_ehci_done_head; 350 struct UX_EHCI_ED_STRUCT 351 *ux_hcd_ehci_ed_list; 352 struct UX_EHCI_TD_STRUCT 353 *ux_hcd_ehci_td_list; 354 struct UX_EHCI_FSISO_TD_STRUCT 355 *ux_hcd_ehci_fsiso_td_list; 356 struct UX_EHCI_HSISO_TD_STRUCT 357 *ux_hcd_ehci_hsiso_td_list; 358 struct UX_EHCI_ED_STRUCT 359 *ux_hcd_ehci_asynch_head_list; 360 struct UX_EHCI_ED_STRUCT 361 *ux_hcd_ehci_asynch_first_list; 362 struct UX_EHCI_ED_STRUCT 363 *ux_hcd_ehci_asynch_last_list; 364 struct UX_EHCI_HSISO_TD_STRUCT 365 *ux_hcd_ehci_hsiso_scan_list; 366 struct UX_EHCI_FSISO_TD_STRUCT 367 *ux_hcd_ehci_fsiso_scan_list; 368 struct UX_TRANSFER_STRUCT 369 *ux_hcd_ehci_iso_done_transfer_head; 370 struct UX_TRANSFER_STRUCT 371 *ux_hcd_ehci_iso_done_transfer_tail; 372 struct UX_EHCI_ED_STRUCT 373 *ux_hcd_ehci_interrupt_ed_list; 374 UX_MUTEX ux_hcd_ehci_periodic_mutex; 375 UX_SEMAPHORE ux_hcd_ehci_protect_semaphore; 376 UX_SEMAPHORE ux_hcd_ehci_doorbell_semaphore; 377 ULONG ux_hcd_ehci_frame_list_size; 378 ULONG ux_hcd_ehci_interrupt_count; 379 ULONG ux_hcd_ehci_embedded_tt; 380 } UX_HCD_EHCI; 381 382 383 /* Define EHCI ED structure. */ 384 385 typedef struct UX_EHCI_ED_STRUCT 386 { 387 388 struct UX_EHCI_ED_STRUCT 389 *ux_ehci_ed_queue_head; 390 ULONG ux_ehci_ed_cap0; 391 ULONG ux_ehci_ed_cap1; 392 struct UX_EHCI_TD_STRUCT 393 *ux_ehci_ed_current_td; 394 struct UX_EHCI_TD_STRUCT 395 *ux_ehci_ed_queue_element; 396 struct UX_EHCI_TD_STRUCT 397 *ux_ehci_ed_alternate_td; 398 ULONG ux_ehci_ed_state; 399 VOID *ux_ehci_ed_bp0; 400 VOID *ux_ehci_ed_bp1; 401 VOID *ux_ehci_ed_bp2; 402 VOID *ux_ehci_ed_bp3; 403 VOID *ux_ehci_ed_bp4; 404 /* 12 DWords, 48 bytes QH for controller end. */ 405 406 ULONG ux_ehci_ed_status; 407 struct UX_EHCI_ED_STRUCT 408 *ux_ehci_ed_next_ed; 409 struct UX_EHCI_ED_STRUCT 410 *ux_ehci_ed_previous_ed; 411 struct UX_EHCI_TD_STRUCT 412 *ux_ehci_ed_first_td; 413 struct UX_EHCI_TD_STRUCT 414 *ux_ehci_ed_last_td; 415 union { 416 struct { /* For anchor. */ 417 struct UX_EHCI_ED_STRUCT 418 *ux_ehci_ed_next_anchor; /* + 1 DWord. */ 419 USHORT ux_ehci_ed_microframe_load[8]; /* + 4 DWords. */ 420 UCHAR ux_ehci_ed_microframe_ssplit_count[8]; /* + 2 DWords. */ 421 } ANCHOR; 422 struct { /* As interrupt ED. */ 423 struct UX_EHCI_ED_STRUCT 424 *ux_ehci_ed_anchor; /* + 1 DWord. */ 425 struct UX_ENDPOINT_STRUCT 426 *ux_ehci_ed_endpoint; /* + 1 Dword. */ 427 } INTR; 428 struct { /* Space: 7 DWord. */ 429 ULONG ux_ehci_ed_reserved[7]; 430 } RESERVED; 431 } REF_AS; 432 /* 24 DWord aligned. */ 433 } UX_EHCI_ED; 434 435 436 /* Define EHCI ED bitmap. */ 437 438 #define UX_EHCI_QH_TYP_ITD 0u 439 #define UX_EHCI_QH_TYP_QH 2u 440 #define UX_EHCI_QH_TYP_SITD 4u 441 #define UX_EHCI_QH_TYP_FSTN 6u 442 443 #define UX_EHCI_QH_T 1u 444 445 #define UX_EHCI_QH_STATIC 0x80000000u 446 #define UX_EHCI_QH_SSPLIT_SCH_FULL_7 0x40000000u 447 #define UX_EHCI_QH_SSPLIT_SCH_FULL_6 0x20000000u 448 #define UX_EHCI_QH_SSPLIT_SCH_FULL_5 0x10000000u 449 #define UX_EHCI_QH_SSPLIT_SCH_FULL_4 0x08000000u 450 #define UX_EHCI_QH_SSPLIT_SCH_FULL_3 0x04000000u 451 #define UX_EHCI_QH_SSPLIT_SCH_FULL_2 0x02000000u 452 #define UX_EHCI_QH_SSPLIT_SCH_FULL_1 0x01000000u 453 #define UX_EHCI_QH_SSPLIT_SCH_FULL_0 0x00800000u 454 455 #define UX_EHCI_QH_MPS_LOC 16u 456 #define UX_EHCI_QH_MPS_MASK 0x07ff0000u 457 #define UX_EHCI_QH_NCR 0xf0000000u 458 #define UX_EHCI_QH_CEF 0x08000000u 459 #define UX_EHCI_QH_ED_AD_LOC 8u 460 #define UX_EHCI_QH_HBPM 0x40000000u 461 #define UX_EHCI_QH_HBPM_LOC 30u 462 #define UX_EHCI_QH_HEAD 0x00008000u 463 464 #define UX_EHCI_QH_HIGH_SPEED 0x00002000u 465 #define UX_EHCI_QH_LOW_SPEED 0x00001000u 466 467 #define UX_EHCI_QH_HUB_ADDR_LOC 16u 468 #define UX_EHCI_QH_PORT_NUMBER_LOC 23u 469 #define UX_EHCI_QH_MULT_LOC 30u 470 #define UX_EHCI_QH_MULT_MASK 0xc0000000u 471 #define UX_EHCI_QH_C_MASK 0x00001c00u 472 #define UX_EHCI_QH_IS_MASK 0x00000001u 473 474 #define UX_EHCI_QH_SMASK_MASK 0x000000FFu 475 #define UX_EHCI_QH_SMASK_0 0x00000001u 476 #define UX_EHCI_QH_SMASK_1 0x00000002u 477 #define UX_EHCI_QH_SMASK_2 0x00000004u 478 #define UX_EHCI_QH_SMASK_3 0x00000008u 479 #define UX_EHCI_QH_SMASK_4 0x00000010u 480 #define UX_EHCI_QH_SMASK_5 0x00000020u 481 #define UX_EHCI_QH_SMASK_6 0x00000040u 482 #define UX_EHCI_QH_SMASK_7 0x00000080u 483 484 #define UX_EHCI_QH_DTC 0x00004000u 485 #define UX_EHCI_QH_TOGGLE 0x80000000u 486 #define UX_EHCI_LINK_ADDRESS_MASK 0xfffffff0u 487 #define UX_EHCI_TOGGLE_0 0u 488 #define UX_EHCI_TOGGLE_1 0x80000000u 489 490 /* Define EHCI TD structure. */ 491 492 typedef struct UX_EHCI_TD_STRUCT 493 { 494 495 struct UX_EHCI_TD_STRUCT 496 *ux_ehci_td_link_pointer; 497 struct UX_EHCI_TD_STRUCT 498 *ux_ehci_td_alternate_link_pointer; 499 ULONG ux_ehci_td_control; 500 VOID *ux_ehci_td_bp0; 501 VOID *ux_ehci_td_bp1; 502 VOID *ux_ehci_td_bp2; 503 VOID *ux_ehci_td_bp3; 504 VOID *ux_ehci_td_bp4; 505 /* 8-DWords, 32-bytes qTD for controller. */ 506 struct UX_TRANSFER_STRUCT 507 *ux_ehci_td_transfer_request; 508 struct UX_EHCI_TD_STRUCT 509 *ux_ehci_td_next_td_transfer_request; 510 struct UX_EHCI_ED_STRUCT 511 *ux_ehci_td_ed; 512 ULONG ux_ehci_td_length; 513 ULONG ux_ehci_td_status; 514 ULONG ux_ehci_td_phase; 515 ULONG ux_ehci_td_reserved_2[2]; 516 /* 16-DWord aligned. */ 517 } UX_EHCI_TD; 518 519 520 /* Define EHCI TD bitmap. */ 521 522 #define UX_EHCI_TD_T 1u 523 #define UX_EHCI_TD_LG_LOC 16u 524 #define UX_EHCI_TD_LG_MASK 0x7fffu 525 #define UX_EHCI_TD_IOC 0x00008000u 526 #define UX_EHCI_TD_CERR 0x00000c00u 527 528 #define UX_EHCI_TD_PING 1u 529 #define UX_EHCI_TD_DO_COMPLETE_SPLIT 2u 530 #define UX_EHCI_TD_MISSED_MICRO_FRAMES 4u 531 #define UX_EHCI_TD_TRANSACTION_ERROR 8u 532 #define UX_EHCI_TD_BABBLE_DETECTED 0x10u 533 #define UX_EHCI_TD_DATA_BUFFER_ERROR 0x20u 534 #define UX_EHCI_TD_HALTED 0x40u 535 #define UX_EHCI_TD_ACTIVE 0x80u 536 537 #define UX_EHCI_PID_OUT 0x00000000u 538 #define UX_EHCI_PID_IN 0x00000100u 539 #define UX_EHCI_PID_SETUP 0x00000200u 540 #define UX_EHCI_PID_MASK 0x00000300u 541 542 #define UX_EHCI_TD_SETUP_PHASE 0x00010000u 543 #define UX_EHCI_TD_DATA_PHASE 0x00020000u 544 #define UX_EHCI_TD_STATUS_PHASE 0x00040000u 545 546 /* Define EHCI ISOCHRONOUS TD extension structure. */ 547 548 typedef struct UX_EHCI_HSISO_ED_STRUCT 549 { 550 struct UX_ENDPOINT_STRUCT 551 *ux_ehci_hsiso_ed_endpoint; 552 struct UX_EHCI_ED_STRUCT 553 *ux_ehci_hsiso_ed_anchor; 554 struct UX_TRANSFER_STRUCT 555 *ux_ehci_hsiso_ed_transfer_head; 556 struct UX_TRANSFER_STRUCT 557 *ux_ehci_hsiso_ed_transfer_tail; 558 struct UX_TRANSFER_STRUCT 559 *ux_ehci_hsiso_ed_transfer_first_new; 560 struct UX_EHCI_HSISO_TD_STRUCT 561 *ux_ehci_hsiso_ed_fr_td[4]; 562 UCHAR ux_ehci_hsiso_ed_frindex; /* 1st usable micro-frame. */ 563 UCHAR ux_ehci_hsiso_ed_frinterval; /* Micro-frame interval. */ 564 UCHAR ux_ehci_hsiso_ed_frinterval_shift; /* Shift for micro-frame interval. */ 565 UCHAR ux_ehci_hsiso_ed_nb_tds; 566 USHORT ux_ehci_hsiso_ed_frstart; /* Start micro-frame. */ 567 USHORT ux_ehci_hsiso_ed_frload; 568 USHORT ux_ehci_hsiso_ed_fr_hc; /* Micro-frame HC process count. */ 569 USHORT ux_ehci_hsiso_ed_fr_sw; /* Micro-frame SW load count. */ 570 } UX_EHCI_HSISO_ED; 571 572 /* Define EHCI ISOCHRONOUS TD structure. */ 573 574 typedef struct UX_EHCI_HSISO_TD_STRUCT 575 { 576 577 union UX_EHCI_PERIODIC_LINK_POINTER_UNION 578 ux_ehci_hsiso_td_next_lp; 579 ULONG ux_ehci_hsiso_td_control[8]; 580 VOID *ux_ehci_hsiso_td_bp[7]; 581 /* 16 DWords, 64-bytes iTD for controller end. */ 582 UCHAR ux_ehci_hsiso_td_status; 583 UCHAR ux_ehci_hsiso_td_frload; /* REQ load map. */ 584 USHORT ux_ehci_hsiso_td_max_trans_size; 585 union UX_EHCI_PERIODIC_LINK_POINTER_UNION 586 ux_ehci_hsiso_td_previous_lp; 587 struct UX_EHCI_HSISO_TD_STRUCT 588 *ux_ehci_hsiso_td_next_scan_td; 589 struct UX_EHCI_HSISO_TD_STRUCT 590 *ux_ehci_hsiso_td_previous_scan_td; 591 struct UX_TRANSFER_STRUCT 592 *ux_ehci_hsiso_td_fr_transfer[3]; 593 struct UX_EHCI_HSISO_ED_STRUCT 594 *ux_ehci_hsiso_td_ed; 595 /* 24 DWord aligned. */ 596 } UX_EHCI_HSISO_TD; 597 598 599 /* Next Link Pointer(LP). */ 600 601 #define UX_EHCI_HSISO_LP_MASK UX_EHCI_LP_MASK 602 603 #define UX_EHCI_HSISO_TYP_MASK UX_EHCI_TYP_MASK 604 #define UX_EHCI_HSISO_TYP_ITD UX_EHCI_TYP_ITD 605 #define UX_EHCI_HSISO_TYP_QH UX_EHCI_TYP_QH 606 #define UX_EHCI_HSISO_TYP_SITD UX_EHCI_TYP_SITD 607 #define UX_EHCI_HSISO_TYP_FSTN UX_EHCI_TYP_FSTN 608 609 #define UX_EHCI_HSISO_T UX_EHCI_T 610 611 /* Transaction Status and Control. */ 612 613 #define UX_EHCI_HSISO_STATUS_MASK 0xF0000000u 614 #define UX_EHCI_HSISO_STATUS_ACTIVE 0x80000000u 615 #define UX_EHCI_HSISO_STATUS_DATA_BUFFER_ERR 0x40000000u 616 #define UX_EHCI_HSISO_STATUS_BABBLE_DETECTED 0x20000000u 617 #define UX_EHCI_HSISO_STATUS_XACT_ERR 0x10000000u 618 619 #define UX_EHCI_HSISO_XACT_LENGTH_MASK 0x0FFF0000u 620 #define UX_EHCI_HSISO_XACT_LENGTH_SHIFT 16 621 #define UX_EHCI_HSISO_XACT_LENGTH_VALUE_MAX 0xC00 622 623 #define UX_EHCI_HSISO_IOC 0x00008000u 624 #define UX_EHCI_HSISO_IOC_SHIFT 15 625 626 #define UX_EHCI_HSISO_PG_MASK 0x00007000u 627 #define UX_EHCI_HSISO_PG_SHIFT 12 628 629 #define UX_EHCI_HSISO_XACT_OFFSET_MASK 0x00000FFFu 630 631 /* Buffer Page Pointer List. */ 632 633 #define UX_EHCI_HSISO_BP_MASK UX_EHCI_BP_MASK 634 635 /* BP0 */ 636 637 #define UX_EHCI_HSISO_ENDPT_MASK UX_EHCI_ENDPT_MASK 638 #define UX_EHCI_HSISO_ENDPT_SHIFT UX_EHCI_ENDPT_SHIFT 639 640 #define UX_EHCI_HSISO_DEVICE_ADDRESS_MASK UX_EHCI_DEVICE_ADDRESS_MASK 641 642 /* BP1 */ 643 644 #define UX_EHCI_HSISO_DIRECTION (0x1u << 11) 645 #define UX_EHCI_HSISO_DIRECTION_IN UX_EHCI_HSISO_DIRECTION 646 #define UX_EHCI_HSISO_DIRECTION_OUT 0 647 648 #define UX_EHCI_HSISO_MAX_PACKET_SIZE_MASK 0x000007FFu 649 #define UX_EHCI_HSISO_MAX_PACKET_SIZE_MAX 0x00000400 650 651 /* BP2 */ 652 653 #define UX_EHCI_HSISO_MULTI_MASK 0x00000003u 654 #define UX_EHCI_HSISO_MULTI_ONE 1 655 #define UX_EHCI_HSISO_MULTI_TWO 2 656 #define UX_EHCI_HSISO_MULTI_THREE 3 657 658 /* Define EHCI FS ISOCHRONOUS TD structure. */ 659 660 typedef struct UX_EHCI_FSISO_TD_STRUCT 661 { 662 union UX_EHCI_PERIODIC_LINK_POINTER_UNION 663 ux_ehci_fsiso_td_next_lp; 664 ULONG ux_ehci_fsiso_td_cap0; /* endpoint */ 665 ULONG ux_ehci_fsiso_td_cap1; /* uFrame schedule */ 666 ULONG ux_ehci_fsiso_td_state; 667 VOID *ux_ehci_fsiso_td_bp[2]; 668 VOID *ux_ehci_fsiso_td_back_pointer; 669 /* 7 DWords, 28-bytes siTD for controller end. */ 670 671 UCHAR ux_ehci_fsiso_td_status; 672 UCHAR ux_ehci_fsiso_td_frindex; 673 UCHAR ux_ehci_fsiso_td_nb_ed_tds; 674 UCHAR reserved[1]; 675 struct UX_ENDPOINT_STRUCT 676 *ux_ehci_fsiso_td_endpoint; 677 struct UX_TRANSFER_STRUCT 678 *ux_ehci_fsiso_td_transfer_head; 679 struct UX_TRANSFER_STRUCT 680 *ux_ehci_fsiso_td_transfer_tail; 681 union UX_EHCI_PERIODIC_LINK_POINTER_UNION 682 ux_ehci_fsiso_td_previous_lp; 683 struct UX_EHCI_FSISO_TD_STRUCT 684 *ux_ehci_fsiso_td_next_scan_td; 685 struct UX_EHCI_FSISO_TD_STRUCT 686 *ux_ehci_fsiso_td_previous_scan_td; 687 struct UX_EHCI_ED_STRUCT 688 *ux_ehci_fsiso_td_anchor; 689 struct UX_EHCI_TD_STRUCT 690 *ux_ehci_fsiso_td_next_ed_td; 691 /* 16-DWord aligned. */ 692 } UX_EHCI_FSISO_TD; 693 694 /* Next Link Pointer (LP). */ 695 696 #define UX_EHCI_FSISO_LP_MASK UX_EHCI_LP_MASK 697 698 #define UX_EHCI_FSISO_TYP_MASK UX_EHCI_TYP_MASK 699 #define UX_EHCI_FSISO_TYP_ITD UX_EHCI_TYP_ITD 700 #define UX_EHCI_FSISO_TYP_QH UX_EHCI_TYP_QH 701 #define UX_EHCI_FSISO_TYP_SITD UX_EHCI_TYP_SITD 702 #define UX_EHCI_FSISO_TYP_FSTN UX_EHCI_TYP_FSTN 703 704 #define UX_EHCI_FSISO_T UX_EHCI_T 705 706 /* Endpoint Capabilities/Characteristics. */ 707 708 #define UX_EHCI_FSISO_DIRECTION 0x80000000u 709 #define UX_EHCI_FSISO_DIRECTION_IN 0x80000000u 710 #define UX_EHCI_FSISO_DIRECTION_OUT 0x00000000 711 712 #define UX_EHCI_FSISO_PORT_NUMBER_MASK 0x7F000000u 713 #define UX_EHCI_FSISO_PORT_NUMBER_SHIFT 24 714 715 #define UX_EHCI_FSISO_HUB_ADDRESS_MASK 0x003F0000u 716 #define UX_EHCI_FSISO_HUB_ADDRESS_SHIFT 16 717 718 #define UX_EHCI_FSISO_ENDPT_MASK UX_EHCI_ENDPT_MASK 719 #define UX_EHCI_FSISO_ENDPT_SHIFT UX_EHCI_ENDPT_SHIFT 720 721 #define UX_EHCI_FSISO_DEVICE_ADDRESS_MASK UX_EHCI_DEVICE_ADDRESS_MASK 722 723 /* Micro-frame Schedule Control. */ 724 725 #define UX_EHCI_FSISO_UFRAME_CMASK_MASK UX_EHCI_CMASK_MASK 726 #define UX_EHCI_FSISO_UFRAME_CMASK_0 UX_EHCI_CMASK_0 727 #define UX_EHCI_FSISO_UFRAME_CMASK_1 UX_EHCI_CMASK_1 728 #define UX_EHCI_FSISO_UFRAME_CMASK_2 UX_EHCI_CMASK_2 729 #define UX_EHCI_FSISO_UFRAME_CMASK_3 UX_EHCI_CMASK_3 730 #define UX_EHCI_FSISO_UFRAME_CMASK_4 UX_EHCI_CMASK_4 731 #define UX_EHCI_FSISO_UFRAME_CMASK_5 UX_EHCI_CMASK_5 732 #define UX_EHCI_FSISO_UFRAME_CMASK_6 UX_EHCI_CMASK_6 733 #define UX_EHCI_FSISO_UFRAME_CMASK_7 UX_EHCI_CMASK_7 734 735 #define UX_EHCI_FSISO_UFRAME_SMASK_MASK UX_EHCI_SMASK_MASK 736 #define UX_EHCI_FSISO_UFRAME_SMASK_0 UX_EHCI_SMASK_0 737 #define UX_EHCI_FSISO_UFRAME_SMASK_1 UX_EHCI_SMASK_1 738 #define UX_EHCI_FSISO_UFRAME_SMASK_2 UX_EHCI_SMASK_2 739 #define UX_EHCI_FSISO_UFRAME_SMASK_3 UX_EHCI_SMASK_3 740 #define UX_EHCI_FSISO_UFRAME_SMASK_4 UX_EHCI_SMASK_4 741 #define UX_EHCI_FSISO_UFRAME_SMASK_5 UX_EHCI_SMASK_5 742 #define UX_EHCI_FSISO_UFRAME_SMASK_6 UX_EHCI_SMASK_6 743 #define UX_EHCI_FSISO_UFRAME_SMASK_7 UX_EHCI_SMASK_7 744 745 /* Transfer State. */ 746 747 /* Transfer Status and Control. */ 748 749 #define UX_EHCI_FSISO_IOC 0x80000000u 750 751 #define UX_EHCI_FSISO_P 0x40000000u 752 753 #define UX_EHCI_FSISO_TOTAL_BYTES_MASK 0x03FF0000u 754 #define UX_EHCI_FSISO_TOTAL_BYTES_SHIFT 16 755 #define UX_EHCI_FSISO_TOTAL_BYTES_MAX_VALUE 1023 756 757 #define UX_EHCI_FSISO_CPROMASK_MASK 0x0000FF00u 758 #define UX_EHCI_FSISO_CPROMASK_SHIFT 8 759 760 #define UX_EHCI_FSISO_STATUS_MASK 0x000000FFu 761 #define UX_EHCI_FSISO_STATUS_ACTIVE 0x00000080u 762 #define UX_EHCI_FSISO_STATUS_ERR 0x00000040u 763 #define UX_EHCI_FSISO_STATUS_DATA_BUFFER_ERR 0x00000020u 764 #define UX_EHCI_FSISO_STATUS_BABBLE_DETECTED 0x00000010u 765 #define UX_EHCI_FSISO_STATUS_XACTERR 0x00000008u 766 #define UX_EHCI_FSISO_STATUS_MISSED_MFRAME 0x00000004u 767 768 #define UX_EHCI_FSISO_STATUS_SPLIT_STATE_MASK 0x00000002u 769 #define UX_EHCI_FSISO_STATUS_SPLIT_STATE_DO_START 0x00000000u 770 #define UX_EHCI_FSISO_STATUS_SPLIT_STATE_DO_COMPLETE 0x00000002u 771 772 /* Buffer Page Pointer List. */ 773 774 #define UX_EHCI_FSISO_BP_MASK UX_EHCI_BP_MASK 775 776 /* BP0 */ 777 778 #define UX_EHCI_FSISO_CURRENT_OFFSET_MASK 0x00000FFFu 779 780 /* BP1 */ 781 782 #define UX_EHCI_FSISO_TP_MASK 0x0000000Cu 783 #define UX_EHCI_FSISO_TP_ALL 0x00000000u 784 #define UX_EHCI_FSISO_TP_BEGIN 0x00000004u 785 #define UX_EHCI_FSISO_TP_MID 0x00000008u 786 #define UX_EHCI_FSISO_TP_END 0x0000000Cu 787 788 #define UX_EHCI_FSISO_TCOUNT_MASK 0x00000007u 789 #define UX_EHCI_FSISO_TCOUNT_MAX 6 790 791 792 /* Define EHCI function prototypes. */ 793 794 void _ux_hcd_ehci_periodic_descriptor_link(VOID* prev, VOID* prev_next, VOID* next_prev, VOID* next); 795 UX_EHCI_TD *_ux_hcd_ehci_asynch_td_process(UX_EHCI_ED *ed, UX_EHCI_TD *td); 796 UX_EHCI_HSISO_TD *_ux_hcd_ehci_hsisochronous_tds_process(UX_HCD_EHCI *hcd_ehci, UX_EHCI_HSISO_TD* itd); 797 UX_EHCI_FSISO_TD *_ux_hcd_ehci_fsisochronous_tds_process(UX_HCD_EHCI *hcd_ehci, UX_EHCI_FSISO_TD* sitd); 798 UINT _ux_hcd_ehci_asynchronous_endpoint_create(UX_HCD_EHCI *hcd_ehci, UX_ENDPOINT *endpoint); 799 UINT _ux_hcd_ehci_asynchronous_endpoint_destroy(UX_HCD_EHCI *hcd_ehci, UX_ENDPOINT *endpoint); 800 UINT _ux_hcd_ehci_controller_disable(UX_HCD_EHCI *hcd_ehci); 801 VOID _ux_hcd_ehci_done_queue_process(UX_HCD_EHCI *hcd_ehci); 802 VOID _ux_hcd_ehci_door_bell_wait(UX_HCD_EHCI *hcd_ehci); 803 UINT _ux_hcd_ehci_ed_clean(UX_EHCI_ED *ed); 804 UX_EHCI_ED *_ux_hcd_ehci_ed_obtain(UX_HCD_EHCI *hcd_ehci); 805 UINT _ux_hcd_ehci_endpoint_reset(UX_HCD_EHCI *hcd_ehci, UX_ENDPOINT *endpoint); 806 UINT _ux_hcd_ehci_entry(UX_HCD *hcd, UINT function, VOID *parameter); 807 UINT _ux_hcd_ehci_frame_number_get(UX_HCD_EHCI *hcd_ehci, ULONG *frame_number); 808 VOID _ux_hcd_ehci_frame_number_set(UX_HCD_EHCI *hcd_ehci, ULONG frame_number); 809 UX_EHCI_FSISO_TD *_ux_hcd_ehci_fsisochronous_td_obtain(UX_HCD_EHCI *hcd_ehci); 810 UX_EHCI_HSISO_TD *_ux_hcd_ehci_hsisochronous_td_obtain(UX_HCD_EHCI *hcd_ehci); 811 UINT _ux_hcd_ehci_initialize(UX_HCD *hcd); 812 UINT _ux_hcd_ehci_interrupt_endpoint_create(UX_HCD_EHCI *hcd_ehci, UX_ENDPOINT *endpoint); 813 UINT _ux_hcd_ehci_interrupt_endpoint_destroy(UX_HCD_EHCI *hcd_ehci, UX_ENDPOINT *endpoint); 814 VOID _ux_hcd_ehci_interrupt_handler(VOID); 815 UINT _ux_hcd_ehci_isochronous_endpoint_create(UX_HCD_EHCI *hcd_ehci, UX_ENDPOINT *endpoint); 816 UINT _ux_hcd_ehci_isochronous_endpoint_destroy(UX_HCD_EHCI *hcd_ehci, UX_ENDPOINT *endpoint); 817 UX_EHCI_ED *_ux_hcd_ehci_least_traffic_list_get(UX_HCD_EHCI *hcd_ehci, ULONG microframe_load[8], ULONG microframe_ssplit_count[8]); 818 UX_EHCI_ED *_ux_hcd_ehci_poll_rate_entry_get(UX_HCD_EHCI *hcd_ehci, UX_EHCI_ED *ed_list, ULONG poll_depth); 819 VOID _ux_hcd_ehci_next_td_clean(UX_EHCI_TD *td); 820 UINT _ux_hcd_ehci_periodic_tree_create(UX_HCD_EHCI *hcd_ehci); 821 UINT _ux_hcd_ehci_port_disable(UX_HCD_EHCI *hcd_ehci, ULONG port_index); 822 UINT _ux_hcd_ehci_port_reset(UX_HCD_EHCI *hcd_ehci, ULONG port_index); 823 UINT _ux_hcd_ehci_port_resume(UX_HCD_EHCI *hcd_ehci, UINT port_index); 824 ULONG _ux_hcd_ehci_port_status_get(UX_HCD_EHCI *hcd_ehci, ULONG port_index); 825 UINT _ux_hcd_ehci_port_suspend(UX_HCD_EHCI *hcd_ehci, ULONG port_index); 826 UINT _ux_hcd_ehci_power_down_port(UX_HCD_EHCI *hcd_ehci, ULONG port_index); 827 UINT _ux_hcd_ehci_power_on_port(UX_HCD_EHCI *hcd_ehci, ULONG port_index); 828 VOID _ux_hcd_ehci_power_root_hubs(UX_HCD_EHCI *hcd_ehci); 829 ULONG _ux_hcd_ehci_register_read(UX_HCD_EHCI *hcd_ehci, ULONG ehci_register); 830 VOID _ux_hcd_ehci_register_write(UX_HCD_EHCI *hcd_ehci, ULONG ehci_register, ULONG value); 831 UX_EHCI_TD *_ux_hcd_ehci_regular_td_obtain(UX_HCD_EHCI *hcd_ehci); 832 UINT _ux_hcd_ehci_request_bulk_transfer(UX_HCD_EHCI *hcd_ehci, UX_TRANSFER *transfer_request); 833 UINT _ux_hcd_ehci_request_control_transfer(UX_HCD_EHCI *hcd_ehci, UX_TRANSFER *transfer_request); 834 UINT _ux_hcd_ehci_request_interrupt_transfer(UX_HCD_EHCI *hcd_ehci, UX_TRANSFER *transfer_request); 835 UINT _ux_hcd_ehci_request_isochronous_transfer(UX_HCD_EHCI *hcd_ehci, UX_TRANSFER *transfer_request); 836 UINT _ux_hcd_ehci_request_transfer(UX_HCD_EHCI *hcd_ehci, UX_TRANSFER *transfer_request); 837 UINT _ux_hcd_ehci_request_transfer_add(UX_HCD_EHCI *hcd_ehci, UX_EHCI_ED *ed, ULONG phase, ULONG pid, 838 ULONG toggle, UCHAR * buffer_address, ULONG buffer_length, UX_TRANSFER *transfer_request); 839 UINT _ux_hcd_ehci_transfer_abort(UX_HCD_EHCI *hcd_ehci,UX_TRANSFER *transfer_request); 840 VOID _ux_hcd_ehci_transfer_request_process(UX_TRANSFER *transfer_request); 841 842 #define ux_hcd_ehci_initialize _ux_hcd_ehci_initialize 843 #define ux_hcd_ehci_interrupt_handler _ux_hcd_ehci_interrupt_handler 844 845 /* Determine if a C++ compiler is being used. If so, complete the standard 846 C conditional started above. */ 847 #ifdef __cplusplus 848 } 849 #endif 850 851 #endif 852 853
