1 /*************************************************************************** 2 * Copyright (c) 2024 Microsoft Corporation 3 * 4 * This program and the accompanying materials are made available under the 5 * terms of the MIT License which is available at 6 * https://opensource.org/licenses/MIT. 7 * 8 * SPDX-License-Identifier: MIT 9 **************************************************************************/ 10 11 12 /**************************************************************************/ 13 /**************************************************************************/ 14 /** */ 15 /** USBX Component */ 16 /** */ 17 /** EHCI Controller */ 18 /** */ 19 /**************************************************************************/ 20 /**************************************************************************/ 21 22 23 /**************************************************************************/ 24 /* */ 25 /* COMPONENT DEFINITION RELEASE */ 26 /* */ 27 /* ux_hcd_ehci.h PORTABLE C */ 28 /* 6.1.8 */ 29 /* AUTHOR */ 30 /* */ 31 /* Chaoqiong Xiao, Microsoft Corporation */ 32 /* */ 33 /* DESCRIPTION */ 34 /* */ 35 /* This file contains all the header and extern functions used by the */ 36 /* USBX host EHCI Controller. */ 37 /* */ 38 /* RELEASE HISTORY */ 39 /* */ 40 /* DATE NAME DESCRIPTION */ 41 /* */ 42 /* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ 43 /* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ 44 /* used UX prefix to refer to */ 45 /* TX symbols instead of using */ 46 /* them directly, */ 47 /* resulting in version 6.1 */ 48 /* 11-09-2020 Chaoqiong Xiao Modified comment(s), */ 49 /* used unsigned defines, */ 50 /* named unions and structs, */ 51 /* resulting in version 6.1.2 */ 52 /* 08-02-2021 Chaoqiong Xiao Modified comment(s), */ 53 /* fixed spelling error, */ 54 /* added extern "C" keyword */ 55 /* for compatibility with C++, */ 56 /* resulting in version 6.1.8 */ 57 /* */ 58 /**************************************************************************/ 59 60 #ifndef UX_HCD_EHCI_H 61 #define UX_HCD_EHCI_H 62 63 /* Determine if a C++ compiler is being used. If so, ensure that standard 64 C is used to process the API information. */ 65 66 #ifdef __cplusplus 67 68 /* Yes, C++ compiler is present. Use standard C. */ 69 extern "C" { 70 71 #endif 72 73 74 /* Possible defined EHCI HCD extensions. */ 75 76 /* Extension for peripheral host mode select (function like). */ 77 /* #define UX_HCD_EHCI_EXT_USB_HOST_MODE_ENABLE(hcd_ehci) */ 78 79 /* Extension for embedded TT (UX_TRUE/UX_FALSE). */ 80 /* #define UX_HCD_EHCI_EXT_EMBEDDED_TT_SUPPORT */ 81 82 /* Extension for phy high speed mode select (function like). */ 83 /* #define UX_HCD_EHCI_EXT_USBPHY_HIGHSPEED_MODE_SET(hcd_ehci, on_off) */ 84 85 /* Define EHCI generic definitions. */ 86 87 #define UX_EHCI_CONTROLLER 2 88 #define UX_EHCI_MAX_PAYLOAD 16384 89 #define UX_EHCI_FRAME_DELAY 4 90 #define UX_EHCI_PAGE_SIZE 4096 91 #define UX_EHCI_PAGE_ALIGN 0xfffff000 92 93 94 /* Define EHCI host controller capability registers. */ 95 96 #define EHCI_HCCR_CAP_LENGTH 0x00 97 #define EHCI_HCCR_HCS_PARAMS 0x01 98 #define EHCI_HCCR_HCC_PARAMS 0x02 99 #define EHCI_HCCR_HCSP_PORT_ROUTE 0x03 100 101 102 /* Define EHCI host controller registers. */ 103 104 #define EHCI_HCOR_USB_COMMAND (hcd_ehci -> ux_hcd_ehci_hcor + 0x00) 105 #define EHCI_HCOR_USB_STATUS (hcd_ehci -> ux_hcd_ehci_hcor + 0x01) 106 #define EHCI_HCOR_USB_INTERRUPT (hcd_ehci -> ux_hcd_ehci_hcor + 0x02) 107 #define EHCI_HCOR_FRAME_INDEX (hcd_ehci -> ux_hcd_ehci_hcor + 0x03) 108 #define EHCI_HCOR_FRAME_LIST_BASE_ADDRESS (hcd_ehci -> ux_hcd_ehci_hcor + 0x05) 109 #define EHCI_HCOR_ASYNCH_LIST_ADDRESS (hcd_ehci -> ux_hcd_ehci_hcor + 0x06) 110 #define EHCI_HCOR_CONFIG_FLAG (hcd_ehci -> ux_hcd_ehci_hcor + 0x10) 111 #define EHCI_HCOR_PORT_SC (hcd_ehci -> ux_hcd_ehci_hcor + 0x11) 112 113 114 /* Define EHCI IO control register values. */ 115 116 #define EHCI_HC_IO_RS 0x00000001u 117 #define EHCI_HC_IO_HCRESET 0x00000002u 118 #define EHCI_HC_IO_PSE 0x00000010u 119 #define EHCI_HC_IO_ASE 0x00000020u 120 #define EHCI_HC_IO_IAAD 0x00000040u 121 #define EHCI_HC_IO_ITC 0x00010000u 122 #define EHCI_HC_IO_FRAME_SIZE_1024 0x00000000u 123 #define EHCI_HC_IO_FRAME_SIZE_512 0x00000004u 124 #define EHCI_HC_IO_FRAME_SIZE_256 0x00000008u 125 #define EHCI_HC_IO_FRAME_SIZE_128 0x0000000Cu 126 #define EHCI_HC_IO_FRAME_SIZE_64 0x00008000u 127 #define EHCI_HC_IO_FRAME_SIZE_32 0x00008004u 128 129 /* The number if entries in the periodic tree can be changed to save space IF and only IF the PFLF flag in the HCCPARAMS register 130 allows it. Setting values less than 1024 in controllers without the ability to change the Frame List Size leads to a EHCI crash. */ 131 132 #ifndef UX_EHCI_FRAME_LIST_ENTRIES 133 #define UX_EHCI_FRAME_LIST_ENTRIES 1024 134 #endif 135 #define UX_EHCI_FRAME_LIST_MASK EHCI_HC_IO_FRAME_SIZE_1024 136 137 /* Define EHCI HCOR status register. */ 138 139 #define EHCI_HC_STS_USB_INT 0x00000001u 140 #define EHCI_HC_STS_USB_ERR_INT 0x00000002u 141 #define EHCI_HC_STS_PCD 0x00000004u 142 #define EHCI_HC_STS_FLR 0x00000008u 143 #define EHCI_HC_STS_HSE 0x00000010u 144 #define EHCI_HC_STS_IAA 0x00000020u 145 #define EHCI_HC_STS_HC_HALTED 0x00001000u 146 #define EHCI_HC_STS_RECLAMATION 0x00002000u 147 #define EHCI_HC_STS_PSS 0x00004000u 148 #define EHCI_HC_STS_ASS 0x00008000u 149 150 #define EHCI_HC_INTERRUPT_ENABLE_NORMAL (EHCI_HC_STS_USB_INT|EHCI_HC_STS_USB_ERR_INT|EHCI_HC_STS_PCD|EHCI_HC_STS_HSE|EHCI_HC_STS_IAA) 151 152 153 /* Define EHCI HCOR root HUB command/status. */ 154 155 #define EHCI_HC_RH_PPC 0x00000010u 156 #define EHCI_HC_RH_PSM 0x00000100u 157 #define EHCI_HC_RH_NPS 0x00000200u 158 #define EHCI_HC_RH_DT 0x00000400u 159 #define EHCI_HC_RH_OCPM 0x00000800u 160 #define EHCI_HC_RH_NOCP 0x00001000u 161 162 #define EHCI_HC_PS_CCS 0x00000001u 163 #define EHCI_HC_PS_CSC 0x00000002u 164 #define EHCI_HC_PS_PE 0x00000004u 165 #define EHCI_HC_PS_PEC 0x00000008u 166 #define EHCI_HC_PS_OCA 0x00000010u 167 #define EHCI_HC_PS_OCC 0x00000020u 168 #define EHCI_HC_PS_FPR 0x00000040u 169 #define EHCI_HC_PS_SUSPEND 0x00000080u 170 #define EHCI_HC_PS_PR 0x00000100u 171 #define EHCI_HC_PS_PP 0x00001000u 172 #define EHCI_HC_PS_SPEED_MASK 0x00000c00u 173 #define EHCI_HC_PS_SPEED_LOW 0x00000400u 174 #define EHCI_HC_PS_PO 0x00002000u 175 #define EHCI_HC_PS_EMBEDDED_TT_SPEED_MASK 0x0c000000u 176 #define EHCI_HC_PS_EMBEDDED_TT_SPEED_FULL 0x00000000u 177 #define EHCI_HC_PS_EMBEDDED_TT_SPEED_LOW 0x04000000u 178 #define EHCI_HC_PS_EMBEDDED_TT_SPEED_HIGH 0x08000000u 179 180 #define EHCI_HC_RH_POWER_STABLE_DELAY 25 181 #define EHCI_HC_RH_RESET_DELAY 50 182 #define EHCI_HC_RH_RESET_SETTLE_DELAY 5 183 184 185 /* Define EHCI interrupt status register definitions. */ 186 187 #define EHCI_HC_INT_IE 0x00000001u 188 #define EHCI_HC_INT_EIE 0x00000002u 189 #define EHCI_HC_INT_PCIE 0x00000004u 190 #define EHCI_HC_INT_FLRE 0x00000008u 191 #define EHCI_HC_INT_HSER 0x00000010u 192 #define EHCI_HC_INT_IAAE 0x00000020u 193 194 195 /* Define EHCI frame interval definition. */ 196 197 #define EHCI_HC_FM_INTERVAL_CLEAR 0x8000ffff 198 #define EHCI_HC_FM_INTERVAL_SET 0x27780000 199 200 201 /* Define EHCI static definition. */ 202 203 #define UX_EHCI_AVAILABLE_BANDWIDTH 6000 204 #define UX_EHCI_STOP 0 205 #define UX_EHCI_START 1 206 #define UX_EHCI_ROUTE_TO_LOCAL_HC 1 207 #define UX_EHCI_INIT_DELAY 1000 208 #define UX_EHCI_RESET_RETRY 1000 209 #define UX_EHCI_RESET_DELAY 100 210 #define UX_EHCI_PORT_RESET_RETRY 10 211 #define UX_EHCI_PORT_RESET_DELAY 50 212 213 214 /* Define EHCI initialization values. */ 215 216 #define UX_EHCI_COMMAND_STATUS_RESET 0 217 #define UX_EHCI_INIT_RESET_DELAY 10 218 219 220 /* Define EHCI completion code errors. */ 221 222 #define UX_EHCI_NO_ERROR 0x00 223 #define UX_EHCI_ERROR_CRC 0x01 224 #define UX_EHCI_ERROR_BIT_STUFFING 0x02 225 #define UX_EHCI_ERROR_DATA_TOGGLE 0x03 226 #define UX_EHCI_ERROR_STALL 0x04 227 #define UX_EHCI_ERROR_DEVICE_NOT_RESPONDING 0x05 228 #define UX_EHCI_ERROR_PID_FAILURE 0x06 229 #define UX_EHCI_ERROR_DATA_OVERRUN 0x08 230 #define UX_EHCI_ERROR_DATA_UNDERRUN 0x09 231 #define UX_EHCI_ERROR_BUFFER_OVERRUN 0x0c 232 #define UX_EHCI_ERROR_BUFFER_UNDERRUN 0x0d 233 #define UX_EHCI_ERROR_NOT_ACCESSED 0x0f 234 #define UX_EHCI_ERROR_NAK 0x10 235 #define UX_EHCI_ERROR_BABBLE 0x11 236 237 /* EHCI general descriptor type (Link Pointer). */ 238 239 #define UX_EHCI_LP_MASK (0xFFFFFFE0u) /* 32-byte align. */ 240 241 #define UX_EHCI_TYP_MASK (0x3u<<1) 242 #define UX_EHCI_TYP_ITD (0x0u<<1) 243 #define UX_EHCI_TYP_QH (0x1u<<1) 244 #define UX_EHCI_TYP_SITD (0x2u<<1) 245 #define UX_EHCI_TYP_FSTN (0x3u<<1) 246 247 #define UX_EHCI_T (0x1u<<0) 248 249 /* EHCI general descriptor type (Capabilities). */ 250 251 #define UX_EHCI_ENDPT_MASK (0xFu<<8) 252 #define UX_EHCI_ENDPT_SHIFT (8) 253 254 #define UX_EHCI_DEVICE_ADDRESS_MASK (0x3Fu<<0) 255 256 #define UX_EHCI_CMASK_MASK (0xFFu<<8) 257 #define UX_EHCI_CMASK_0 (0x01u<<8) 258 #define UX_EHCI_CMASK_1 (0x02u<<8) 259 #define UX_EHCI_CMASK_2 (0x04u<<8) 260 #define UX_EHCI_CMASK_3 (0x08u<<8) 261 #define UX_EHCI_CMASK_4 (0x10u<<8) 262 #define UX_EHCI_CMASK_5 (0x20u<<8) 263 #define UX_EHCI_CMASK_6 (0x40u<<8) 264 #define UX_EHCI_CMASK_7 (0x80u<<8) 265 #define UX_EHCI_CMASK_ISOOUT_ANY (0x00u<<8) 266 #define UX_EHCI_CMASK_INT_Y0 (0x1Cu<<8) 267 #define UX_EHCI_CMASK_INT_Y1 (0x31u<<8) 268 #define UX_EHCI_CMASK_INT_Y2 (0x70u<<8) 269 #define UX_EHCI_CMASK_INT_Y3 (0xE0u<<8) 270 #define UX_EHCI_CMASK_INT_Y4 (0xC1u<<8) 271 #define UX_EHCI_CMASK_INT_Y5 (0x81u<<8) 272 #define UX_EHCI_CMASK_INT_Y7 (0x07u<<8) 273 #define UX_EHCI_CMASK_ISOIN_C1 (0x01u<<8) 274 #define UX_EHCI_CMASK_ISOIN_C2 (0x03u<<8) 275 #define UX_EHCI_CMASK_ISOIN_C3 (0x07u<<8) 276 #define UX_EHCI_CMASK_ISOIN_C4 (0x0Fu<<8) 277 #define UX_EHCI_CMASK_ISOIN_C5 (0x1Fu<<8) 278 #define UX_EHCI_CMASK_ISOIN_C6 (0x3Fu<<8) 279 280 #define UX_EHCI_SMASK_MASK (0xFFu<<0) 281 #define UX_EHCI_SMASK_0 (0x01u<<0) 282 #define UX_EHCI_SMASK_1 (0x02u<<0) 283 #define UX_EHCI_SMASK_2 (0x04u<<0) 284 #define UX_EHCI_SMASK_3 (0x08u<<0) 285 #define UX_EHCI_SMASK_4 (0x10u<<0) 286 #define UX_EHCI_SMASK_5 (0x20u<<0) 287 #define UX_EHCI_SMASK_6 (0x40u<<0) 288 #define UX_EHCI_SMASK_7 (0x80u<<0) 289 #define UX_EHCI_SMASK_INTERVAL_1 (0xFFu<<0) 290 #define UX_EHCI_SMASK_INTERVAL_2 (0x55u<<0) 291 #define UX_EHCI_SMASK_INTERVAL_3 (0x11u<<0) 292 #define UX_EHCI_SMASK_INTERVAL_4 (0x01u<<0) 293 294 295 /* EHCI general descriptor type (Buffer pointer page part). */ 296 297 #define UX_EHCI_BP_MASK (0xFFFFF000u) /* 4K align. */ 298 299 /* Define EHCI pointers. */ 300 301 typedef union UX_EHCI_POINTER_UNION { 302 ULONG value; 303 VOID *void_ptr; 304 UCHAR *u8_ptr; 305 USHORT *u16_ptr; 306 ULONG *u32_ptr; 307 } UX_EHCI_POINTER; 308 309 typedef union UX_EHCI_LINK_POINTER_UNION { 310 ULONG value; 311 VOID *void_ptr; 312 UCHAR *u8_ptr; 313 USHORT *u16_ptr; 314 ULONG *u32_ptr; 315 struct UX_EHCI_ED_STRUCT *qh_ptr; 316 struct UX_EHCI_ED_STRUCT *ed_ptr; 317 struct UX_EHCI_TD_STRUCT *td_ptr; 318 struct UX_EHCI_HSISO_TD_STRUCT *itd_ptr; 319 struct UX_EHCI_FSISO_TD_STRUCT *sitd_ptr; 320 } UX_EHCI_LINK_POINTER; 321 322 typedef union UX_EHCI_PERIODIC_LINK_POINTER_UNION { 323 ULONG value; 324 VOID *void_ptr; 325 UCHAR *u8_ptr; 326 USHORT *u16_ptr; 327 ULONG *u32_ptr; 328 struct UX_EHCI_ED_STRUCT *qh_ptr; 329 struct UX_EHCI_ED_STRUCT *ed_ptr; 330 struct UX_EHCI_HSISO_TD_STRUCT *itd_ptr; 331 struct UX_EHCI_FSISO_TD_STRUCT *sitd_ptr; 332 } UX_EHCI_PERIODIC_LINK_POINTER; 333 334 335 /* Define the EHCI structure. */ 336 337 typedef struct UX_HCD_EHCI_STRUCT 338 { 339 340 struct UX_HCD_STRUCT 341 *ux_hcd_ehci_hcd_owner; 342 ULONG ux_hcd_ehci_hcor; 343 struct UX_EHCI_ED_STRUCT 344 **ux_hcd_ehci_frame_list; 345 ULONG *ux_hcd_ehci_base; 346 UINT ux_hcd_ehci_nb_root_hubs; 347 struct UX_EHCI_TD_STRUCT 348 *ux_hcd_ehci_done_head; 349 struct UX_EHCI_ED_STRUCT 350 *ux_hcd_ehci_ed_list; 351 struct UX_EHCI_TD_STRUCT 352 *ux_hcd_ehci_td_list; 353 struct UX_EHCI_FSISO_TD_STRUCT 354 *ux_hcd_ehci_fsiso_td_list; 355 struct UX_EHCI_HSISO_TD_STRUCT 356 *ux_hcd_ehci_hsiso_td_list; 357 struct UX_EHCI_ED_STRUCT 358 *ux_hcd_ehci_asynch_head_list; 359 struct UX_EHCI_ED_STRUCT 360 *ux_hcd_ehci_asynch_first_list; 361 struct UX_EHCI_ED_STRUCT 362 *ux_hcd_ehci_asynch_last_list; 363 struct UX_EHCI_HSISO_TD_STRUCT 364 *ux_hcd_ehci_hsiso_scan_list; 365 struct UX_EHCI_FSISO_TD_STRUCT 366 *ux_hcd_ehci_fsiso_scan_list; 367 struct UX_TRANSFER_STRUCT 368 *ux_hcd_ehci_iso_done_transfer_head; 369 struct UX_TRANSFER_STRUCT 370 *ux_hcd_ehci_iso_done_transfer_tail; 371 struct UX_EHCI_ED_STRUCT 372 *ux_hcd_ehci_interrupt_ed_list; 373 UX_MUTEX ux_hcd_ehci_periodic_mutex; 374 UX_SEMAPHORE ux_hcd_ehci_protect_semaphore; 375 UX_SEMAPHORE ux_hcd_ehci_doorbell_semaphore; 376 ULONG ux_hcd_ehci_frame_list_size; 377 ULONG ux_hcd_ehci_interrupt_count; 378 ULONG ux_hcd_ehci_embedded_tt; 379 } UX_HCD_EHCI; 380 381 382 /* Define EHCI ED structure. */ 383 384 typedef struct UX_EHCI_ED_STRUCT 385 { 386 387 struct UX_EHCI_ED_STRUCT 388 *ux_ehci_ed_queue_head; 389 ULONG ux_ehci_ed_cap0; 390 ULONG ux_ehci_ed_cap1; 391 struct UX_EHCI_TD_STRUCT 392 *ux_ehci_ed_current_td; 393 struct UX_EHCI_TD_STRUCT 394 *ux_ehci_ed_queue_element; 395 struct UX_EHCI_TD_STRUCT 396 *ux_ehci_ed_alternate_td; 397 ULONG ux_ehci_ed_state; 398 VOID *ux_ehci_ed_bp0; 399 VOID *ux_ehci_ed_bp1; 400 VOID *ux_ehci_ed_bp2; 401 VOID *ux_ehci_ed_bp3; 402 VOID *ux_ehci_ed_bp4; 403 /* 12 DWords, 48 bytes QH for controller end. */ 404 405 ULONG ux_ehci_ed_status; 406 struct UX_EHCI_ED_STRUCT 407 *ux_ehci_ed_next_ed; 408 struct UX_EHCI_ED_STRUCT 409 *ux_ehci_ed_previous_ed; 410 struct UX_EHCI_TD_STRUCT 411 *ux_ehci_ed_first_td; 412 struct UX_EHCI_TD_STRUCT 413 *ux_ehci_ed_last_td; 414 union { 415 struct { /* For anchor. */ 416 struct UX_EHCI_ED_STRUCT 417 *ux_ehci_ed_next_anchor; /* + 1 DWord. */ 418 USHORT ux_ehci_ed_microframe_load[8]; /* + 4 DWords. */ 419 UCHAR ux_ehci_ed_microframe_ssplit_count[8]; /* + 2 DWords. */ 420 } ANCHOR; 421 struct { /* As interrupt ED. */ 422 struct UX_EHCI_ED_STRUCT 423 *ux_ehci_ed_anchor; /* + 1 DWord. */ 424 struct UX_ENDPOINT_STRUCT 425 *ux_ehci_ed_endpoint; /* + 1 Dword. */ 426 } INTR; 427 struct { /* Space: 7 DWord. */ 428 ULONG ux_ehci_ed_reserved[7]; 429 } RESERVED; 430 } REF_AS; 431 /* 24 DWord aligned. */ 432 } UX_EHCI_ED; 433 434 435 /* Define EHCI ED bitmap. */ 436 437 #define UX_EHCI_QH_TYP_ITD 0u 438 #define UX_EHCI_QH_TYP_QH 2u 439 #define UX_EHCI_QH_TYP_SITD 4u 440 #define UX_EHCI_QH_TYP_FSTN 6u 441 442 #define UX_EHCI_QH_T 1u 443 444 #define UX_EHCI_QH_STATIC 0x80000000u 445 #define UX_EHCI_QH_SSPLIT_SCH_FULL_7 0x40000000u 446 #define UX_EHCI_QH_SSPLIT_SCH_FULL_6 0x20000000u 447 #define UX_EHCI_QH_SSPLIT_SCH_FULL_5 0x10000000u 448 #define UX_EHCI_QH_SSPLIT_SCH_FULL_4 0x08000000u 449 #define UX_EHCI_QH_SSPLIT_SCH_FULL_3 0x04000000u 450 #define UX_EHCI_QH_SSPLIT_SCH_FULL_2 0x02000000u 451 #define UX_EHCI_QH_SSPLIT_SCH_FULL_1 0x01000000u 452 #define UX_EHCI_QH_SSPLIT_SCH_FULL_0 0x00800000u 453 454 #define UX_EHCI_QH_MPS_LOC 16u 455 #define UX_EHCI_QH_MPS_MASK 0x07ff0000u 456 #define UX_EHCI_QH_NCR 0xf0000000u 457 #define UX_EHCI_QH_CEF 0x08000000u 458 #define UX_EHCI_QH_ED_AD_LOC 8u 459 #define UX_EHCI_QH_HBPM 0x40000000u 460 #define UX_EHCI_QH_HBPM_LOC 30u 461 #define UX_EHCI_QH_HEAD 0x00008000u 462 463 #define UX_EHCI_QH_HIGH_SPEED 0x00002000u 464 #define UX_EHCI_QH_LOW_SPEED 0x00001000u 465 466 #define UX_EHCI_QH_HUB_ADDR_LOC 16u 467 #define UX_EHCI_QH_PORT_NUMBER_LOC 23u 468 #define UX_EHCI_QH_MULT_LOC 30u 469 #define UX_EHCI_QH_MULT_MASK 0xc0000000u 470 #define UX_EHCI_QH_C_MASK 0x00001c00u 471 #define UX_EHCI_QH_IS_MASK 0x00000001u 472 473 #define UX_EHCI_QH_SMASK_MASK 0x000000FFu 474 #define UX_EHCI_QH_SMASK_0 0x00000001u 475 #define UX_EHCI_QH_SMASK_1 0x00000002u 476 #define UX_EHCI_QH_SMASK_2 0x00000004u 477 #define UX_EHCI_QH_SMASK_3 0x00000008u 478 #define UX_EHCI_QH_SMASK_4 0x00000010u 479 #define UX_EHCI_QH_SMASK_5 0x00000020u 480 #define UX_EHCI_QH_SMASK_6 0x00000040u 481 #define UX_EHCI_QH_SMASK_7 0x00000080u 482 483 #define UX_EHCI_QH_DTC 0x00004000u 484 #define UX_EHCI_QH_TOGGLE 0x80000000u 485 #define UX_EHCI_LINK_ADDRESS_MASK 0xfffffff0u 486 #define UX_EHCI_TOGGLE_0 0u 487 #define UX_EHCI_TOGGLE_1 0x80000000u 488 489 /* Define EHCI TD structure. */ 490 491 typedef struct UX_EHCI_TD_STRUCT 492 { 493 494 struct UX_EHCI_TD_STRUCT 495 *ux_ehci_td_link_pointer; 496 struct UX_EHCI_TD_STRUCT 497 *ux_ehci_td_alternate_link_pointer; 498 ULONG ux_ehci_td_control; 499 VOID *ux_ehci_td_bp0; 500 VOID *ux_ehci_td_bp1; 501 VOID *ux_ehci_td_bp2; 502 VOID *ux_ehci_td_bp3; 503 VOID *ux_ehci_td_bp4; 504 /* 8-DWords, 32-bytes qTD for controller. */ 505 struct UX_TRANSFER_STRUCT 506 *ux_ehci_td_transfer_request; 507 struct UX_EHCI_TD_STRUCT 508 *ux_ehci_td_next_td_transfer_request; 509 struct UX_EHCI_ED_STRUCT 510 *ux_ehci_td_ed; 511 ULONG ux_ehci_td_length; 512 ULONG ux_ehci_td_status; 513 ULONG ux_ehci_td_phase; 514 ULONG ux_ehci_td_reserved_2[2]; 515 /* 16-DWord aligned. */ 516 } UX_EHCI_TD; 517 518 519 /* Define EHCI TD bitmap. */ 520 521 #define UX_EHCI_TD_T 1u 522 #define UX_EHCI_TD_LG_LOC 16u 523 #define UX_EHCI_TD_LG_MASK 0x7fffu 524 #define UX_EHCI_TD_IOC 0x00008000u 525 #define UX_EHCI_TD_CERR 0x00000c00u 526 527 #define UX_EHCI_TD_PING 1u 528 #define UX_EHCI_TD_DO_COMPLETE_SPLIT 2u 529 #define UX_EHCI_TD_MISSED_MICRO_FRAMES 4u 530 #define UX_EHCI_TD_TRANSACTION_ERROR 8u 531 #define UX_EHCI_TD_BABBLE_DETECTED 0x10u 532 #define UX_EHCI_TD_DATA_BUFFER_ERROR 0x20u 533 #define UX_EHCI_TD_HALTED 0x40u 534 #define UX_EHCI_TD_ACTIVE 0x80u 535 536 #define UX_EHCI_PID_OUT 0x00000000u 537 #define UX_EHCI_PID_IN 0x00000100u 538 #define UX_EHCI_PID_SETUP 0x00000200u 539 #define UX_EHCI_PID_MASK 0x00000300u 540 541 #define UX_EHCI_TD_SETUP_PHASE 0x00010000u 542 #define UX_EHCI_TD_DATA_PHASE 0x00020000u 543 #define UX_EHCI_TD_STATUS_PHASE 0x00040000u 544 545 /* Define EHCI ISOCHRONOUS TD extension structure. */ 546 547 typedef struct UX_EHCI_HSISO_ED_STRUCT 548 { 549 struct UX_ENDPOINT_STRUCT 550 *ux_ehci_hsiso_ed_endpoint; 551 struct UX_EHCI_ED_STRUCT 552 *ux_ehci_hsiso_ed_anchor; 553 struct UX_TRANSFER_STRUCT 554 *ux_ehci_hsiso_ed_transfer_head; 555 struct UX_TRANSFER_STRUCT 556 *ux_ehci_hsiso_ed_transfer_tail; 557 struct UX_TRANSFER_STRUCT 558 *ux_ehci_hsiso_ed_transfer_first_new; 559 struct UX_EHCI_HSISO_TD_STRUCT 560 *ux_ehci_hsiso_ed_fr_td[4]; 561 UCHAR ux_ehci_hsiso_ed_frindex; /* 1st usable micro-frame. */ 562 UCHAR ux_ehci_hsiso_ed_frinterval; /* Micro-frame interval. */ 563 UCHAR ux_ehci_hsiso_ed_frinterval_shift; /* Shift for micro-frame interval. */ 564 UCHAR ux_ehci_hsiso_ed_nb_tds; 565 USHORT ux_ehci_hsiso_ed_frstart; /* Start micro-frame. */ 566 USHORT ux_ehci_hsiso_ed_frload; 567 USHORT ux_ehci_hsiso_ed_fr_hc; /* Micro-frame HC process count. */ 568 USHORT ux_ehci_hsiso_ed_fr_sw; /* Micro-frame SW load count. */ 569 } UX_EHCI_HSISO_ED; 570 571 /* Define EHCI ISOCHRONOUS TD structure. */ 572 573 typedef struct UX_EHCI_HSISO_TD_STRUCT 574 { 575 576 union UX_EHCI_PERIODIC_LINK_POINTER_UNION 577 ux_ehci_hsiso_td_next_lp; 578 ULONG ux_ehci_hsiso_td_control[8]; 579 VOID *ux_ehci_hsiso_td_bp[7]; 580 /* 16 DWords, 64-bytes iTD for controller end. */ 581 UCHAR ux_ehci_hsiso_td_status; 582 UCHAR ux_ehci_hsiso_td_frload; /* REQ load map. */ 583 USHORT ux_ehci_hsiso_td_max_trans_size; 584 union UX_EHCI_PERIODIC_LINK_POINTER_UNION 585 ux_ehci_hsiso_td_previous_lp; 586 struct UX_EHCI_HSISO_TD_STRUCT 587 *ux_ehci_hsiso_td_next_scan_td; 588 struct UX_EHCI_HSISO_TD_STRUCT 589 *ux_ehci_hsiso_td_previous_scan_td; 590 struct UX_TRANSFER_STRUCT 591 *ux_ehci_hsiso_td_fr_transfer[3]; 592 struct UX_EHCI_HSISO_ED_STRUCT 593 *ux_ehci_hsiso_td_ed; 594 /* 24 DWord aligned. */ 595 } UX_EHCI_HSISO_TD; 596 597 598 /* Next Link Pointer(LP). */ 599 600 #define UX_EHCI_HSISO_LP_MASK UX_EHCI_LP_MASK 601 602 #define UX_EHCI_HSISO_TYP_MASK UX_EHCI_TYP_MASK 603 #define UX_EHCI_HSISO_TYP_ITD UX_EHCI_TYP_ITD 604 #define UX_EHCI_HSISO_TYP_QH UX_EHCI_TYP_QH 605 #define UX_EHCI_HSISO_TYP_SITD UX_EHCI_TYP_SITD 606 #define UX_EHCI_HSISO_TYP_FSTN UX_EHCI_TYP_FSTN 607 608 #define UX_EHCI_HSISO_T UX_EHCI_T 609 610 /* Transaction Status and Control. */ 611 612 #define UX_EHCI_HSISO_STATUS_MASK 0xF0000000u 613 #define UX_EHCI_HSISO_STATUS_ACTIVE 0x80000000u 614 #define UX_EHCI_HSISO_STATUS_DATA_BUFFER_ERR 0x40000000u 615 #define UX_EHCI_HSISO_STATUS_BABBLE_DETECTED 0x20000000u 616 #define UX_EHCI_HSISO_STATUS_XACT_ERR 0x10000000u 617 618 #define UX_EHCI_HSISO_XACT_LENGTH_MASK 0x0FFF0000u 619 #define UX_EHCI_HSISO_XACT_LENGTH_SHIFT 16 620 #define UX_EHCI_HSISO_XACT_LENGTH_VALUE_MAX 0xC00 621 622 #define UX_EHCI_HSISO_IOC 0x00008000u 623 #define UX_EHCI_HSISO_IOC_SHIFT 15 624 625 #define UX_EHCI_HSISO_PG_MASK 0x00007000u 626 #define UX_EHCI_HSISO_PG_SHIFT 12 627 628 #define UX_EHCI_HSISO_XACT_OFFSET_MASK 0x00000FFFu 629 630 /* Buffer Page Pointer List. */ 631 632 #define UX_EHCI_HSISO_BP_MASK UX_EHCI_BP_MASK 633 634 /* BP0 */ 635 636 #define UX_EHCI_HSISO_ENDPT_MASK UX_EHCI_ENDPT_MASK 637 #define UX_EHCI_HSISO_ENDPT_SHIFT UX_EHCI_ENDPT_SHIFT 638 639 #define UX_EHCI_HSISO_DEVICE_ADDRESS_MASK UX_EHCI_DEVICE_ADDRESS_MASK 640 641 /* BP1 */ 642 643 #define UX_EHCI_HSISO_DIRECTION (0x1u << 11) 644 #define UX_EHCI_HSISO_DIRECTION_IN UX_EHCI_HSISO_DIRECTION 645 #define UX_EHCI_HSISO_DIRECTION_OUT 0 646 647 #define UX_EHCI_HSISO_MAX_PACKET_SIZE_MASK 0x000007FFu 648 #define UX_EHCI_HSISO_MAX_PACKET_SIZE_MAX 0x00000400 649 650 /* BP2 */ 651 652 #define UX_EHCI_HSISO_MULTI_MASK 0x00000003u 653 #define UX_EHCI_HSISO_MULTI_ONE 1 654 #define UX_EHCI_HSISO_MULTI_TWO 2 655 #define UX_EHCI_HSISO_MULTI_THREE 3 656 657 /* Define EHCI FS ISOCHRONOUS TD structure. */ 658 659 typedef struct UX_EHCI_FSISO_TD_STRUCT 660 { 661 union UX_EHCI_PERIODIC_LINK_POINTER_UNION 662 ux_ehci_fsiso_td_next_lp; 663 ULONG ux_ehci_fsiso_td_cap0; /* endpoint */ 664 ULONG ux_ehci_fsiso_td_cap1; /* uFrame schedule */ 665 ULONG ux_ehci_fsiso_td_state; 666 VOID *ux_ehci_fsiso_td_bp[2]; 667 VOID *ux_ehci_fsiso_td_back_pointer; 668 /* 7 DWords, 28-bytes siTD for controller end. */ 669 670 UCHAR ux_ehci_fsiso_td_status; 671 UCHAR ux_ehci_fsiso_td_frindex; 672 UCHAR ux_ehci_fsiso_td_nb_ed_tds; 673 UCHAR reserved[1]; 674 struct UX_ENDPOINT_STRUCT 675 *ux_ehci_fsiso_td_endpoint; 676 struct UX_TRANSFER_STRUCT 677 *ux_ehci_fsiso_td_transfer_head; 678 struct UX_TRANSFER_STRUCT 679 *ux_ehci_fsiso_td_transfer_tail; 680 union UX_EHCI_PERIODIC_LINK_POINTER_UNION 681 ux_ehci_fsiso_td_previous_lp; 682 struct UX_EHCI_FSISO_TD_STRUCT 683 *ux_ehci_fsiso_td_next_scan_td; 684 struct UX_EHCI_FSISO_TD_STRUCT 685 *ux_ehci_fsiso_td_previous_scan_td; 686 struct UX_EHCI_ED_STRUCT 687 *ux_ehci_fsiso_td_anchor; 688 struct UX_EHCI_TD_STRUCT 689 *ux_ehci_fsiso_td_next_ed_td; 690 /* 16-DWord aligned. */ 691 } UX_EHCI_FSISO_TD; 692 693 /* Next Link Pointer (LP). */ 694 695 #define UX_EHCI_FSISO_LP_MASK UX_EHCI_LP_MASK 696 697 #define UX_EHCI_FSISO_TYP_MASK UX_EHCI_TYP_MASK 698 #define UX_EHCI_FSISO_TYP_ITD UX_EHCI_TYP_ITD 699 #define UX_EHCI_FSISO_TYP_QH UX_EHCI_TYP_QH 700 #define UX_EHCI_FSISO_TYP_SITD UX_EHCI_TYP_SITD 701 #define UX_EHCI_FSISO_TYP_FSTN UX_EHCI_TYP_FSTN 702 703 #define UX_EHCI_FSISO_T UX_EHCI_T 704 705 /* Endpoint Capabilities/Characteristics. */ 706 707 #define UX_EHCI_FSISO_DIRECTION 0x80000000u 708 #define UX_EHCI_FSISO_DIRECTION_IN 0x80000000u 709 #define UX_EHCI_FSISO_DIRECTION_OUT 0x00000000 710 711 #define UX_EHCI_FSISO_PORT_NUMBER_MASK 0x7F000000u 712 #define UX_EHCI_FSISO_PORT_NUMBER_SHIFT 24 713 714 #define UX_EHCI_FSISO_HUB_ADDRESS_MASK 0x003F0000u 715 #define UX_EHCI_FSISO_HUB_ADDRESS_SHIFT 16 716 717 #define UX_EHCI_FSISO_ENDPT_MASK UX_EHCI_ENDPT_MASK 718 #define UX_EHCI_FSISO_ENDPT_SHIFT UX_EHCI_ENDPT_SHIFT 719 720 #define UX_EHCI_FSISO_DEVICE_ADDRESS_MASK UX_EHCI_DEVICE_ADDRESS_MASK 721 722 /* Micro-frame Schedule Control. */ 723 724 #define UX_EHCI_FSISO_UFRAME_CMASK_MASK UX_EHCI_CMASK_MASK 725 #define UX_EHCI_FSISO_UFRAME_CMASK_0 UX_EHCI_CMASK_0 726 #define UX_EHCI_FSISO_UFRAME_CMASK_1 UX_EHCI_CMASK_1 727 #define UX_EHCI_FSISO_UFRAME_CMASK_2 UX_EHCI_CMASK_2 728 #define UX_EHCI_FSISO_UFRAME_CMASK_3 UX_EHCI_CMASK_3 729 #define UX_EHCI_FSISO_UFRAME_CMASK_4 UX_EHCI_CMASK_4 730 #define UX_EHCI_FSISO_UFRAME_CMASK_5 UX_EHCI_CMASK_5 731 #define UX_EHCI_FSISO_UFRAME_CMASK_6 UX_EHCI_CMASK_6 732 #define UX_EHCI_FSISO_UFRAME_CMASK_7 UX_EHCI_CMASK_7 733 734 #define UX_EHCI_FSISO_UFRAME_SMASK_MASK UX_EHCI_SMASK_MASK 735 #define UX_EHCI_FSISO_UFRAME_SMASK_0 UX_EHCI_SMASK_0 736 #define UX_EHCI_FSISO_UFRAME_SMASK_1 UX_EHCI_SMASK_1 737 #define UX_EHCI_FSISO_UFRAME_SMASK_2 UX_EHCI_SMASK_2 738 #define UX_EHCI_FSISO_UFRAME_SMASK_3 UX_EHCI_SMASK_3 739 #define UX_EHCI_FSISO_UFRAME_SMASK_4 UX_EHCI_SMASK_4 740 #define UX_EHCI_FSISO_UFRAME_SMASK_5 UX_EHCI_SMASK_5 741 #define UX_EHCI_FSISO_UFRAME_SMASK_6 UX_EHCI_SMASK_6 742 #define UX_EHCI_FSISO_UFRAME_SMASK_7 UX_EHCI_SMASK_7 743 744 /* Transfer State. */ 745 746 /* Transfer Status and Control. */ 747 748 #define UX_EHCI_FSISO_IOC 0x80000000u 749 750 #define UX_EHCI_FSISO_P 0x40000000u 751 752 #define UX_EHCI_FSISO_TOTAL_BYTES_MASK 0x03FF0000u 753 #define UX_EHCI_FSISO_TOTAL_BYTES_SHIFT 16 754 #define UX_EHCI_FSISO_TOTAL_BYTES_MAX_VALUE 1023 755 756 #define UX_EHCI_FSISO_CPROMASK_MASK 0x0000FF00u 757 #define UX_EHCI_FSISO_CPROMASK_SHIFT 8 758 759 #define UX_EHCI_FSISO_STATUS_MASK 0x000000FFu 760 #define UX_EHCI_FSISO_STATUS_ACTIVE 0x00000080u 761 #define UX_EHCI_FSISO_STATUS_ERR 0x00000040u 762 #define UX_EHCI_FSISO_STATUS_DATA_BUFFER_ERR 0x00000020u 763 #define UX_EHCI_FSISO_STATUS_BABBLE_DETECTED 0x00000010u 764 #define UX_EHCI_FSISO_STATUS_XACTERR 0x00000008u 765 #define UX_EHCI_FSISO_STATUS_MISSED_MFRAME 0x00000004u 766 767 #define UX_EHCI_FSISO_STATUS_SPLIT_STATE_MASK 0x00000002u 768 #define UX_EHCI_FSISO_STATUS_SPLIT_STATE_DO_START 0x00000000u 769 #define UX_EHCI_FSISO_STATUS_SPLIT_STATE_DO_COMPLETE 0x00000002u 770 771 /* Buffer Page Pointer List. */ 772 773 #define UX_EHCI_FSISO_BP_MASK UX_EHCI_BP_MASK 774 775 /* BP0 */ 776 777 #define UX_EHCI_FSISO_CURRENT_OFFSET_MASK 0x00000FFFu 778 779 /* BP1 */ 780 781 #define UX_EHCI_FSISO_TP_MASK 0x0000000Cu 782 #define UX_EHCI_FSISO_TP_ALL 0x00000000u 783 #define UX_EHCI_FSISO_TP_BEGIN 0x00000004u 784 #define UX_EHCI_FSISO_TP_MID 0x00000008u 785 #define UX_EHCI_FSISO_TP_END 0x0000000Cu 786 787 #define UX_EHCI_FSISO_TCOUNT_MASK 0x00000007u 788 #define UX_EHCI_FSISO_TCOUNT_MAX 6 789 790 791 /* Define EHCI function prototypes. */ 792 793 void _ux_hcd_ehci_periodic_descriptor_link(VOID* prev, VOID* prev_next, VOID* next_prev, VOID* next); 794 UX_EHCI_TD *_ux_hcd_ehci_asynch_td_process(UX_EHCI_ED *ed, UX_EHCI_TD *td); 795 UX_EHCI_HSISO_TD *_ux_hcd_ehci_hsisochronous_tds_process(UX_HCD_EHCI *hcd_ehci, UX_EHCI_HSISO_TD* itd); 796 UX_EHCI_FSISO_TD *_ux_hcd_ehci_fsisochronous_tds_process(UX_HCD_EHCI *hcd_ehci, UX_EHCI_FSISO_TD* sitd); 797 UINT _ux_hcd_ehci_asynchronous_endpoint_create(UX_HCD_EHCI *hcd_ehci, UX_ENDPOINT *endpoint); 798 UINT _ux_hcd_ehci_asynchronous_endpoint_destroy(UX_HCD_EHCI *hcd_ehci, UX_ENDPOINT *endpoint); 799 UINT _ux_hcd_ehci_controller_disable(UX_HCD_EHCI *hcd_ehci); 800 VOID _ux_hcd_ehci_done_queue_process(UX_HCD_EHCI *hcd_ehci); 801 VOID _ux_hcd_ehci_door_bell_wait(UX_HCD_EHCI *hcd_ehci); 802 UINT _ux_hcd_ehci_ed_clean(UX_EHCI_ED *ed); 803 UX_EHCI_ED *_ux_hcd_ehci_ed_obtain(UX_HCD_EHCI *hcd_ehci); 804 UINT _ux_hcd_ehci_endpoint_reset(UX_HCD_EHCI *hcd_ehci, UX_ENDPOINT *endpoint); 805 UINT _ux_hcd_ehci_entry(UX_HCD *hcd, UINT function, VOID *parameter); 806 UINT _ux_hcd_ehci_frame_number_get(UX_HCD_EHCI *hcd_ehci, ULONG *frame_number); 807 VOID _ux_hcd_ehci_frame_number_set(UX_HCD_EHCI *hcd_ehci, ULONG frame_number); 808 UX_EHCI_FSISO_TD *_ux_hcd_ehci_fsisochronous_td_obtain(UX_HCD_EHCI *hcd_ehci); 809 UX_EHCI_HSISO_TD *_ux_hcd_ehci_hsisochronous_td_obtain(UX_HCD_EHCI *hcd_ehci); 810 UINT _ux_hcd_ehci_initialize(UX_HCD *hcd); 811 UINT _ux_hcd_ehci_interrupt_endpoint_create(UX_HCD_EHCI *hcd_ehci, UX_ENDPOINT *endpoint); 812 UINT _ux_hcd_ehci_interrupt_endpoint_destroy(UX_HCD_EHCI *hcd_ehci, UX_ENDPOINT *endpoint); 813 VOID _ux_hcd_ehci_interrupt_handler(VOID); 814 UINT _ux_hcd_ehci_isochronous_endpoint_create(UX_HCD_EHCI *hcd_ehci, UX_ENDPOINT *endpoint); 815 UINT _ux_hcd_ehci_isochronous_endpoint_destroy(UX_HCD_EHCI *hcd_ehci, UX_ENDPOINT *endpoint); 816 UX_EHCI_ED *_ux_hcd_ehci_least_traffic_list_get(UX_HCD_EHCI *hcd_ehci, ULONG microframe_load[8], ULONG microframe_ssplit_count[8]); 817 UX_EHCI_ED *_ux_hcd_ehci_poll_rate_entry_get(UX_HCD_EHCI *hcd_ehci, UX_EHCI_ED *ed_list, ULONG poll_depth); 818 VOID _ux_hcd_ehci_next_td_clean(UX_EHCI_TD *td); 819 UINT _ux_hcd_ehci_periodic_tree_create(UX_HCD_EHCI *hcd_ehci); 820 UINT _ux_hcd_ehci_port_disable(UX_HCD_EHCI *hcd_ehci, ULONG port_index); 821 UINT _ux_hcd_ehci_port_reset(UX_HCD_EHCI *hcd_ehci, ULONG port_index); 822 UINT _ux_hcd_ehci_port_resume(UX_HCD_EHCI *hcd_ehci, UINT port_index); 823 ULONG _ux_hcd_ehci_port_status_get(UX_HCD_EHCI *hcd_ehci, ULONG port_index); 824 UINT _ux_hcd_ehci_port_suspend(UX_HCD_EHCI *hcd_ehci, ULONG port_index); 825 UINT _ux_hcd_ehci_power_down_port(UX_HCD_EHCI *hcd_ehci, ULONG port_index); 826 UINT _ux_hcd_ehci_power_on_port(UX_HCD_EHCI *hcd_ehci, ULONG port_index); 827 VOID _ux_hcd_ehci_power_root_hubs(UX_HCD_EHCI *hcd_ehci); 828 ULONG _ux_hcd_ehci_register_read(UX_HCD_EHCI *hcd_ehci, ULONG ehci_register); 829 VOID _ux_hcd_ehci_register_write(UX_HCD_EHCI *hcd_ehci, ULONG ehci_register, ULONG value); 830 UX_EHCI_TD *_ux_hcd_ehci_regular_td_obtain(UX_HCD_EHCI *hcd_ehci); 831 UINT _ux_hcd_ehci_request_bulk_transfer(UX_HCD_EHCI *hcd_ehci, UX_TRANSFER *transfer_request); 832 UINT _ux_hcd_ehci_request_control_transfer(UX_HCD_EHCI *hcd_ehci, UX_TRANSFER *transfer_request); 833 UINT _ux_hcd_ehci_request_interrupt_transfer(UX_HCD_EHCI *hcd_ehci, UX_TRANSFER *transfer_request); 834 UINT _ux_hcd_ehci_request_isochronous_transfer(UX_HCD_EHCI *hcd_ehci, UX_TRANSFER *transfer_request); 835 UINT _ux_hcd_ehci_request_transfer(UX_HCD_EHCI *hcd_ehci, UX_TRANSFER *transfer_request); 836 UINT _ux_hcd_ehci_request_transfer_add(UX_HCD_EHCI *hcd_ehci, UX_EHCI_ED *ed, ULONG phase, ULONG pid, 837 ULONG toggle, UCHAR * buffer_address, ULONG buffer_length, UX_TRANSFER *transfer_request); 838 UINT _ux_hcd_ehci_transfer_abort(UX_HCD_EHCI *hcd_ehci,UX_TRANSFER *transfer_request); 839 VOID _ux_hcd_ehci_transfer_request_process(UX_TRANSFER *transfer_request); 840 841 #define ux_hcd_ehci_initialize _ux_hcd_ehci_initialize 842 #define ux_hcd_ehci_interrupt_handler _ux_hcd_ehci_interrupt_handler 843 844 /* Determine if a C++ compiler is being used. If so, complete the standard 845 C conditional started above. */ 846 #ifdef __cplusplus 847 } 848 #endif 849 850 #endif 851 852
