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/ThreadX-v6.4.1/ports_smp/cortex_a9_smp/ac5/src/
Dtx_thread_smp_protection_wait_list_macros.h58 LDR r5, [r4] ; Get the value of the head variable
61 ADD r5, r5, #1 ; Increment the head variable
69 CMP r5, r3 ; Compare the head to it variable
74 EOR r5, r5, r5 ; We're at the max. Set it to zero variable
80 STR r5, [r4] ; Store the new head variable
146 LDR r5, =_tx_thread_smp_protect_wait_list ; Get the address of the list variable
154 LDR r5, =_tx_thread_smp_protect_wait_list_size ; Load max cores address variable
155 LDR r5, [r5] ; Load max cores value variable
156 CMP r4, r5 ; Compare max cores to tail variable
/ThreadX-v6.4.1/ports_smp/cortex_a5_smp/ac5/src/
Dtx_thread_smp_protection_wait_list_macros.h58 LDR r5, [r4] ; Get the value of the head variable
61 ADD r5, r5, #1 ; Increment the head variable
69 CMP r5, r3 ; Compare the head to it variable
74 EOR r5, r5, r5 ; We're at the max. Set it to zero variable
80 STR r5, [r4] ; Store the new head variable
146 LDR r5, =_tx_thread_smp_protect_wait_list ; Get the address of the list variable
154 LDR r5, =_tx_thread_smp_protect_wait_list_size ; Load max cores address variable
155 LDR r5, [r5] ; Load max cores value variable
156 CMP r4, r5 ; Compare max cores to tail variable
/ThreadX-v6.4.1/ports_smp/cortex_a7_smp/ac5/src/
Dtx_thread_smp_protection_wait_list_macros.h58 LDR r5, [r4] ; Get the value of the head variable
61 ADD r5, r5, #1 ; Increment the head variable
69 CMP r5, r3 ; Compare the head to it variable
74 EOR r5, r5, r5 ; We're at the max. Set it to zero variable
80 STR r5, [r4] ; Store the new head variable
146 LDR r5, =_tx_thread_smp_protect_wait_list ; Get the address of the list variable
154 LDR r5, =_tx_thread_smp_protect_wait_list_size ; Load max cores address variable
155 LDR r5, [r5] ; Load max cores value variable
156 CMP r4, r5 ; Compare max cores to tail variable