| /ThreadX-v6.4.1/ports_smp/cortex_a9_smp/ac5/src/ |
| D | tx_thread_smp_protection_wait_list_macros.h | 33 LDR r3, [r2, #12] ; Pickup ownership count variable 34 ADD r3, r3, #1 ; Increment ownership count variable 35 STR r3, [r2, #12] ; Store ownership count variable 41 ADD r4, r3, r4 ; Build index into the current thread array variable 42 LDR r3, [r4] ; Pickup current thread for this core variable 56 MOV r3, #0xFFFFFFFF ; Build the invalid core value variable 60 STR r3, [r6, r5, LSL #2] ; Store the invalid core value variable 67 LDR r3, =_tx_thread_smp_protect_wait_list_size ; Load address of core list size variable 68 LDR r3, [r3] ; Load the max cores value variable 69 CMP r5, r3 ; Compare the head to it variable [all …]
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| /ThreadX-v6.4.1/ports_smp/cortex_a7_smp/ac5/src/ |
| D | tx_thread_smp_protection_wait_list_macros.h | 33 LDR r3, [r2, #12] ; Pickup ownership count variable 34 ADD r3, r3, #1 ; Increment ownership count variable 35 STR r3, [r2, #12] ; Store ownership count variable 41 ADD r4, r3, r4 ; Build index into the current thread array variable 42 LDR r3, [r4] ; Pickup current thread for this core variable 56 MOV r3, #0xFFFFFFFF ; Build the invalid core value variable 60 STR r3, [r6, r5, LSL #2] ; Store the invalid core value variable 67 LDR r3, =_tx_thread_smp_protect_wait_list_size ; Load address of core list size variable 68 LDR r3, [r3] ; Load the max cores value variable 69 CMP r5, r3 ; Compare the head to it variable [all …]
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| /ThreadX-v6.4.1/ports_smp/cortex_a5_smp/ac5/src/ |
| D | tx_thread_smp_protection_wait_list_macros.h | 33 LDR r3, [r2, #12] ; Pickup ownership count variable 34 ADD r3, r3, #1 ; Increment ownership count variable 35 STR r3, [r2, #12] ; Store ownership count variable 41 ADD r4, r3, r4 ; Build index into the current thread array variable 42 LDR r3, [r4] ; Pickup current thread for this core variable 56 MOV r3, #0xFFFFFFFF ; Build the invalid core value variable 60 STR r3, [r6, r5, LSL #2] ; Store the invalid core value variable 67 LDR r3, =_tx_thread_smp_protect_wait_list_size ; Load address of core list size variable 68 LDR r3, [r3] ; Load the max cores value variable 69 CMP r5, r3 ; Compare the head to it variable [all …]
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