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/ThreadX-v6.4.1/ports_smp/cortex_a9_smp/ac5/src/
Dtx_thread_smp_protection_wait_list_macros.h28 STR r1, [r2, #8] ; Store this core variable
39 LSL r3, r1, #2 ; Build offset to array indexes variable
101 LDR r1, =_tx_thread_smp_protect_wait_list_lock_protect_in_force variable
147 STR r1, [r5, r4, LSL #2] ; Store the new core value variable
188 EOR r1, r1, r1 ; Clear for 'core_index' variable
206 ADD r1, r1, #1 ; Increment cur index variable
233 CMP r1, r2 ; Compare cur index and tail variable
238 MOV r2, r1 ; Move current index to next index register variable
265 MOV r1, r2 variable
278 LDR r1, [r0] ; Load tail value variable
[all …]
/ThreadX-v6.4.1/ports_smp/cortex_a5_smp/ac5/src/
Dtx_thread_smp_protection_wait_list_macros.h28 STR r1, [r2, #8] ; Store this core variable
39 LSL r3, r1, #2 ; Build offset to array indexes variable
101 LDR r1, =_tx_thread_smp_protect_wait_list_lock_protect_in_force variable
147 STR r1, [r5, r4, LSL #2] ; Store the new core value variable
188 EOR r1, r1, r1 ; Clear for 'core_index' variable
206 ADD r1, r1, #1 ; Increment cur index variable
233 CMP r1, r2 ; Compare cur index and tail variable
238 MOV r2, r1 ; Move current index to next index register variable
265 MOV r1, r2 variable
278 LDR r1, [r0] ; Load tail value variable
[all …]
/ThreadX-v6.4.1/ports_smp/cortex_a7_smp/ac5/src/
Dtx_thread_smp_protection_wait_list_macros.h28 STR r1, [r2, #8] ; Store this core variable
39 LSL r3, r1, #2 ; Build offset to array indexes variable
101 LDR r1, =_tx_thread_smp_protect_wait_list_lock_protect_in_force variable
147 STR r1, [r5, r4, LSL #2] ; Store the new core value variable
188 EOR r1, r1, r1 ; Clear for 'core_index' variable
206 ADD r1, r1, #1 ; Increment cur index variable
233 CMP r1, r2 ; Compare cur index and tail variable
238 MOV r2, r1 ; Move current index to next index register variable
265 MOV r1, r2 variable
278 LDR r1, [r0] ; Load tail value variable
[all …]