1/**************************************************************************/
2/*   Copyright (c) Cadence Design Systems, Inc.                           */
3/*                                                                        */
4/* Permission is hereby granted, free of charge, to any person obtaining  */
5/* a copy of this software and associated documentation files (the        */
6/* "Software"), to deal in the Software without restriction, including    */
7/* without limitation the rights to use, copy, modify, merge, publish,    */
8/* distribute, sublicense, and/or sell copies of the Software, and to     */
9/* permit persons to whom the Software is furnished to do so, subject to  */
10/* the following conditions:                                              */
11/*                                                                        */
12/* The above copyright notice and this permission notice shall be         */
13/* included in all copies or substantial portions of the Software.        */
14/*                                                                        */
15/* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,        */
16/* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF     */
17/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. */
18/* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY   */
19/* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,   */
20/* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE      */
21/* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.                 */
22/**************************************************************************/
23
24/**************************************************************************/
25/*                                                                        */
26/*  DESCRIPTION                                                           */
27/*                                                                        */
28/*    Xtensa interrupt handling data and assembly routines.               */
29/*    Also see xtensa_intr.c.                                             */
30/*                                                                        */
31/*  RELEASE HISTORY                                                       */
32/*                                                                        */
33/*    DATE              NAME                      DESCRIPTION             */
34/*                                                                        */
35/*  12-31-2020     Cadence Design Systems   Initial Version 6.1.3         */
36/*                                                                        */
37/**************************************************************************/
38
39
40#include <xtensa/hal.h>
41#include <xtensa/config/core.h>
42
43#include "tx_port.h"
44#include "xtensa_context.h"
45
46#if XCHAL_HAVE_INTERRUPTS
47
48/*
49-------------------------------------------------------------------------------
50  INTENABLE virtualization information.
51-------------------------------------------------------------------------------
52*/
53
54#if XCHAL_HAVE_XEA2
55
56    .data
57    .global _xt_intdata
58    .align  8
59_xt_intdata:
60    .global _xt_intenable
61    .type   _xt_intenable,@object
62    .size   _xt_intenable,4
63    .global _xt_vpri_mask
64    .type   _xt_vpri_mask,@object
65    .size   _xt_vpri_mask,4
66
67_xt_intenable:     .word   0             /* Virtual INTENABLE     */
68_xt_vpri_mask:     .word   0xFFFFFFFF    /* Virtual priority mask */
69
70#endif
71
72/*
73-------------------------------------------------------------------------------
74  System interrupt stack.
75-------------------------------------------------------------------------------
76*/
77
78#if (XCHAL_HAVE_XEA2 || XCHAL_HAVE_ISB)
79    .data
80#else
81    .section    .intr.top, "aw"
82#endif
83
84    .global _xt_interrupt_stack
85    .global _xt_interrupt_stack_top
86    .align  16
87
88_xt_interrupt_stack:
89    .space  TX_SYSTEM_STACK_SIZE
90_xt_interrupt_stack_top:
91
92
93/*
94-------------------------------------------------------------------------------
95  Table of C-callable interrupt handlers for each interrupt. For XEA2 configs,
96  not all slots can be filled, because interrupts at level > EXCM_LEVEL will
97  not be dispatched to a C handler by default.
98-------------------------------------------------------------------------------
99*/
100
101#if (XCHAL_HAVE_XEA2 || XCHAL_HAVE_ISB)
102    .data
103#else
104    .section    .intr.data, "aw"
105#endif
106
107    .global _xt_interrupt_table
108    .align  16
109
110_xt_interrupt_table:
111
112/*
113-------------------------------------------------------------------------------
114  If using the interrupt wrapper, make the first entry in the interrupt table
115  point to the wrapper (XEA3) or leave it empty (XEA2).
116-------------------------------------------------------------------------------
117*/
118#if XCHAL_HAVE_XEA3
119    .word   xt_interrupt_wrapper
120    .word   0
121#elif XT_USE_INT_WRAPPER
122    .word   0
123    .word   0
124#endif
125
126    .set    i, 0
127    .rept   XCHAL_NUM_INTERRUPTS
128    .word   xt_unhandled_interrupt      /* handler address               */
129    .word   i                           /* handler arg (default: intnum) */
130    .set    i, i+1
131    .endr
132
133#endif /* XCHAL_HAVE_INTERRUPTS */
134
135
136#if XCHAL_HAVE_EXCEPTIONS
137
138/*
139-------------------------------------------------------------------------------
140  Table of C-callable exception handlers for each exception. Note that not all
141  slots will be active, because some exceptions (e.g. coprocessor exceptions)
142  are always handled by the OS and cannot be hooked by user handlers.
143-------------------------------------------------------------------------------
144*/
145
146    .data
147    .global _xt_exception_table
148    .align  4
149
150_xt_exception_table:
151    .rept   XCHAL_EXCCAUSE_NUM
152    .word   xt_unhandled_exception    /* handler address */
153    .endr
154
155#endif
156
157