1 /**************************************************************************/
2 /* */
3 /* Copyright (c) Microsoft Corporation. All rights reserved. */
4 /* */
5 /* This software is licensed under the Microsoft Software License */
6 /* Terms for Microsoft Azure RTOS. Full text of the license can be */
7 /* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
8 /* and in the root directory of this software. */
9 /* */
10 /**************************************************************************/
11
12
13 /**************************************************************************/
14 /**************************************************************************/
15 /** */
16 /** USBX Component */
17 /** */
18 /** EHCI Controller Driver */
19 /** */
20 /**************************************************************************/
21 /**************************************************************************/
22
23
24 /* Include necessary system files. */
25
26 #define UX_SOURCE_CODE
27
28 #include "ux_api.h"
29 #include "ux_hcd_ehci.h"
30 #include "ux_host_stack.h"
31
32
33 /* EHCI HCD extension for host mode select. */
34 #ifndef UX_HCD_EHCI_EXT_USBPHY_HIGHSPEED_MODE_SET
35
36 #if defined(K66)
37
38 #define UX_EHCI_USBPHY_CTRL_K66 0x400A2000
39 #define UX_EHCI_USBPHY_CTRL_SET_BIT1 ((*(volatile ULONG *)(UX_EHCI_USBPHY_CTRL_K66 + 0x34)) = 0x02)
40 #define UX_EHCI_USBPHY_CTRL_CLEAR_BIT1 ((*(volatile ULONG *)(UX_EHCI_USBPHY_CTRL_K66 + 0x38)) = 0x02)
41
42 #define UX_HCD_EHCI_EXT_USBPHY_HIGHSPEED_MODE_SET(hcd_ehci, on_off) do \
43 { \
44 if (on_off) \
45 UX_EHCI_USBPHY_CTRL_SET_BIT1; \
46 else \
47 UX_EHCI_USBPHY_CTRL_CLEAR_BIT1; \
48 } while(0)
49
50 #elif defined(IMX6UL) || defined(MIMXRT)
51
52 #if defined(IMX6UL)
53 #define UX_EHCI_USBPHY1 (0x020C9000)
54 #define UX_EHCI_USBPHY2 (0x020CA000)
55 #define UX_EHCI_BASE1 (0x02184100)
56 #define UX_EHCI_BASE2 (0x02184300)
57 #elif defined(MIMXRT)
58 #define UX_EHCI_USBPHY1 (0x400D9000u)
59 #define UX_EHCI_USBPHY2 (0x400DA000u)
60 #define UX_EHCI_BASE1 (0x402E0100u)
61 #define UX_EHCI_BASE2 (0x402E0300u)
62 #endif
63
64 #define UX_EHCI_USBPHY_CTRL_SET_BIT1(base) ((*(volatile ULONG *) ( base + 0x34)) = 0x02)
65 #define UX_EHCI_USBPHY_CTRL_CLEAR_BIT1(base) ((*(volatile ULONG *) ( base + 0x38)) = 0x02)
66
67 #define UX_HCD_EHCI_EXT_USBPHY_HIGHSPEED_MODE_SET(hcd_ehci, on_off) do \
68 { \
69 ULONG base; \
70 if ((ULONG)hcd_ehci -> ux_hcd_ehci_base == UX_EHCI_BASE1) \
71 base = (UX_EHCI_USBPHY1); \
72 else \
73 base = (UX_EHCI_USBPHY2); \
74 if (on_off) \
75 UX_EHCI_USBPHY_CTRL_SET_BIT1(base); \
76 else \
77 UX_EHCI_USBPHY_CTRL_CLEAR_BIT1(base); \
78 } while(0)
79
80 #else
81 #define UX_HCD_EHCI_EXT_USBPHY_HIGHSPEED_MODE_SET(hcd_ehci, on_off)
82 #endif
83
84 #endif /* ifndef UX_HCD_EHCI_EXT_USBPHY_HIGHSPEED_MODE_SET */
85
86 /**************************************************************************/
87 /* */
88 /* FUNCTION RELEASE */
89 /* */
90 /* _ux_hcd_ehci_port_status_get PORTABLE C */
91 /* 6.1.8 */
92 /* AUTHOR */
93 /* */
94 /* Chaoqiong Xiao, Microsoft Corporation */
95 /* */
96 /* DESCRIPTION */
97 /* */
98 /* This function will return the status for each port attached to the */
99 /* root HUB. */
100 /* */
101 /* INPUT */
102 /* */
103 /* hcd_ehci Pointer to EHCI controller */
104 /* port_index Port index to get status for */
105 /* */
106 /* OUTPUT */
107 /* */
108 /* Port Status */
109 /* */
110 /* Status of the root hub port with the following format: */
111 /* */
112 /* bit 0 device connection status */
113 /* if 0 : no device connected */
114 /* if 1 : device connected to the port */
115 /* bit 1 port enable status */
116 /* if 0 : port disabled */
117 /* if 1 : port enabled */
118 /* bit 2 port suspend status */
119 /* if 0 : port is not suspended */
120 /* if 1 : port is suspended */
121 /* bit 3 port overcurrent status */
122 /* if 0 : port has no overcurrent condition */
123 /* if 1 : port has overcurrent condition */
124 /* bit 4 port reset status */
125 /* if 0 : port is not in reset */
126 /* if 1 : port is in reset */
127 /* bit 5 port power status */
128 /* if 0 : port power is off */
129 /* if 1 : port power is on */
130 /* bit 6-7 device attached speed */
131 /* if 00 : low speed device attached */
132 /* if 01 : full speed device attached */
133 /* if 10 : high speed device attached */
134 /* CALLS */
135 /* */
136 /* _ux_hcd_ehci_register_read Read EHCI register */
137 /* */
138 /* CALLED BY */
139 /* */
140 /* EHCI Controller Driver */
141 /* */
142 /* RELEASE HISTORY */
143 /* */
144 /* DATE NAME DESCRIPTION */
145 /* */
146 /* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */
147 /* 09-30-2020 Chaoqiong Xiao Modified comment(s), */
148 /* fixed NXP register base, */
149 /* resulting in version 6.1 */
150 /* 08-02-2021 Wen Wang Modified comment(s), */
151 /* fixed spelling error, */
152 /* resulting in version 6.1.8 */
153 /* */
154 /**************************************************************************/
_ux_hcd_ehci_port_status_get(UX_HCD_EHCI * hcd_ehci,ULONG port_index)155 ULONG _ux_hcd_ehci_port_status_get(UX_HCD_EHCI *hcd_ehci, ULONG port_index)
156 {
157
158 ULONG ehci_register_port_status;
159 ULONG port_status;
160
161
162 /* Check to see if this port is valid on this controller. */
163 if (hcd_ehci -> ux_hcd_ehci_nb_root_hubs < port_index)
164 {
165
166 /* Error trap. */
167 _ux_system_error_handler(UX_SYSTEM_LEVEL_THREAD, UX_SYSTEM_CONTEXT_HCD, UX_PORT_INDEX_UNKNOWN);
168
169 /* If trace is enabled, insert this event into the trace buffer. */
170 UX_TRACE_IN_LINE_INSERT(UX_TRACE_ERROR, UX_PORT_INDEX_UNKNOWN, port_index, 0, 0, UX_TRACE_ERRORS, 0, 0)
171
172 return(UX_PORT_INDEX_UNKNOWN);
173 }
174
175 /* The port is valid, build the status mask for this port. This function
176 returns a controller agnostic bit field. */
177 port_status = 0;
178 ehci_register_port_status = _ux_hcd_ehci_register_read(hcd_ehci, EHCI_HCOR_PORT_SC + port_index);
179
180 /* Device Connection Status. */
181 if (ehci_register_port_status & EHCI_HC_PS_CCS)
182 port_status |= UX_PS_CCS;
183 else
184 {
185
186 /* When disconnected PHY does not know speed. */
187 UX_HCD_EHCI_EXT_USBPHY_HIGHSPEED_MODE_SET(hcd_ehci, UX_FALSE);
188 }
189
190 /* Port Enable Status. */
191 if (ehci_register_port_status & EHCI_HC_PS_PE)
192 port_status |= UX_PS_PES;
193
194 /* Port Suspend Status. */
195 if (ehci_register_port_status & EHCI_HC_PS_SUSPEND)
196 {
197 port_status |= UX_PS_PSS;
198
199 /* When suspend put PHY in normal to avoid wrong disconnect status. */
200 UX_HCD_EHCI_EXT_USBPHY_HIGHSPEED_MODE_SET(hcd_ehci, UX_FALSE);
201 }
202
203 /* Port Overcurrent Status. */
204 if (ehci_register_port_status & EHCI_HC_PS_OCC)
205 port_status |= UX_PS_POCI;
206
207 /* Port Reset Status. */
208 if (ehci_register_port_status & EHCI_HC_PS_PR)
209 port_status |= UX_PS_PRS;
210
211 /* Port Power Status. */
212 if (ehci_register_port_status & EHCI_HC_PS_PP)
213 port_status |= UX_PS_PPS;
214
215 /* Port Device Attached speed. This field is valid only if the CCS bit is active.
216 Only EHCI high speed devices are meaningful in a regular EHCI controller.
217 In embedded EHCI with built-in TTs some bits reflect the true speed of
218 the device behind the TT. */
219 if (ehci_register_port_status & EHCI_HC_PS_CCS)
220 {
221 /* Check for EHCI with embedded TT. */
222 if (hcd_ehci -> ux_hcd_ehci_embedded_tt == UX_TRUE)
223 {
224
225 /* Isolate speed from the non EHCI compliant POTSC bits. */
226 switch (ehci_register_port_status & EHCI_HC_PS_EMBEDDED_TT_SPEED_MASK)
227 {
228
229 case EHCI_HC_PS_EMBEDDED_TT_SPEED_FULL :
230
231 /* Full speed. */
232 port_status |= UX_PS_DS_FS;
233 break;
234
235 case EHCI_HC_PS_EMBEDDED_TT_SPEED_LOW :
236
237 /* Low speed. */
238 port_status |= UX_PS_DS_LS;
239 break;
240
241 case EHCI_HC_PS_EMBEDDED_TT_SPEED_HIGH :
242
243 /* High speed. */
244 port_status |= UX_PS_DS_HS;
245 break;
246
247 }
248 }
249 else
250
251 /* No embedded TT. Fall back to default HS. */
252 port_status |= UX_PS_DS_HS;
253 }
254
255 /* Return port status. */
256 return(port_status);
257 }
258
259
