1 2 /**************************************************************************/ 3 /* Copyright (c) Cadence Design Systems, Inc. */ 4 /* */ 5 /* Permission is hereby granted, free of charge, to any person obtaining */ 6 /* a copy of this software and associated documentation files (the */ 7 /* "Software"), to deal in the Software without restriction, including */ 8 /* without limitation the rights to use, copy, modify, merge, publish, */ 9 /* distribute, sublicense, and/or sell copies of the Software, and to */ 10 /* permit persons to whom the Software is furnished to do so, subject to */ 11 /* the following conditions: */ 12 /* */ 13 /* The above copyright notice and this permission notice shall be */ 14 /* included in all copies or substantial portions of the Software. */ 15 /* */ 16 /* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, */ 17 /* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF */ 18 /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. */ 19 /* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY */ 20 /* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, */ 21 /* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE */ 22 /* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ 23 /**************************************************************************/ 24 25 /************************************************************************** 26 27 XTENSA CONTEXT FRAMES AND MACROS FOR RTOS ASSEMBLER SOURCES 28 29 This header contains definitions and macros for use primarily by Xtensa 30 RTOS assembly source files. It includes and uses the Xtensa hardware 31 abstraction layer (HAL) to deal with config specifics. It may also be 32 included in C source files. 33 34 NOTE: The Xtensa architecture requires stack pointer alignment to 16 bytes. 35 36 ***************************************************************************/ 37 38 #ifndef XTENSA_CONTEXT_H 39 #define XTENSA_CONTEXT_H 40 41 #ifdef __ASSEMBLER__ 42 #include <xtensa/coreasm.h> 43 #endif 44 45 #include <xtensa/config/tie.h> 46 #include <xtensa/corebits.h> 47 #include <xtensa/config/system.h> 48 49 #if defined (__ASSEMBLER__) 50 #include "tx_api_asm.h" 51 #endif 52 53 54 /* Align a value up to nearest n-byte boundary, where n is a power of 2. */ 55 #define ALIGNUP(n, val) (((val) + (n)-1) & -(n)) 56 57 58 /* 59 ------------------------------------------------------------------------------- 60 Macros that help define structures for both C and assembler. 61 ------------------------------------------------------------------------------- 62 */ 63 #if defined(_ASMLANGUAGE) || defined(__ASSEMBLER__) 64 65 #define XSTRUCT_BEGIN .pushsection .text; .struct 0 66 #define XSTRUCT_FIELD(ctype,size,asname,name) asname: .space size 67 #define XSTRUCT_AFIELD(ctype,size,asname,name,n) asname: .space (size)*(n) 68 #define XSTRUCT_END(sname) sname##Size:; .popsection 69 70 #else 71 72 #define XSTRUCT_BEGIN typedef struct { 73 #define XSTRUCT_FIELD(ctype,size,asname,name) ctype name; 74 #define XSTRUCT_AFIELD(ctype,size,asname,name,n) ctype name[n]; 75 #define XSTRUCT_END(sname) } sname; 76 77 #endif //_ASMLANGUAGE || __ASSEMBLER__ 78 79 80 /* 81 ------------------------------------------------------------------------------- 82 INTERRUPT/EXCEPTION STACK FRAME FOR A THREAD OR NESTED INTERRUPT 83 84 A stack frame of this structure is allocated for any interrupt or exception. 85 It goes on the current stack. If the RTOS has a system stack for handling 86 interrupts, every thread stack must allow space for just one interrupt stack 87 frame, then nested interrupt stack frames go on the system stack. 88 89 The frame includes basic registers (explicit) and "extra" registers introduced 90 by user TIE or the use of the MAC16 option in the user's Xtensa config. 91 The frame size is minimized by omitting regs not applicable to user's config. 92 93 For Windowed ABI, this stack frame includes the interruptee's base save area, 94 another base save area to manage gcc nested functions, and a little temporary 95 space to help manage the spilling of the register windows. 96 ------------------------------------------------------------------------------- 97 */ 98 99 #if XCHAL_HAVE_XEA2 100 101 XSTRUCT_BEGIN 102 XSTRUCT_FIELD (long, 4, XT_STK_EXIT, exit) /* exit point for dispatch */ 103 XSTRUCT_FIELD (long, 4, XT_STK_PC, pc) /* return PC */ 104 XSTRUCT_FIELD (long, 4, XT_STK_PS, ps) /* return PS */ 105 XSTRUCT_FIELD (long, 4, XT_STK_A0, a0) 106 XSTRUCT_FIELD (long, 4, XT_STK_A1, a1) /* stack pointer before interrupt */ 107 XSTRUCT_FIELD (long, 4, XT_STK_A2, a2) 108 XSTRUCT_FIELD (long, 4, XT_STK_A3, a3) 109 XSTRUCT_FIELD (long, 4, XT_STK_A4, a4) 110 XSTRUCT_FIELD (long, 4, XT_STK_A5, a5) 111 XSTRUCT_FIELD (long, 4, XT_STK_A6, a6) 112 XSTRUCT_FIELD (long, 4, XT_STK_A7, a7) 113 XSTRUCT_FIELD (long, 4, XT_STK_A8, a8) 114 XSTRUCT_FIELD (long, 4, XT_STK_A9, a9) 115 XSTRUCT_FIELD (long, 4, XT_STK_A10, a10) 116 XSTRUCT_FIELD (long, 4, XT_STK_A11, a11) 117 XSTRUCT_FIELD (long, 4, XT_STK_A12, a12) 118 XSTRUCT_FIELD (long, 4, XT_STK_A13, a13) 119 XSTRUCT_FIELD (long, 4, XT_STK_A14, a14) 120 XSTRUCT_FIELD (long, 4, XT_STK_A15, a15) 121 XSTRUCT_FIELD (long, 4, XT_STK_SAR, sar) 122 XSTRUCT_FIELD (long, 4, XT_STK_EXCCAUSE, exccause) 123 XSTRUCT_FIELD (long, 4, XT_STK_EXCVADDR, excvaddr) 124 #if XCHAL_HAVE_LOOPS 125 XSTRUCT_FIELD (long, 4, XT_STK_LBEG, lbeg) 126 XSTRUCT_FIELD (long, 4, XT_STK_LEND, lend) 127 XSTRUCT_FIELD (long, 4, XT_STK_LCOUNT, lcount) 128 #endif 129 #if XCHAL_HAVE_EXCLUSIVE 130 XSTRUCT_FIELD (long, 4, XT_STK_ATOMCTL, atomctl) 131 #endif 132 #ifndef __XTENSA_CALL0_ABI__ 133 /* Temporary space for saving stuff during window spill */ 134 XSTRUCT_FIELD (long, 4, XT_STK_TMP0, tmp0) 135 XSTRUCT_FIELD (long, 4, XT_STK_TMP1, tmp1) 136 XSTRUCT_FIELD (long, 4, XT_STK_TMP2, tmp2) 137 #endif 138 #ifdef XT_USE_SWPRI 139 /* Storage for virtual priority mask */ 140 XSTRUCT_FIELD (long, 4, XT_STK_VPRI, vpri) 141 #endif 142 #ifdef XT_USE_OVLY 143 /* Storage for overlay state */ 144 XSTRUCT_FIELD (long, 4, XT_STK_OVLY, ovly) 145 #endif 146 XSTRUCT_END(XtExcFrame) 147 148 #endif /* XCHAL_HAVE_XEA2 */ 149 150 #if XCHAL_HAVE_XEA3 151 152 XSTRUCT_BEGIN 153 XSTRUCT_FIELD (long, 4, XT_STK_ATOMCTL, atomctl) 154 XSTRUCT_FIELD (long, 4, XT_STK_LCOUNT, lcount) 155 XSTRUCT_FIELD (long, 4, XT_STK_LEND, lend) 156 XSTRUCT_FIELD (long, 4, XT_STK_LBEG, lbeg) 157 XSTRUCT_FIELD (long, 4, XT_STK_PC, pc) 158 XSTRUCT_FIELD (long, 4, XT_STK_PS, ps) 159 XSTRUCT_FIELD (long, 4, XT_STK_EXCCAUSE, exccause) 160 XSTRUCT_FIELD (long, 4, XT_STK_EXCVADDR, excvaddr) 161 #ifdef __XTENSA_CALL0_ABI__ 162 XSTRUCT_FIELD (long, 4, XT_STK_A0, a0) 163 XSTRUCT_FIELD (long, 4, XT_STK_A1, a1) 164 XSTRUCT_FIELD (long, 4, XT_STK_A2, a2) 165 XSTRUCT_FIELD (long, 4, XT_STK_A3, a3) 166 XSTRUCT_FIELD (long, 4, XT_STK_A4, a4) 167 XSTRUCT_FIELD (long, 4, XT_STK_A5, a5) 168 XSTRUCT_FIELD (long, 4, XT_STK_A6, a6) 169 XSTRUCT_FIELD (long, 4, XT_STK_A7, a7) 170 #endif 171 XSTRUCT_FIELD (long, 4, XT_STK_A8, a8) 172 XSTRUCT_FIELD (long, 4, XT_STK_A9, a9) 173 XSTRUCT_FIELD (long, 4, XT_STK_A10, a10) 174 XSTRUCT_FIELD (long, 4, XT_STK_A11, a11) 175 XSTRUCT_FIELD (long, 4, XT_STK_A12, a12) 176 XSTRUCT_FIELD (long, 4, XT_STK_A13, a13) 177 XSTRUCT_FIELD (long, 4, XT_STK_A14, a14) 178 XSTRUCT_FIELD (long, 4, XT_STK_A15, a15) 179 #ifdef __XTENSA_WINDOWED_ABI__ 180 XSTRUCT_AFIELD(long, 4, XT_STK_SPILL, spill, 8) 181 #endif 182 XSTRUCT_END(XtExcFrame) 183 184 #endif /* XCHAL_HAVE_XEA3 */ 185 186 #if defined(_ASMLANGUAGE) || defined(__ASSEMBLER__) 187 #define XT_STK_NEXT1 XtExcFrameSize 188 #else 189 #define XT_STK_NEXT1 sizeof(XtExcFrame) 190 #endif 191 192 193 /* Allocate extra storage if needed for non-CP TIE state. Allow for alignment 194 padding as needed. 195 */ 196 #if XCHAL_EXTRA_SA_SIZE != 0 197 198 #if XCHAL_EXTRA_SA_ALIGN <= 16 199 #define XT_STK_EXTRA ALIGNUP(XCHAL_EXTRA_SA_ALIGN, XT_STK_NEXT1) 200 #else 201 /* If need more alignment than stack, add space for dynamic alignment */ 202 #define XT_STK_EXTRA (ALIGNUP(XCHAL_EXTRA_SA_ALIGN, XT_STK_NEXT1) + XCHAL_EXTRA_SA_ALIGN) 203 #endif 204 #define XT_STK_NEXT2 (XT_STK_EXTRA + XCHAL_EXTRA_SA_SIZE) 205 206 #else 207 208 /* No extra storage required */ 209 #define XT_STK_NEXT2 XT_STK_NEXT1 210 211 #endif 212 213 214 #if XCHAL_HAVE_XEA3 215 216 /* Total frame size */ 217 #define XT_STK_FRMSZ (ALIGNUP(0x10, XT_STK_NEXT2)) 218 219 /* Exception/interrupt frame size */ 220 #define XT_STK_XFRM_SZ XT_STK_NEXT1 221 222 /* Extra save area size (including alignment padding) */ 223 #define XT_STK_XTRA_SZ (XT_STK_FRMSZ - XT_STK_XFRM_SZ) 224 225 /* Alignment padding area size */ 226 #if XCHAL_EXTRA_SA_SIZE != 0 227 #define XT_STK_ALIGN_SZ (XT_STK_EXTRA - XT_STK_NEXT1) 228 #endif 229 230 #else 231 232 /* 233 ------------------------------------------------------------------------------- 234 This is the frame size. Add space for 4 registers (interruptee's base save 235 area) and some space for gcc nested functions if any. 236 ------------------------------------------------------------------------------- 237 */ 238 #define XT_STK_FRMSZ (ALIGNUP(0x10, XT_STK_NEXT2) + 0x20) 239 240 #endif 241 242 /* 243 ------------------------------------------------------------------------------- 244 CO-PROCESSOR STATE SAVE AREA FOR A THREAD 245 246 The RTOS must provide an area per thread to save the state of co-processors 247 when that thread does not have control. Co-processors are context-switched 248 lazily (on demand) only when a new thread uses a co-processor instruction, 249 otherwise a thread retains ownership of the co-processor even when it loses 250 control of the processor. An Xtensa co-processor exception is triggered when 251 any co-processor instruction is executed by a thread that is not the owner, 252 and the context switch of that co-processor is then peformed by the handler. 253 Ownership represents which thread's state is currently in the co-processor. 254 255 Co-processors may not be used by interrupt or exception handlers. If an 256 co-processor instruction is executed by an interrupt or exception handler, 257 the co-processor exception handler will trigger a kernel panic and freeze. 258 This restriction is introduced to reduce the overhead of saving and restoring 259 co-processor state (which can be quite large) and in particular remove that 260 overhead from interrupt handlers. 261 262 The co-processor state save area may be in any convenient per-thread location 263 such as in the thread control block or above the thread stack area. It need 264 not be in the interrupt stack frame since interrupts don't use co-processors. 265 266 Along with the save area for each co-processor, two bitmasks with flags per 267 co-processor (laid out as in the CPENABLE reg) help manage context-switching 268 co-processors as efficiently as possible: 269 270 XT_CPENABLE 271 The contents of a non-running thread's CPENABLE register. 272 It represents the co-processors owned (and whose state is still needed) 273 by the thread. When a thread is preempted, its CPENABLE is saved here. 274 When a thread solicits a context-swtich, its CPENABLE is cleared - the 275 compiler has saved the (caller-saved) co-proc state if it needs to. 276 When a non-running thread loses ownership of a CP, its bit is cleared. 277 When a thread runs, it's XT_CPENABLE is loaded into the CPENABLE reg. 278 Avoids co-processor exceptions when no change of ownership is needed. 279 280 XT_CPSTORED 281 A bitmask with the same layout as CPENABLE, a bit per co-processor. 282 Indicates whether the state of each co-processor is saved in the state 283 save area. When a thread enters the kernel, only the state of co-procs 284 still enabled in CPENABLE is saved. When the co-processor exception 285 handler assigns ownership of a co-processor to a thread, it restores 286 the saved state only if this bit is set, and clears this bit. 287 288 XT_CP_CS_ST 289 A bitmask with the same layout as CPENABLE, a bit per co-processor. 290 Indicates whether callee-saved state is saved in the state save area. 291 Callee-saved state is saved by itself on a solicited context switch, 292 and restored when needed by the coprocessor exception handler. 293 Unsolicited switches will cause the entire coprocessor to be saved 294 when necessary. 295 296 XT_CP_ASA 297 Pointer to the aligned save area. Allows it to be aligned more than 298 the overall save area (which might only be stack-aligned or TCB-aligned). 299 Especially relevant for Xtensa cores configured with a very large data 300 path that requires alignment greater than 16 bytes (ABI stack alignment). 301 ------------------------------------------------------------------------------- 302 */ 303 304 #if XCHAL_CP_NUM > 0 305 306 /* Offsets of each coprocessor save area within the 'aligned save area': */ 307 #define XT_CP0_SA 0 308 #define XT_CP1_SA ALIGNUP(XCHAL_CP1_SA_ALIGN, XT_CP0_SA + XCHAL_CP0_SA_SIZE) 309 #define XT_CP2_SA ALIGNUP(XCHAL_CP2_SA_ALIGN, XT_CP1_SA + XCHAL_CP1_SA_SIZE) 310 #define XT_CP3_SA ALIGNUP(XCHAL_CP3_SA_ALIGN, XT_CP2_SA + XCHAL_CP2_SA_SIZE) 311 #define XT_CP4_SA ALIGNUP(XCHAL_CP4_SA_ALIGN, XT_CP3_SA + XCHAL_CP3_SA_SIZE) 312 #define XT_CP5_SA ALIGNUP(XCHAL_CP5_SA_ALIGN, XT_CP4_SA + XCHAL_CP4_SA_SIZE) 313 #define XT_CP6_SA ALIGNUP(XCHAL_CP6_SA_ALIGN, XT_CP5_SA + XCHAL_CP5_SA_SIZE) 314 #define XT_CP7_SA ALIGNUP(XCHAL_CP7_SA_ALIGN, XT_CP6_SA + XCHAL_CP6_SA_SIZE) 315 #define XT_CP_SA_SIZE ALIGNUP(16, XT_CP7_SA + XCHAL_CP7_SA_SIZE) 316 317 /* Offsets within the overall save area: */ 318 #define XT_CPENABLE 0 /* (2 bytes) coprocessors active for this thread */ 319 #define XT_CPSTORED 2 /* (2 bytes) coprocessors saved for this thread */ 320 #define XT_CP_CS_ST 4 /* (2 bytes) coprocessor callee-saved regs stored for this thread */ 321 #define XT_CP_ASA 8 /* (4 bytes) ptr to aligned save area */ 322 /* Overall size allows for dynamic alignment: */ 323 #define XT_CP_SIZE (12 + XT_CP_SA_SIZE + XCHAL_TOTAL_SA_ALIGN) 324 #else 325 #define XT_CP_SIZE 0 326 #endif 327 328 329 /* 330 ------------------------------------------------------------------------------- 331 MACROS TO HANDLE ABI SPECIFICS OF FUNCTION ENTRY AND RETURN 332 333 Convenient where the frame size requirements are the same for both ABIs. 334 ENTRY(sz), RET(sz) are for framed functions (have locals or make calls). 335 ENTRY0, RET0 are for frameless functions (no locals, no calls). 336 337 where size = size of stack frame in bytes (must be >0 and aligned to 16). 338 For framed functions the frame is created and the return address saved at 339 base of frame (Call0 ABI) or as determined by hardware (Windowed ABI). 340 For frameless functions, there is no frame and return address remains in a0. 341 Note: Because CPP macros expand to a single line, macros requiring multi-line 342 expansions are implemented as assembler macros. 343 ------------------------------------------------------------------------------- 344 */ 345 346 #ifdef __ASSEMBLER__ 347 #ifdef __XTENSA_CALL0_ABI__ 348 /* Call0 */ 349 #define ENTRY(sz) entry1 sz 350 .macro entry1 size=0x10 351 addi sp, sp, -\size 352 s32i a0, sp, 0 353 .endm 354 #define ENTRY0 355 #define RET(sz) ret1 sz 356 .macro ret1 size=0x10 357 l32i a0, sp, 0 358 addi sp, sp, \size 359 ret 360 .endm 361 #define RET0 ret 362 #else 363 /* Windowed */ 364 #if XCHAL_HAVE_XEA3 365 #define ENTRY(sz) entry sp, (sz + 0x20) 366 #define ENTRY0 entry sp, 0x20 367 #else 368 #define ENTRY(sz) entry sp, (sz + 0x10) 369 #define ENTRY0 entry sp, 0x10 370 #endif 371 #define RET(sz) retw 372 #define RET0 retw 373 #endif 374 #endif 375 376 377 /* 378 ------------------------------------------------------------------------------- 379 This flag is meant for internal use. Have all interrupts be dispatched via a 380 common wrapper, which takes care of doing some OS-specific stuff common to 381 all interrupt handlers. Said stuff cannot safely be handled in the RTOS_ENTER 382 and RTOS_EXIT macros. 383 ------------------------------------------------------------------------------- 384 */ 385 #if (defined TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || (defined XT_INTEXC_HOOKS) 386 #define XT_USE_INT_WRAPPER 1 387 #else 388 #define XT_USE_INT_WRAPPER 0 389 #endif 390 391 #if XCHAL_HAVE_XEA3 392 #ifdef XT_USE_SWPRI 393 //#warning "Software prioritization of interrupts (XT_USE_SWPRI) not supported for XEA3." 394 #endif 395 396 #ifdef __ASSEMBLER__ 397 398 // RTOS-specific entry macro. Use only a8, a12-a14. 399 400 .macro XT_RTOS_INT_ENTER 401 402 .endm 403 404 // RTOS-specific exit macro. Use only a8-a14. 405 // (In call0, a15 holds user SP, must be preserved) 406 407 .macro XT_RTOS_INT_EXIT 408 409 // Check nesting count and branch on nest state. 410 movi a8, _tx_thread_system_state 411 movi a9, _tx_thread_execute_ptr // a9 <- &_tx_thread_execute_ptr (new) 412 movi a10, _tx_thread_preempt_disable // a10 <- &_tx_thread_preempt_disable 413 l32i a8, a8, 0 414 bnez a8, .Lnested // state != 0 means nested 415 416 movi a8, _tx_thread_current_ptr // a8 <- &_tx_thread_current_ptr (old) 417 l32i a9, a9, 0 // a9 <- _tx_thread_execute_ptr 418 l32i a11, a8, 0 // a11 <- _tx_thread_current_ptr 419 beqz a11, .Lsched // no old thread, go to scheduler 420 l32i a10, a10, 0 // a10 <- _tx_thread_preempt_disable 421 beq a11, a9, .Lnested // no change, restore current thread 422 bgei a10, 1, .Lnested // no preemption, restore current thread 423 424 // Preemption, save remaining state of current (outgoing) thread 425 426 movi a12, _tx_timer_time_slice // a12 <- &_tx_timer_time_slice 427 addi a10, a1, -XT_STK_FRMSZ 428 s32i a10, a11, tx_thread_stack_ptr // save outgoing thread stack pointer 429 l32i a10, a12, 0 // a10 <- _tx_timer_time_slice 430 beqz a10, .Ldont_save_ts 431 s32i a10, a11, tx_thread_time_slice // save outgoing time slice value 432 movi a10, 0 433 s32i a10, a12, 0 // disable time slice 434 .Ldont_save_ts: 435 s32i a10, a11, tx_thread_solicited // mark as preempted 436 s32i a10, a8, 0 // Clear _tx_thread_current_ptr 437 #if XCHAL_CP_NUM > 0 438 rsr a12, CPENABLE // Save and clear CPENABLE 439 s16i a12, a11, tx_thread_cp_state + XT_CPENABLE 440 wsr a10, CPENABLE 441 #endif 442 443 // Save non-CP TIE state if any 444 #if XCHAL_EXTRA_SA_SIZE > 0 445 addi a10, a1, -XT_STK_FRMSZ + XT_STK_ALIGN_SZ // where to save 446 #if XCHAL_EXTRA_SA_ALIGN > 16 447 movi a12, -XCHAL_EXTRA_SA_ALIGN 448 and a10, a10, a12 // align dynamically >16 bytes 449 #endif 450 xchal_ncp_store a10, a11, a12, a13, a14 451 #endif 452 453 // If windowed ABI, a0-a7 was not saved by dispatch code. 454 // These don't go into the exception frame, but below the 455 // exception frame pointer. 456 457 #ifdef __XTENSA_WINDOWED_ABI__ 458 addi a10, a1, -XT_STK_FRMSZ -32 459 s32i a0, a10, 0 460 s32i a2, a10, 8 461 s32i a3, a10, 12 462 s32i a4, a10, 16 463 s32i a5, a10, 20 464 s32i a6, a10, 24 465 s32i a7, a10, 28 466 #endif 467 468 .Lsched: 469 // When we get here, interrupts are disabled, a8 = &_tx_thread_current_ptr, 470 // a9 = _tx_thread_execute_ptr 471 movi a9, _tx_thread_execute_ptr // a9 <- &_tx_thread_execute_ptr (new) 472 l32i a9, a9, 0 // a9 <- _tx_thread_execute_ptr 473 s32i a9, a8, 0 // _tx_thread_current_ptr = _tx_thread_execute_ptr 474 beqz a9, _xt_idle // go idle if _tx_thread_execute_ptr == 0 475 l32i a10, a9, tx_thread_run_count 476 l32i a11, a9, tx_thread_time_slice 477 movi a12, _tx_timer_time_slice 478 addi a10, a10, 1 479 s32i a10, a9, tx_thread_run_count 480 s32i a11, a12, 0 // _tx_timer_time_slice = _tx_thread_current_ptr->tx_thread_time_slice 481 482 #ifdef TX_THREAD_SAFE_CLIB 483 #if XSHAL_CLIB == XTHAL_CLIB_NEWLIB 484 movi a10, _impure_ptr 485 #elif XSHAL_CLIB == XTHAL_CLIB_XCLIB 486 movi a10, _reent_ptr 487 #else 488 #error TX_THREAD_SAFE_CLIB defined with unsupported C library. 489 #endif 490 l32i a11, a9, tx_thread_clib_ptr 491 s32i a11, a10, 0 492 #endif 493 494 #if XCHAL_CP_NUM > 0 495 l16ui a10, a9, tx_thread_cp_state + XT_CPENABLE 496 wsr a10, CPENABLE // restore CPENABLE 497 #endif 498 499 l32i a1, a9, tx_thread_stack_ptr // SP = _tx_thread_execute_ptr->tx_thread_stack_ptr 500 501 #ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY 502 // Call the thread entry function to indicate the thread is executing. 503 // SP should be pointing to a safe region at this point. 504 #ifdef __XTENSA_CALL0_ABI__ 505 call0 _tx_execution_thread_enter 506 #else 507 call8 _tx_execution_thread_enter 508 #endif 509 #endif 510 511 l32i a2, a9, tx_thread_solicited // a2 = solicited flag 512 beqz a2, 1f 513 514 // Solicited restore 515 addi a1, a1, XT_STK_FRMSZ // restore original SP 516 addi a2, a1, -XT_STK_XFRM_SZ 517 l32i a3, a2, XT_STK_PC // a3 = return PC 518 519 movi a2, PS_DI 520 xps a2, a2 // disable interrupts 521 movi a2, 0 522 wsr.ms a2 // restore normal DISPST 523 rsync 524 jx a3 // return to yield point 525 526 1: 527 // Preempt restore 528 #if XCHAL_EXTRA_SA_SIZE > 0 529 addi a10, a1, XT_STK_ALIGN_SZ // where to restore from 530 #if XCHAL_EXTRA_SA_ALIGN > 16 531 movi a12, -XCHAL_EXTRA_SA_ALIGN 532 and a10, a10, a12 // align dynamically >16 bytes 533 #endif 534 xchal_ncp_load a10, a11, a12, a13, a14 535 #endif 536 537 #ifdef __XTENSA_WINDOWED_ABI__ 538 // Restore a0-a7 for windowed ABI 539 addi a8, a1, -32 540 l32i a0, a8, 0 541 l32i a2, a8, 8 542 l32i a3, a8, 12 543 l32i a4, a8, 16 544 l32i a5, a8, 20 545 l32i a6, a8, 24 546 l32i a7, a8, 28 547 #else 548 // For call0, dispatch exit code expects a15 = original SP 549 addi a15, a1, XT_STK_FRMSZ 550 #endif 551 552 addi a1, a1, XT_STK_FRMSZ // set up SP for dispatch exit 553 554 .Lnested: 555 // Return to the current saved context. 556 557 .endm 558 559 #endif /* __ASSEMBLER__ */ 560 #endif /* XCHAL_HAVE_XEA3 */ 561 562 #endif /* XTENSA_CONTEXT_H */ 563 564
