1 /* ------------------------------------------
2 * Copyright (c) 2016, Synopsys, Inc. All rights reserved.
3
4 * Redistribution and use in source and binary forms, with or without modification,
5 * are permitted provided that the following conditions are met:
6
7 * 1) Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9
10 * 2) Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation and/or
12 * other materials provided with the distribution.
13
14 * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
15 * be used to endorse or promote products derived from this software without
16 * specific prior written permission.
17
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
20 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
21 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
22 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
23 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
24 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
25 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
27 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 --------------------------------------------- */
29
30 #include "arc/arc_reg.h"
31
32 /*********************************************************************
33 * Core Intc setup
34 *********************************************************************/
35
36 #ifndef __ARC_HDR__
37 #define __ARC_HDR__
38
39 #ifndef NULL
40 #define NULL 0
41 #endif
42
43 #define IRQ_TIMER 16
44 #define IRQ_IPI 19
45
46 #define CORE_PRIMARY 1
47 #define CORE_SECONDARY 2
48
49 #define INTERRUPT_ENABLE (1 << 4) // according ISA (SETI instruction details)
50 #define INTERRUPT_LEVEL(L) ((L) << 0)//simple macro for user-friendly name conversion
51
52
53
__ffs(unsigned long x)54 static inline int __ffs(unsigned long x)
55 {
56 int n;
57
58 asm volatile(
59 " ffs.f %0, %1 \n" /* 0..31; Z set if src 0 */
60 " mov.z %0, 0 \n" /* return 0 if 0 */
61 : "=r"(n)
62 : "r"(x)
63 : "cc");
64
65 return n;
66 }
67
68 #define AUX_ID 0x004
69
smp_processor_id()70 static inline int smp_processor_id()
71 {
72 unsigned int id = _lr(AUX_ID);
73 return (id >> 8) & 0xFF;
74 }
75
arc_halt(void)76 static inline void arc_halt(void)
77 {
78 asm volatile("flag 1\n");
79 }
80
81 /* no need for volatile */
82 typedef unsigned int spinlock_t;
83
spinlock_acquire(unsigned int * lock)84 static inline void spinlock_acquire(unsigned int *lock)
85 {
86 unsigned int val;
87
88 asm volatile(
89 "1: llock %[val], [%[slock]] \n"
90 " breq %[val], %[LOCKED], 1b \n" /* spin while LOCKED */
91 " scond %[LOCKED], [%[slock]] \n" /* acquire */
92 " bnz 1b \n"
93 " dmb 3 \n"
94 : [val] "=&r" (val)
95 : [slock] "r" (lock),
96 [LOCKED] "r" (1)
97 : "memory", "cc");
98 }
99
spinlock_release(unsigned int * lock)100 static inline void spinlock_release(unsigned int *lock)
101 {
102 __asm__ __volatile__(
103 " dmb 3 \n"
104 " st %[UNLOCKED], [%[slock]] \n"
105 :
106 : [slock] "r" (lock),
107 [UNLOCKED] "r" (0)
108 : "memory");
109 }
110
arc_enable_ints(void)111 static inline void arc_enable_ints(void)
112 {
113 _seti(1);
114 }
115
116 extern void arc_timer_setup(unsigned int);
117 extern void arc_register_isr(int irq, void (*fn)(int), int arg_to_isr);
118 extern void arc_ici_send(unsigned int cpu);
119
120 #endif
121
