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Searched defs:ENABLE_INTS (Results 1 – 11 of 11) sorted by relevance

/ThreadX-v6.4.1/ports/arm9/ac5/src/
Dtx_thread_schedule.s34 ENABLE_INTS EQU 0xC0 ; IRQ & FIQ Interrupts enabled mask define
36 ENABLE_INTS EQU 0x80 ; IRQ Interrupts enabled mask define
/ThreadX-v6.4.1/ports/arm11/ac5/src/
Dtx_thread_schedule.s34 ENABLE_INTS EQU 0xC0 ; IRQ & FIQ Interrupts enabled mask define
36 ENABLE_INTS EQU 0x80 ; IRQ Interrupts enabled mask define
/ThreadX-v6.4.1/ports/arm9/iar/src/
Dtx_thread_schedule.s33 ENABLE_INTS DEFINE 0xC0 ; IRQ & FIQ Interrupts enabled mask label
35 ENABLE_INTS DEFINE 0x80 ; IRQ Interrupts enabled mask label
/ThreadX-v6.4.1/ports/arm11/gnu/src/
Dtx_thread_schedule.S26 ENABLE_INTS = 0xC0 @ IRQ & FIQ Interrupts enabled mask define
28 ENABLE_INTS = 0x80 @ IRQ Interrupts enabled mask define
/ThreadX-v6.4.1/ports/arm11/iar/src/
Dtx_thread_schedule.s33 ENABLE_INTS DEFINE 0xC0 ; IRQ & FIQ Interrupts enabled mask label
35 ENABLE_INTS DEFINE 0x80 ; IRQ Interrupts enabled mask label
/ThreadX-v6.4.1/ports/arm9/gnu/src/
Dtx_thread_schedule.S26 ENABLE_INTS = 0xC0 @ IRQ & FIQ Interrupts enabled mask define
28 ENABLE_INTS = 0x80 @ IRQ Interrupts enabled mask define
/ThreadX-v6.4.1/ports/cortex_a9/iar/src/
Dtx_thread_schedule.s33 ENABLE_INTS DEFINE 0xC0 ; IRQ & FIQ Interrupts enabled mask label
35 ENABLE_INTS DEFINE 0x80 ; IRQ Interrupts enabled mask label
/ThreadX-v6.4.1/ports/cortex_a5/iar/src/
Dtx_thread_schedule.s33 ENABLE_INTS DEFINE 0xC0 ; IRQ & FIQ Interrupts enabled mask label
35 ENABLE_INTS DEFINE 0x80 ; IRQ Interrupts enabled mask label
/ThreadX-v6.4.1/ports/cortex_a7/iar/src/
Dtx_thread_schedule.s33 ENABLE_INTS DEFINE 0xC0 ; IRQ & FIQ Interrupts enabled mask label
35 ENABLE_INTS DEFINE 0x80 ; IRQ Interrupts enabled mask label
/ThreadX-v6.4.1/ports/cortex_a8/iar/src/
Dtx_thread_schedule.s33 ENABLE_INTS DEFINE 0xC0 ; IRQ & FIQ Interrupts enabled mask label
35 ENABLE_INTS DEFINE 0x80 ; IRQ Interrupts enabled mask label
/ThreadX-v6.4.1/ports_module/cortex_a7/ac5/module_manager/src/
Dtx_thread_schedule.s46 ENABLE_INTS EQU 0xC0 ; IRQ & FIQ Interrupts enabled mask define
48 ENABLE_INTS EQU 0x80 ; IRQ Interrupts enabled mask define