1 //
2 // Copyright (c) 2010-2024 Antmicro
3 //
4 //  This file is licensed under the MIT License.
5 //  Full license text is available in 'licenses/MIT.txt'.
6 //
7 using System;
8 using System.Linq;
9 using System.Collections.Generic;
10 using Antmicro.Renode.Peripherals.CPU;
11 using Antmicro.Renode.Peripherals.CPU.Registers;
12 using Antmicro.Renode.Utilities.Binding;
13 
14 namespace Antmicro.Renode.Peripherals.CoSimulated
15 {
16     public partial class CoSimulatedRiscV32
17     {
18         [Register]
19         public RegisterValue ZERO
20         {
21             get
22             {
23                 return GetRegisterValue32((int)CoSimulatedRiscV32Registers.ZERO);
24             }
25             set
26             {
27                 SetRegisterValue32((int)CoSimulatedRiscV32Registers.ZERO, value);
28             }
29         }
30         [Register]
31         public RegisterValue RA
32         {
33             get
34             {
35                 return GetRegisterValue32((int)CoSimulatedRiscV32Registers.RA);
36             }
37             set
38             {
39                 SetRegisterValue32((int)CoSimulatedRiscV32Registers.RA, value);
40             }
41         }
42         [Register]
43         public RegisterValue SP
44         {
45             get
46             {
47                 return GetRegisterValue32((int)CoSimulatedRiscV32Registers.SP);
48             }
49             set
50             {
51                 SetRegisterValue32((int)CoSimulatedRiscV32Registers.SP, value);
52             }
53         }
54         [Register]
55         public RegisterValue GP
56         {
57             get
58             {
59                 return GetRegisterValue32((int)CoSimulatedRiscV32Registers.GP);
60             }
61             set
62             {
63                 SetRegisterValue32((int)CoSimulatedRiscV32Registers.GP, value);
64             }
65         }
66         [Register]
67         public RegisterValue TP
68         {
69             get
70             {
71                 return GetRegisterValue32((int)CoSimulatedRiscV32Registers.TP);
72             }
73             set
74             {
75                 SetRegisterValue32((int)CoSimulatedRiscV32Registers.TP, value);
76             }
77         }
78         [Register]
79         public RegisterValue FP
80         {
81             get
82             {
83                 return GetRegisterValue32((int)CoSimulatedRiscV32Registers.FP);
84             }
85             set
86             {
87                 SetRegisterValue32((int)CoSimulatedRiscV32Registers.FP, value);
88             }
89         }
90         [Register]
91         public override RegisterValue PC
92         {
93             get
94             {
95                 return GetRegisterValue32((int)CoSimulatedRiscV32Registers.PC);
96             }
97             set
98             {
99                 SetRegisterValue32((int)CoSimulatedRiscV32Registers.PC, value);
100             }
101         }
102         [Register]
103         public RegisterValue SSTATUS
104         {
105             get
106             {
107                 return GetRegisterValue32((int)CoSimulatedRiscV32Registers.SSTATUS);
108             }
109             set
110             {
111                 SetRegisterValue32((int)CoSimulatedRiscV32Registers.SSTATUS, value);
112             }
113         }
114         [Register]
115         public RegisterValue SIE
116         {
117             get
118             {
119                 return GetRegisterValue32((int)CoSimulatedRiscV32Registers.SIE);
120             }
121             set
122             {
123                 SetRegisterValue32((int)CoSimulatedRiscV32Registers.SIE, value);
124             }
125         }
126         [Register]
127         public RegisterValue STVEC
128         {
129             get
130             {
131                 return GetRegisterValue32((int)CoSimulatedRiscV32Registers.STVEC);
132             }
133             set
134             {
135                 SetRegisterValue32((int)CoSimulatedRiscV32Registers.STVEC, value);
136             }
137         }
138         [Register]
139         public RegisterValue SSCRATCH
140         {
141             get
142             {
143                 return GetRegisterValue32((int)CoSimulatedRiscV32Registers.SSCRATCH);
144             }
145             set
146             {
147                 SetRegisterValue32((int)CoSimulatedRiscV32Registers.SSCRATCH, value);
148             }
149         }
150         [Register]
151         public RegisterValue SEPC
152         {
153             get
154             {
155                 return GetRegisterValue32((int)CoSimulatedRiscV32Registers.SEPC);
156             }
157             set
158             {
159                 SetRegisterValue32((int)CoSimulatedRiscV32Registers.SEPC, value);
160             }
161         }
162         [Register]
163         public RegisterValue SCAUSE
164         {
165             get
166             {
167                 return GetRegisterValue32((int)CoSimulatedRiscV32Registers.SCAUSE);
168             }
169             set
170             {
171                 SetRegisterValue32((int)CoSimulatedRiscV32Registers.SCAUSE, value);
172             }
173         }
174         [Register]
175         public RegisterValue STVAL
176         {
177             get
178             {
179                 return GetRegisterValue32((int)CoSimulatedRiscV32Registers.STVAL);
180             }
181             set
182             {
183                 SetRegisterValue32((int)CoSimulatedRiscV32Registers.STVAL, value);
184             }
185         }
186         [Register]
187         public RegisterValue SIP
188         {
189             get
190             {
191                 return GetRegisterValue32((int)CoSimulatedRiscV32Registers.SIP);
192             }
193             set
194             {
195                 SetRegisterValue32((int)CoSimulatedRiscV32Registers.SIP, value);
196             }
197         }
198         [Register]
199         public RegisterValue SATP
200         {
201             get
202             {
203                 return GetRegisterValue32((int)CoSimulatedRiscV32Registers.SATP);
204             }
205             set
206             {
207                 SetRegisterValue32((int)CoSimulatedRiscV32Registers.SATP, value);
208             }
209         }
210         [Register]
211         public RegisterValue SPTBR
212         {
213             get
214             {
215                 return GetRegisterValue32((int)CoSimulatedRiscV32Registers.SPTBR);
216             }
217             set
218             {
219                 SetRegisterValue32((int)CoSimulatedRiscV32Registers.SPTBR, value);
220             }
221         }
222         [Register]
223         public RegisterValue MSTATUS
224         {
225             get
226             {
227                 return GetRegisterValue32((int)CoSimulatedRiscV32Registers.MSTATUS);
228             }
229             set
230             {
231                 SetRegisterValue32((int)CoSimulatedRiscV32Registers.MSTATUS, value);
232             }
233         }
234         [Register]
235         public RegisterValue MISA
236         {
237             get
238             {
239                 return GetRegisterValue32((int)CoSimulatedRiscV32Registers.MISA);
240             }
241             set
242             {
243                 SetRegisterValue32((int)CoSimulatedRiscV32Registers.MISA, value);
244             }
245         }
246         [Register]
247         public RegisterValue MEDELEG
248         {
249             get
250             {
251                 return GetRegisterValue32((int)CoSimulatedRiscV32Registers.MEDELEG);
252             }
253             set
254             {
255                 SetRegisterValue32((int)CoSimulatedRiscV32Registers.MEDELEG, value);
256             }
257         }
258         [Register]
259         public RegisterValue MIDELEG
260         {
261             get
262             {
263                 return GetRegisterValue32((int)CoSimulatedRiscV32Registers.MIDELEG);
264             }
265             set
266             {
267                 SetRegisterValue32((int)CoSimulatedRiscV32Registers.MIDELEG, value);
268             }
269         }
270         [Register]
271         public RegisterValue MIE
272         {
273             get
274             {
275                 return GetRegisterValue32((int)CoSimulatedRiscV32Registers.MIE);
276             }
277             set
278             {
279                 SetRegisterValue32((int)CoSimulatedRiscV32Registers.MIE, value);
280             }
281         }
282         [Register]
283         public RegisterValue MTVEC
284         {
285             get
286             {
287                 return GetRegisterValue32((int)CoSimulatedRiscV32Registers.MTVEC);
288             }
289             set
290             {
291                 SetRegisterValue32((int)CoSimulatedRiscV32Registers.MTVEC, value);
292             }
293         }
294         [Register]
295         public RegisterValue MSCRATCH
296         {
297             get
298             {
299                 return GetRegisterValue32((int)CoSimulatedRiscV32Registers.MSCRATCH);
300             }
301             set
302             {
303                 SetRegisterValue32((int)CoSimulatedRiscV32Registers.MSCRATCH, value);
304             }
305         }
306         [Register]
307         public RegisterValue MEPC
308         {
309             get
310             {
311                 return GetRegisterValue32((int)CoSimulatedRiscV32Registers.MEPC);
312             }
313             set
314             {
315                 SetRegisterValue32((int)CoSimulatedRiscV32Registers.MEPC, value);
316             }
317         }
318         [Register]
319         public RegisterValue MCAUSE
320         {
321             get
322             {
323                 return GetRegisterValue32((int)CoSimulatedRiscV32Registers.MCAUSE);
324             }
325             set
326             {
327                 SetRegisterValue32((int)CoSimulatedRiscV32Registers.MCAUSE, value);
328             }
329         }
330         [Register]
331         public RegisterValue MTVAL
332         {
333             get
334             {
335                 return GetRegisterValue32((int)CoSimulatedRiscV32Registers.MTVAL);
336             }
337             set
338             {
339                 SetRegisterValue32((int)CoSimulatedRiscV32Registers.MTVAL, value);
340             }
341         }
342         [Register]
343         public RegisterValue MIP
344         {
345             get
346             {
347                 return GetRegisterValue32((int)CoSimulatedRiscV32Registers.MIP);
348             }
349             set
350             {
351                 SetRegisterValue32((int)CoSimulatedRiscV32Registers.MIP, value);
352             }
353         }
354         [Register]
355         public RegisterValue PRIV
356         {
357             get
358             {
359                 return GetRegisterValue32((int)CoSimulatedRiscV32Registers.PRIV);
360             }
361             set
362             {
363                 SetRegisterValue32((int)CoSimulatedRiscV32Registers.PRIV, value);
364             }
365         }
366         public RegistersGroup X { get; private set; }
367         public RegistersGroup T { get; private set; }
368         public RegistersGroup S { get; private set; }
369         public RegistersGroup A { get; private set; }
370         public RegistersGroup F { get; private set; }
371 
InitializeRegisters()372         protected override void InitializeRegisters()
373         {
374             var indexValueMapX = new Dictionary<int, CoSimulatedRiscV32Registers>
375             {
376                 { 0, CoSimulatedRiscV32Registers.X0 },
377                 { 1, CoSimulatedRiscV32Registers.X1 },
378                 { 2, CoSimulatedRiscV32Registers.X2 },
379                 { 3, CoSimulatedRiscV32Registers.X3 },
380                 { 4, CoSimulatedRiscV32Registers.X4 },
381                 { 5, CoSimulatedRiscV32Registers.X5 },
382                 { 6, CoSimulatedRiscV32Registers.X6 },
383                 { 7, CoSimulatedRiscV32Registers.X7 },
384                 { 8, CoSimulatedRiscV32Registers.X8 },
385                 { 9, CoSimulatedRiscV32Registers.X9 },
386                 { 10, CoSimulatedRiscV32Registers.X10 },
387                 { 11, CoSimulatedRiscV32Registers.X11 },
388                 { 12, CoSimulatedRiscV32Registers.X12 },
389                 { 13, CoSimulatedRiscV32Registers.X13 },
390                 { 14, CoSimulatedRiscV32Registers.X14 },
391                 { 15, CoSimulatedRiscV32Registers.X15 },
392                 { 16, CoSimulatedRiscV32Registers.X16 },
393                 { 17, CoSimulatedRiscV32Registers.X17 },
394                 { 18, CoSimulatedRiscV32Registers.X18 },
395                 { 19, CoSimulatedRiscV32Registers.X19 },
396                 { 20, CoSimulatedRiscV32Registers.X20 },
397                 { 21, CoSimulatedRiscV32Registers.X21 },
398                 { 22, CoSimulatedRiscV32Registers.X22 },
399                 { 23, CoSimulatedRiscV32Registers.X23 },
400                 { 24, CoSimulatedRiscV32Registers.X24 },
401                 { 25, CoSimulatedRiscV32Registers.X25 },
402                 { 26, CoSimulatedRiscV32Registers.X26 },
403                 { 27, CoSimulatedRiscV32Registers.X27 },
404                 { 28, CoSimulatedRiscV32Registers.X28 },
405                 { 29, CoSimulatedRiscV32Registers.X29 },
406                 { 30, CoSimulatedRiscV32Registers.X30 },
407                 { 31, CoSimulatedRiscV32Registers.X31 },
408             };
409             X = new RegistersGroup(
410                 indexValueMapX.Keys,
411                 i => GetRegister((int)indexValueMapX[i]),
412                 (i, v) => SetRegister((int)indexValueMapX[i], v));
413 
414             var indexValueMapT = new Dictionary<int, CoSimulatedRiscV32Registers>
415             {
416                 { 0, CoSimulatedRiscV32Registers.T0 },
417                 { 1, CoSimulatedRiscV32Registers.T1 },
418                 { 2, CoSimulatedRiscV32Registers.T2 },
419                 { 3, CoSimulatedRiscV32Registers.T3 },
420                 { 4, CoSimulatedRiscV32Registers.T4 },
421                 { 5, CoSimulatedRiscV32Registers.T5 },
422                 { 6, CoSimulatedRiscV32Registers.T6 },
423             };
424             T = new RegistersGroup(
425                 indexValueMapT.Keys,
426                 i => GetRegister((int)indexValueMapT[i]),
427                 (i, v) => SetRegister((int)indexValueMapT[i], v));
428 
429             var indexValueMapS = new Dictionary<int, CoSimulatedRiscV32Registers>
430             {
431                 { 0, CoSimulatedRiscV32Registers.S0 },
432                 { 1, CoSimulatedRiscV32Registers.S1 },
433                 { 2, CoSimulatedRiscV32Registers.S2 },
434                 { 3, CoSimulatedRiscV32Registers.S3 },
435                 { 4, CoSimulatedRiscV32Registers.S4 },
436                 { 5, CoSimulatedRiscV32Registers.S5 },
437                 { 6, CoSimulatedRiscV32Registers.S6 },
438                 { 7, CoSimulatedRiscV32Registers.S7 },
439                 { 8, CoSimulatedRiscV32Registers.S8 },
440                 { 9, CoSimulatedRiscV32Registers.S9 },
441                 { 10, CoSimulatedRiscV32Registers.S10 },
442                 { 11, CoSimulatedRiscV32Registers.S11 },
443             };
444             S = new RegistersGroup(
445                 indexValueMapS.Keys,
446                 i => GetRegister((int)indexValueMapS[i]),
447                 (i, v) => SetRegister((int)indexValueMapS[i], v));
448 
449             var indexValueMapA = new Dictionary<int, CoSimulatedRiscV32Registers>
450             {
451                 { 0, CoSimulatedRiscV32Registers.A0 },
452                 { 1, CoSimulatedRiscV32Registers.A1 },
453                 { 2, CoSimulatedRiscV32Registers.A2 },
454                 { 3, CoSimulatedRiscV32Registers.A3 },
455                 { 4, CoSimulatedRiscV32Registers.A4 },
456                 { 5, CoSimulatedRiscV32Registers.A5 },
457                 { 6, CoSimulatedRiscV32Registers.A6 },
458                 { 7, CoSimulatedRiscV32Registers.A7 },
459             };
460             A = new RegistersGroup(
461                 indexValueMapA.Keys,
462                 i => GetRegister((int)indexValueMapA[i]),
463                 (i, v) => SetRegister((int)indexValueMapA[i], v));
464 
465             var indexValueMapF = new Dictionary<int, CoSimulatedRiscV32Registers>
466             {
467                 { 0, CoSimulatedRiscV32Registers.F0 },
468                 { 1, CoSimulatedRiscV32Registers.F1 },
469                 { 2, CoSimulatedRiscV32Registers.F2 },
470                 { 3, CoSimulatedRiscV32Registers.F3 },
471                 { 4, CoSimulatedRiscV32Registers.F4 },
472                 { 5, CoSimulatedRiscV32Registers.F5 },
473                 { 6, CoSimulatedRiscV32Registers.F6 },
474                 { 7, CoSimulatedRiscV32Registers.F7 },
475                 { 8, CoSimulatedRiscV32Registers.F8 },
476                 { 9, CoSimulatedRiscV32Registers.F9 },
477                 { 10, CoSimulatedRiscV32Registers.F10 },
478                 { 11, CoSimulatedRiscV32Registers.F11 },
479                 { 12, CoSimulatedRiscV32Registers.F12 },
480                 { 13, CoSimulatedRiscV32Registers.F13 },
481                 { 14, CoSimulatedRiscV32Registers.F14 },
482                 { 15, CoSimulatedRiscV32Registers.F15 },
483                 { 16, CoSimulatedRiscV32Registers.F16 },
484                 { 17, CoSimulatedRiscV32Registers.F17 },
485                 { 18, CoSimulatedRiscV32Registers.F18 },
486                 { 19, CoSimulatedRiscV32Registers.F19 },
487                 { 20, CoSimulatedRiscV32Registers.F20 },
488                 { 21, CoSimulatedRiscV32Registers.F21 },
489                 { 22, CoSimulatedRiscV32Registers.F22 },
490                 { 23, CoSimulatedRiscV32Registers.F23 },
491                 { 24, CoSimulatedRiscV32Registers.F24 },
492                 { 25, CoSimulatedRiscV32Registers.F25 },
493                 { 26, CoSimulatedRiscV32Registers.F26 },
494                 { 27, CoSimulatedRiscV32Registers.F27 },
495                 { 28, CoSimulatedRiscV32Registers.F28 },
496                 { 29, CoSimulatedRiscV32Registers.F29 },
497                 { 30, CoSimulatedRiscV32Registers.F30 },
498                 { 31, CoSimulatedRiscV32Registers.F31 },
499             };
500             F = new RegistersGroup(
501                 indexValueMapF.Keys,
502                 i => GetRegister((int)indexValueMapF[i]),
503                 (i, v) => SetRegister((int)indexValueMapF[i], v));
504 
505         }
506 
507         private static readonly Dictionary<CoSimulatedRiscV32Registers, CPURegister> mapping = new Dictionary<CoSimulatedRiscV32Registers, CPURegister>
508         {
509             { CoSimulatedRiscV32Registers.ZERO,  new CPURegister(0, 32, isGeneral: true, isReadonly: true) },
510             { CoSimulatedRiscV32Registers.RA,  new CPURegister(1, 32, isGeneral: true, isReadonly: false) },
511             { CoSimulatedRiscV32Registers.SP,  new CPURegister(2, 32, isGeneral: true, isReadonly: false) },
512             { CoSimulatedRiscV32Registers.GP,  new CPURegister(3, 32, isGeneral: true, isReadonly: false) },
513             { CoSimulatedRiscV32Registers.TP,  new CPURegister(4, 32, isGeneral: true, isReadonly: false) },
514             { CoSimulatedRiscV32Registers.X5,  new CPURegister(5, 32, isGeneral: true, isReadonly: false) },
515             { CoSimulatedRiscV32Registers.X6,  new CPURegister(6, 32, isGeneral: true, isReadonly: false) },
516             { CoSimulatedRiscV32Registers.X7,  new CPURegister(7, 32, isGeneral: true, isReadonly: false) },
517             { CoSimulatedRiscV32Registers.FP,  new CPURegister(8, 32, isGeneral: true, isReadonly: false) },
518             { CoSimulatedRiscV32Registers.X9,  new CPURegister(9, 32, isGeneral: true, isReadonly: false) },
519             { CoSimulatedRiscV32Registers.X10,  new CPURegister(10, 32, isGeneral: true, isReadonly: false) },
520             { CoSimulatedRiscV32Registers.X11,  new CPURegister(11, 32, isGeneral: true, isReadonly: false) },
521             { CoSimulatedRiscV32Registers.X12,  new CPURegister(12, 32, isGeneral: true, isReadonly: false) },
522             { CoSimulatedRiscV32Registers.X13,  new CPURegister(13, 32, isGeneral: true, isReadonly: false) },
523             { CoSimulatedRiscV32Registers.X14,  new CPURegister(14, 32, isGeneral: true, isReadonly: false) },
524             { CoSimulatedRiscV32Registers.X15,  new CPURegister(15, 32, isGeneral: true, isReadonly: false) },
525             { CoSimulatedRiscV32Registers.X16,  new CPURegister(16, 32, isGeneral: true, isReadonly: false) },
526             { CoSimulatedRiscV32Registers.X17,  new CPURegister(17, 32, isGeneral: true, isReadonly: false) },
527             { CoSimulatedRiscV32Registers.X18,  new CPURegister(18, 32, isGeneral: true, isReadonly: false) },
528             { CoSimulatedRiscV32Registers.X19,  new CPURegister(19, 32, isGeneral: true, isReadonly: false) },
529             { CoSimulatedRiscV32Registers.X20,  new CPURegister(20, 32, isGeneral: true, isReadonly: false) },
530             { CoSimulatedRiscV32Registers.X21,  new CPURegister(21, 32, isGeneral: true, isReadonly: false) },
531             { CoSimulatedRiscV32Registers.X22,  new CPURegister(22, 32, isGeneral: true, isReadonly: false) },
532             { CoSimulatedRiscV32Registers.X23,  new CPURegister(23, 32, isGeneral: true, isReadonly: false) },
533             { CoSimulatedRiscV32Registers.X24,  new CPURegister(24, 32, isGeneral: true, isReadonly: false) },
534             { CoSimulatedRiscV32Registers.X25,  new CPURegister(25, 32, isGeneral: true, isReadonly: false) },
535             { CoSimulatedRiscV32Registers.X26,  new CPURegister(26, 32, isGeneral: true, isReadonly: false) },
536             { CoSimulatedRiscV32Registers.X27,  new CPURegister(27, 32, isGeneral: true, isReadonly: false) },
537             { CoSimulatedRiscV32Registers.X28,  new CPURegister(28, 32, isGeneral: true, isReadonly: false) },
538             { CoSimulatedRiscV32Registers.X29,  new CPURegister(29, 32, isGeneral: true, isReadonly: false) },
539             { CoSimulatedRiscV32Registers.X30,  new CPURegister(30, 32, isGeneral: true, isReadonly: false) },
540             { CoSimulatedRiscV32Registers.X31,  new CPURegister(31, 32, isGeneral: true, isReadonly: false) },
541             { CoSimulatedRiscV32Registers.PC,  new CPURegister(32, 32, isGeneral: true, isReadonly: false) },
542             { CoSimulatedRiscV32Registers.F0,  new CPURegister(33, 32, isGeneral: false, isReadonly: false) },
543             { CoSimulatedRiscV32Registers.F1,  new CPURegister(34, 32, isGeneral: false, isReadonly: false) },
544             { CoSimulatedRiscV32Registers.F2,  new CPURegister(35, 32, isGeneral: false, isReadonly: false) },
545             { CoSimulatedRiscV32Registers.F3,  new CPURegister(36, 32, isGeneral: false, isReadonly: false) },
546             { CoSimulatedRiscV32Registers.F4,  new CPURegister(37, 32, isGeneral: false, isReadonly: false) },
547             { CoSimulatedRiscV32Registers.F5,  new CPURegister(38, 32, isGeneral: false, isReadonly: false) },
548             { CoSimulatedRiscV32Registers.F6,  new CPURegister(39, 32, isGeneral: false, isReadonly: false) },
549             { CoSimulatedRiscV32Registers.F7,  new CPURegister(40, 32, isGeneral: false, isReadonly: false) },
550             { CoSimulatedRiscV32Registers.F8,  new CPURegister(41, 32, isGeneral: false, isReadonly: false) },
551             { CoSimulatedRiscV32Registers.F9,  new CPURegister(42, 32, isGeneral: false, isReadonly: false) },
552             { CoSimulatedRiscV32Registers.F10,  new CPURegister(43, 32, isGeneral: false, isReadonly: false) },
553             { CoSimulatedRiscV32Registers.F11,  new CPURegister(44, 32, isGeneral: false, isReadonly: false) },
554             { CoSimulatedRiscV32Registers.F12,  new CPURegister(45, 32, isGeneral: false, isReadonly: false) },
555             { CoSimulatedRiscV32Registers.F13,  new CPURegister(46, 32, isGeneral: false, isReadonly: false) },
556             { CoSimulatedRiscV32Registers.F14,  new CPURegister(47, 32, isGeneral: false, isReadonly: false) },
557             { CoSimulatedRiscV32Registers.F15,  new CPURegister(48, 32, isGeneral: false, isReadonly: false) },
558             { CoSimulatedRiscV32Registers.F16,  new CPURegister(49, 32, isGeneral: false, isReadonly: false) },
559             { CoSimulatedRiscV32Registers.F17,  new CPURegister(50, 32, isGeneral: false, isReadonly: false) },
560             { CoSimulatedRiscV32Registers.F18,  new CPURegister(51, 32, isGeneral: false, isReadonly: false) },
561             { CoSimulatedRiscV32Registers.F19,  new CPURegister(52, 32, isGeneral: false, isReadonly: false) },
562             { CoSimulatedRiscV32Registers.F20,  new CPURegister(53, 32, isGeneral: false, isReadonly: false) },
563             { CoSimulatedRiscV32Registers.F21,  new CPURegister(54, 32, isGeneral: false, isReadonly: false) },
564             { CoSimulatedRiscV32Registers.F22,  new CPURegister(55, 32, isGeneral: false, isReadonly: false) },
565             { CoSimulatedRiscV32Registers.F23,  new CPURegister(56, 32, isGeneral: false, isReadonly: false) },
566             { CoSimulatedRiscV32Registers.F24,  new CPURegister(57, 32, isGeneral: false, isReadonly: false) },
567             { CoSimulatedRiscV32Registers.F25,  new CPURegister(58, 32, isGeneral: false, isReadonly: false) },
568             { CoSimulatedRiscV32Registers.F26,  new CPURegister(59, 32, isGeneral: false, isReadonly: false) },
569             { CoSimulatedRiscV32Registers.F27,  new CPURegister(60, 32, isGeneral: false, isReadonly: false) },
570             { CoSimulatedRiscV32Registers.F28,  new CPURegister(61, 32, isGeneral: false, isReadonly: false) },
571             { CoSimulatedRiscV32Registers.F29,  new CPURegister(62, 32, isGeneral: false, isReadonly: false) },
572             { CoSimulatedRiscV32Registers.F30,  new CPURegister(63, 32, isGeneral: false, isReadonly: false) },
573             { CoSimulatedRiscV32Registers.F31,  new CPURegister(64, 32, isGeneral: false, isReadonly: false) },
574             { CoSimulatedRiscV32Registers.SSTATUS,  new CPURegister(256, 32, isGeneral: false, isReadonly: false) },
575             { CoSimulatedRiscV32Registers.SIE,  new CPURegister(260, 32, isGeneral: false, isReadonly: false) },
576             { CoSimulatedRiscV32Registers.STVEC,  new CPURegister(261, 32, isGeneral: false, isReadonly: false) },
577             { CoSimulatedRiscV32Registers.SSCRATCH,  new CPURegister(320, 32, isGeneral: false, isReadonly: false) },
578             { CoSimulatedRiscV32Registers.SEPC,  new CPURegister(321, 32, isGeneral: false, isReadonly: false) },
579             { CoSimulatedRiscV32Registers.SCAUSE,  new CPURegister(322, 32, isGeneral: false, isReadonly: false) },
580             { CoSimulatedRiscV32Registers.STVAL,  new CPURegister(323, 32, isGeneral: false, isReadonly: false) },
581             { CoSimulatedRiscV32Registers.SIP,  new CPURegister(324, 32, isGeneral: false, isReadonly: false) },
582             { CoSimulatedRiscV32Registers.SATP,  new CPURegister(384, 32, isGeneral: false, isReadonly: false) },
583             { CoSimulatedRiscV32Registers.MSTATUS,  new CPURegister(768, 32, isGeneral: false, isReadonly: false) },
584             { CoSimulatedRiscV32Registers.MISA,  new CPURegister(769, 32, isGeneral: false, isReadonly: false) },
585             { CoSimulatedRiscV32Registers.MEDELEG,  new CPURegister(770, 32, isGeneral: false, isReadonly: false) },
586             { CoSimulatedRiscV32Registers.MIDELEG,  new CPURegister(771, 32, isGeneral: false, isReadonly: false) },
587             { CoSimulatedRiscV32Registers.MIE,  new CPURegister(772, 32, isGeneral: false, isReadonly: false) },
588             { CoSimulatedRiscV32Registers.MTVEC,  new CPURegister(773, 32, isGeneral: false, isReadonly: false) },
589             { CoSimulatedRiscV32Registers.MSCRATCH,  new CPURegister(832, 32, isGeneral: false, isReadonly: false) },
590             { CoSimulatedRiscV32Registers.MEPC,  new CPURegister(833, 32, isGeneral: false, isReadonly: false) },
591             { CoSimulatedRiscV32Registers.MCAUSE,  new CPURegister(834, 32, isGeneral: false, isReadonly: false) },
592             { CoSimulatedRiscV32Registers.MTVAL,  new CPURegister(835, 32, isGeneral: false, isReadonly: false) },
593             { CoSimulatedRiscV32Registers.MIP,  new CPURegister(836, 32, isGeneral: false, isReadonly: false) },
594             { CoSimulatedRiscV32Registers.PRIV,  new CPURegister(4096, 32, isGeneral: false, isReadonly: false) },
595         };
596     }
597 
598     public enum CoSimulatedRiscV32Registers
599     {
600         ZERO = 0,
601         RA = 1,
602         SP = 2,
603         GP = 3,
604         TP = 4,
605         FP = 8,
606         PC = 32,
607         SSTATUS = 256,
608         SIE = 260,
609         STVEC = 261,
610         SSCRATCH = 320,
611         SEPC = 321,
612         SCAUSE = 322,
613         STVAL = 323,
614         SIP = 324,
615         SATP = 384,
616         SPTBR = 384,
617         MSTATUS = 768,
618         MISA = 769,
619         MEDELEG = 770,
620         MIDELEG = 771,
621         MIE = 772,
622         MTVEC = 773,
623         MSCRATCH = 832,
624         MEPC = 833,
625         MCAUSE = 834,
626         MTVAL = 835,
627         MIP = 836,
628         PRIV = 4096,
629         X0 = 0,
630         X1 = 1,
631         X2 = 2,
632         X3 = 3,
633         X4 = 4,
634         X5 = 5,
635         X6 = 6,
636         X7 = 7,
637         X8 = 8,
638         X9 = 9,
639         X10 = 10,
640         X11 = 11,
641         X12 = 12,
642         X13 = 13,
643         X14 = 14,
644         X15 = 15,
645         X16 = 16,
646         X17 = 17,
647         X18 = 18,
648         X19 = 19,
649         X20 = 20,
650         X21 = 21,
651         X22 = 22,
652         X23 = 23,
653         X24 = 24,
654         X25 = 25,
655         X26 = 26,
656         X27 = 27,
657         X28 = 28,
658         X29 = 29,
659         X30 = 30,
660         X31 = 31,
661         T0 = 5,
662         T1 = 6,
663         T2 = 7,
664         T3 = 28,
665         T4 = 29,
666         T5 = 30,
667         T6 = 31,
668         S0 = 8,
669         S1 = 9,
670         S2 = 18,
671         S3 = 19,
672         S4 = 20,
673         S5 = 21,
674         S6 = 22,
675         S7 = 23,
676         S8 = 24,
677         S9 = 25,
678         S10 = 26,
679         S11 = 27,
680         A0 = 10,
681         A1 = 11,
682         A2 = 12,
683         A3 = 13,
684         A4 = 14,
685         A5 = 15,
686         A6 = 16,
687         A7 = 17,
688         F0 = 33,
689         F1 = 34,
690         F2 = 35,
691         F3 = 36,
692         F4 = 37,
693         F5 = 38,
694         F6 = 39,
695         F7 = 40,
696         F8 = 41,
697         F9 = 42,
698         F10 = 43,
699         F11 = 44,
700         F12 = 45,
701         F13 = 46,
702         F14 = 47,
703         F15 = 48,
704         F16 = 49,
705         F17 = 50,
706         F18 = 51,
707         F19 = 52,
708         F20 = 53,
709         F21 = 54,
710         F22 = 55,
711         F23 = 56,
712         F24 = 57,
713         F25 = 58,
714         F26 = 59,
715         F27 = 60,
716         F28 = 61,
717         F29 = 62,
718         F30 = 63,
719         F31 = 64,
720     }
721 }
722