Searched refs:privilegedArchitecture (Results 1 – 9 of 9) sorted by relevance
| /Renode-Infrastructure-v1.15.3-29f510e/src/Emulator/Cores/RiscV/ |
| D | Ri5cy.cs | 15 …privilegedArchitecture = PrivilegedArchitecture.Priv1_10, Endianess endianness = Endianess.LittleE… in Ri5cy() argument
|
| D | IbexRiscV32.cs | 15 …privilegedArchitecture = PrivilegedArchitecture.Priv1_11, Endianess endianness = Endianess.LittleE… in IbexRiscV32() argument
|
| D | RiscV32.cs | 21 …[NameAlias("privilegeArchitecture")] PrivilegedArchitecture privilegedArchitecture = PrivilegedArc… in RiscV32() 30 …: base(timeProvider, hartId, cpuType, machine, privilegedArchitecture, endianness, CpuBitness.Bits… in RiscV32()
|
| D | RiscV64.cs | 21 …[NameAlias("privilegeArchitecture")] PrivilegedArchitecture privilegedArchitecture = PrivilegedArc… in RiscV64() 30 …: base(timeProvider, hartId, cpuType, machine, privilegedArchitecture, endianness, CpuBitness.Bits… in RiscV64()
|
| D | VeeR_EL2.cs | 18 …der timeProvider = null, uint hartId = 0, PrivilegedArchitecture privilegedArchitecture = Privileg… in VeeR_EL2() argument 20 …: base(machine, cpuType, timeProvider, hartId, privilegedArchitecture, endianness, allowUnalignedA… in VeeR_EL2()
|
| D | VexRiscv.cs | 20 …privilegedArchitecture = PrivilegedArchitecture.Priv1_10, string cpuType = "rv32im_Zicsr_Zifencei"… in VexRiscv() argument
|
| D | BaseRiscV.cs | 35 PrivilegedArchitecture privilegedArchitecture, in BaseRiscV() argument 50 this.privilegedArchitecture = privilegedArchitecture; in BaseRiscV() 187 …if(privilegedArchitecture >= PrivilegedArchitecture.Priv1_10 && IsValidInterruptOnlyInV1_09(number… in OnGPIO() 645 TlibSetPrivilegeArchitecture((int)privilegedArchitecture); in EnableArchitectureVariants() 859 private readonly PrivilegedArchitecture privilegedArchitecture; field in Antmicro.Renode.Peripherals.CPU.BaseRiscV
|
| D | CV32E40P.cs | 17 …= 0, [NameAlias("privilegeArchitecture")] PrivilegedArchitecture privilegedArchitecture = Privileg… in CV32E40P() argument 18 …: base(machine, cpuType, timeProvider, hartId, privilegedArchitecture, endianness, allowUnalignedA… in CV32E40P()
|
| D | OpenTitan_BigNumberAcceleratorCore.cs | 27 …ovider: null, cpuType: "rv32im_zicsr", machine: null, hartId: 0, privilegedArchitecture: Privilege… in OpenTitan_BigNumberAcceleratorCore()
|