1 //
2 // Copyright (c) 2010-2024 Antmicro
3 //
4 // This file is licensed under the MIT License.
5 // Full license text is available in 'licenses/MIT.txt'.
6 //
7 
8 using System;
9 using Antmicro.Renode.Core;
10 using Antmicro.Renode.Core.Structure.Registers;
11 
12 namespace Antmicro.Renode.Peripherals.Bus
13 {
14     // The peripheral is a model of ARM CoreLink NIC-400.
15     public class ARM_NetworkInterconnect : BasicDoubleWordPeripheral, IKnownSize
16     {
ARM_NetworkInterconnect(IMachine machine)17         public ARM_NetworkInterconnect(IMachine machine) : base(machine)
18         {
19             DefineRegisters();
20         }
21 
22         public long Size => 0x100000;
23         public uint UserDefinedPeripheralID { get; set; } = 0x0;
24 
DefineRegisters()25         private void DefineRegisters()
26         {
27             Registers.PeripheralID4.Define(this, 0x04)
28                 .WithReservedBits(8, 24)
29                 .WithValueField(0, 8, FieldMode.Read, name: "JEP106 Continuation code");
30             Registers.PeripheralID0.Define(this, 0x0)
31                 .WithReservedBits(8, 24)
32                 .WithValueField(0, 8, FieldMode.Read, name: "Part Number [7:0]");
33             Registers.PeripheralID1.Define(this, 0xB4)
34                 .WithReservedBits(8, 24)
35                 .WithValueField(4, 4, FieldMode.Read, name: "JEP106 Identity")
36                 .WithValueField(0, 4, FieldMode.Read, name: "Part Number [11:8]");
37             Registers.PeripheralID2.Define(this, 0x4B)
38                 .WithReservedBits(8, 24)
39                 .WithValueField(4, 4, FieldMode.Read, name: "Part Revision")
40                 .WithFlag(3, FieldMode.Read, name: "JEP106 Code flag")
41                 .WithValueField(0, 3, FieldMode.Read, name: "JEP Identity [6:4]");
42             Registers.PeripheralID3.Define(this, UserDefinedPeripheralID)
43                 .WithReservedBits(8, 24)
44                 .WithValueField(0, 8, FieldMode.Read, name: "User Peripheral ID");
45             Registers.ComponentID0.Define(this, 0x0D)
46                 .WithReservedBits(8, 24)
47                 .WithValueField(0, 8, FieldMode.Read, name: "Preamble");
48             Registers.ComponentID1.Define(this, 0xF0)
49                 .WithReservedBits(8, 24)
50                 .WithValueField(0, 8, FieldMode.Read, name: "Generic IP component class");
51             Registers.ComponentID2.Define(this, 0x05)
52                 .WithReservedBits(8, 24)
53                 .WithValueField(0, 8, FieldMode.Read, name: "Preamble");
54             Registers.ComponentID3.Define(this, 0xB1)
55                 .WithReservedBits(8, 24)
56                 .WithValueField(0, 8, FieldMode.Read, name: "Preamble");
57         }
58 
59         private enum Registers
60         {
61             Remap = 0x0, // remap
62             Security_0 = 0x08, // security<n>
63 
64             PeripheralID4 = 0x1FD0,
65             PeripheralID5 = 0x1FD4,
66             PeripheralID6 = 0x1FD8,
67             PeripheralID7 = 0x1FDC,
68             PeripheralID0 = 0x1FE0,
69             PeripheralID1 = 0x1FE4,
70             PeripheralID2 = 0x1FE8,
71             PeripheralID3 = 0x1FEC,
72             ComponentID0 = 0x1FF0,
73             ComponentID1 = 0x1FF4,
74             ComponentID2 = 0x1FF8,
75             ComponentID3 = 0x1FFC,
76 
77             MasterBusMatrixFunctionalityModification_0 = 0x2008, // AMIB fn_mod_bm_iss<n>
78             MasterSynchronizationMode_0 = 0x2020, // AMIB sync_mode<n>
79             MasterBypassMerge_0 = 0x2024, // AMIB fn_mod2<n>
80             MasterLongBurstModification_0 = 0x202C, // AMIB fn_mod_lb<n>
81             MasterWFIFOTidemark_0 = 0x2040, // AMIB wr_tidemark<n>
82             MasterAHBControl_0 = 0x2044, // AMIB ahb_cntl<n>
83             MasterFunctionalityModification_0 = 0x2108, // AMIB fn_mod<n>
84 
85             SlaveSynchronizationMode_0 = 0x42020, // ASIB sync_mode<n>
86             SlaveBypassMerge_0 = 0x42024, // ASIB fn_mod<n>
87             SlaveFunctionalityModificationAHB_0 = 0x42028, // ASIB fn_mod_ahb<n>
88             SlaveLongBurst_0 = 0x4202C, // ASIB fn_mod_lb<n>
89             SlaveWFIFOTidemark_0 = 0x42040, // ASIB wr_tidemark<n>
90             SlaveReadChannelQoS_0 = 0x42100, // ASIB read_qos<n>
91             SlaveWriteChanelQoS_0 = 0x42104, // ASIB write_qos<n>
92             SlaveFunctionalityModification_0 = 0x42108, // ASIB fn_mod<n>
93 
94             InternalBusMatrixFunctionalityModification_0 = 0xC2008, // IB fn_mod_bm_iss<n>
95             InternalSynchronizationMode_0 = 0xC2020, // IB sync_mode<n>
96             InternalBypassMerge_0 = 0xC2024, // IB fn_mod2<n>
97             InternalLongBurst_0 = 0xC202C, // IB fn_mod_lb<n>
98             InternalWFIFOTidemark_0 = 0xC2040, // IB wr_tidemark<n>
99             InternalFunctionalityModification_0 = 0xC2108, // IB fn_mod<n>
100         }
101     }
102 }
103