1 // Generated by PeakRDL-renode 2 3 using Antmicro.Renode.Core.Structure.Registers; 4 using Antmicro.Renode.Peripherals.Bus; 5 6 namespace Antmicro.Renode.Peripherals.I3C 7 { 8 public partial class Caliptra_I3C : IProvidesRegisterCollection<DoubleWordRegisterCollection>, IPeripheral, IDoubleWordPeripheral 9 { 10 /// <summary> Register "HCI_VERSION" at 0x0 </summary> 11 protected HciVersionType HciVersion; 12 /// <summary> Register "HC_CONTROL" at 0x4 </summary> 13 protected HcControlType HcControl; 14 /// <summary> Register "CONTROLLER_DEVICE_ADDR" at 0x8 </summary> 15 protected ControllerDeviceAddrType ControllerDeviceAddr; 16 /// <summary> Register "HC_CAPABILITIES" at 0xc </summary> 17 protected HcCapabilitiesType HcCapabilities; 18 /// <summary> Register "RESET_CONTROL" at 0x10 </summary> 19 protected ResetControlType ResetControl; 20 /// <summary> Register "PRESENT_STATE" at 0x14 </summary> 21 protected PresentStateType PresentState; 22 /// <summary> Register "INTR_STATUS" at 0x20 </summary> 23 protected IntrStatusType IntrStatus; 24 /// <summary> Register "INTR_STATUS_ENABLE" at 0x24 </summary> 25 protected IntrStatusEnableType IntrStatusEnable; 26 /// <summary> Register "INTR_SIGNAL_ENABLE" at 0x28 </summary> 27 protected IntrSignalEnableType IntrSignalEnable; 28 /// <summary> Register "INTR_FORCE" at 0x2c </summary> 29 protected IntrForceType IntrForce; 30 /// <summary> Register "DAT_SECTION_OFFSET" at 0x30 </summary> 31 protected DatSectionOffsetType DatSectionOffset; 32 /// <summary> Register "DCT_SECTION_OFFSET" at 0x34 </summary> 33 protected DctSectionOffsetType DctSectionOffset; 34 /// <summary> Register "RING_HEADERS_SECTION_OFFSET" at 0x38 </summary> 35 protected RingHeadersSectionOffsetType RingHeadersSectionOffset; 36 /// <summary> Register "PIO_SECTION_OFFSET" at 0x3c </summary> 37 protected PioSectionOffsetType PioSectionOffset; 38 /// <summary> Register "EXT_CAPS_SECTION_OFFSET" at 0x40 </summary> 39 protected ExtCapsSectionOffsetType ExtCapsSectionOffset; 40 /// <summary> Register "INT_CTRL_CMDS_EN" at 0x4c </summary> 41 protected IntCtrlCmdsEnType IntCtrlCmdsEn; 42 /// <summary> Register "IBI_NOTIFY_CTRL" at 0x58 </summary> 43 protected IbiNotifyCtrlType IbiNotifyCtrl; 44 /// <summary> Register "IBI_DATA_ABORT_CTRL" at 0x5c </summary> 45 protected IbiDataAbortCtrlType IbiDataAbortCtrl; 46 /// <summary> Register "DEV_CTX_BASE_LO" at 0x60 </summary> 47 protected DevCtxBaseLoType DevCtxBaseLo; 48 /// <summary> Register "DEV_CTX_BASE_HI" at 0x64 </summary> 49 protected DevCtxBaseHiType DevCtxBaseHi; 50 /// <summary> Register "DEV_CTX_SG" at 0x68 </summary> 51 protected DevCtxSgType DevCtxSg; 52 /// <summary> Register "COMMAND_PORT" at 0x80 </summary> 53 protected CommandPortType CommandPort; 54 /// <summary> Register "RESPONSE_PORT" at 0x84 </summary> 55 protected ResponsePortType ResponsePort; 56 /// <summary> Register "TX_DATA_PORT" at 0x88 and Register "RX_DATA_PORT" at 0x88 </summary> 57 protected PIOTxRxDataPortType PIOTxRxDataPort; 58 /// <summary> Register "IBI_PORT" at 0x8c </summary> 59 protected PIOIbiPortType PIOIbiPort; 60 /// <summary> Register "QUEUE_THLD_CTRL" at 0x90 </summary> 61 protected PIOQueueThldCtrlType PIOQueueThldCtrl; 62 /// <summary> Register "DATA_BUFFER_THLD_CTRL" at 0x94 </summary> 63 protected PIODataBufferThldCtrlType PIODataBufferThldCtrl; 64 /// <summary> Register "QUEUE_SIZE" at 0x98 </summary> 65 protected PIOQueueSizeType PIOQueueSize; 66 /// <summary> Register "ALT_QUEUE_SIZE" at 0x9c </summary> 67 protected AltQueueSizeType AltQueueSize; 68 /// <summary> Register "PIO_INTR_STATUS" at 0xa0 </summary> 69 protected PioIntrStatusType PioIntrStatus; 70 /// <summary> Register "PIO_INTR_STATUS_ENABLE" at 0xa4 </summary> 71 protected PioIntrStatusEnableType PioIntrStatusEnable; 72 /// <summary> Register "PIO_INTR_SIGNAL_ENABLE" at 0xa8 </summary> 73 protected PioIntrSignalEnableType PioIntrSignalEnable; 74 /// <summary> Register "PIO_INTR_FORCE" at 0xac </summary> 75 protected PioIntrForceType PioIntrForce; 76 /// <summary> Register "PIO_CONTROL" at 0xb0 </summary> 77 protected PioControlType PioControl; 78 /// <summary> Register "EXTCAP_HEADER" at 0x100 </summary> 79 protected SecureFirmwareRecoveryInterfaceExtcapHeaderType SecureFirmwareRecoveryInterfaceExtcapHeader; 80 /// <summary> Register "PROT_CAP_0" at 0x104 </summary> 81 protected ProtCap0Type ProtCap0; 82 /// <summary> Register "PROT_CAP_1" at 0x108 </summary> 83 protected ProtCap1Type ProtCap1; 84 /// <summary> Register "PROT_CAP_2" at 0x10c </summary> 85 protected ProtCap2Type ProtCap2; 86 /// <summary> Register "PROT_CAP_3" at 0x110 </summary> 87 protected ProtCap3Type ProtCap3; 88 /// <summary> Register "DEVICE_ID_0" at 0x114 </summary> 89 protected DeviceId0Type DeviceId0; 90 /// <summary> Register "DEVICE_ID_1" at 0x118 </summary> 91 protected DeviceId1Type DeviceId1; 92 /// <summary> Register "DEVICE_ID_2" at 0x11c </summary> 93 protected DeviceId2Type DeviceId2; 94 /// <summary> Register "DEVICE_ID_3" at 0x120 </summary> 95 protected DeviceId3Type DeviceId3; 96 /// <summary> Register "DEVICE_ID_4" at 0x124 </summary> 97 protected DeviceId4Type DeviceId4; 98 /// <summary> Register "DEVICE_ID_5" at 0x128 </summary> 99 protected DeviceId5Type DeviceId5; 100 /// <summary> Register "DEVICE_ID_RESERVED" at 0x12c </summary> 101 protected DeviceIdReservedType DeviceIdReserved; 102 /// <summary> Register "DEVICE_STATUS_0" at 0x130 </summary> 103 protected DeviceStatus0Type DeviceStatus0; 104 /// <summary> Register "DEVICE_STATUS_1" at 0x134 </summary> 105 protected DeviceStatus1Type DeviceStatus1; 106 /// <summary> Register "DEVICE_RESET" at 0x138 </summary> 107 protected DeviceResetType DeviceReset; 108 /// <summary> Register "RECOVERY_CTRL" at 0x13c </summary> 109 protected RecoveryCtrlType RecoveryCtrl; 110 /// <summary> Register "RECOVERY_STATUS" at 0x140 </summary> 111 protected RecoveryStatusType RecoveryStatus; 112 /// <summary> Register "HW_STATUS" at 0x144 </summary> 113 protected HwStatusType HwStatus; 114 /// <summary> Register "INDIRECT_FIFO_CTRL_0" at 0x148 </summary> 115 protected IndirectFifoCtrl0Type IndirectFifoCtrl0; 116 /// <summary> Register "INDIRECT_FIFO_CTRL_1" at 0x14c </summary> 117 protected IndirectFifoCtrl1Type IndirectFifoCtrl1; 118 /// <summary> Register "INDIRECT_FIFO_STATUS_0" at 0x150 </summary> 119 protected IndirectFifoStatus0Type IndirectFifoStatus0; 120 /// <summary> Register "INDIRECT_FIFO_STATUS_1" at 0x154 </summary> 121 protected IndirectFifoStatus1Type IndirectFifoStatus1; 122 /// <summary> Register "INDIRECT_FIFO_STATUS_2" at 0x158 </summary> 123 protected IndirectFifoStatus2Type IndirectFifoStatus2; 124 /// <summary> Register "INDIRECT_FIFO_STATUS_3" at 0x15c </summary> 125 protected IndirectFifoStatus3Type IndirectFifoStatus3; 126 /// <summary> Register "INDIRECT_FIFO_STATUS_4" at 0x160 </summary> 127 protected IndirectFifoStatus4Type IndirectFifoStatus4; 128 /// <summary> Register "INDIRECT_FIFO_RESERVED" at 0x164 </summary> 129 protected IndirectFifoReservedType IndirectFifoReserved; 130 /// <summary> Register "INDIRECT_FIFO_DATA" at 0x168 </summary> 131 protected IndirectFifoDataType IndirectFifoData; 132 /// <summary> Register "EXTCAP_HEADER" at 0x180 </summary> 133 protected StandbyControllerModeRegistersExtcapHeaderType StandbyControllerModeRegistersExtcapHeader; 134 /// <summary> Register "STBY_CR_CONTROL" at 0x184 </summary> 135 protected StbyCrControlType StbyCrControl; 136 /// <summary> Register "STBY_CR_DEVICE_ADDR" at 0x188 </summary> 137 protected StbyCrDeviceAddrType StbyCrDeviceAddr; 138 /// <summary> Register "STBY_CR_CAPABILITIES" at 0x18c </summary> 139 protected StbyCrCapabilitiesType StbyCrCapabilities; 140 /// <summary> Register "__rsvd_0" at 0x190 </summary> 141 protected Rsvd0Type Rsvd0; 142 /// <summary> Register "STBY_CR_STATUS" at 0x194 </summary> 143 protected StbyCrStatusType StbyCrStatus; 144 /// <summary> Register "STBY_CR_DEVICE_CHAR" at 0x198 </summary> 145 protected StbyCrDeviceCharType StbyCrDeviceChar; 146 /// <summary> Register "STBY_CR_DEVICE_PID_LO" at 0x19c </summary> 147 protected StbyCrDevicePidLoType StbyCrDevicePidLo; 148 /// <summary> Register "STBY_CR_INTR_STATUS" at 0x1a0 </summary> 149 protected StbyCrIntrStatusType StbyCrIntrStatus; 150 /// <summary> Register "__rsvd_1" at 0x1a4 </summary> 151 protected Rsvd1Type Rsvd1; 152 /// <summary> Register "STBY_CR_INTR_SIGNAL_ENABLE" at 0x1a8 </summary> 153 protected StbyCrIntrSignalEnableType StbyCrIntrSignalEnable; 154 /// <summary> Register "STBY_CR_INTR_FORCE" at 0x1ac </summary> 155 protected StbyCrIntrForceType StbyCrIntrForce; 156 /// <summary> Register "STBY_CR_CCC_CONFIG_GETCAPS" at 0x1b0 </summary> 157 protected StbyCrCccConfigGetcapsType StbyCrCccConfigGetcaps; 158 /// <summary> Register "STBY_CR_CCC_CONFIG_RSTACT_PARAMS" at 0x1b4 </summary> 159 protected StbyCrCccConfigRstactParamsType StbyCrCccConfigRstactParams; 160 /// <summary> Register "STBY_CR_VIRT_DEVICE_ADDR" at 0x1b8 </summary> 161 protected StbyCrVirtDeviceAddrType StbyCrVirtDeviceAddr; 162 /// <summary> Register "__rsvd_3" at 0x1bc </summary> 163 protected Rsvd3Type Rsvd3; 164 /// <summary> Register "EXTCAP_HEADER" at 0x1c0 </summary> 165 protected TargetTransactionInterfaceRegistersExtcapHeaderType TargetTransactionInterfaceRegistersExtcapHeader; 166 /// <summary> Register "CONTROL" at 0x1c4 </summary> 167 protected ControlType Control; 168 /// <summary> Register "STATUS" at 0x1c8 </summary> 169 protected StatusType Status; 170 /// <summary> Register "RESET_CONTROL" at 0x1cc </summary> 171 protected TargetTransactionInterfaceResetControlType TargetTransactionInterfaceResetControl; 172 /// <summary> Register "INTERRUPT_STATUS" at 0x1d0 </summary> 173 protected InterruptStatusType InterruptStatus; 174 /// <summary> Register "INTERRUPT_ENABLE" at 0x1d4 </summary> 175 protected InterruptEnableType InterruptEnable; 176 /// <summary> Register "INTERRUPT_FORCE" at 0x1d8 </summary> 177 protected InterruptForceType InterruptForce; 178 /// <summary> Register "RX_DESC_QUEUE_PORT" at 0x1dc </summary> 179 protected RxDescQueuePortType RxDescQueuePort; 180 /// <summary> Register "RX_DATA_PORT" at 0x1e0 </summary> 181 protected TargetTransactionInterfaceRxDataPortType TargetTransactionInterfaceRxDataPort; 182 /// <summary> Register "TX_DESC_QUEUE_PORT" at 0x1e4 </summary> 183 protected TxDescQueuePortType TxDescQueuePort; 184 /// <summary> Register "TX_DATA_PORT" at 0x1e8 </summary> 185 protected TargetTransactionInterfaceTxDataPortType TargetTransactionInterfaceTxDataPort; 186 /// <summary> Register "IBI_PORT" at 0x1ec </summary> 187 protected TargetTransactionInterfaceIbiPortType TargetTransactionInterfaceIbiPort; 188 /// <summary> Register "QUEUE_SIZE" at 0x1f0 </summary> 189 protected TargetTransactionInterfaceQueueSizeType TargetTransactionInterfaceQueueSize; 190 /// <summary> Register "IBI_QUEUE_SIZE" at 0x1f4 </summary> 191 protected IbiQueueSizeType IbiQueueSize; 192 /// <summary> Register "QUEUE_THLD_CTRL" at 0x1f8 </summary> 193 protected TargetTransactionInterfaceQueueThldCtrlType TargetTransactionInterfaceQueueThldCtrl; 194 /// <summary> Register "DATA_BUFFER_THLD_CTRL" at 0x1fc </summary> 195 protected TargetTransactionInterfaceDataBufferThldCtrlType TargetTransactionInterfaceDataBufferThldCtrl; 196 /// <summary> Register "EXTCAP_HEADER" at 0x200 </summary> 197 protected SoCManagementInterfaceRegistersExtcapHeaderType SoCManagementInterfaceRegistersExtcapHeader; 198 /// <summary> Register "SOC_MGMT_CONTROL" at 0x204 </summary> 199 protected SocMgmtControlType SocMgmtControl; 200 /// <summary> Register "SOC_MGMT_STATUS" at 0x208 </summary> 201 protected SocMgmtStatusType SocMgmtStatus; 202 /// <summary> Register "SOC_MGMT_RSVD_0" at 0x20c </summary> 203 protected SocMgmtRsvd0Type SocMgmtRsvd0; 204 /// <summary> Register "SOC_MGMT_RSVD_1" at 0x210 </summary> 205 protected SocMgmtRsvd1Type SocMgmtRsvd1; 206 /// <summary> Register "SOC_MGMT_RSVD_2" at 0x214 </summary> 207 protected SocMgmtRsvd2Type SocMgmtRsvd2; 208 /// <summary> Register "SOC_MGMT_RSVD_3" at 0x218 </summary> 209 protected SocMgmtRsvd3Type SocMgmtRsvd3; 210 /// <summary> Register "SOC_PAD_CONF" at 0x21c </summary> 211 protected SocPadConfType SocPadConf; 212 /// <summary> Register "SOC_PAD_ATTR" at 0x220 </summary> 213 protected SocPadAttrType SocPadAttr; 214 /// <summary> Register "SOC_MGMT_FEATURE_2" at 0x224 </summary> 215 protected SocMgmtFeature2Type SocMgmtFeature2; 216 /// <summary> Register "SOC_MGMT_FEATURE_3" at 0x228 </summary> 217 protected SocMgmtFeature3Type SocMgmtFeature3; 218 /// <summary> Register "T_R_REG" at 0x22c </summary> 219 protected TRRegType TRReg; 220 /// <summary> Register "T_F_REG" at 0x230 </summary> 221 protected TFRegType TFReg; 222 /// <summary> Register "T_SU_DAT_REG" at 0x234 </summary> 223 protected TSuDatRegType TSuDatReg; 224 /// <summary> Register "T_HD_DAT_REG" at 0x238 </summary> 225 protected THdDatRegType THdDatReg; 226 /// <summary> Register "T_HIGH_REG" at 0x23c </summary> 227 protected THighRegType THighReg; 228 /// <summary> Register "T_LOW_REG" at 0x240 </summary> 229 protected TLowRegType TLowReg; 230 /// <summary> Register "T_HD_STA_REG" at 0x244 </summary> 231 protected THdStaRegType THdStaReg; 232 /// <summary> Register "T_SU_STA_REG" at 0x248 </summary> 233 protected TSuStaRegType TSuStaReg; 234 /// <summary> Register "T_SU_STO_REG" at 0x24c </summary> 235 protected TSuStoRegType TSuStoReg; 236 /// <summary> Register "T_FREE_REG" at 0x250 </summary> 237 protected TFreeRegType TFreeReg; 238 /// <summary> Register "T_AVAL_REG" at 0x254 </summary> 239 protected TAvalRegType TAvalReg; 240 /// <summary> Register "T_IDLE_REG" at 0x258 </summary> 241 protected TIdleRegType TIdleReg; 242 /// <summary> Register "EXTCAP_HEADER" at 0x260 </summary> 243 protected ControllerConfigRegistersExtcapHeaderType ControllerConfigRegistersExtcapHeader; 244 /// <summary> Register "CONTROLLER_CONFIG" at 0x264 </summary> 245 protected ControllerConfigType ControllerConfig; 246 /// <summary> Register "TERMINATION_EXTCAP_HEADER" at 0x268 </summary> 247 protected TerminationExtcapHeaderType TerminationExtcapHeader; 248 /// <summary> Memory "DAT" at 0x400 </summary> 249 protected Dat_DatMemoryContainer Dat; 250 /// <summary> Memory "DCT" at 0x800 </summary> 251 protected Dct_DctMemoryContainer Dct; 252 253 public DoubleWordRegisterCollection RegistersCollection { get; } 254 Caliptra_I3C()255 public Caliptra_I3C() 256 { 257 RegistersCollection = new DoubleWordRegisterCollection(this); 258 HciVersion = new HciVersionType(this); 259 HcControl = new HcControlType(this); 260 ControllerDeviceAddr = new ControllerDeviceAddrType(this); 261 HcCapabilities = new HcCapabilitiesType(this); 262 ResetControl = new ResetControlType(this); 263 PresentState = new PresentStateType(this); 264 IntrStatus = new IntrStatusType(this); 265 IntrStatusEnable = new IntrStatusEnableType(this); 266 IntrSignalEnable = new IntrSignalEnableType(this); 267 IntrForce = new IntrForceType(this); 268 DatSectionOffset = new DatSectionOffsetType(this); 269 DctSectionOffset = new DctSectionOffsetType(this); 270 RingHeadersSectionOffset = new RingHeadersSectionOffsetType(this); 271 PioSectionOffset = new PioSectionOffsetType(this); 272 ExtCapsSectionOffset = new ExtCapsSectionOffsetType(this); 273 IntCtrlCmdsEn = new IntCtrlCmdsEnType(this); 274 IbiNotifyCtrl = new IbiNotifyCtrlType(this); 275 IbiDataAbortCtrl = new IbiDataAbortCtrlType(this); 276 DevCtxBaseLo = new DevCtxBaseLoType(this); 277 DevCtxBaseHi = new DevCtxBaseHiType(this); 278 DevCtxSg = new DevCtxSgType(this); 279 CommandPort = new CommandPortType(this); 280 ResponsePort = new ResponsePortType(this); 281 TargetTransactionInterfaceTxDataPort = new TargetTransactionInterfaceTxDataPortType(this); 282 PIOIbiPort = new PIOIbiPortType(this); 283 PIOQueueThldCtrl = new PIOQueueThldCtrlType(this); 284 PIODataBufferThldCtrl = new PIODataBufferThldCtrlType(this); 285 PIOQueueSize = new PIOQueueSizeType(this); 286 AltQueueSize = new AltQueueSizeType(this); 287 PioIntrStatus = new PioIntrStatusType(this); 288 PioIntrStatusEnable = new PioIntrStatusEnableType(this); 289 PioIntrSignalEnable = new PioIntrSignalEnableType(this); 290 PioIntrForce = new PioIntrForceType(this); 291 PioControl = new PioControlType(this); 292 SecureFirmwareRecoveryInterfaceExtcapHeader = new SecureFirmwareRecoveryInterfaceExtcapHeaderType(this); 293 ProtCap0 = new ProtCap0Type(this); 294 ProtCap1 = new ProtCap1Type(this); 295 ProtCap2 = new ProtCap2Type(this); 296 ProtCap3 = new ProtCap3Type(this); 297 DeviceId0 = new DeviceId0Type(this); 298 DeviceId1 = new DeviceId1Type(this); 299 DeviceId2 = new DeviceId2Type(this); 300 DeviceId3 = new DeviceId3Type(this); 301 DeviceId4 = new DeviceId4Type(this); 302 DeviceId5 = new DeviceId5Type(this); 303 DeviceIdReserved = new DeviceIdReservedType(this); 304 DeviceStatus0 = new DeviceStatus0Type(this); 305 DeviceStatus1 = new DeviceStatus1Type(this); 306 DeviceReset = new DeviceResetType(this); 307 RecoveryCtrl = new RecoveryCtrlType(this); 308 RecoveryStatus = new RecoveryStatusType(this); 309 HwStatus = new HwStatusType(this); 310 IndirectFifoCtrl0 = new IndirectFifoCtrl0Type(this); 311 IndirectFifoCtrl1 = new IndirectFifoCtrl1Type(this); 312 IndirectFifoStatus0 = new IndirectFifoStatus0Type(this); 313 IndirectFifoStatus1 = new IndirectFifoStatus1Type(this); 314 IndirectFifoStatus2 = new IndirectFifoStatus2Type(this); 315 IndirectFifoStatus3 = new IndirectFifoStatus3Type(this); 316 IndirectFifoStatus4 = new IndirectFifoStatus4Type(this); 317 IndirectFifoReserved = new IndirectFifoReservedType(this); 318 IndirectFifoData = new IndirectFifoDataType(this); 319 StandbyControllerModeRegistersExtcapHeader = new StandbyControllerModeRegistersExtcapHeaderType(this); 320 StbyCrControl = new StbyCrControlType(this); 321 StbyCrDeviceAddr = new StbyCrDeviceAddrType(this); 322 StbyCrCapabilities = new StbyCrCapabilitiesType(this); 323 Rsvd0 = new Rsvd0Type(this); 324 StbyCrStatus = new StbyCrStatusType(this); 325 StbyCrDeviceChar = new StbyCrDeviceCharType(this); 326 StbyCrDevicePidLo = new StbyCrDevicePidLoType(this); 327 StbyCrIntrStatus = new StbyCrIntrStatusType(this); 328 Rsvd1 = new Rsvd1Type(this); 329 StbyCrIntrSignalEnable = new StbyCrIntrSignalEnableType(this); 330 StbyCrIntrForce = new StbyCrIntrForceType(this); 331 StbyCrCccConfigGetcaps = new StbyCrCccConfigGetcapsType(this); 332 StbyCrCccConfigRstactParams = new StbyCrCccConfigRstactParamsType(this); 333 StbyCrVirtDeviceAddr = new StbyCrVirtDeviceAddrType(this); 334 Rsvd3 = new Rsvd3Type(this); 335 TargetTransactionInterfaceRegistersExtcapHeader = new TargetTransactionInterfaceRegistersExtcapHeaderType(this); 336 Control = new ControlType(this); 337 Status = new StatusType(this); 338 TargetTransactionInterfaceResetControl = new TargetTransactionInterfaceResetControlType(this); 339 InterruptStatus = new InterruptStatusType(this); 340 InterruptEnable = new InterruptEnableType(this); 341 InterruptForce = new InterruptForceType(this); 342 RxDescQueuePort = new RxDescQueuePortType(this); 343 TxDescQueuePort = new TxDescQueuePortType(this); 344 PIOTxRxDataPort = new PIOTxRxDataPortType(this); 345 TargetTransactionInterfaceIbiPort = new TargetTransactionInterfaceIbiPortType(this); 346 TargetTransactionInterfaceQueueSize = new TargetTransactionInterfaceQueueSizeType(this); 347 IbiQueueSize = new IbiQueueSizeType(this); 348 TargetTransactionInterfaceQueueThldCtrl = new TargetTransactionInterfaceQueueThldCtrlType(this); 349 TargetTransactionInterfaceDataBufferThldCtrl = new TargetTransactionInterfaceDataBufferThldCtrlType(this); 350 SoCManagementInterfaceRegistersExtcapHeader = new SoCManagementInterfaceRegistersExtcapHeaderType(this); 351 SocMgmtControl = new SocMgmtControlType(this); 352 SocMgmtStatus = new SocMgmtStatusType(this); 353 SocMgmtRsvd0 = new SocMgmtRsvd0Type(this); 354 SocMgmtRsvd1 = new SocMgmtRsvd1Type(this); 355 SocMgmtRsvd2 = new SocMgmtRsvd2Type(this); 356 SocMgmtRsvd3 = new SocMgmtRsvd3Type(this); 357 SocPadConf = new SocPadConfType(this); 358 SocPadAttr = new SocPadAttrType(this); 359 SocMgmtFeature2 = new SocMgmtFeature2Type(this); 360 SocMgmtFeature3 = new SocMgmtFeature3Type(this); 361 TRReg = new TRRegType(this); 362 TFReg = new TFRegType(this); 363 TSuDatReg = new TSuDatRegType(this); 364 THdDatReg = new THdDatRegType(this); 365 THighReg = new THighRegType(this); 366 TLowReg = new TLowRegType(this); 367 THdStaReg = new THdStaRegType(this); 368 TSuStaReg = new TSuStaRegType(this); 369 TSuStoReg = new TSuStoRegType(this); 370 TFreeReg = new TFreeRegType(this); 371 TAvalReg = new TAvalRegType(this); 372 TIdleReg = new TIdleRegType(this); 373 ControllerConfigRegistersExtcapHeader = new ControllerConfigRegistersExtcapHeaderType(this); 374 ControllerConfig = new ControllerConfigType(this); 375 TerminationExtcapHeader = new TerminationExtcapHeaderType(this); 376 Dat = new Dat_DatMemoryContainer(); 377 Dct = new Dct_DctMemoryContainer(); 378 this.Init(); 379 } 380 Init()381 partial void Init(); 382 Reset()383 partial void Reset(); 384 IPeripheral.Reset()385 void IPeripheral.Reset() 386 { 387 this.Reset(); 388 RegistersCollection.Reset(); 389 } 390 IDoubleWordPeripheral.ReadDoubleWord(long offset)391 uint IDoubleWordPeripheral.ReadDoubleWord(long offset) 392 { 393 if(offset >= 1024 && offset < 1024L + Dat.Size) 394 { 395 return Dat.ReadDoubleWord(offset - 1024); 396 } 397 if(offset >= 2048 && offset < 2048L + Dct.Size) 398 { 399 return Dct.ReadDoubleWord(offset - 2048); 400 } 401 return RegistersCollection.Read(offset); 402 } 403 IDoubleWordPeripheral.WriteDoubleWord(long offset, uint value)404 void IDoubleWordPeripheral.WriteDoubleWord(long offset, uint value) 405 { 406 if(offset >= 1024 && offset < 1024L + Dat.Size) 407 { 408 Dat.WriteDoubleWord(offset - 1024, value); 409 return; 410 } 411 if(offset >= 2048 && offset < 2048L + Dct.Size) 412 { 413 Dct.WriteDoubleWord(offset - 2048, value); 414 return; 415 } 416 RegistersCollection.Write(offset, value); 417 } 418 419 public struct HciVersionType 420 { 421 /// <summary> Field "VERSION" at 0x0, width: 32 bits </summary> 422 public IValueRegisterField VERSION; 423 HciVersionTypeAntmicro.Renode.Peripherals.I3C.Caliptra_I3C.HciVersionType424 public HciVersionType(IProvidesRegisterCollection<DoubleWordRegisterCollection> parent) 425 { 426 parent.RegistersCollection.DefineRegister(0, 4294967295, true) 427 .WithValueField(0, 32, out VERSION, mode: FieldMode.Read, name: "VERSION"); 428 } 429 } 430 431 public struct HcControlType 432 { 433 /// <summary> Field "IBA_INCLUDE" at 0x0, width: 1 bits </summary> 434 public IFlagRegisterField IBA_INCLUDE; 435 /// <summary> Field "AUTOCMD_DATA_RPT" at 0x3, width: 1 bits </summary> 436 public IFlagRegisterField AUTOCMD_DATA_RPT; 437 /// <summary> Field "DATA_BYTE_ORDER_MODE" at 0x4, width: 1 bits </summary> 438 public IFlagRegisterField DATA_BYTE_ORDER_MODE; 439 /// <summary> Field "MODE_SELECTOR" at 0x6, width: 1 bits </summary> 440 public IFlagRegisterField MODE_SELECTOR; 441 /// <summary> Field "I2C_DEV_PRESENT" at 0x7, width: 1 bits </summary> 442 public IFlagRegisterField I2C_DEV_PRESENT; 443 /// <summary> Field "HOT_JOIN_CTRL" at 0x8, width: 1 bits </summary> 444 public IFlagRegisterField HOT_JOIN_CTRL; 445 /// <summary> Field "HALT_ON_CMD_SEQ_TIMEOUT" at 0xc, width: 1 bits </summary> 446 public IFlagRegisterField HALT_ON_CMD_SEQ_TIMEOUT; 447 /// <summary> Field "ABORT" at 0x1d, width: 1 bits </summary> 448 public IFlagRegisterField ABORT; 449 /// <summary> Field "RESUME" at 0x1e, width: 1 bits </summary> 450 public IFlagRegisterField RESUME; 451 /// <summary> Field "BUS_ENABLE" at 0x1f, width: 1 bits </summary> 452 public IFlagRegisterField BUS_ENABLE; 453 HcControlTypeAntmicro.Renode.Peripherals.I3C.Caliptra_I3C.HcControlType454 public HcControlType(IProvidesRegisterCollection<DoubleWordRegisterCollection> parent) 455 { 456 parent.RegistersCollection.DefineRegister(4, 64, true) 457 .WithFlag(0, out IBA_INCLUDE, name: "IBA_INCLUDE") 458 .WithFlag(3, out AUTOCMD_DATA_RPT, mode: FieldMode.Read, name: "AUTOCMD_DATA_RPT") 459 .WithFlag(4, out DATA_BYTE_ORDER_MODE, mode: FieldMode.Read, name: "DATA_BYTE_ORDER_MODE") 460 .WithFlag(6, out MODE_SELECTOR, mode: FieldMode.Read, name: "MODE_SELECTOR") 461 .WithFlag(7, out I2C_DEV_PRESENT, name: "I2C_DEV_PRESENT") 462 .WithFlag(8, out HOT_JOIN_CTRL, name: "HOT_JOIN_CTRL") 463 .WithFlag(12, out HALT_ON_CMD_SEQ_TIMEOUT, name: "HALT_ON_CMD_SEQ_TIMEOUT") 464 .WithFlag(29, out ABORT, name: "ABORT") 465 .WithFlag(30, out RESUME, mode: FieldMode.Read | FieldMode.WriteOneToClear, name: "RESUME") 466 .WithFlag(31, out BUS_ENABLE, name: "BUS_ENABLE"); 467 } 468 } 469 470 public struct ControllerDeviceAddrType 471 { 472 /// <summary> Field "DYNAMIC_ADDR" at 0x10, width: 7 bits </summary> 473 public IValueRegisterField DYNAMIC_ADDR; 474 /// <summary> Field "DYNAMIC_ADDR_VALID" at 0x1f, width: 1 bits </summary> 475 public IFlagRegisterField DYNAMIC_ADDR_VALID; 476 ControllerDeviceAddrTypeAntmicro.Renode.Peripherals.I3C.Caliptra_I3C.ControllerDeviceAddrType477 public ControllerDeviceAddrType(IProvidesRegisterCollection<DoubleWordRegisterCollection> parent) 478 { 479 parent.RegistersCollection.DefineRegister(8, 0, true) 480 .WithValueField(16, 7, out DYNAMIC_ADDR, name: "DYNAMIC_ADDR") 481 .WithFlag(31, out DYNAMIC_ADDR_VALID, name: "DYNAMIC_ADDR_VALID"); 482 } 483 } 484 485 public struct ResetControlType 486 { 487 public IFlagRegisterField SOFT_RST; 488 public IFlagRegisterField CMD_QUEUE_RST; 489 public IFlagRegisterField RESP_QUEUE_RST; 490 public IFlagRegisterField TX_FIFO_RST; 491 public IFlagRegisterField RX_FIFO_RST; 492 public IFlagRegisterField IBI_QUEUE_RST; 493 ResetControlTypeAntmicro.Renode.Peripherals.I3C.Caliptra_I3C.ResetControlType494 public ResetControlType(IProvidesRegisterCollection<DoubleWordRegisterCollection> parent) 495 { 496 parent.RegistersCollection.DefineRegister(16, 0) 497 .WithFlag(0, out SOFT_RST, name: "SOFT_RST") 498 .WithFlag(1, out CMD_QUEUE_RST, name: "CMD_QUEUE_RST") 499 .WithFlag(2, out RESP_QUEUE_RST, name: "RESP_QUEUE_RST") 500 .WithFlag(3, out TX_FIFO_RST, name: "TX_FIFO_RST") 501 .WithFlag(4, out RX_FIFO_RST, name: "RX_FIFO_RST") 502 .WithFlag(5, out IBI_QUEUE_RST, name: "IBI_QUEUE_RST"); 503 } 504 } 505 506 public struct HcCapabilitiesType 507 { 508 /// <summary> Field "COMBO_COMMAND" at 0x2, width: 1 bits </summary> 509 public IFlagRegisterField COMBO_COMMAND; 510 /// <summary> Field "AUTO_COMMAND" at 0x3, width: 1 bits </summary> 511 public IFlagRegisterField AUTO_COMMAND; 512 /// <summary> Field "STANDBY_CR_CAP" at 0x5, width: 1 bits </summary> 513 public IFlagRegisterField STANDBY_CR_CAP; 514 /// <summary> Field "HDR_DDR_EN" at 0x6, width: 1 bits </summary> 515 public IFlagRegisterField HDR_DDR_EN; 516 /// <summary> Field "HDR_TS_EN" at 0x7, width: 1 bits </summary> 517 public IFlagRegisterField HDR_TS_EN; 518 /// <summary> Field "CMD_CCC_DEFBYTE" at 0xa, width: 1 bits </summary> 519 public IFlagRegisterField CMD_CCC_DEFBYTE; 520 /// <summary> Field "IBI_DATA_ABORT_EN" at 0xb, width: 1 bits </summary> 521 public IFlagRegisterField IBI_DATA_ABORT_EN; 522 /// <summary> Field "IBI_CREDIT_COUNT_EN" at 0xc, width: 1 bits </summary> 523 public IFlagRegisterField IBI_CREDIT_COUNT_EN; 524 /// <summary> Field "SCHEDULED_COMMANDS_EN" at 0xd, width: 1 bits </summary> 525 public IFlagRegisterField SCHEDULED_COMMANDS_EN; 526 /// <summary> Field "CMD_SIZE" at 0x14, width: 2 bits </summary> 527 public IValueRegisterField CMD_SIZE; 528 /// <summary> Field "SG_CAPABILITY_CR_EN" at 0x1c, width: 1 bits </summary> 529 public IFlagRegisterField SG_CAPABILITY_CR_EN; 530 /// <summary> Field "SG_CAPABILITY_IBI_EN" at 0x1d, width: 1 bits </summary> 531 public IFlagRegisterField SG_CAPABILITY_IBI_EN; 532 /// <summary> Field "SG_CAPABILITY_DC_EN" at 0x1e, width: 1 bits </summary> 533 public IFlagRegisterField SG_CAPABILITY_DC_EN; 534 HcCapabilitiesTypeAntmicro.Renode.Peripherals.I3C.Caliptra_I3C.HcCapabilitiesType535 public HcCapabilitiesType(IProvidesRegisterCollection<DoubleWordRegisterCollection> parent) 536 { 537 parent.RegistersCollection.DefineRegister(12, 1024, true) 538 .WithFlag(2, out COMBO_COMMAND, mode: FieldMode.Read, name: "COMBO_COMMAND") 539 .WithFlag(3, out AUTO_COMMAND, mode: FieldMode.Read, name: "AUTO_COMMAND") 540 .WithFlag(5, out STANDBY_CR_CAP, mode: FieldMode.Read, name: "STANDBY_CR_CAP") 541 .WithFlag(6, out HDR_DDR_EN, mode: FieldMode.Read, name: "HDR_DDR_EN") 542 .WithFlag(7, out HDR_TS_EN, mode: FieldMode.Read, name: "HDR_TS_EN") 543 .WithFlag(10, out CMD_CCC_DEFBYTE, mode: FieldMode.Read, name: "CMD_CCC_DEFBYTE") 544 .WithFlag(11, out IBI_DATA_ABORT_EN, mode: FieldMode.Read, name: "IBI_DATA_ABORT_EN") 545 .WithFlag(12, out IBI_CREDIT_COUNT_EN, mode: FieldMode.Read, name: "IBI_CREDIT_COUNT_EN") 546 .WithFlag(13, out SCHEDULED_COMMANDS_EN, mode: FieldMode.Read, name: "SCHEDULED_COMMANDS_EN") 547 .WithValueField(20, 2, out CMD_SIZE, mode: FieldMode.Read, name: "CMD_SIZE") 548 .WithFlag(28, out SG_CAPABILITY_CR_EN, mode: FieldMode.Read, name: "SG_CAPABILITY_CR_EN") 549 .WithFlag(29, out SG_CAPABILITY_IBI_EN, mode: FieldMode.Read, name: "SG_CAPABILITY_IBI_EN") 550 .WithFlag(30, out SG_CAPABILITY_DC_EN, mode: FieldMode.Read, name: "SG_CAPABILITY_DC_EN"); 551 } 552 } 553 554 public struct TargetTransactionInterfaceResetControlType 555 { 556 /// <summary> Field "SOFT_RST" at 0x0, width: 1 bits </summary> 557 public IFlagRegisterField SOFT_RST; 558 /// <summary> Field "TX_DESC_RST" at 0x1, width: 1 bits </summary> 559 public IFlagRegisterField TX_DESC_RST; 560 /// <summary> Field "RX_DESC_RST" at 0x2, width: 1 bits </summary> 561 public IFlagRegisterField RX_DESC_RST; 562 /// <summary> Field "TX_DATA_RST" at 0x3, width: 1 bits </summary> 563 public IFlagRegisterField TX_DATA_RST; 564 /// <summary> Field "RX_DATA_RST" at 0x4, width: 1 bits </summary> 565 public IFlagRegisterField RX_DATA_RST; 566 /// <summary> Field "IBI_QUEUE_RST" at 0x5, width: 1 bits </summary> 567 public IFlagRegisterField IBI_QUEUE_RST; 568 TargetTransactionInterfaceResetControlTypeAntmicro.Renode.Peripherals.I3C.Caliptra_I3C.TargetTransactionInterfaceResetControlType569 public TargetTransactionInterfaceResetControlType(IProvidesRegisterCollection<DoubleWordRegisterCollection> parent) 570 { 571 parent.RegistersCollection.DefineRegister(460, 0, true) 572 .WithFlag(0, out SOFT_RST, name: "SOFT_RST") 573 .WithFlag(1, out TX_DESC_RST, name: "TX_DESC_RST") 574 .WithFlag(2, out RX_DESC_RST, name: "RX_DESC_RST") 575 .WithFlag(3, out TX_DATA_RST, name: "TX_DATA_RST") 576 .WithFlag(4, out RX_DATA_RST, name: "RX_DATA_RST") 577 .WithFlag(5, out IBI_QUEUE_RST, name: "IBI_QUEUE_RST"); 578 } 579 } 580 581 public struct PresentStateType 582 { 583 /// <summary> Field "AC_CURRENT_OWN" at 0x2, width: 1 bits </summary> 584 public IFlagRegisterField AC_CURRENT_OWN; 585 PresentStateTypeAntmicro.Renode.Peripherals.I3C.Caliptra_I3C.PresentStateType586 public PresentStateType(IProvidesRegisterCollection<DoubleWordRegisterCollection> parent) 587 { 588 parent.RegistersCollection.DefineRegister(20, 0, true) 589 .WithFlag(2, out AC_CURRENT_OWN, mode: FieldMode.Read, name: "AC_CURRENT_OWN"); 590 } 591 } 592 593 public struct IntrStatusType 594 { 595 /// <summary> Field "HC_INTERNAL_ERR_STAT" at 0xa, width: 1 bits </summary> 596 public IFlagRegisterField HC_INTERNAL_ERR_STAT; 597 /// <summary> Field "HC_SEQ_CANCEL_STAT" at 0xb, width: 1 bits </summary> 598 public IFlagRegisterField HC_SEQ_CANCEL_STAT; 599 /// <summary> Field "HC_WARN_CMD_SEQ_STALL_STAT" at 0xc, width: 1 bits </summary> 600 public IFlagRegisterField HC_WARN_CMD_SEQ_STALL_STAT; 601 /// <summary> Field "HC_ERR_CMD_SEQ_TIMEOUT_STAT" at 0xd, width: 1 bits </summary> 602 public IFlagRegisterField HC_ERR_CMD_SEQ_TIMEOUT_STAT; 603 /// <summary> Field "SCHED_CMD_MISSED_TICK_STAT" at 0xe, width: 1 bits </summary> 604 public IFlagRegisterField SCHED_CMD_MISSED_TICK_STAT; 605 IntrStatusTypeAntmicro.Renode.Peripherals.I3C.Caliptra_I3C.IntrStatusType606 public IntrStatusType(IProvidesRegisterCollection<DoubleWordRegisterCollection> parent) 607 { 608 parent.RegistersCollection.DefineRegister(32, 0, true) 609 .WithFlag(10, out HC_INTERNAL_ERR_STAT, mode: FieldMode.Read | FieldMode.WriteOneToClear, name: "HC_INTERNAL_ERR_STAT") 610 .WithFlag(11, out HC_SEQ_CANCEL_STAT, mode: FieldMode.Read | FieldMode.WriteOneToClear, name: "HC_SEQ_CANCEL_STAT") 611 .WithFlag(12, out HC_WARN_CMD_SEQ_STALL_STAT, mode: FieldMode.Read | FieldMode.WriteOneToClear, name: "HC_WARN_CMD_SEQ_STALL_STAT") 612 .WithFlag(13, out HC_ERR_CMD_SEQ_TIMEOUT_STAT, mode: FieldMode.Read | FieldMode.WriteOneToClear, name: "HC_ERR_CMD_SEQ_TIMEOUT_STAT") 613 .WithFlag(14, out SCHED_CMD_MISSED_TICK_STAT, mode: FieldMode.Read | FieldMode.WriteOneToClear, name: "SCHED_CMD_MISSED_TICK_STAT"); 614 } 615 } 616 617 public struct IntrStatusEnableType 618 { 619 /// <summary> Field "HC_INTERNAL_ERR_STAT_EN" at 0xa, width: 1 bits </summary> 620 public IFlagRegisterField HC_INTERNAL_ERR_STAT_EN; 621 /// <summary> Field "HC_SEQ_CANCEL_STAT_EN" at 0xb, width: 1 bits </summary> 622 public IFlagRegisterField HC_SEQ_CANCEL_STAT_EN; 623 /// <summary> Field "HC_WARN_CMD_SEQ_STALL_STAT_EN" at 0xc, width: 1 bits </summary> 624 public IFlagRegisterField HC_WARN_CMD_SEQ_STALL_STAT_EN; 625 /// <summary> Field "HC_ERR_CMD_SEQ_TIMEOUT_STAT_EN" at 0xd, width: 1 bits </summary> 626 public IFlagRegisterField HC_ERR_CMD_SEQ_TIMEOUT_STAT_EN; 627 /// <summary> Field "SCHED_CMD_MISSED_TICK_STAT_EN" at 0xe, width: 1 bits </summary> 628 public IFlagRegisterField SCHED_CMD_MISSED_TICK_STAT_EN; 629 IntrStatusEnableTypeAntmicro.Renode.Peripherals.I3C.Caliptra_I3C.IntrStatusEnableType630 public IntrStatusEnableType(IProvidesRegisterCollection<DoubleWordRegisterCollection> parent) 631 { 632 parent.RegistersCollection.DefineRegister(36, 0, true) 633 .WithFlag(10, out HC_INTERNAL_ERR_STAT_EN, name: "HC_INTERNAL_ERR_STAT_EN") 634 .WithFlag(11, out HC_SEQ_CANCEL_STAT_EN, name: "HC_SEQ_CANCEL_STAT_EN") 635 .WithFlag(12, out HC_WARN_CMD_SEQ_STALL_STAT_EN, name: "HC_WARN_CMD_SEQ_STALL_STAT_EN") 636 .WithFlag(13, out HC_ERR_CMD_SEQ_TIMEOUT_STAT_EN, name: "HC_ERR_CMD_SEQ_TIMEOUT_STAT_EN") 637 .WithFlag(14, out SCHED_CMD_MISSED_TICK_STAT_EN, name: "SCHED_CMD_MISSED_TICK_STAT_EN"); 638 } 639 } 640 641 public struct IntrSignalEnableType 642 { 643 /// <summary> Field "HC_INTERNAL_ERR_SIGNAL_EN" at 0xa, width: 1 bits </summary> 644 public IFlagRegisterField HC_INTERNAL_ERR_SIGNAL_EN; 645 /// <summary> Field "HC_SEQ_CANCEL_SIGNAL_EN" at 0xb, width: 1 bits </summary> 646 public IFlagRegisterField HC_SEQ_CANCEL_SIGNAL_EN; 647 /// <summary> Field "HC_WARN_CMD_SEQ_STALL_SIGNAL_EN" at 0xc, width: 1 bits </summary> 648 public IFlagRegisterField HC_WARN_CMD_SEQ_STALL_SIGNAL_EN; 649 /// <summary> Field "HC_ERR_CMD_SEQ_TIMEOUT_SIGNAL_EN" at 0xd, width: 1 bits </summary> 650 public IFlagRegisterField HC_ERR_CMD_SEQ_TIMEOUT_SIGNAL_EN; 651 /// <summary> Field "SCHED_CMD_MISSED_TICK_SIGNAL_EN" at 0xe, width: 1 bits </summary> 652 public IFlagRegisterField SCHED_CMD_MISSED_TICK_SIGNAL_EN; 653 IntrSignalEnableTypeAntmicro.Renode.Peripherals.I3C.Caliptra_I3C.IntrSignalEnableType654 public IntrSignalEnableType(IProvidesRegisterCollection<DoubleWordRegisterCollection> parent) 655 { 656 parent.RegistersCollection.DefineRegister(40, 0, true) 657 .WithFlag(10, out HC_INTERNAL_ERR_SIGNAL_EN, name: "HC_INTERNAL_ERR_SIGNAL_EN") 658 .WithFlag(11, out HC_SEQ_CANCEL_SIGNAL_EN, name: "HC_SEQ_CANCEL_SIGNAL_EN") 659 .WithFlag(12, out HC_WARN_CMD_SEQ_STALL_SIGNAL_EN, name: "HC_WARN_CMD_SEQ_STALL_SIGNAL_EN") 660 .WithFlag(13, out HC_ERR_CMD_SEQ_TIMEOUT_SIGNAL_EN, name: "HC_ERR_CMD_SEQ_TIMEOUT_SIGNAL_EN") 661 .WithFlag(14, out SCHED_CMD_MISSED_TICK_SIGNAL_EN, name: "SCHED_CMD_MISSED_TICK_SIGNAL_EN"); 662 } 663 } 664 665 public struct IntrForceType 666 { 667 /// <summary> Field "HC_INTERNAL_ERR_FORCE" at 0xa, width: 1 bits </summary> 668 public IFlagRegisterField HC_INTERNAL_ERR_FORCE; 669 /// <summary> Field "HC_SEQ_CANCEL_FORCE" at 0xb, width: 1 bits </summary> 670 public IFlagRegisterField HC_SEQ_CANCEL_FORCE; 671 /// <summary> Field "HC_WARN_CMD_SEQ_STALL_FORCE" at 0xc, width: 1 bits </summary> 672 public IFlagRegisterField HC_WARN_CMD_SEQ_STALL_FORCE; 673 /// <summary> Field "HC_ERR_CMD_SEQ_TIMEOUT_FORCE" at 0xd, width: 1 bits </summary> 674 public IFlagRegisterField HC_ERR_CMD_SEQ_TIMEOUT_FORCE; 675 /// <summary> Field "SCHED_CMD_MISSED_TICK_FORCE" at 0xe, width: 1 bits </summary> 676 public IFlagRegisterField SCHED_CMD_MISSED_TICK_FORCE; 677 IntrForceTypeAntmicro.Renode.Peripherals.I3C.Caliptra_I3C.IntrForceType678 public IntrForceType(IProvidesRegisterCollection<DoubleWordRegisterCollection> parent) 679 { 680 parent.RegistersCollection.DefineRegister(44, 0, true) 681 .WithFlag(10, out HC_INTERNAL_ERR_FORCE, mode: FieldMode.Write, name: "HC_INTERNAL_ERR_FORCE") 682 .WithFlag(11, out HC_SEQ_CANCEL_FORCE, mode: FieldMode.Write, name: "HC_SEQ_CANCEL_FORCE") 683 .WithFlag(12, out HC_WARN_CMD_SEQ_STALL_FORCE, mode: FieldMode.Write, name: "HC_WARN_CMD_SEQ_STALL_FORCE") 684 .WithFlag(13, out HC_ERR_CMD_SEQ_TIMEOUT_FORCE, mode: FieldMode.Write, name: "HC_ERR_CMD_SEQ_TIMEOUT_FORCE") 685 .WithFlag(14, out SCHED_CMD_MISSED_TICK_FORCE, mode: FieldMode.Write, name: "SCHED_CMD_MISSED_TICK_FORCE"); 686 } 687 } 688 689 public struct DatSectionOffsetType 690 { 691 /// <summary> Field "TABLE_OFFSET" at 0x0, width: 12 bits </summary> 692 public IValueRegisterField TABLE_OFFSET; 693 /// <summary> Field "TABLE_SIZE" at 0xc, width: 7 bits </summary> 694 public IValueRegisterField TABLE_SIZE; 695 /// <summary> Field "ENTRY_SIZE" at 0x1c, width: 4 bits </summary> 696 public IValueRegisterField ENTRY_SIZE; 697 DatSectionOffsetTypeAntmicro.Renode.Peripherals.I3C.Caliptra_I3C.DatSectionOffsetType698 public DatSectionOffsetType(IProvidesRegisterCollection<DoubleWordRegisterCollection> parent) 699 { 700 parent.RegistersCollection.DefineRegister(48, 524287, true) 701 .WithValueField(0, 12, out TABLE_OFFSET, mode: FieldMode.Read, name: "TABLE_OFFSET") 702 .WithValueField(12, 7, out TABLE_SIZE, mode: FieldMode.Read, name: "TABLE_SIZE") 703 .WithValueField(28, 4, out ENTRY_SIZE, mode: FieldMode.Read, name: "ENTRY_SIZE"); 704 } 705 } 706 707 public struct DctSectionOffsetType 708 { 709 /// <summary> Field "TABLE_OFFSET" at 0x0, width: 12 bits </summary> 710 public IValueRegisterField TABLE_OFFSET; 711 /// <summary> Field "TABLE_SIZE" at 0xc, width: 7 bits </summary> 712 public IValueRegisterField TABLE_SIZE; 713 /// <summary> Field "TABLE_INDEX" at 0x13, width: 5 bits </summary> 714 public IValueRegisterField TABLE_INDEX; 715 /// <summary> Field "ENTRY_SIZE" at 0x1c, width: 4 bits </summary> 716 public IValueRegisterField ENTRY_SIZE; 717 DctSectionOffsetTypeAntmicro.Renode.Peripherals.I3C.Caliptra_I3C.DctSectionOffsetType718 public DctSectionOffsetType(IProvidesRegisterCollection<DoubleWordRegisterCollection> parent) 719 { 720 parent.RegistersCollection.DefineRegister(52, 524287, true) 721 .WithValueField(0, 12, out TABLE_OFFSET, mode: FieldMode.Read, name: "TABLE_OFFSET") 722 .WithValueField(12, 7, out TABLE_SIZE, mode: FieldMode.Read, name: "TABLE_SIZE") 723 .WithValueField(19, 5, out TABLE_INDEX, name: "TABLE_INDEX") 724 .WithValueField(28, 4, out ENTRY_SIZE, mode: FieldMode.Read, name: "ENTRY_SIZE"); 725 } 726 } 727 728 public struct RingHeadersSectionOffsetType 729 { 730 /// <summary> Field "SECTION_OFFSET" at 0x0, width: 16 bits </summary> 731 public IValueRegisterField SECTION_OFFSET; 732 RingHeadersSectionOffsetTypeAntmicro.Renode.Peripherals.I3C.Caliptra_I3C.RingHeadersSectionOffsetType733 public RingHeadersSectionOffsetType(IProvidesRegisterCollection<DoubleWordRegisterCollection> parent) 734 { 735 parent.RegistersCollection.DefineRegister(56, 0, true) 736 .WithValueField(0, 16, out SECTION_OFFSET, mode: FieldMode.Read, name: "SECTION_OFFSET"); 737 } 738 } 739 740 public struct PioSectionOffsetType 741 { 742 /// <summary> Field "SECTION_OFFSET" at 0x0, width: 16 bits </summary> 743 public IValueRegisterField SECTION_OFFSET; 744 PioSectionOffsetTypeAntmicro.Renode.Peripherals.I3C.Caliptra_I3C.PioSectionOffsetType745 public PioSectionOffsetType(IProvidesRegisterCollection<DoubleWordRegisterCollection> parent) 746 { 747 parent.RegistersCollection.DefineRegister(60, 65535, true) 748 .WithValueField(0, 16, out SECTION_OFFSET, mode: FieldMode.Read, name: "SECTION_OFFSET"); 749 } 750 } 751 752 public struct ExtCapsSectionOffsetType 753 { 754 /// <summary> Field "SECTION_OFFSET" at 0x0, width: 16 bits </summary> 755 public IValueRegisterField SECTION_OFFSET; 756 ExtCapsSectionOffsetTypeAntmicro.Renode.Peripherals.I3C.Caliptra_I3C.ExtCapsSectionOffsetType757 public ExtCapsSectionOffsetType(IProvidesRegisterCollection<DoubleWordRegisterCollection> parent) 758 { 759 parent.RegistersCollection.DefineRegister(64, 65535, true) 760 .WithValueField(0, 16, out SECTION_OFFSET, mode: FieldMode.Read, name: "SECTION_OFFSET"); 761 } 762 } 763 764 public struct IntCtrlCmdsEnType 765 { 766 /// <summary> Field "ICC_SUPPORT" at 0x0, width: 1 bits </summary> 767 public IFlagRegisterField ICC_SUPPORT; 768 /// <summary> Field "MIPI_CMDS_SUPPORTED" at 0x1, width: 15 bits </summary> 769 public IValueRegisterField MIPI_CMDS_SUPPORTED; 770 IntCtrlCmdsEnTypeAntmicro.Renode.Peripherals.I3C.Caliptra_I3C.IntCtrlCmdsEnType771 public IntCtrlCmdsEnType(IProvidesRegisterCollection<DoubleWordRegisterCollection> parent) 772 { 773 parent.RegistersCollection.DefineRegister(76, 65535, true) 774 .WithFlag(0, out ICC_SUPPORT, mode: FieldMode.Read, name: "ICC_SUPPORT") 775 .WithValueField(1, 15, out MIPI_CMDS_SUPPORTED, mode: FieldMode.Read, name: "MIPI_CMDS_SUPPORTED"); 776 } 777 } 778 779 public struct IbiNotifyCtrlType 780 { 781 /// <summary> Field "NOTIFY_HJ_REJECTED" at 0x0, width: 1 bits </summary> 782 public IFlagRegisterField NOTIFY_HJ_REJECTED; 783 /// <summary> Field "NOTIFY_CRR_REJECTED" at 0x1, width: 1 bits </summary> 784 public IFlagRegisterField NOTIFY_CRR_REJECTED; 785 /// <summary> Field "NOTIFY_IBI_REJECTED" at 0x3, width: 1 bits </summary> 786 public IFlagRegisterField NOTIFY_IBI_REJECTED; 787 IbiNotifyCtrlTypeAntmicro.Renode.Peripherals.I3C.Caliptra_I3C.IbiNotifyCtrlType788 public IbiNotifyCtrlType(IProvidesRegisterCollection<DoubleWordRegisterCollection> parent) 789 { 790 parent.RegistersCollection.DefineRegister(88, 0, true) 791 .WithFlag(0, out NOTIFY_HJ_REJECTED, name: "NOTIFY_HJ_REJECTED") 792 .WithFlag(1, out NOTIFY_CRR_REJECTED, name: "NOTIFY_CRR_REJECTED") 793 .WithFlag(3, out NOTIFY_IBI_REJECTED, name: "NOTIFY_IBI_REJECTED"); 794 } 795 } 796 797 public struct IbiDataAbortCtrlType 798 { 799 /// <summary> Field "MATCH_IBI_ID" at 0x8, width: 8 bits </summary> 800 public IValueRegisterField MATCH_IBI_ID; 801 /// <summary> Field "AFTER_N_CHUNKS" at 0x10, width: 2 bits </summary> 802 public IValueRegisterField AFTER_N_CHUNKS; 803 /// <summary> Field "MATCH_STATUS_TYPE" at 0x12, width: 3 bits </summary> 804 public IValueRegisterField MATCH_STATUS_TYPE; 805 /// <summary> Field "IBI_DATA_ABORT_MON" at 0x1f, width: 1 bits </summary> 806 public IFlagRegisterField IBI_DATA_ABORT_MON; 807 IbiDataAbortCtrlTypeAntmicro.Renode.Peripherals.I3C.Caliptra_I3C.IbiDataAbortCtrlType808 public IbiDataAbortCtrlType(IProvidesRegisterCollection<DoubleWordRegisterCollection> parent) 809 { 810 parent.RegistersCollection.DefineRegister(92, 0, true) 811 .WithValueField(8, 8, out MATCH_IBI_ID, name: "MATCH_IBI_ID") 812 .WithValueField(16, 2, out AFTER_N_CHUNKS, name: "AFTER_N_CHUNKS") 813 .WithValueField(18, 3, out MATCH_STATUS_TYPE, name: "MATCH_STATUS_TYPE") 814 .WithFlag(31, out IBI_DATA_ABORT_MON, name: "IBI_DATA_ABORT_MON"); 815 } 816 } 817 818 public struct DevCtxBaseLoType 819 { 820 /// <summary> Field "BASE_LO" at 0x0, width: 1 bits </summary> 821 public IFlagRegisterField BASE_LO; 822 DevCtxBaseLoTypeAntmicro.Renode.Peripherals.I3C.Caliptra_I3C.DevCtxBaseLoType823 public DevCtxBaseLoType(IProvidesRegisterCollection<DoubleWordRegisterCollection> parent) 824 { 825 parent.RegistersCollection.DefineRegister(96, 0, true) 826 .WithFlag(0, out BASE_LO, name: "BASE_LO"); 827 } 828 } 829 830 public struct DevCtxBaseHiType 831 { 832 /// <summary> Field "BASE_HI" at 0x0, width: 1 bits </summary> 833 public IFlagRegisterField BASE_HI; 834 DevCtxBaseHiTypeAntmicro.Renode.Peripherals.I3C.Caliptra_I3C.DevCtxBaseHiType835 public DevCtxBaseHiType(IProvidesRegisterCollection<DoubleWordRegisterCollection> parent) 836 { 837 parent.RegistersCollection.DefineRegister(100, 0, true) 838 .WithFlag(0, out BASE_HI, name: "BASE_HI"); 839 } 840 } 841 842 public struct DevCtxSgType 843 { 844 /// <summary> Field "LIST_SIZE" at 0x0, width: 16 bits </summary> 845 public IValueRegisterField LIST_SIZE; 846 /// <summary> Field "BLP" at 0x1f, width: 1 bits </summary> 847 public IFlagRegisterField BLP; 848 DevCtxSgTypeAntmicro.Renode.Peripherals.I3C.Caliptra_I3C.DevCtxSgType849 public DevCtxSgType(IProvidesRegisterCollection<DoubleWordRegisterCollection> parent) 850 { 851 parent.RegistersCollection.DefineRegister(104, 0, true) 852 .WithValueField(0, 16, out LIST_SIZE, mode: FieldMode.Read, name: "LIST_SIZE") 853 .WithFlag(31, out BLP, mode: FieldMode.Read, name: "BLP"); 854 } 855 } 856 857 public struct CommandPortType 858 { 859 /// <summary> Field "COMMAND_DATA" at 0x0, width: 32 bits </summary> 860 public IValueRegisterField COMMAND_DATA; 861 CommandPortTypeAntmicro.Renode.Peripherals.I3C.Caliptra_I3C.CommandPortType862 public CommandPortType(IProvidesRegisterCollection<DoubleWordRegisterCollection> parent) 863 { 864 parent.RegistersCollection.DefineRegister(128, 0, true) 865 .WithValueField(0, 32, out COMMAND_DATA, mode: FieldMode.Write, name: "COMMAND_DATA"); 866 } 867 } 868 869 public struct PIOTxRxDataPortType 870 { 871 public IValueRegisterField DATA; 872 PIOTxRxDataPortTypeAntmicro.Renode.Peripherals.I3C.Caliptra_I3C.PIOTxRxDataPortType873 public PIOTxRxDataPortType(IProvidesRegisterCollection<DoubleWordRegisterCollection> parent) 874 { 875 parent.RegistersCollection.DefineRegister(136) 876 .WithValueField(0, 32, out DATA, name: "TX_DATA/RX_DATA"); 877 } 878 } 879 880 public struct ResponsePortType 881 { 882 /// <summary> Field "RESPONSE_DATA" at 0x0, width: 32 bits </summary> 883 public IValueRegisterField RESPONSE_DATA; 884 ResponsePortTypeAntmicro.Renode.Peripherals.I3C.Caliptra_I3C.ResponsePortType885 public ResponsePortType(IProvidesRegisterCollection<DoubleWordRegisterCollection> parent) 886 { 887 parent.RegistersCollection.DefineRegister(132, 0, true) 888 .WithValueField(0, 32, out RESPONSE_DATA, mode: FieldMode.Read, name: "RESPONSE_DATA"); 889 } 890 } 891 892 public struct TargetTransactionInterfaceTxDataPortType 893 { 894 /// <summary> Field "TX_DATA" at 0x0, width: 32 bits </summary> 895 public IValueRegisterField TX_DATA; 896 TargetTransactionInterfaceTxDataPortTypeAntmicro.Renode.Peripherals.I3C.Caliptra_I3C.TargetTransactionInterfaceTxDataPortType897 public TargetTransactionInterfaceTxDataPortType(IProvidesRegisterCollection<DoubleWordRegisterCollection> parent) 898 { 899 parent.RegistersCollection.DefineRegister(488, 0, true) 900 .WithValueField(0, 32, out TX_DATA, mode: FieldMode.Write, name: "TX_DATA"); 901 } 902 } 903 904 public struct TargetTransactionInterfaceRxDataPortType 905 { 906 /// <summary> Field "RX_DATA" at 0x0, width: 32 bits </summary> 907 public IValueRegisterField RX_DATA; 908 TargetTransactionInterfaceRxDataPortTypeAntmicro.Renode.Peripherals.I3C.Caliptra_I3C.TargetTransactionInterfaceRxDataPortType909 public TargetTransactionInterfaceRxDataPortType(IProvidesRegisterCollection<DoubleWordRegisterCollection> parent) 910 { 911 parent.RegistersCollection.DefineRegister(480, 0, true) 912 .WithValueField(0, 32, out RX_DATA, mode: FieldMode.Read, name: "RX_DATA"); 913 } 914 } 915 916 public struct PIOIbiPortType 917 { 918 public IValueRegisterField IBI_DATA; 919 PIOIbiPortTypeAntmicro.Renode.Peripherals.I3C.Caliptra_I3C.PIOIbiPortType920 public PIOIbiPortType(IProvidesRegisterCollection<DoubleWordRegisterCollection> parent) 921 { 922 parent.RegistersCollection.DefineRegister(140) 923 .WithValueField(0, 32, out IBI_DATA, mode: FieldMode.Read, name: "IBI_DATA"); 924 } 925 } 926 927 public struct TargetTransactionInterfaceIbiPortType 928 { 929 /// <summary> Field "IBI_DATA" at 0x0, width: 32 bits </summary> 930 public IValueRegisterField IBI_DATA; 931 TargetTransactionInterfaceIbiPortTypeAntmicro.Renode.Peripherals.I3C.Caliptra_I3C.TargetTransactionInterfaceIbiPortType932 public TargetTransactionInterfaceIbiPortType(IProvidesRegisterCollection<DoubleWordRegisterCollection> parent) 933 { 934 parent.RegistersCollection.DefineRegister(492, 0, true) 935 .WithValueField(0, 32, out IBI_DATA, mode: FieldMode.Write, name: "IBI_DATA"); 936 } 937 } 938 939 public struct PIOQueueThldCtrlType 940 { 941 public IValueRegisterField CMD_EMPTY_BUF_THLD; 942 public IValueRegisterField RESP_BUF_THLD; 943 public IValueRegisterField IBI_DATA_SEGMENT_SIZE; 944 public IValueRegisterField IBI_STATUS_THLD; 945 PIOQueueThldCtrlTypeAntmicro.Renode.Peripherals.I3C.Caliptra_I3C.PIOQueueThldCtrlType946 public PIOQueueThldCtrlType(IProvidesRegisterCollection<DoubleWordRegisterCollection> parent) 947 { 948 parent.RegistersCollection.DefineRegister(144, 16843009) 949 .WithValueField(0, 8, out CMD_EMPTY_BUF_THLD, name: "CMD_EMPTY_BUF_THLD") 950 .WithValueField(8, 8, out RESP_BUF_THLD, name: "RESP_BUF_THLD") 951 .WithValueField(16, 8, out IBI_DATA_SEGMENT_SIZE, name: "IBI_DATA_SEGMENT_SIZE") 952 .WithValueField(24, 8, out IBI_STATUS_THLD, name: "IBI_STATUS_THLD"); 953 } 954 } 955 956 public struct TargetTransactionInterfaceQueueThldCtrlType 957 { 958 /// <summary> Field "TX_DESC_THLD" at 0x0, width: 8 bits </summary> 959 public IValueRegisterField TX_DESC_THLD; 960 /// <summary> Field "RX_DESC_THLD" at 0x8, width: 8 bits </summary> 961 public IValueRegisterField RX_DESC_THLD; 962 /// <summary> Field "IBI_THLD" at 0x18, width: 8 bits </summary> 963 public IValueRegisterField IBI_THLD; 964 TargetTransactionInterfaceQueueThldCtrlTypeAntmicro.Renode.Peripherals.I3C.Caliptra_I3C.TargetTransactionInterfaceQueueThldCtrlType965 public TargetTransactionInterfaceQueueThldCtrlType(IProvidesRegisterCollection<DoubleWordRegisterCollection> parent) 966 { 967 parent.RegistersCollection.DefineRegister(504, 4278255615, true) 968 .WithValueField(0, 8, out TX_DESC_THLD, name: "TX_DESC_THLD") 969 .WithValueField(8, 8, out RX_DESC_THLD, name: "RX_DESC_THLD") 970 .WithValueField(24, 8, out IBI_THLD, name: "IBI_THLD"); 971 } 972 } 973 974 public struct PIODataBufferThldCtrlType 975 { 976 public IValueRegisterField TX_BUF_THLD; 977 public IValueRegisterField RX_BUF_THLD; 978 public IValueRegisterField TX_START_THLD; 979 public IValueRegisterField RX_START_THLD; 980 PIODataBufferThldCtrlTypeAntmicro.Renode.Peripherals.I3C.Caliptra_I3C.PIODataBufferThldCtrlType981 public PIODataBufferThldCtrlType(IProvidesRegisterCollection<DoubleWordRegisterCollection> parent) 982 { 983 parent.RegistersCollection.DefineRegister(148, 16843009) 984 .WithValueField(0, 3, out TX_BUF_THLD, name: "TX_BUF_THLD") 985 .WithValueField(8, 3, out RX_BUF_THLD, name: "TX_BUF_THLD") 986 .WithValueField(16, 3, out TX_START_THLD, name: "TX_START_THLD") 987 .WithValueField(24, 3, out RX_START_THLD, name: "RX_START_THLD"); 988 } 989 } 990 991 public struct TargetTransactionInterfaceDataBufferThldCtrlType 992 { 993 /// <summary> Field "TX_DATA_THLD" at 0x0, width: 3 bits </summary> 994 public IValueRegisterField TX_DATA_THLD; 995 /// <summary> Field "RX_DATA_THLD" at 0x8, width: 3 bits </summary> 996 public IValueRegisterField RX_DATA_THLD; 997 /// <summary> Field "TX_START_THLD" at 0x10, width: 3 bits </summary> 998 public IValueRegisterField TX_START_THLD; 999 /// <summary> Field "RX_START_THLD" at 0x18, width: 3 bits </summary> 1000 public IValueRegisterField RX_START_THLD; 1001 TargetTransactionInterfaceDataBufferThldCtrlTypeAntmicro.Renode.Peripherals.I3C.Caliptra_I3C.TargetTransactionInterfaceDataBufferThldCtrlType1002 public TargetTransactionInterfaceDataBufferThldCtrlType(IProvidesRegisterCollection<DoubleWordRegisterCollection> parent) 1003 { 1004 parent.RegistersCollection.DefineRegister(508, 117901063, true) 1005 .WithValueField(0, 3, out TX_DATA_THLD, name: "TX_DATA_THLD") 1006 .WithValueField(8, 3, out RX_DATA_THLD, name: "RX_DATA_THLD") 1007 .WithValueField(16, 3, out TX_START_THLD, name: "TX_START_THLD") 1008 .WithValueField(24, 3, out RX_START_THLD, name: "RX_START_THLD"); 1009 } 1010 } 1011 1012 public struct PIOQueueSizeType 1013 { 1014 public IValueRegisterField CR_QUEUE_SIZE; 1015 public IValueRegisterField IBI_STATUS_SIZE; 1016 public IValueRegisterField RX_DATA_BUFFER_SIZE; 1017 public IValueRegisterField TX_DATA_BUFFER_SIZE; 1018 PIOQueueSizeTypeAntmicro.Renode.Peripherals.I3C.Caliptra_I3C.PIOQueueSizeType1019 public PIOQueueSizeType(IProvidesRegisterCollection<DoubleWordRegisterCollection> parent) 1020 { 1021 parent.RegistersCollection.DefineRegister(152) 1022 .WithValueField(0, 8, out CR_QUEUE_SIZE, mode: FieldMode.Read, name: "CR_QUEUE_SIZE") 1023 .WithValueField(8, 8, out IBI_STATUS_SIZE, mode: FieldMode.Read, name: "IBI_STATUS_SIZE") 1024 .WithValueField(16, 8, out RX_DATA_BUFFER_SIZE, mode: FieldMode.Read, name: "RX_DATA_BUFFER_SIZE") 1025 .WithValueField(24, 8, out TX_DATA_BUFFER_SIZE, mode: FieldMode.Read, name: "TX_DATA_BUFFER_SIZE"); 1026 } 1027 } 1028 1029 public struct TargetTransactionInterfaceQueueSizeType 1030 { 1031 /// <summary> Field "RX_DESC_BUFFER_SIZE" at 0x0, width: 8 bits </summary> 1032 public IValueRegisterField RX_DESC_BUFFER_SIZE; 1033 /// <summary> Field "TX_DESC_BUFFER_SIZE" at 0x8, width: 8 bits </summary> 1034 public IValueRegisterField TX_DESC_BUFFER_SIZE; 1035 /// <summary> Field "RX_DATA_BUFFER_SIZE" at 0x10, width: 8 bits </summary> 1036 public IValueRegisterField RX_DATA_BUFFER_SIZE; 1037 /// <summary> Field "TX_DATA_BUFFER_SIZE" at 0x18, width: 8 bits </summary> 1038 public IValueRegisterField TX_DATA_BUFFER_SIZE; 1039 TargetTransactionInterfaceQueueSizeTypeAntmicro.Renode.Peripherals.I3C.Caliptra_I3C.TargetTransactionInterfaceQueueSizeType1040 public TargetTransactionInterfaceQueueSizeType(IProvidesRegisterCollection<DoubleWordRegisterCollection> parent) 1041 { 1042 parent.RegistersCollection.DefineRegister(496, 4294967295, true) 1043 .WithValueField(0, 8, out RX_DESC_BUFFER_SIZE, mode: FieldMode.Read, name: "RX_DESC_BUFFER_SIZE") 1044 .WithValueField(8, 8, out TX_DESC_BUFFER_SIZE, mode: FieldMode.Read, name: "TX_DESC_BUFFER_SIZE") 1045 .WithValueField(16, 8, out RX_DATA_BUFFER_SIZE, mode: FieldMode.Read, name: "RX_DATA_BUFFER_SIZE") 1046 .WithValueField(24, 8, out TX_DATA_BUFFER_SIZE, mode: FieldMode.Read, name: "TX_DATA_BUFFER_SIZE"); 1047 } 1048 } 1049 1050 public struct AltQueueSizeType 1051 { 1052 /// <summary> Field "ALT_RESP_QUEUE_SIZE" at 0x0, width: 8 bits </summary> 1053 public IValueRegisterField ALT_RESP_QUEUE_SIZE; 1054 /// <summary> Field "ALT_RESP_QUEUE_EN" at 0x18, width: 1 bits </summary> 1055 public IFlagRegisterField ALT_RESP_QUEUE_EN; 1056 /// <summary> Field "EXT_IBI_QUEUE_EN" at 0x1c, width: 1 bits </summary> 1057 public IFlagRegisterField EXT_IBI_QUEUE_EN; 1058 AltQueueSizeTypeAntmicro.Renode.Peripherals.I3C.Caliptra_I3C.AltQueueSizeType1059 public AltQueueSizeType(IProvidesRegisterCollection<DoubleWordRegisterCollection> parent) 1060 { 1061 parent.RegistersCollection.DefineRegister(156, 16777471, true) 1062 .WithValueField(0, 8, out ALT_RESP_QUEUE_SIZE, mode: FieldMode.Read, name: "ALT_RESP_QUEUE_SIZE") 1063 .WithFlag(24, out ALT_RESP_QUEUE_EN, mode: FieldMode.Read, name: "ALT_RESP_QUEUE_EN") 1064 .WithFlag(28, out EXT_IBI_QUEUE_EN, mode: FieldMode.Read, name: "EXT_IBI_QUEUE_EN"); 1065 } 1066 } 1067 1068 public struct PioIntrStatusType 1069 { 1070 /// <summary> Field "TX_THLD_STAT" at 0x0, width: 1 bits </summary> 1071 public IFlagRegisterField TX_THLD_STAT; 1072 /// <summary> Field "RX_THLD_STAT" at 0x1, width: 1 bits </summary> 1073 public IFlagRegisterField RX_THLD_STAT; 1074 /// <summary> Field "IBI_STATUS_THLD_STAT" at 0x2, width: 1 bits </summary> 1075 public IFlagRegisterField IBI_STATUS_THLD_STAT; 1076 /// <summary> Field "CMD_QUEUE_READY_STAT" at 0x3, width: 1 bits </summary> 1077 public IFlagRegisterField CMD_QUEUE_READY_STAT; 1078 /// <summary> Field "RESP_READY_STAT" at 0x4, width: 1 bits </summary> 1079 public IFlagRegisterField RESP_READY_STAT; 1080 /// <summary> Field "TRANSFER_ABORT_STAT" at 0x5, width: 1 bits </summary> 1081 public IFlagRegisterField TRANSFER_ABORT_STAT; 1082 /// <summary> Field "TRANSFER_ERR_STAT" at 0x9, width: 1 bits </summary> 1083 public IFlagRegisterField TRANSFER_ERR_STAT; 1084 PioIntrStatusTypeAntmicro.Renode.Peripherals.I3C.Caliptra_I3C.PioIntrStatusType1085 public PioIntrStatusType(IProvidesRegisterCollection<DoubleWordRegisterCollection> parent) 1086 { 1087 parent.RegistersCollection.DefineRegister(160, 0, true) 1088 .WithFlag(0, out TX_THLD_STAT, mode: FieldMode.Read, name: "TX_THLD_STAT") 1089 .WithFlag(1, out RX_THLD_STAT, mode: FieldMode.Read, name: "RX_THLD_STAT") 1090 .WithFlag(2, out IBI_STATUS_THLD_STAT, mode: FieldMode.Read, name: "IBI_STATUS_THLD_STAT") 1091 .WithFlag(3, out CMD_QUEUE_READY_STAT, mode: FieldMode.Read, name: "CMD_QUEUE_READY_STAT") 1092 .WithFlag(4, out RESP_READY_STAT, mode: FieldMode.Read, name: "RESP_READY_STAT") 1093 .WithFlag(5, out TRANSFER_ABORT_STAT, mode: FieldMode.Read | FieldMode.WriteOneToClear, name: "TRANSFER_ABORT_STAT") 1094 .WithFlag(9, out TRANSFER_ERR_STAT, mode: FieldMode.Read | FieldMode.WriteOneToClear, name: "TRANSFER_ERR_STAT"); 1095 } 1096 } 1097 1098 public struct PioIntrStatusEnableType 1099 { 1100 /// <summary> Field "TX_THLD_STAT_EN" at 0x0, width: 1 bits </summary> 1101 public IFlagRegisterField TX_THLD_STAT_EN; 1102 /// <summary> Field "RX_THLD_STAT_EN" at 0x1, width: 1 bits </summary> 1103 public IFlagRegisterField RX_THLD_STAT_EN; 1104 /// <summary> Field "IBI_STATUS_THLD_STAT_EN" at 0x2, width: 1 bits </summary> 1105 public IFlagRegisterField IBI_STATUS_THLD_STAT_EN; 1106 /// <summary> Field "CMD_QUEUE_READY_STAT_EN" at 0x3, width: 1 bits </summary> 1107 public IFlagRegisterField CMD_QUEUE_READY_STAT_EN; 1108 /// <summary> Field "RESP_READY_STAT_EN" at 0x4, width: 1 bits </summary> 1109 public IFlagRegisterField RESP_READY_STAT_EN; 1110 /// <summary> Field "TRANSFER_ABORT_STAT_EN" at 0x5, width: 1 bits </summary> 1111 public IFlagRegisterField TRANSFER_ABORT_STAT_EN; 1112 /// <summary> Field "TRANSFER_ERR_STAT_EN" at 0x9, width: 1 bits </summary> 1113 public IFlagRegisterField TRANSFER_ERR_STAT_EN; 1114 PioIntrStatusEnableTypeAntmicro.Renode.Peripherals.I3C.Caliptra_I3C.PioIntrStatusEnableType1115 public PioIntrStatusEnableType(IProvidesRegisterCollection<DoubleWordRegisterCollection> parent) 1116 { 1117 parent.RegistersCollection.DefineRegister(164, 0, true) 1118 .WithFlag(0, out TX_THLD_STAT_EN, name: "TX_THLD_STAT_EN") 1119 .WithFlag(1, out RX_THLD_STAT_EN, name: "RX_THLD_STAT_EN") 1120 .WithFlag(2, out IBI_STATUS_THLD_STAT_EN, name: "IBI_STATUS_THLD_STAT_EN") 1121 .WithFlag(3, out CMD_QUEUE_READY_STAT_EN, name: "CMD_QUEUE_READY_STAT_EN") 1122 .WithFlag(4, out RESP_READY_STAT_EN, name: "RESP_READY_STAT_EN") 1123 .WithFlag(5, out TRANSFER_ABORT_STAT_EN, name: "TRANSFER_ABORT_STAT_EN") 1124 .WithFlag(9, out TRANSFER_ERR_STAT_EN, name: "TRANSFER_ERR_STAT_EN"); 1125 } 1126 } 1127 1128 public struct PioIntrSignalEnableType 1129 { 1130 /// <summary> Field "TX_THLD_SIGNAL_EN" at 0x0, width: 1 bits </summary> 1131 public IFlagRegisterField TX_THLD_SIGNAL_EN; 1132 /// <summary> Field "RX_THLD_SIGNAL_EN" at 0x1, width: 1 bits </summary> 1133 public IFlagRegisterField RX_THLD_SIGNAL_EN; 1134 /// <summary> Field "IBI_STATUS_THLD_SIGNAL_EN" at 0x2, width: 1 bits </summary> 1135 public IFlagRegisterField IBI_STATUS_THLD_SIGNAL_EN; 1136 /// <summary> Field "CMD_QUEUE_READY_SIGNAL_EN" at 0x3, width: 1 bits </summary> 1137 public IFlagRegisterField CMD_QUEUE_READY_SIGNAL_EN; 1138 /// <summary> Field "RESP_READY_SIGNAL_EN" at 0x4, width: 1 bits </summary> 1139 public IFlagRegisterField RESP_READY_SIGNAL_EN; 1140 /// <summary> Field "TRANSFER_ABORT_SIGNAL_EN" at 0x5, width: 1 bits </summary> 1141 public IFlagRegisterField TRANSFER_ABORT_SIGNAL_EN; 1142 /// <summary> Field "TRANSFER_ERR_SIGNAL_EN" at 0x9, width: 1 bits </summary> 1143 public IFlagRegisterField TRANSFER_ERR_SIGNAL_EN; 1144 PioIntrSignalEnableTypeAntmicro.Renode.Peripherals.I3C.Caliptra_I3C.PioIntrSignalEnableType1145 public PioIntrSignalEnableType(IProvidesRegisterCollection<DoubleWordRegisterCollection> parent) 1146 { 1147 parent.RegistersCollection.DefineRegister(168, 0, true) 1148 .WithFlag(0, out TX_THLD_SIGNAL_EN, name: "TX_THLD_SIGNAL_EN") 1149 .WithFlag(1, out RX_THLD_SIGNAL_EN, name: "RX_THLD_SIGNAL_EN") 1150 .WithFlag(2, out IBI_STATUS_THLD_SIGNAL_EN, name: "IBI_STATUS_THLD_SIGNAL_EN") 1151 .WithFlag(3, out CMD_QUEUE_READY_SIGNAL_EN, name: "CMD_QUEUE_READY_SIGNAL_EN") 1152 .WithFlag(4, out RESP_READY_SIGNAL_EN, name: "RESP_READY_SIGNAL_EN") 1153 .WithFlag(5, out TRANSFER_ABORT_SIGNAL_EN, name: "TRANSFER_ABORT_SIGNAL_EN") 1154 .WithFlag(9, out TRANSFER_ERR_SIGNAL_EN, name: "TRANSFER_ERR_SIGNAL_EN"); 1155 } 1156 } 1157 1158 public struct PioIntrForceType 1159 { 1160 /// <summary> Field "TX_THLD_FORCE" at 0x0, width: 1 bits </summary> 1161 public IFlagRegisterField TX_THLD_FORCE; 1162 /// <summary> Field "RX_THLD_FORCE" at 0x1, width: 1 bits </summary> 1163 public IFlagRegisterField RX_THLD_FORCE; 1164 /// <summary> Field "IBI_THLD_FORCE" at 0x2, width: 1 bits </summary> 1165 public IFlagRegisterField IBI_THLD_FORCE; 1166 /// <summary> Field "CMD_QUEUE_READY_FORCE" at 0x3, width: 1 bits </summary> 1167 public IFlagRegisterField CMD_QUEUE_READY_FORCE; 1168 /// <summary> Field "RESP_READY_FORCE" at 0x4, width: 1 bits </summary> 1169 public IFlagRegisterField RESP_READY_FORCE; 1170 /// <summary> Field "TRANSFER_ABORT_FORCE" at 0x5, width: 1 bits </summary> 1171 public IFlagRegisterField TRANSFER_ABORT_FORCE; 1172 /// <summary> Field "TRANSFER_ERR_FORCE" at 0x9, width: 1 bits </summary> 1173 public IFlagRegisterField TRANSFER_ERR_FORCE; 1174 PioIntrForceTypeAntmicro.Renode.Peripherals.I3C.Caliptra_I3C.PioIntrForceType1175 public PioIntrForceType(IProvidesRegisterCollection<DoubleWordRegisterCollection> parent) 1176 { 1177 parent.RegistersCollection.DefineRegister(172, 0, true) 1178 .WithFlag(0, out TX_THLD_FORCE, mode: FieldMode.Write, name: "TX_THLD_FORCE") 1179 .WithFlag(1, out RX_THLD_FORCE, mode: FieldMode.Write, name: "RX_THLD_FORCE") 1180 .WithFlag(2, out IBI_THLD_FORCE, mode: FieldMode.Write, name: "IBI_THLD_FORCE") 1181 .WithFlag(3, out CMD_QUEUE_READY_FORCE, mode: FieldMode.Write, name: "CMD_QUEUE_READY_FORCE") 1182 .WithFlag(4, out RESP_READY_FORCE, mode: FieldMode.Write, name: "RESP_READY_FORCE") 1183 .WithFlag(5, out TRANSFER_ABORT_FORCE, mode: FieldMode.Write, name: "TRANSFER_ABORT_FORCE") 1184 .WithFlag(9, out TRANSFER_ERR_FORCE, mode: FieldMode.Write, name: "TRANSFER_ERR_FORCE"); 1185 } 1186 } 1187 1188 public struct PioControlType 1189 { 1190 /// <summary> Field "ENABLE" at 0x0, width: 1 bits </summary> 1191 public IFlagRegisterField ENABLE; 1192 /// <summary> Field "RS" at 0x1, width: 1 bits </summary> 1193 public IFlagRegisterField RS; 1194 /// <summary> Field "ABORT" at 0x2, width: 1 bits </summary> 1195 public IFlagRegisterField ABORT; 1196 PioControlTypeAntmicro.Renode.Peripherals.I3C.Caliptra_I3C.PioControlType1197 public PioControlType(IProvidesRegisterCollection<DoubleWordRegisterCollection> parent) 1198 { 1199 parent.RegistersCollection.DefineRegister(176, 1, true) 1200 .WithFlag(0, out ENABLE, name: "ENABLE") 1201 .WithFlag(1, out RS, name: "RS") 1202 .WithFlag(2, out ABORT, name: "ABORT"); 1203 } 1204 } 1205 1206 public struct SecureFirmwareRecoveryInterfaceExtcapHeaderType 1207 { 1208 /// <summary> Field "CAP_ID" at 0x0, width: 8 bits </summary> 1209 public IValueRegisterField CAP_ID; 1210 /// <summary> Field "CAP_LENGTH" at 0x8, width: 16 bits </summary> 1211 public IValueRegisterField CAP_LENGTH; 1212 SecureFirmwareRecoveryInterfaceExtcapHeaderTypeAntmicro.Renode.Peripherals.I3C.Caliptra_I3C.SecureFirmwareRecoveryInterfaceExtcapHeaderType1213 public SecureFirmwareRecoveryInterfaceExtcapHeaderType(IProvidesRegisterCollection<DoubleWordRegisterCollection> parent) 1214 { 1215 parent.RegistersCollection.DefineRegister(256, 8384, true) 1216 .WithValueField(0, 8, out CAP_ID, mode: FieldMode.Read, name: "CAP_ID") 1217 .WithValueField(8, 16, out CAP_LENGTH, mode: FieldMode.Read, name: "CAP_LENGTH"); 1218 } 1219 } 1220 1221 public struct StandbyControllerModeRegistersExtcapHeaderType 1222 { 1223 /// <summary> Field "CAP_ID" at 0x0, width: 8 bits </summary> 1224 public IValueRegisterField CAP_ID; 1225 /// <summary> Field "CAP_LENGTH" at 0x8, width: 16 bits </summary> 1226 public IValueRegisterField CAP_LENGTH; 1227 StandbyControllerModeRegistersExtcapHeaderTypeAntmicro.Renode.Peripherals.I3C.Caliptra_I3C.StandbyControllerModeRegistersExtcapHeaderType1228 public StandbyControllerModeRegistersExtcapHeaderType(IProvidesRegisterCollection<DoubleWordRegisterCollection> parent) 1229 { 1230 parent.RegistersCollection.DefineRegister(384, 4114, true) 1231 .WithValueField(0, 8, out CAP_ID, mode: FieldMode.Read, name: "CAP_ID") 1232 .WithValueField(8, 16, out CAP_LENGTH, mode: FieldMode.Read, name: "CAP_LENGTH"); 1233 } 1234 } 1235 1236 public struct SoCManagementInterfaceRegistersExtcapHeaderType 1237 { 1238 /// <summary> Field "CAP_ID" at 0x0, width: 8 bits </summary> 1239 public IValueRegisterField CAP_ID; 1240 /// <summary> Field "CAP_LENGTH" at 0x8, width: 16 bits </summary> 1241 public IValueRegisterField CAP_LENGTH; 1242 SoCManagementInterfaceRegistersExtcapHeaderTypeAntmicro.Renode.Peripherals.I3C.Caliptra_I3C.SoCManagementInterfaceRegistersExtcapHeaderType1243 public SoCManagementInterfaceRegistersExtcapHeaderType(IProvidesRegisterCollection<DoubleWordRegisterCollection> parent) 1244 { 1245 parent.RegistersCollection.DefineRegister(512, 6337, true) 1246 .WithValueField(0, 8, out CAP_ID, mode: FieldMode.Read, name: "CAP_ID") 1247 .WithValueField(8, 16, out CAP_LENGTH, mode: FieldMode.Read, name: "CAP_LENGTH"); 1248 } 1249 } 1250 1251 public struct TargetTransactionInterfaceRegistersExtcapHeaderType 1252 { 1253 /// <summary> Field "CAP_ID" at 0x0, width: 8 bits </summary> 1254 public IValueRegisterField CAP_ID; 1255 /// <summary> Field "CAP_LENGTH" at 0x8, width: 16 bits </summary> 1256 public IValueRegisterField CAP_LENGTH; 1257 TargetTransactionInterfaceRegistersExtcapHeaderTypeAntmicro.Renode.Peripherals.I3C.Caliptra_I3C.TargetTransactionInterfaceRegistersExtcapHeaderType1258 public TargetTransactionInterfaceRegistersExtcapHeaderType(IProvidesRegisterCollection<DoubleWordRegisterCollection> parent) 1259 { 1260 parent.RegistersCollection.DefineRegister(448, 4292, true) 1261 .WithValueField(0, 8, out CAP_ID, mode: FieldMode.Read, name: "CAP_ID") 1262 .WithValueField(8, 16, out CAP_LENGTH, mode: FieldMode.Read, name: "CAP_LENGTH"); 1263 } 1264 } 1265 1266 public struct ControllerConfigRegistersExtcapHeaderType 1267 { 1268 /// <summary> Field "CAP_ID" at 0x0, width: 8 bits </summary> 1269 public IValueRegisterField CAP_ID; 1270 /// <summary> Field "CAP_LENGTH" at 0x8, width: 16 bits </summary> 1271 public IValueRegisterField CAP_LENGTH; 1272 ControllerConfigRegistersExtcapHeaderTypeAntmicro.Renode.Peripherals.I3C.Caliptra_I3C.ControllerConfigRegistersExtcapHeaderType1273 public ControllerConfigRegistersExtcapHeaderType(IProvidesRegisterCollection<DoubleWordRegisterCollection> parent) 1274 { 1275 parent.RegistersCollection.DefineRegister(608, 514, true) 1276 .WithValueField(0, 8, out CAP_ID, mode: FieldMode.Read, name: "CAP_ID") 1277 .WithValueField(8, 16, out CAP_LENGTH, mode: FieldMode.Read, name: "CAP_LENGTH"); 1278 } 1279 } 1280 1281 public struct ProtCap0Type 1282 { 1283 /// <summary> Field "REC_MAGIC_STRING_0" at 0x0, width: 32 bits </summary> 1284 public IValueRegisterField REC_MAGIC_STRING_0; 1285 ProtCap0TypeAntmicro.Renode.Peripherals.I3C.Caliptra_I3C.ProtCap0Type1286 public ProtCap0Type(IProvidesRegisterCollection<DoubleWordRegisterCollection> parent) 1287 { 1288 parent.RegistersCollection.DefineRegister(260, 4294967295, true) 1289 .WithValueField(0, 32, out REC_MAGIC_STRING_0, mode: FieldMode.Read, name: "REC_MAGIC_STRING_0"); 1290 } 1291 } 1292 1293 public struct ProtCap1Type 1294 { 1295 /// <summary> Field "REC_MAGIC_STRING_1" at 0x0, width: 32 bits </summary> 1296 public IValueRegisterField REC_MAGIC_STRING_1; 1297 ProtCap1TypeAntmicro.Renode.Peripherals.I3C.Caliptra_I3C.ProtCap1Type1298 public ProtCap1Type(IProvidesRegisterCollection<DoubleWordRegisterCollection> parent) 1299 { 1300 parent.RegistersCollection.DefineRegister(264, 4294967295, true) 1301 .WithValueField(0, 32, out REC_MAGIC_STRING_1, mode: FieldMode.Read, name: "REC_MAGIC_STRING_1"); 1302 } 1303 } 1304 1305 public struct ProtCap2Type 1306 { 1307 /// <summary> Field "REC_PROT_VERSION" at 0x0, width: 16 bits </summary> 1308 public IValueRegisterField REC_PROT_VERSION; 1309 /// <summary> Field "AGENT_CAPS" at 0x10, width: 16 bits </summary> 1310 public IValueRegisterField AGENT_CAPS; 1311 ProtCap2TypeAntmicro.Renode.Peripherals.I3C.Caliptra_I3C.ProtCap2Type1312 public ProtCap2Type(IProvidesRegisterCollection<DoubleWordRegisterCollection> parent) 1313 { 1314 parent.RegistersCollection.DefineRegister(268, 0, true) 1315 .WithValueField(0, 16, out REC_PROT_VERSION, name: "REC_PROT_VERSION") 1316 .WithValueField(16, 16, out AGENT_CAPS, name: "AGENT_CAPS"); 1317 } 1318 } 1319 1320 public struct ProtCap3Type 1321 { 1322 /// <summary> Field "NUM_OF_CMS_REGIONS" at 0x0, width: 8 bits </summary> 1323 public IValueRegisterField NUM_OF_CMS_REGIONS; 1324 /// <summary> Field "MAX_RESP_TIME" at 0x8, width: 8 bits </summary> 1325 public IValueRegisterField MAX_RESP_TIME; 1326 /// <summary> Field "HEARTBEAT_PERIOD" at 0x10, width: 8 bits </summary> 1327 public IValueRegisterField HEARTBEAT_PERIOD; 1328 ProtCap3TypeAntmicro.Renode.Peripherals.I3C.Caliptra_I3C.ProtCap3Type1329 public ProtCap3Type(IProvidesRegisterCollection<DoubleWordRegisterCollection> parent) 1330 { 1331 parent.RegistersCollection.DefineRegister(272, 0, true) 1332 .WithValueField(0, 8, out NUM_OF_CMS_REGIONS, name: "NUM_OF_CMS_REGIONS") 1333 .WithValueField(8, 8, out MAX_RESP_TIME, name: "MAX_RESP_TIME") 1334 .WithValueField(16, 8, out HEARTBEAT_PERIOD, name: "HEARTBEAT_PERIOD"); 1335 } 1336 } 1337 1338 public struct DeviceId0Type 1339 { 1340 /// <summary> Field "DESC_TYPE" at 0x0, width: 8 bits </summary> 1341 public IValueRegisterField DESC_TYPE; 1342 /// <summary> Field "VENDOR_SPECIFIC_STR_LENGTH" at 0x8, width: 8 bits </summary> 1343 public IValueRegisterField VENDOR_SPECIFIC_STR_LENGTH; 1344 /// <summary> Field "DATA" at 0x10, width: 16 bits </summary> 1345 public IValueRegisterField DATA; 1346 DeviceId0TypeAntmicro.Renode.Peripherals.I3C.Caliptra_I3C.DeviceId0Type1347 public DeviceId0Type(IProvidesRegisterCollection<DoubleWordRegisterCollection> parent) 1348 { 1349 parent.RegistersCollection.DefineRegister(276, 0, true) 1350 .WithValueField(0, 8, out DESC_TYPE, name: "DESC_TYPE") 1351 .WithValueField(8, 8, out VENDOR_SPECIFIC_STR_LENGTH, name: "VENDOR_SPECIFIC_STR_LENGTH") 1352 .WithValueField(16, 16, out DATA, name: "DATA"); 1353 } 1354 } 1355 1356 public struct DeviceId1Type 1357 { 1358 /// <summary> Field "DATA" at 0x0, width: 32 bits </summary> 1359 public IValueRegisterField DATA; 1360 DeviceId1TypeAntmicro.Renode.Peripherals.I3C.Caliptra_I3C.DeviceId1Type1361 public DeviceId1Type(IProvidesRegisterCollection<DoubleWordRegisterCollection> parent) 1362 { 1363 parent.RegistersCollection.DefineRegister(280, 0, true) 1364 .WithValueField(0, 32, out DATA, name: "DATA"); 1365 } 1366 } 1367 1368 public struct DeviceId2Type 1369 { 1370 /// <summary> Field "DATA" at 0x0, width: 32 bits </summary> 1371 public IValueRegisterField DATA; 1372 DeviceId2TypeAntmicro.Renode.Peripherals.I3C.Caliptra_I3C.DeviceId2Type1373 public DeviceId2Type(IProvidesRegisterCollection<DoubleWordRegisterCollection> parent) 1374 { 1375 parent.RegistersCollection.DefineRegister(284, 0, true) 1376 .WithValueField(0, 32, out DATA, name: "DATA"); 1377 } 1378 } 1379 1380 public struct DeviceId3Type 1381 { 1382 /// <summary> Field "DATA" at 0x0, width: 32 bits </summary> 1383 public IValueRegisterField DATA; 1384 DeviceId3TypeAntmicro.Renode.Peripherals.I3C.Caliptra_I3C.DeviceId3Type1385 public DeviceId3Type(IProvidesRegisterCollection<DoubleWordRegisterCollection> parent) 1386 { 1387 parent.RegistersCollection.DefineRegister(288, 0, true) 1388 .WithValueField(0, 32, out DATA, name: "DATA"); 1389 } 1390 } 1391 1392 public struct DeviceId4Type 1393 { 1394 /// <summary> Field "DATA" at 0x0, width: 32 bits </summary> 1395 public IValueRegisterField DATA; 1396 DeviceId4TypeAntmicro.Renode.Peripherals.I3C.Caliptra_I3C.DeviceId4Type1397 public DeviceId4Type(IProvidesRegisterCollection<DoubleWordRegisterCollection> parent) 1398 { 1399 parent.RegistersCollection.DefineRegister(292, 0, true) 1400 .WithValueField(0, 32, out DATA, name: "DATA"); 1401 } 1402 } 1403 1404 public struct DeviceId5Type 1405 { 1406 /// <summary> Field "DATA" at 0x0, width: 32 bits </summary> 1407 public IValueRegisterField DATA; 1408 DeviceId5TypeAntmicro.Renode.Peripherals.I3C.Caliptra_I3C.DeviceId5Type1409 public DeviceId5Type(IProvidesRegisterCollection<DoubleWordRegisterCollection> parent) 1410 { 1411 parent.RegistersCollection.DefineRegister(296, 0, true) 1412 .WithValueField(0, 32, out DATA, name: "DATA"); 1413 } 1414 } 1415 1416 public struct DeviceIdReservedType 1417 { 1418 /// <summary> Field "DATA" at 0x0, width: 32 bits </summary> 1419 public IValueRegisterField DATA; 1420 DeviceIdReservedTypeAntmicro.Renode.Peripherals.I3C.Caliptra_I3C.DeviceIdReservedType1421 public DeviceIdReservedType(IProvidesRegisterCollection<DoubleWordRegisterCollection> parent) 1422 { 1423 parent.RegistersCollection.DefineRegister(300, 0, true) 1424 .WithValueField(0, 32, out DATA, mode: FieldMode.Read, name: "DATA"); 1425 } 1426 } 1427 1428 public struct DeviceStatus0Type 1429 { 1430 /// <summary> Field "DEV_STATUS" at 0x0, width: 8 bits </summary> 1431 public IValueRegisterField DEV_STATUS; 1432 /// <summary> Field "PROT_ERROR" at 0x8, width: 8 bits </summary> 1433 public IValueRegisterField PROT_ERROR; 1434 /// <summary> Field "REC_REASON_CODE" at 0x10, width: 16 bits </summary> 1435 public IValueRegisterField REC_REASON_CODE; 1436 DeviceStatus0TypeAntmicro.Renode.Peripherals.I3C.Caliptra_I3C.DeviceStatus0Type1437 public DeviceStatus0Type(IProvidesRegisterCollection<DoubleWordRegisterCollection> parent) 1438 { 1439 parent.RegistersCollection.DefineRegister(304, 0, true) 1440 .WithValueField(0, 8, out DEV_STATUS, name: "DEV_STATUS") 1441 .WithValueField(8, 8, out PROT_ERROR, mode: FieldMode.ReadToClear | FieldMode.Write, name: "PROT_ERROR") 1442 .WithValueField(16, 16, out REC_REASON_CODE, name: "REC_REASON_CODE"); 1443 } 1444 } 1445 1446 public struct DeviceStatus1Type 1447 { 1448 /// <summary> Field "HEARTBEAT" at 0x0, width: 16 bits </summary> 1449 public IValueRegisterField HEARTBEAT; 1450 /// <summary> Field "VENDOR_STATUS_LENGTH" at 0x10, width: 9 bits </summary> 1451 public IValueRegisterField VENDOR_STATUS_LENGTH; 1452 /// <summary> Field "VENDOR_STATUS" at 0x19, width: 7 bits </summary> 1453 public IValueRegisterField VENDOR_STATUS; 1454 DeviceStatus1TypeAntmicro.Renode.Peripherals.I3C.Caliptra_I3C.DeviceStatus1Type1455 public DeviceStatus1Type(IProvidesRegisterCollection<DoubleWordRegisterCollection> parent) 1456 { 1457 parent.RegistersCollection.DefineRegister(308, 0, true) 1458 .WithValueField(0, 16, out HEARTBEAT, name: "HEARTBEAT") 1459 .WithValueField(16, 9, out VENDOR_STATUS_LENGTH, name: "VENDOR_STATUS_LENGTH") 1460 .WithValueField(25, 7, out VENDOR_STATUS, name: "VENDOR_STATUS"); 1461 } 1462 } 1463 1464 public struct DeviceResetType 1465 { 1466 /// <summary> Field "RESET_CTRL" at 0x0, width: 8 bits </summary> 1467 public IValueRegisterField RESET_CTRL; 1468 /// <summary> Field "FORCED_RECOVERY" at 0x8, width: 8 bits </summary> 1469 public IValueRegisterField FORCED_RECOVERY; 1470 /// <summary> Field "IF_CTRL" at 0x10, width: 8 bits </summary> 1471 public IValueRegisterField IF_CTRL; 1472 DeviceResetTypeAntmicro.Renode.Peripherals.I3C.Caliptra_I3C.DeviceResetType1473 public DeviceResetType(IProvidesRegisterCollection<DoubleWordRegisterCollection> parent) 1474 { 1475 parent.RegistersCollection.DefineRegister(312, 0, true) 1476 .WithValueField(0, 8, out RESET_CTRL, mode: FieldMode.Read | FieldMode.WriteOneToClear, name: "RESET_CTRL") 1477 .WithValueField(8, 8, out FORCED_RECOVERY, name: "FORCED_RECOVERY") 1478 .WithValueField(16, 8, out IF_CTRL, name: "IF_CTRL"); 1479 } 1480 } 1481 1482 public struct RecoveryCtrlType 1483 { 1484 /// <summary> Field "CMS" at 0x0, width: 8 bits </summary> 1485 public IValueRegisterField CMS; 1486 /// <summary> Field "REC_IMG_SEL" at 0x8, width: 8 bits </summary> 1487 public IValueRegisterField REC_IMG_SEL; 1488 /// <summary> Field "ACTIVATE_REC_IMG" at 0x10, width: 8 bits </summary> 1489 public IValueRegisterField ACTIVATE_REC_IMG; 1490 RecoveryCtrlTypeAntmicro.Renode.Peripherals.I3C.Caliptra_I3C.RecoveryCtrlType1491 public RecoveryCtrlType(IProvidesRegisterCollection<DoubleWordRegisterCollection> parent) 1492 { 1493 parent.RegistersCollection.DefineRegister(316, 0, true) 1494 .WithValueField(0, 8, out CMS, name: "CMS") 1495 .WithValueField(8, 8, out REC_IMG_SEL, name: "REC_IMG_SEL") 1496 .WithValueField(16, 8, out ACTIVATE_REC_IMG, mode: FieldMode.Read | FieldMode.WriteOneToClear, name: "ACTIVATE_REC_IMG"); 1497 } 1498 } 1499 1500 public struct RecoveryStatusType 1501 { 1502 /// <summary> Field "DEV_REC_STATUS" at 0x0, width: 4 bits </summary> 1503 public IValueRegisterField DEV_REC_STATUS; 1504 /// <summary> Field "REC_IMG_INDEX" at 0x4, width: 4 bits </summary> 1505 public IValueRegisterField REC_IMG_INDEX; 1506 /// <summary> Field "VENDOR_SPECIFIC_STATUS" at 0x8, width: 8 bits </summary> 1507 public IValueRegisterField VENDOR_SPECIFIC_STATUS; 1508 RecoveryStatusTypeAntmicro.Renode.Peripherals.I3C.Caliptra_I3C.RecoveryStatusType1509 public RecoveryStatusType(IProvidesRegisterCollection<DoubleWordRegisterCollection> parent) 1510 { 1511 parent.RegistersCollection.DefineRegister(320, 0, true) 1512 .WithValueField(0, 4, out DEV_REC_STATUS, name: "DEV_REC_STATUS") 1513 .WithValueField(4, 4, out REC_IMG_INDEX, name: "REC_IMG_INDEX") 1514 .WithValueField(8, 8, out VENDOR_SPECIFIC_STATUS, name: "VENDOR_SPECIFIC_STATUS"); 1515 } 1516 } 1517 1518 public struct HwStatusType 1519 { 1520 /// <summary> Field "TEMP_CRITICAL" at 0x0, width: 1 bits </summary> 1521 public IFlagRegisterField TEMP_CRITICAL; 1522 /// <summary> Field "SOFT_ERR" at 0x1, width: 1 bits </summary> 1523 public IFlagRegisterField SOFT_ERR; 1524 /// <summary> Field "FATAL_ERR" at 0x2, width: 1 bits </summary> 1525 public IFlagRegisterField FATAL_ERR; 1526 /// <summary> Field "RESERVED_7_3" at 0x3, width: 5 bits </summary> 1527 public IValueRegisterField RESERVED_7_3; 1528 /// <summary> Field "VENDOR_HW_STATUS" at 0x8, width: 8 bits </summary> 1529 public IValueRegisterField VENDOR_HW_STATUS; 1530 /// <summary> Field "CTEMP" at 0x10, width: 8 bits </summary> 1531 public IValueRegisterField CTEMP; 1532 /// <summary> Field "VENDOR_HW_STATUS_LEN" at 0x18, width: 8 bits </summary> 1533 public IValueRegisterField VENDOR_HW_STATUS_LEN; 1534 HwStatusTypeAntmicro.Renode.Peripherals.I3C.Caliptra_I3C.HwStatusType1535 public HwStatusType(IProvidesRegisterCollection<DoubleWordRegisterCollection> parent) 1536 { 1537 parent.RegistersCollection.DefineRegister(324, 0, true) 1538 .WithFlag(0, out TEMP_CRITICAL, name: "TEMP_CRITICAL") 1539 .WithFlag(1, out SOFT_ERR, name: "SOFT_ERR") 1540 .WithFlag(2, out FATAL_ERR, name: "FATAL_ERR") 1541 .WithValueField(3, 5, out RESERVED_7_3, name: "RESERVED_7_3") 1542 .WithValueField(8, 8, out VENDOR_HW_STATUS, name: "VENDOR_HW_STATUS") 1543 .WithValueField(16, 8, out CTEMP, name: "CTEMP") 1544 .WithValueField(24, 8, out VENDOR_HW_STATUS_LEN, name: "VENDOR_HW_STATUS_LEN"); 1545 } 1546 } 1547 1548 public struct IndirectFifoCtrl0Type 1549 { 1550 /// <summary> Field "CMS" at 0x0, width: 8 bits </summary> 1551 public IValueRegisterField CMS; 1552 /// <summary> Field "RESET" at 0x8, width: 8 bits </summary> 1553 public IValueRegisterField RESET; 1554 IndirectFifoCtrl0TypeAntmicro.Renode.Peripherals.I3C.Caliptra_I3C.IndirectFifoCtrl0Type1555 public IndirectFifoCtrl0Type(IProvidesRegisterCollection<DoubleWordRegisterCollection> parent) 1556 { 1557 parent.RegistersCollection.DefineRegister(328, 0, true) 1558 .WithValueField(0, 8, out CMS, name: "CMS") 1559 .WithValueField(8, 8, out RESET, name: "RESET"); 1560 } 1561 } 1562 1563 public struct IndirectFifoCtrl1Type 1564 { 1565 /// <summary> Field "IMAGE_SIZE" at 0x0, width: 32 bits </summary> 1566 public IValueRegisterField IMAGE_SIZE; 1567 IndirectFifoCtrl1TypeAntmicro.Renode.Peripherals.I3C.Caliptra_I3C.IndirectFifoCtrl1Type1568 public IndirectFifoCtrl1Type(IProvidesRegisterCollection<DoubleWordRegisterCollection> parent) 1569 { 1570 parent.RegistersCollection.DefineRegister(332, 0, true) 1571 .WithValueField(0, 32, out IMAGE_SIZE, name: "IMAGE_SIZE"); 1572 } 1573 } 1574 1575 public struct IndirectFifoStatus0Type 1576 { 1577 /// <summary> Field "EMPTY" at 0x0, width: 1 bits </summary> 1578 public IFlagRegisterField EMPTY; 1579 /// <summary> Field "FULL" at 0x1, width: 1 bits </summary> 1580 public IFlagRegisterField FULL; 1581 /// <summary> Field "REGION_TYPE" at 0x8, width: 3 bits </summary> 1582 public IValueRegisterField REGION_TYPE; 1583 IndirectFifoStatus0TypeAntmicro.Renode.Peripherals.I3C.Caliptra_I3C.IndirectFifoStatus0Type1584 public IndirectFifoStatus0Type(IProvidesRegisterCollection<DoubleWordRegisterCollection> parent) 1585 { 1586 parent.RegistersCollection.DefineRegister(336, 1, true) 1587 .WithFlag(0, out EMPTY, mode: FieldMode.Read, name: "EMPTY") 1588 .WithFlag(1, out FULL, mode: FieldMode.Read, name: "FULL") 1589 .WithValueField(8, 3, out REGION_TYPE, mode: FieldMode.Read, name: "REGION_TYPE"); 1590 } 1591 } 1592 1593 public struct IndirectFifoStatus1Type 1594 { 1595 /// <summary> Field "WRITE_INDEX" at 0x0, width: 32 bits </summary> 1596 public IValueRegisterField WRITE_INDEX; 1597 IndirectFifoStatus1TypeAntmicro.Renode.Peripherals.I3C.Caliptra_I3C.IndirectFifoStatus1Type1598 public IndirectFifoStatus1Type(IProvidesRegisterCollection<DoubleWordRegisterCollection> parent) 1599 { 1600 parent.RegistersCollection.DefineRegister(340, 0, true) 1601 .WithValueField(0, 32, out WRITE_INDEX, mode: FieldMode.Read, name: "WRITE_INDEX"); 1602 } 1603 } 1604 1605 public struct IndirectFifoStatus2Type 1606 { 1607 /// <summary> Field "READ_INDEX" at 0x0, width: 32 bits </summary> 1608 public IValueRegisterField READ_INDEX; 1609 IndirectFifoStatus2TypeAntmicro.Renode.Peripherals.I3C.Caliptra_I3C.IndirectFifoStatus2Type1610 public IndirectFifoStatus2Type(IProvidesRegisterCollection<DoubleWordRegisterCollection> parent) 1611 { 1612 parent.RegistersCollection.DefineRegister(344, 0, true) 1613 .WithValueField(0, 32, out READ_INDEX, mode: FieldMode.Read, name: "READ_INDEX"); 1614 } 1615 } 1616 1617 public struct IndirectFifoStatus3Type 1618 { 1619 /// <summary> Field "FIFO_SIZE" at 0x0, width: 32 bits </summary> 1620 public IValueRegisterField FIFO_SIZE; 1621 IndirectFifoStatus3TypeAntmicro.Renode.Peripherals.I3C.Caliptra_I3C.IndirectFifoStatus3Type1622 public IndirectFifoStatus3Type(IProvidesRegisterCollection<DoubleWordRegisterCollection> parent) 1623 { 1624 parent.RegistersCollection.DefineRegister(348, 4294967295, true) 1625 .WithValueField(0, 32, out FIFO_SIZE, mode: FieldMode.Read, name: "FIFO_SIZE"); 1626 } 1627 } 1628 1629 public struct IndirectFifoStatus4Type 1630 { 1631 /// <summary> Field "MAX_TRANSFER_SIZE" at 0x0, width: 32 bits </summary> 1632 public IValueRegisterField MAX_TRANSFER_SIZE; 1633 IndirectFifoStatus4TypeAntmicro.Renode.Peripherals.I3C.Caliptra_I3C.IndirectFifoStatus4Type1634 public IndirectFifoStatus4Type(IProvidesRegisterCollection<DoubleWordRegisterCollection> parent) 1635 { 1636 parent.RegistersCollection.DefineRegister(352, 0, true) 1637 .WithValueField(0, 32, out MAX_TRANSFER_SIZE, mode: FieldMode.Read, name: "MAX_TRANSFER_SIZE"); 1638 } 1639 } 1640 1641 public struct IndirectFifoReservedType 1642 { 1643 /// <summary> Field "DATA" at 0x0, width: 32 bits </summary> 1644 public IValueRegisterField DATA; 1645 IndirectFifoReservedTypeAntmicro.Renode.Peripherals.I3C.Caliptra_I3C.IndirectFifoReservedType1646 public IndirectFifoReservedType(IProvidesRegisterCollection<DoubleWordRegisterCollection> parent) 1647 { 1648 parent.RegistersCollection.DefineRegister(356, 0, true) 1649 .WithValueField(0, 32, out DATA, mode: FieldMode.Read, name: "DATA"); 1650 } 1651 } 1652 1653 public struct IndirectFifoDataType 1654 { 1655 /// <summary> Field "DATA" at 0x0, width: 32 bits </summary> 1656 public IValueRegisterField DATA; 1657 IndirectFifoDataTypeAntmicro.Renode.Peripherals.I3C.Caliptra_I3C.IndirectFifoDataType1658 public IndirectFifoDataType(IProvidesRegisterCollection<DoubleWordRegisterCollection> parent) 1659 { 1660 parent.RegistersCollection.DefineRegister(360, 0, true) 1661 .WithValueField(0, 32, out DATA, name: "DATA"); 1662 } 1663 } 1664 1665 public struct StbyCrControlType 1666 { 1667 /// <summary> Field "PENDING_RX_NACK" at 0x0, width: 1 bits </summary> 1668 public IFlagRegisterField PENDING_RX_NACK; 1669 /// <summary> Field "HANDOFF_DELAY_NACK" at 0x1, width: 1 bits </summary> 1670 public IFlagRegisterField HANDOFF_DELAY_NACK; 1671 /// <summary> Field "ACR_FSM_OP_SELECT" at 0x2, width: 1 bits </summary> 1672 public IFlagRegisterField ACR_FSM_OP_SELECT; 1673 /// <summary> Field "PRIME_ACCEPT_GETACCCR" at 0x3, width: 1 bits </summary> 1674 public IFlagRegisterField PRIME_ACCEPT_GETACCCR; 1675 /// <summary> Field "HANDOFF_DEEP_SLEEP" at 0x4, width: 1 bits </summary> 1676 public IFlagRegisterField HANDOFF_DEEP_SLEEP; 1677 /// <summary> Field "CR_REQUEST_SEND" at 0x5, width: 1 bits </summary> 1678 public IFlagRegisterField CR_REQUEST_SEND; 1679 /// <summary> Field "BAST_CCC_IBI_RING" at 0x8, width: 3 bits </summary> 1680 public IValueRegisterField BAST_CCC_IBI_RING; 1681 /// <summary> Field "TARGET_XACT_ENABLE" at 0xc, width: 1 bits </summary> 1682 public IFlagRegisterField TARGET_XACT_ENABLE; 1683 /// <summary> Field "DAA_SETAASA_ENABLE" at 0xd, width: 1 bits </summary> 1684 public IFlagRegisterField DAA_SETAASA_ENABLE; 1685 /// <summary> Field "DAA_SETDASA_ENABLE" at 0xe, width: 1 bits </summary> 1686 public IFlagRegisterField DAA_SETDASA_ENABLE; 1687 /// <summary> Field "DAA_ENTDAA_ENABLE" at 0xf, width: 1 bits </summary> 1688 public IFlagRegisterField DAA_ENTDAA_ENABLE; 1689 /// <summary> Field "RSTACT_DEFBYTE_02" at 0x14, width: 1 bits </summary> 1690 public IFlagRegisterField RSTACT_DEFBYTE_02; 1691 /// <summary> Field "STBY_CR_ENABLE_INIT" at 0x1e, width: 2 bits </summary> 1692 public IValueRegisterField STBY_CR_ENABLE_INIT; 1693 StbyCrControlTypeAntmicro.Renode.Peripherals.I3C.Caliptra_I3C.StbyCrControlType1694 public StbyCrControlType(IProvidesRegisterCollection<DoubleWordRegisterCollection> parent) 1695 { 1696 parent.RegistersCollection.DefineRegister(388, 4096, true) 1697 .WithFlag(0, out PENDING_RX_NACK, name: "PENDING_RX_NACK") 1698 .WithFlag(1, out HANDOFF_DELAY_NACK, name: "HANDOFF_DELAY_NACK") 1699 .WithFlag(2, out ACR_FSM_OP_SELECT, name: "ACR_FSM_OP_SELECT") 1700 .WithFlag(3, out PRIME_ACCEPT_GETACCCR, name: "PRIME_ACCEPT_GETACCCR") 1701 .WithFlag(4, out HANDOFF_DEEP_SLEEP, mode: FieldMode.Read | FieldMode.Write, name: "HANDOFF_DEEP_SLEEP") 1702 .WithFlag(5, out CR_REQUEST_SEND, mode: FieldMode.Write, name: "CR_REQUEST_SEND") 1703 .WithValueField(8, 3, out BAST_CCC_IBI_RING, name: "BAST_CCC_IBI_RING") 1704 .WithFlag(12, out TARGET_XACT_ENABLE, name: "TARGET_XACT_ENABLE") 1705 .WithFlag(13, out DAA_SETAASA_ENABLE, name: "DAA_SETAASA_ENABLE") 1706 .WithFlag(14, out DAA_SETDASA_ENABLE, name: "DAA_SETDASA_ENABLE") 1707 .WithFlag(15, out DAA_ENTDAA_ENABLE, name: "DAA_ENTDAA_ENABLE") 1708 .WithFlag(20, out RSTACT_DEFBYTE_02, name: "RSTACT_DEFBYTE_02") 1709 .WithValueField(30, 2, out STBY_CR_ENABLE_INIT, name: "STBY_CR_ENABLE_INIT"); 1710 } 1711 } 1712 1713 public struct StbyCrDeviceAddrType 1714 { 1715 /// <summary> Field "STATIC_ADDR" at 0x0, width: 7 bits </summary> 1716 public IValueRegisterField STATIC_ADDR; 1717 /// <summary> Field "STATIC_ADDR_VALID" at 0xf, width: 1 bits </summary> 1718 public IFlagRegisterField STATIC_ADDR_VALID; 1719 /// <summary> Field "DYNAMIC_ADDR" at 0x10, width: 7 bits </summary> 1720 public IValueRegisterField DYNAMIC_ADDR; 1721 /// <summary> Field "DYNAMIC_ADDR_VALID" at 0x1f, width: 1 bits </summary> 1722 public IFlagRegisterField DYNAMIC_ADDR_VALID; 1723 StbyCrDeviceAddrTypeAntmicro.Renode.Peripherals.I3C.Caliptra_I3C.StbyCrDeviceAddrType1724 public StbyCrDeviceAddrType(IProvidesRegisterCollection<DoubleWordRegisterCollection> parent) 1725 { 1726 parent.RegistersCollection.DefineRegister(392, 0, true) 1727 .WithValueField(0, 7, out STATIC_ADDR, name: "STATIC_ADDR") 1728 .WithFlag(15, out STATIC_ADDR_VALID, name: "STATIC_ADDR_VALID") 1729 .WithValueField(16, 7, out DYNAMIC_ADDR, name: "DYNAMIC_ADDR") 1730 .WithFlag(31, out DYNAMIC_ADDR_VALID, name: "DYNAMIC_ADDR_VALID"); 1731 } 1732 } 1733 1734 public struct StbyCrCapabilitiesType 1735 { 1736 /// <summary> Field "SIMPLE_CRR_SUPPORT" at 0x5, width: 1 bits </summary> 1737 public IFlagRegisterField SIMPLE_CRR_SUPPORT; 1738 /// <summary> Field "TARGET_XACT_SUPPORT" at 0xc, width: 1 bits </summary> 1739 public IFlagRegisterField TARGET_XACT_SUPPORT; 1740 /// <summary> Field "DAA_SETAASA_SUPPORT" at 0xd, width: 1 bits </summary> 1741 public IFlagRegisterField DAA_SETAASA_SUPPORT; 1742 /// <summary> Field "DAA_SETDASA_SUPPORT" at 0xe, width: 1 bits </summary> 1743 public IFlagRegisterField DAA_SETDASA_SUPPORT; 1744 /// <summary> Field "DAA_ENTDAA_SUPPORT" at 0xf, width: 1 bits </summary> 1745 public IFlagRegisterField DAA_ENTDAA_SUPPORT; 1746 StbyCrCapabilitiesTypeAntmicro.Renode.Peripherals.I3C.Caliptra_I3C.StbyCrCapabilitiesType1747 public StbyCrCapabilitiesType(IProvidesRegisterCollection<DoubleWordRegisterCollection> parent) 1748 { 1749 parent.RegistersCollection.DefineRegister(396, 28672, true) 1750 .WithFlag(5, out SIMPLE_CRR_SUPPORT, mode: FieldMode.Read, name: "SIMPLE_CRR_SUPPORT") 1751 .WithFlag(12, out TARGET_XACT_SUPPORT, mode: FieldMode.Read, name: "TARGET_XACT_SUPPORT") 1752 .WithFlag(13, out DAA_SETAASA_SUPPORT, mode: FieldMode.Read, name: "DAA_SETAASA_SUPPORT") 1753 .WithFlag(14, out DAA_SETDASA_SUPPORT, mode: FieldMode.Read, name: "DAA_SETDASA_SUPPORT") 1754 .WithFlag(15, out DAA_ENTDAA_SUPPORT, mode: FieldMode.Read, name: "DAA_ENTDAA_SUPPORT"); 1755 } 1756 } 1757 1758 public struct Rsvd0Type 1759 { 1760 /// <summary> Field "__rsvd" at 0x0, width: 32 bits </summary> 1761 public IValueRegisterField __RSVD; 1762 Rsvd0TypeAntmicro.Renode.Peripherals.I3C.Caliptra_I3C.Rsvd0Type1763 public Rsvd0Type(IProvidesRegisterCollection<DoubleWordRegisterCollection> parent) 1764 { 1765 parent.RegistersCollection.DefineRegister(400, 0, true) 1766 .WithValueField(0, 32, out __RSVD, name: "__RSVD"); 1767 } 1768 } 1769 1770 public struct StbyCrStatusType 1771 { 1772 /// <summary> Field "AC_CURRENT_OWN" at 0x2, width: 1 bits </summary> 1773 public IFlagRegisterField AC_CURRENT_OWN; 1774 /// <summary> Field "SIMPLE_CRR_STATUS" at 0x5, width: 3 bits </summary> 1775 public IValueRegisterField SIMPLE_CRR_STATUS; 1776 /// <summary> Field "HJ_REQ_STATUS" at 0x8, width: 1 bits </summary> 1777 public IFlagRegisterField HJ_REQ_STATUS; 1778 StbyCrStatusTypeAntmicro.Renode.Peripherals.I3C.Caliptra_I3C.StbyCrStatusType1779 public StbyCrStatusType(IProvidesRegisterCollection<DoubleWordRegisterCollection> parent) 1780 { 1781 parent.RegistersCollection.DefineRegister(404, 0, true) 1782 .WithFlag(2, out AC_CURRENT_OWN, name: "AC_CURRENT_OWN") 1783 .WithValueField(5, 3, out SIMPLE_CRR_STATUS, name: "SIMPLE_CRR_STATUS") 1784 .WithFlag(8, out HJ_REQ_STATUS, name: "HJ_REQ_STATUS"); 1785 } 1786 } 1787 1788 public struct StbyCrDeviceCharType 1789 { 1790 /// <summary> Field "PID_HI" at 0x1, width: 15 bits </summary> 1791 public IValueRegisterField PID_HI; 1792 /// <summary> Field "DCR" at 0x10, width: 8 bits </summary> 1793 public IValueRegisterField DCR; 1794 /// <summary> Field "BCR_VAR" at 0x18, width: 5 bits </summary> 1795 public IValueRegisterField BCR_VAR; 1796 /// <summary> Field "BCR_FIXED" at 0x1d, width: 3 bits </summary> 1797 public IValueRegisterField BCR_FIXED; 1798 StbyCrDeviceCharTypeAntmicro.Renode.Peripherals.I3C.Caliptra_I3C.StbyCrDeviceCharType1799 public StbyCrDeviceCharType(IProvidesRegisterCollection<DoubleWordRegisterCollection> parent) 1800 { 1801 parent.RegistersCollection.DefineRegister(408, 4294967294, true) 1802 .WithValueField(1, 15, out PID_HI, name: "PID_HI") 1803 .WithValueField(16, 8, out DCR, name: "DCR") 1804 .WithValueField(24, 5, out BCR_VAR, name: "BCR_VAR") 1805 .WithValueField(29, 3, out BCR_FIXED, name: "BCR_FIXED"); 1806 } 1807 } 1808 1809 public struct StbyCrDevicePidLoType 1810 { 1811 /// <summary> Field "PID_LO" at 0x0, width: 32 bits </summary> 1812 public IValueRegisterField PID_LO; 1813 StbyCrDevicePidLoTypeAntmicro.Renode.Peripherals.I3C.Caliptra_I3C.StbyCrDevicePidLoType1814 public StbyCrDevicePidLoType(IProvidesRegisterCollection<DoubleWordRegisterCollection> parent) 1815 { 1816 parent.RegistersCollection.DefineRegister(412, 4294967295, true) 1817 .WithValueField(0, 32, out PID_LO, name: "PID_LO"); 1818 } 1819 } 1820 1821 public struct StbyCrIntrStatusType 1822 { 1823 /// <summary> Field "ACR_HANDOFF_OK_REMAIN_STAT" at 0x0, width: 1 bits </summary> 1824 public IFlagRegisterField ACR_HANDOFF_OK_REMAIN_STAT; 1825 /// <summary> Field "ACR_HANDOFF_OK_PRIMED_STAT" at 0x1, width: 1 bits </summary> 1826 public IFlagRegisterField ACR_HANDOFF_OK_PRIMED_STAT; 1827 /// <summary> Field "ACR_HANDOFF_ERR_FAIL_STAT" at 0x2, width: 1 bits </summary> 1828 public IFlagRegisterField ACR_HANDOFF_ERR_FAIL_STAT; 1829 /// <summary> Field "ACR_HANDOFF_ERR_M3_STAT" at 0x3, width: 1 bits </summary> 1830 public IFlagRegisterField ACR_HANDOFF_ERR_M3_STAT; 1831 /// <summary> Field "CRR_RESPONSE_STAT" at 0xa, width: 1 bits </summary> 1832 public IFlagRegisterField CRR_RESPONSE_STAT; 1833 /// <summary> Field "STBY_CR_DYN_ADDR_STAT" at 0xb, width: 1 bits </summary> 1834 public IFlagRegisterField STBY_CR_DYN_ADDR_STAT; 1835 /// <summary> Field "STBY_CR_ACCEPT_NACKED_STAT" at 0xc, width: 1 bits </summary> 1836 public IFlagRegisterField STBY_CR_ACCEPT_NACKED_STAT; 1837 /// <summary> Field "STBY_CR_ACCEPT_OK_STAT" at 0xd, width: 1 bits </summary> 1838 public IFlagRegisterField STBY_CR_ACCEPT_OK_STAT; 1839 /// <summary> Field "STBY_CR_ACCEPT_ERR_STAT" at 0xe, width: 1 bits </summary> 1840 public IFlagRegisterField STBY_CR_ACCEPT_ERR_STAT; 1841 /// <summary> Field "STBY_CR_OP_RSTACT_STAT" at 0x10, width: 1 bits </summary> 1842 public IFlagRegisterField STBY_CR_OP_RSTACT_STAT; 1843 /// <summary> Field "CCC_PARAM_MODIFIED_STAT" at 0x11, width: 1 bits </summary> 1844 public IFlagRegisterField CCC_PARAM_MODIFIED_STAT; 1845 /// <summary> Field "CCC_UNHANDLED_NACK_STAT" at 0x12, width: 1 bits </summary> 1846 public IFlagRegisterField CCC_UNHANDLED_NACK_STAT; 1847 /// <summary> Field "CCC_FATAL_RSTDAA_ERR_STAT" at 0x13, width: 1 bits </summary> 1848 public IFlagRegisterField CCC_FATAL_RSTDAA_ERR_STAT; 1849 StbyCrIntrStatusTypeAntmicro.Renode.Peripherals.I3C.Caliptra_I3C.StbyCrIntrStatusType1850 public StbyCrIntrStatusType(IProvidesRegisterCollection<DoubleWordRegisterCollection> parent) 1851 { 1852 parent.RegistersCollection.DefineRegister(416, 0, true) 1853 .WithFlag(0, out ACR_HANDOFF_OK_REMAIN_STAT, name: "ACR_HANDOFF_OK_REMAIN_STAT") 1854 .WithFlag(1, out ACR_HANDOFF_OK_PRIMED_STAT, name: "ACR_HANDOFF_OK_PRIMED_STAT") 1855 .WithFlag(2, out ACR_HANDOFF_ERR_FAIL_STAT, name: "ACR_HANDOFF_ERR_FAIL_STAT") 1856 .WithFlag(3, out ACR_HANDOFF_ERR_M3_STAT, name: "ACR_HANDOFF_ERR_M3_STAT") 1857 .WithFlag(10, out CRR_RESPONSE_STAT, name: "CRR_RESPONSE_STAT") 1858 .WithFlag(11, out STBY_CR_DYN_ADDR_STAT, name: "STBY_CR_DYN_ADDR_STAT") 1859 .WithFlag(12, out STBY_CR_ACCEPT_NACKED_STAT, name: "STBY_CR_ACCEPT_NACKED_STAT") 1860 .WithFlag(13, out STBY_CR_ACCEPT_OK_STAT, name: "STBY_CR_ACCEPT_OK_STAT") 1861 .WithFlag(14, out STBY_CR_ACCEPT_ERR_STAT, name: "STBY_CR_ACCEPT_ERR_STAT") 1862 .WithFlag(16, out STBY_CR_OP_RSTACT_STAT, name: "STBY_CR_OP_RSTACT_STAT") 1863 .WithFlag(17, out CCC_PARAM_MODIFIED_STAT, name: "CCC_PARAM_MODIFIED_STAT") 1864 .WithFlag(18, out CCC_UNHANDLED_NACK_STAT, name: "CCC_UNHANDLED_NACK_STAT") 1865 .WithFlag(19, out CCC_FATAL_RSTDAA_ERR_STAT, name: "CCC_FATAL_RSTDAA_ERR_STAT"); 1866 } 1867 } 1868 1869 public struct Rsvd1Type 1870 { 1871 /// <summary> Field "__rsvd" at 0x0, width: 32 bits </summary> 1872 public IValueRegisterField __RSVD; 1873 Rsvd1TypeAntmicro.Renode.Peripherals.I3C.Caliptra_I3C.Rsvd1Type1874 public Rsvd1Type(IProvidesRegisterCollection<DoubleWordRegisterCollection> parent) 1875 { 1876 parent.RegistersCollection.DefineRegister(420, 0, true) 1877 .WithValueField(0, 32, out __RSVD, name: "__RSVD"); 1878 } 1879 } 1880 1881 public struct StbyCrIntrSignalEnableType 1882 { 1883 /// <summary> Field "ACR_HANDOFF_OK_REMAIN_SIGNAL_EN" at 0x0, width: 1 bits </summary> 1884 public IFlagRegisterField ACR_HANDOFF_OK_REMAIN_SIGNAL_EN; 1885 /// <summary> Field "ACR_HANDOFF_OK_PRIMED_SIGNAL_EN" at 0x1, width: 1 bits </summary> 1886 public IFlagRegisterField ACR_HANDOFF_OK_PRIMED_SIGNAL_EN; 1887 /// <summary> Field "ACR_HANDOFF_ERR_FAIL_SIGNAL_EN" at 0x2, width: 1 bits </summary> 1888 public IFlagRegisterField ACR_HANDOFF_ERR_FAIL_SIGNAL_EN; 1889 /// <summary> Field "ACR_HANDOFF_ERR_M3_SIGNAL_EN" at 0x3, width: 1 bits </summary> 1890 public IFlagRegisterField ACR_HANDOFF_ERR_M3_SIGNAL_EN; 1891 /// <summary> Field "CRR_RESPONSE_SIGNAL_EN" at 0xa, width: 1 bits </summary> 1892 public IFlagRegisterField CRR_RESPONSE_SIGNAL_EN; 1893 /// <summary> Field "STBY_CR_DYN_ADDR_SIGNAL_EN" at 0xb, width: 1 bits </summary> 1894 public IFlagRegisterField STBY_CR_DYN_ADDR_SIGNAL_EN; 1895 /// <summary> Field "STBY_CR_ACCEPT_NACKED_SIGNAL_EN" at 0xc, width: 1 bits </summary> 1896 public IFlagRegisterField STBY_CR_ACCEPT_NACKED_SIGNAL_EN; 1897 /// <summary> Field "STBY_CR_ACCEPT_OK_SIGNAL_EN" at 0xd, width: 1 bits </summary> 1898 public IFlagRegisterField STBY_CR_ACCEPT_OK_SIGNAL_EN; 1899 /// <summary> Field "STBY_CR_ACCEPT_ERR_SIGNAL_EN" at 0xe, width: 1 bits </summary> 1900 public IFlagRegisterField STBY_CR_ACCEPT_ERR_SIGNAL_EN; 1901 /// <summary> Field "STBY_CR_OP_RSTACT_SIGNAL_EN" at 0x10, width: 1 bits </summary> 1902 public IFlagRegisterField STBY_CR_OP_RSTACT_SIGNAL_EN; 1903 /// <summary> Field "CCC_PARAM_MODIFIED_SIGNAL_EN" at 0x11, width: 1 bits </summary> 1904 public IFlagRegisterField CCC_PARAM_MODIFIED_SIGNAL_EN; 1905 /// <summary> Field "CCC_UNHANDLED_NACK_SIGNAL_EN" at 0x12, width: 1 bits </summary> 1906 public IFlagRegisterField CCC_UNHANDLED_NACK_SIGNAL_EN; 1907 /// <summary> Field "CCC_FATAL_RSTDAA_ERR_SIGNAL_EN" at 0x13, width: 1 bits </summary> 1908 public IFlagRegisterField CCC_FATAL_RSTDAA_ERR_SIGNAL_EN; 1909 StbyCrIntrSignalEnableTypeAntmicro.Renode.Peripherals.I3C.Caliptra_I3C.StbyCrIntrSignalEnableType1910 public StbyCrIntrSignalEnableType(IProvidesRegisterCollection<DoubleWordRegisterCollection> parent) 1911 { 1912 parent.RegistersCollection.DefineRegister(424, 0, true) 1913 .WithFlag(0, out ACR_HANDOFF_OK_REMAIN_SIGNAL_EN, name: "ACR_HANDOFF_OK_REMAIN_SIGNAL_EN") 1914 .WithFlag(1, out ACR_HANDOFF_OK_PRIMED_SIGNAL_EN, name: "ACR_HANDOFF_OK_PRIMED_SIGNAL_EN") 1915 .WithFlag(2, out ACR_HANDOFF_ERR_FAIL_SIGNAL_EN, name: "ACR_HANDOFF_ERR_FAIL_SIGNAL_EN") 1916 .WithFlag(3, out ACR_HANDOFF_ERR_M3_SIGNAL_EN, name: "ACR_HANDOFF_ERR_M3_SIGNAL_EN") 1917 .WithFlag(10, out CRR_RESPONSE_SIGNAL_EN, name: "CRR_RESPONSE_SIGNAL_EN") 1918 .WithFlag(11, out STBY_CR_DYN_ADDR_SIGNAL_EN, name: "STBY_CR_DYN_ADDR_SIGNAL_EN") 1919 .WithFlag(12, out STBY_CR_ACCEPT_NACKED_SIGNAL_EN, name: "STBY_CR_ACCEPT_NACKED_SIGNAL_EN") 1920 .WithFlag(13, out STBY_CR_ACCEPT_OK_SIGNAL_EN, name: "STBY_CR_ACCEPT_OK_SIGNAL_EN") 1921 .WithFlag(14, out STBY_CR_ACCEPT_ERR_SIGNAL_EN, name: "STBY_CR_ACCEPT_ERR_SIGNAL_EN") 1922 .WithFlag(16, out STBY_CR_OP_RSTACT_SIGNAL_EN, name: "STBY_CR_OP_RSTACT_SIGNAL_EN") 1923 .WithFlag(17, out CCC_PARAM_MODIFIED_SIGNAL_EN, name: "CCC_PARAM_MODIFIED_SIGNAL_EN") 1924 .WithFlag(18, out CCC_UNHANDLED_NACK_SIGNAL_EN, name: "CCC_UNHANDLED_NACK_SIGNAL_EN") 1925 .WithFlag(19, out CCC_FATAL_RSTDAA_ERR_SIGNAL_EN, name: "CCC_FATAL_RSTDAA_ERR_SIGNAL_EN"); 1926 } 1927 } 1928 1929 public struct StbyCrIntrForceType 1930 { 1931 /// <summary> Field "CRR_RESPONSE_FORCE" at 0xa, width: 1 bits </summary> 1932 public IFlagRegisterField CRR_RESPONSE_FORCE; 1933 /// <summary> Field "STBY_CR_DYN_ADDR_FORCE" at 0xb, width: 1 bits </summary> 1934 public IFlagRegisterField STBY_CR_DYN_ADDR_FORCE; 1935 /// <summary> Field "STBY_CR_ACCEPT_NACKED_FORCE" at 0xc, width: 1 bits </summary> 1936 public IFlagRegisterField STBY_CR_ACCEPT_NACKED_FORCE; 1937 /// <summary> Field "STBY_CR_ACCEPT_OK_FORCE" at 0xd, width: 1 bits </summary> 1938 public IFlagRegisterField STBY_CR_ACCEPT_OK_FORCE; 1939 /// <summary> Field "STBY_CR_ACCEPT_ERR_FORCE" at 0xe, width: 1 bits </summary> 1940 public IFlagRegisterField STBY_CR_ACCEPT_ERR_FORCE; 1941 /// <summary> Field "STBY_CR_OP_RSTACT_FORCE" at 0x10, width: 1 bits </summary> 1942 public IFlagRegisterField STBY_CR_OP_RSTACT_FORCE; 1943 /// <summary> Field "CCC_PARAM_MODIFIED_FORCE" at 0x11, width: 1 bits </summary> 1944 public IFlagRegisterField CCC_PARAM_MODIFIED_FORCE; 1945 /// <summary> Field "CCC_UNHANDLED_NACK_FORCE" at 0x12, width: 1 bits </summary> 1946 public IFlagRegisterField CCC_UNHANDLED_NACK_FORCE; 1947 /// <summary> Field "CCC_FATAL_RSTDAA_ERR_FORCE" at 0x13, width: 1 bits </summary> 1948 public IFlagRegisterField CCC_FATAL_RSTDAA_ERR_FORCE; 1949 StbyCrIntrForceTypeAntmicro.Renode.Peripherals.I3C.Caliptra_I3C.StbyCrIntrForceType1950 public StbyCrIntrForceType(IProvidesRegisterCollection<DoubleWordRegisterCollection> parent) 1951 { 1952 parent.RegistersCollection.DefineRegister(428, 0, true) 1953 .WithFlag(10, out CRR_RESPONSE_FORCE, name: "CRR_RESPONSE_FORCE") 1954 .WithFlag(11, out STBY_CR_DYN_ADDR_FORCE, name: "STBY_CR_DYN_ADDR_FORCE") 1955 .WithFlag(12, out STBY_CR_ACCEPT_NACKED_FORCE, name: "STBY_CR_ACCEPT_NACKED_FORCE") 1956 .WithFlag(13, out STBY_CR_ACCEPT_OK_FORCE, name: "STBY_CR_ACCEPT_OK_FORCE") 1957 .WithFlag(14, out STBY_CR_ACCEPT_ERR_FORCE, name: "STBY_CR_ACCEPT_ERR_FORCE") 1958 .WithFlag(16, out STBY_CR_OP_RSTACT_FORCE, mode: FieldMode.Write, name: "STBY_CR_OP_RSTACT_FORCE") 1959 .WithFlag(17, out CCC_PARAM_MODIFIED_FORCE, name: "CCC_PARAM_MODIFIED_FORCE") 1960 .WithFlag(18, out CCC_UNHANDLED_NACK_FORCE, name: "CCC_UNHANDLED_NACK_FORCE") 1961 .WithFlag(19, out CCC_FATAL_RSTDAA_ERR_FORCE, name: "CCC_FATAL_RSTDAA_ERR_FORCE"); 1962 } 1963 } 1964 1965 public struct StbyCrCccConfigGetcapsType 1966 { 1967 /// <summary> Field "F2_CRCAP1_BUS_CONFIG" at 0x0, width: 3 bits </summary> 1968 public IValueRegisterField F2_CRCAP1_BUS_CONFIG; 1969 /// <summary> Field "F2_CRCAP2_DEV_INTERACT" at 0x8, width: 4 bits </summary> 1970 public IValueRegisterField F2_CRCAP2_DEV_INTERACT; 1971 StbyCrCccConfigGetcapsTypeAntmicro.Renode.Peripherals.I3C.Caliptra_I3C.StbyCrCccConfigGetcapsType1972 public StbyCrCccConfigGetcapsType(IProvidesRegisterCollection<DoubleWordRegisterCollection> parent) 1973 { 1974 parent.RegistersCollection.DefineRegister(432, 0, true) 1975 .WithValueField(0, 3, out F2_CRCAP1_BUS_CONFIG, name: "F2_CRCAP1_BUS_CONFIG") 1976 .WithValueField(8, 4, out F2_CRCAP2_DEV_INTERACT, name: "F2_CRCAP2_DEV_INTERACT"); 1977 } 1978 } 1979 1980 public struct StbyCrCccConfigRstactParamsType 1981 { 1982 /// <summary> Field "RST_ACTION" at 0x0, width: 8 bits </summary> 1983 public IValueRegisterField RST_ACTION; 1984 /// <summary> Field "RESET_TIME_PERIPHERAL" at 0x8, width: 8 bits </summary> 1985 public IValueRegisterField RESET_TIME_PERIPHERAL; 1986 /// <summary> Field "RESET_TIME_TARGET" at 0x10, width: 8 bits </summary> 1987 public IValueRegisterField RESET_TIME_TARGET; 1988 /// <summary> Field "RESET_DYNAMIC_ADDR" at 0x1f, width: 1 bits </summary> 1989 public IFlagRegisterField RESET_DYNAMIC_ADDR; 1990 StbyCrCccConfigRstactParamsTypeAntmicro.Renode.Peripherals.I3C.Caliptra_I3C.StbyCrCccConfigRstactParamsType1991 public StbyCrCccConfigRstactParamsType(IProvidesRegisterCollection<DoubleWordRegisterCollection> parent) 1992 { 1993 parent.RegistersCollection.DefineRegister(436, 2147483648, true) 1994 .WithValueField(0, 8, out RST_ACTION, mode: FieldMode.Read, name: "RST_ACTION") 1995 .WithValueField(8, 8, out RESET_TIME_PERIPHERAL, name: "RESET_TIME_PERIPHERAL") 1996 .WithValueField(16, 8, out RESET_TIME_TARGET, name: "RESET_TIME_TARGET") 1997 .WithFlag(31, out RESET_DYNAMIC_ADDR, name: "RESET_DYNAMIC_ADDR"); 1998 } 1999 } 2000 2001 public struct StbyCrVirtDeviceAddrType 2002 { 2003 /// <summary> Field "VIRT_STATIC_ADDR" at 0x0, width: 7 bits </summary> 2004 public IValueRegisterField VIRT_STATIC_ADDR; 2005 /// <summary> Field "VIRT_STATIC_ADDR_VALID" at 0xf, width: 1 bits </summary> 2006 public IFlagRegisterField VIRT_STATIC_ADDR_VALID; 2007 /// <summary> Field "VIRT_DYNAMIC_ADDR" at 0x10, width: 7 bits </summary> 2008 public IValueRegisterField VIRT_DYNAMIC_ADDR; 2009 /// <summary> Field "VIRT_DYNAMIC_ADDR_VALID" at 0x1f, width: 1 bits </summary> 2010 public IFlagRegisterField VIRT_DYNAMIC_ADDR_VALID; 2011 StbyCrVirtDeviceAddrTypeAntmicro.Renode.Peripherals.I3C.Caliptra_I3C.StbyCrVirtDeviceAddrType2012 public StbyCrVirtDeviceAddrType(IProvidesRegisterCollection<DoubleWordRegisterCollection> parent) 2013 { 2014 parent.RegistersCollection.DefineRegister(440, 0, true) 2015 .WithValueField(0, 7, out VIRT_STATIC_ADDR, name: "VIRT_STATIC_ADDR") 2016 .WithFlag(15, out VIRT_STATIC_ADDR_VALID, name: "VIRT_STATIC_ADDR_VALID") 2017 .WithValueField(16, 7, out VIRT_DYNAMIC_ADDR, name: "VIRT_DYNAMIC_ADDR") 2018 .WithFlag(31, out VIRT_DYNAMIC_ADDR_VALID, name: "VIRT_DYNAMIC_ADDR_VALID"); 2019 } 2020 } 2021 2022 public struct Rsvd3Type 2023 { 2024 /// <summary> Field "__rsvd" at 0x0, width: 32 bits </summary> 2025 public IValueRegisterField __RSVD; 2026 Rsvd3TypeAntmicro.Renode.Peripherals.I3C.Caliptra_I3C.Rsvd3Type2027 public Rsvd3Type(IProvidesRegisterCollection<DoubleWordRegisterCollection> parent) 2028 { 2029 parent.RegistersCollection.DefineRegister(444, 0, true) 2030 .WithValueField(0, 32, out __RSVD, name: "__RSVD"); 2031 } 2032 } 2033 2034 public struct ControlType 2035 { 2036 /// <summary> Field "HJ_EN" at 0xa, width: 1 bits </summary> 2037 public IFlagRegisterField HJ_EN; 2038 /// <summary> Field "CRR_EN" at 0xb, width: 1 bits </summary> 2039 public IFlagRegisterField CRR_EN; 2040 /// <summary> Field "IBI_EN" at 0xc, width: 1 bits </summary> 2041 public IFlagRegisterField IBI_EN; 2042 /// <summary> Field "IBI_RETRY_NUM" at 0xd, width: 3 bits </summary> 2043 public IValueRegisterField IBI_RETRY_NUM; 2044 ControlTypeAntmicro.Renode.Peripherals.I3C.Caliptra_I3C.ControlType2045 public ControlType(IProvidesRegisterCollection<DoubleWordRegisterCollection> parent) 2046 { 2047 parent.RegistersCollection.DefineRegister(452, 5120, true) 2048 .WithFlag(10, out HJ_EN, name: "HJ_EN") 2049 .WithFlag(11, out CRR_EN, name: "CRR_EN") 2050 .WithFlag(12, out IBI_EN, name: "IBI_EN") 2051 .WithValueField(13, 3, out IBI_RETRY_NUM, name: "IBI_RETRY_NUM"); 2052 } 2053 } 2054 2055 public struct StatusType 2056 { 2057 /// <summary> Field "PROTOCOL_ERROR" at 0xd, width: 1 bits </summary> 2058 public IFlagRegisterField PROTOCOL_ERROR; 2059 /// <summary> Field "LAST_IBI_STATUS" at 0xe, width: 2 bits </summary> 2060 public IValueRegisterField LAST_IBI_STATUS; 2061 StatusTypeAntmicro.Renode.Peripherals.I3C.Caliptra_I3C.StatusType2062 public StatusType(IProvidesRegisterCollection<DoubleWordRegisterCollection> parent) 2063 { 2064 parent.RegistersCollection.DefineRegister(456, 0, true) 2065 .WithFlag(13, out PROTOCOL_ERROR, mode: FieldMode.Read, name: "PROTOCOL_ERROR") 2066 .WithValueField(14, 2, out LAST_IBI_STATUS, mode: FieldMode.Read, name: "LAST_IBI_STATUS"); 2067 } 2068 } 2069 2070 public struct InterruptStatusType 2071 { 2072 /// <summary> Field "RX_DESC_STAT" at 0x0, width: 1 bits </summary> 2073 public IFlagRegisterField RX_DESC_STAT; 2074 /// <summary> Field "TX_DESC_STAT" at 0x1, width: 1 bits </summary> 2075 public IFlagRegisterField TX_DESC_STAT; 2076 /// <summary> Field "RX_DESC_TIMEOUT" at 0x2, width: 1 bits </summary> 2077 public IFlagRegisterField RX_DESC_TIMEOUT; 2078 /// <summary> Field "TX_DESC_TIMEOUT" at 0x3, width: 1 bits </summary> 2079 public IFlagRegisterField TX_DESC_TIMEOUT; 2080 /// <summary> Field "TX_DATA_THLD_STAT" at 0x8, width: 1 bits </summary> 2081 public IFlagRegisterField TX_DATA_THLD_STAT; 2082 /// <summary> Field "RX_DATA_THLD_STAT" at 0x9, width: 1 bits </summary> 2083 public IFlagRegisterField RX_DATA_THLD_STAT; 2084 /// <summary> Field "TX_DESC_THLD_STAT" at 0xa, width: 1 bits </summary> 2085 public IFlagRegisterField TX_DESC_THLD_STAT; 2086 /// <summary> Field "RX_DESC_THLD_STAT" at 0xb, width: 1 bits </summary> 2087 public IFlagRegisterField RX_DESC_THLD_STAT; 2088 /// <summary> Field "IBI_THLD_STAT" at 0xc, width: 1 bits </summary> 2089 public IFlagRegisterField IBI_THLD_STAT; 2090 /// <summary> Field "IBI_DONE" at 0xd, width: 1 bits </summary> 2091 public IFlagRegisterField IBI_DONE; 2092 /// <summary> Field "PENDING_INTERRUPT" at 0xf, width: 4 bits </summary> 2093 public IValueRegisterField PENDING_INTERRUPT; 2094 /// <summary> Field "TRANSFER_ABORT_STAT" at 0x19, width: 1 bits </summary> 2095 public IFlagRegisterField TRANSFER_ABORT_STAT; 2096 /// <summary> Field "TRANSFER_ERR_STAT" at 0x1f, width: 1 bits </summary> 2097 public IFlagRegisterField TRANSFER_ERR_STAT; 2098 InterruptStatusTypeAntmicro.Renode.Peripherals.I3C.Caliptra_I3C.InterruptStatusType2099 public InterruptStatusType(IProvidesRegisterCollection<DoubleWordRegisterCollection> parent) 2100 { 2101 parent.RegistersCollection.DefineRegister(464, 0, true) 2102 .WithFlag(0, out RX_DESC_STAT, mode: FieldMode.Read | FieldMode.WriteOneToClear, name: "RX_DESC_STAT") 2103 .WithFlag(1, out TX_DESC_STAT, mode: FieldMode.Read | FieldMode.WriteOneToClear, name: "TX_DESC_STAT") 2104 .WithFlag(2, out RX_DESC_TIMEOUT, mode: FieldMode.Read | FieldMode.WriteOneToClear, name: "RX_DESC_TIMEOUT") 2105 .WithFlag(3, out TX_DESC_TIMEOUT, mode: FieldMode.Read | FieldMode.WriteOneToClear, name: "TX_DESC_TIMEOUT") 2106 .WithFlag(8, out TX_DATA_THLD_STAT, mode: FieldMode.Read | FieldMode.WriteOneToClear, name: "TX_DATA_THLD_STAT") 2107 .WithFlag(9, out RX_DATA_THLD_STAT, mode: FieldMode.Read | FieldMode.WriteOneToClear, name: "RX_DATA_THLD_STAT") 2108 .WithFlag(10, out TX_DESC_THLD_STAT, mode: FieldMode.Read | FieldMode.WriteOneToClear, name: "TX_DESC_THLD_STAT") 2109 .WithFlag(11, out RX_DESC_THLD_STAT, mode: FieldMode.Read | FieldMode.WriteOneToClear, name: "RX_DESC_THLD_STAT") 2110 .WithFlag(12, out IBI_THLD_STAT, mode: FieldMode.Read | FieldMode.WriteOneToClear, name: "IBI_THLD_STAT") 2111 .WithFlag(13, out IBI_DONE, mode: FieldMode.Read | FieldMode.WriteOneToClear, name: "IBI_DONE") 2112 .WithValueField(15, 4, out PENDING_INTERRUPT, mode: FieldMode.Read | FieldMode.WriteOneToClear, name: "PENDING_INTERRUPT") 2113 .WithFlag(25, out TRANSFER_ABORT_STAT, mode: FieldMode.Read | FieldMode.WriteOneToClear, name: "TRANSFER_ABORT_STAT") 2114 .WithFlag(31, out TRANSFER_ERR_STAT, mode: FieldMode.Read | FieldMode.WriteOneToClear, name: "TRANSFER_ERR_STAT"); 2115 } 2116 } 2117 2118 public struct InterruptEnableType 2119 { 2120 /// <summary> Field "RX_DESC_STAT_EN" at 0x0, width: 1 bits </summary> 2121 public IFlagRegisterField RX_DESC_STAT_EN; 2122 /// <summary> Field "TX_DESC_STAT_EN" at 0x1, width: 1 bits </summary> 2123 public IFlagRegisterField TX_DESC_STAT_EN; 2124 /// <summary> Field "RX_DESC_TIMEOUT_EN" at 0x2, width: 1 bits </summary> 2125 public IFlagRegisterField RX_DESC_TIMEOUT_EN; 2126 /// <summary> Field "TX_DESC_TIMEOUT_EN" at 0x3, width: 1 bits </summary> 2127 public IFlagRegisterField TX_DESC_TIMEOUT_EN; 2128 /// <summary> Field "TX_DATA_THLD_STAT_EN" at 0x8, width: 1 bits </summary> 2129 public IFlagRegisterField TX_DATA_THLD_STAT_EN; 2130 /// <summary> Field "RX_DATA_THLD_STAT_EN" at 0x9, width: 1 bits </summary> 2131 public IFlagRegisterField RX_DATA_THLD_STAT_EN; 2132 /// <summary> Field "TX_DESC_THLD_STAT_EN" at 0xa, width: 1 bits </summary> 2133 public IFlagRegisterField TX_DESC_THLD_STAT_EN; 2134 /// <summary> Field "RX_DESC_THLD_STAT_EN" at 0xb, width: 1 bits </summary> 2135 public IFlagRegisterField RX_DESC_THLD_STAT_EN; 2136 /// <summary> Field "IBI_THLD_STAT_EN" at 0xc, width: 1 bits </summary> 2137 public IFlagRegisterField IBI_THLD_STAT_EN; 2138 /// <summary> Field "IBI_DONE_EN" at 0xd, width: 1 bits </summary> 2139 public IFlagRegisterField IBI_DONE_EN; 2140 /// <summary> Field "TRANSFER_ABORT_STAT_EN" at 0x19, width: 1 bits </summary> 2141 public IFlagRegisterField TRANSFER_ABORT_STAT_EN; 2142 /// <summary> Field "TRANSFER_ERR_STAT_EN" at 0x1f, width: 1 bits </summary> 2143 public IFlagRegisterField TRANSFER_ERR_STAT_EN; 2144 InterruptEnableTypeAntmicro.Renode.Peripherals.I3C.Caliptra_I3C.InterruptEnableType2145 public InterruptEnableType(IProvidesRegisterCollection<DoubleWordRegisterCollection> parent) 2146 { 2147 parent.RegistersCollection.DefineRegister(468, 0, true) 2148 .WithFlag(0, out RX_DESC_STAT_EN, name: "RX_DESC_STAT_EN") 2149 .WithFlag(1, out TX_DESC_STAT_EN, name: "TX_DESC_STAT_EN") 2150 .WithFlag(2, out RX_DESC_TIMEOUT_EN, name: "RX_DESC_TIMEOUT_EN") 2151 .WithFlag(3, out TX_DESC_TIMEOUT_EN, name: "TX_DESC_TIMEOUT_EN") 2152 .WithFlag(8, out TX_DATA_THLD_STAT_EN, name: "TX_DATA_THLD_STAT_EN") 2153 .WithFlag(9, out RX_DATA_THLD_STAT_EN, name: "RX_DATA_THLD_STAT_EN") 2154 .WithFlag(10, out TX_DESC_THLD_STAT_EN, name: "TX_DESC_THLD_STAT_EN") 2155 .WithFlag(11, out RX_DESC_THLD_STAT_EN, name: "RX_DESC_THLD_STAT_EN") 2156 .WithFlag(12, out IBI_THLD_STAT_EN, name: "IBI_THLD_STAT_EN") 2157 .WithFlag(13, out IBI_DONE_EN, name: "IBI_DONE_EN") 2158 .WithFlag(25, out TRANSFER_ABORT_STAT_EN, name: "TRANSFER_ABORT_STAT_EN") 2159 .WithFlag(31, out TRANSFER_ERR_STAT_EN, name: "TRANSFER_ERR_STAT_EN"); 2160 } 2161 } 2162 2163 public struct InterruptForceType 2164 { 2165 /// <summary> Field "RX_DESC_STAT_FORCE" at 0x0, width: 1 bits </summary> 2166 public IFlagRegisterField RX_DESC_STAT_FORCE; 2167 /// <summary> Field "TX_DESC_STAT_FORCE" at 0x1, width: 1 bits </summary> 2168 public IFlagRegisterField TX_DESC_STAT_FORCE; 2169 /// <summary> Field "RX_DESC_TIMEOUT_FORCE" at 0x2, width: 1 bits </summary> 2170 public IFlagRegisterField RX_DESC_TIMEOUT_FORCE; 2171 /// <summary> Field "TX_DESC_TIMEOUT_FORCE" at 0x3, width: 1 bits </summary> 2172 public IFlagRegisterField TX_DESC_TIMEOUT_FORCE; 2173 /// <summary> Field "TX_DATA_THLD_FORCE" at 0x8, width: 1 bits </summary> 2174 public IFlagRegisterField TX_DATA_THLD_FORCE; 2175 /// <summary> Field "RX_DATA_THLD_FORCE" at 0x9, width: 1 bits </summary> 2176 public IFlagRegisterField RX_DATA_THLD_FORCE; 2177 /// <summary> Field "TX_DESC_THLD_FORCE" at 0xa, width: 1 bits </summary> 2178 public IFlagRegisterField TX_DESC_THLD_FORCE; 2179 /// <summary> Field "RX_DESC_THLD_FORCE" at 0xb, width: 1 bits </summary> 2180 public IFlagRegisterField RX_DESC_THLD_FORCE; 2181 /// <summary> Field "IBI_THLD_FORCE" at 0xc, width: 1 bits </summary> 2182 public IFlagRegisterField IBI_THLD_FORCE; 2183 /// <summary> Field "IBI_DONE_FORCE" at 0xd, width: 1 bits </summary> 2184 public IFlagRegisterField IBI_DONE_FORCE; 2185 /// <summary> Field "TRANSFER_ABORT_STAT_FORCE" at 0x19, width: 1 bits </summary> 2186 public IFlagRegisterField TRANSFER_ABORT_STAT_FORCE; 2187 /// <summary> Field "TRANSFER_ERR_STAT_FORCE" at 0x1f, width: 1 bits </summary> 2188 public IFlagRegisterField TRANSFER_ERR_STAT_FORCE; 2189 InterruptForceTypeAntmicro.Renode.Peripherals.I3C.Caliptra_I3C.InterruptForceType2190 public InterruptForceType(IProvidesRegisterCollection<DoubleWordRegisterCollection> parent) 2191 { 2192 parent.RegistersCollection.DefineRegister(472, 0, true) 2193 .WithFlag(0, out RX_DESC_STAT_FORCE, name: "RX_DESC_STAT_FORCE") 2194 .WithFlag(1, out TX_DESC_STAT_FORCE, name: "TX_DESC_STAT_FORCE") 2195 .WithFlag(2, out RX_DESC_TIMEOUT_FORCE, name: "RX_DESC_TIMEOUT_FORCE") 2196 .WithFlag(3, out TX_DESC_TIMEOUT_FORCE, name: "TX_DESC_TIMEOUT_FORCE") 2197 .WithFlag(8, out TX_DATA_THLD_FORCE, name: "TX_DATA_THLD_FORCE") 2198 .WithFlag(9, out RX_DATA_THLD_FORCE, name: "RX_DATA_THLD_FORCE") 2199 .WithFlag(10, out TX_DESC_THLD_FORCE, name: "TX_DESC_THLD_FORCE") 2200 .WithFlag(11, out RX_DESC_THLD_FORCE, name: "RX_DESC_THLD_FORCE") 2201 .WithFlag(12, out IBI_THLD_FORCE, name: "IBI_THLD_FORCE") 2202 .WithFlag(13, out IBI_DONE_FORCE, name: "IBI_DONE_FORCE") 2203 .WithFlag(25, out TRANSFER_ABORT_STAT_FORCE, name: "TRANSFER_ABORT_STAT_FORCE") 2204 .WithFlag(31, out TRANSFER_ERR_STAT_FORCE, name: "TRANSFER_ERR_STAT_FORCE"); 2205 } 2206 } 2207 2208 public struct RxDescQueuePortType 2209 { 2210 /// <summary> Field "RX_DESC" at 0x0, width: 32 bits </summary> 2211 public IValueRegisterField RX_DESC; 2212 RxDescQueuePortTypeAntmicro.Renode.Peripherals.I3C.Caliptra_I3C.RxDescQueuePortType2213 public RxDescQueuePortType(IProvidesRegisterCollection<DoubleWordRegisterCollection> parent) 2214 { 2215 parent.RegistersCollection.DefineRegister(476, 0, true) 2216 .WithValueField(0, 32, out RX_DESC, mode: FieldMode.Read, name: "RX_DESC"); 2217 } 2218 } 2219 2220 public struct TxDescQueuePortType 2221 { 2222 /// <summary> Field "TX_DESC" at 0x0, width: 32 bits </summary> 2223 public IValueRegisterField TX_DESC; 2224 TxDescQueuePortTypeAntmicro.Renode.Peripherals.I3C.Caliptra_I3C.TxDescQueuePortType2225 public TxDescQueuePortType(IProvidesRegisterCollection<DoubleWordRegisterCollection> parent) 2226 { 2227 parent.RegistersCollection.DefineRegister(484, 0, true) 2228 .WithValueField(0, 32, out TX_DESC, mode: FieldMode.Write, name: "TX_DESC"); 2229 } 2230 } 2231 2232 public struct IbiQueueSizeType 2233 { 2234 /// <summary> Field "IBI_QUEUE_SIZE" at 0x0, width: 8 bits </summary> 2235 public IValueRegisterField IBI_QUEUE_SIZE; 2236 IbiQueueSizeTypeAntmicro.Renode.Peripherals.I3C.Caliptra_I3C.IbiQueueSizeType2237 public IbiQueueSizeType(IProvidesRegisterCollection<DoubleWordRegisterCollection> parent) 2238 { 2239 parent.RegistersCollection.DefineRegister(500, 255, true) 2240 .WithValueField(0, 8, out IBI_QUEUE_SIZE, mode: FieldMode.Read, name: "IBI_QUEUE_SIZE"); 2241 } 2242 } 2243 2244 public struct SocMgmtControlType 2245 { 2246 /// <summary> Field "PLACEHOLDER" at 0x0, width: 32 bits </summary> 2247 public IValueRegisterField PLACEHOLDER; 2248 SocMgmtControlTypeAntmicro.Renode.Peripherals.I3C.Caliptra_I3C.SocMgmtControlType2249 public SocMgmtControlType(IProvidesRegisterCollection<DoubleWordRegisterCollection> parent) 2250 { 2251 parent.RegistersCollection.DefineRegister(516, 0, true) 2252 .WithValueField(0, 32, out PLACEHOLDER, name: "PLACEHOLDER"); 2253 } 2254 } 2255 2256 public struct SocMgmtStatusType 2257 { 2258 /// <summary> Field "PLACEHOLDER" at 0x0, width: 32 bits </summary> 2259 public IValueRegisterField PLACEHOLDER; 2260 SocMgmtStatusTypeAntmicro.Renode.Peripherals.I3C.Caliptra_I3C.SocMgmtStatusType2261 public SocMgmtStatusType(IProvidesRegisterCollection<DoubleWordRegisterCollection> parent) 2262 { 2263 parent.RegistersCollection.DefineRegister(520, 0, true) 2264 .WithValueField(0, 32, out PLACEHOLDER, name: "PLACEHOLDER"); 2265 } 2266 } 2267 2268 public struct SocMgmtRsvd0Type 2269 { 2270 /// <summary> Field "PLACEHOLDER" at 0x0, width: 32 bits </summary> 2271 public IValueRegisterField PLACEHOLDER; 2272 SocMgmtRsvd0TypeAntmicro.Renode.Peripherals.I3C.Caliptra_I3C.SocMgmtRsvd0Type2273 public SocMgmtRsvd0Type(IProvidesRegisterCollection<DoubleWordRegisterCollection> parent) 2274 { 2275 parent.RegistersCollection.DefineRegister(524, 0, true) 2276 .WithValueField(0, 32, out PLACEHOLDER, name: "PLACEHOLDER"); 2277 } 2278 } 2279 2280 public struct SocMgmtRsvd1Type 2281 { 2282 /// <summary> Field "PLACEHOLDER" at 0x0, width: 32 bits </summary> 2283 public IValueRegisterField PLACEHOLDER; 2284 SocMgmtRsvd1TypeAntmicro.Renode.Peripherals.I3C.Caliptra_I3C.SocMgmtRsvd1Type2285 public SocMgmtRsvd1Type(IProvidesRegisterCollection<DoubleWordRegisterCollection> parent) 2286 { 2287 parent.RegistersCollection.DefineRegister(528, 0, true) 2288 .WithValueField(0, 32, out PLACEHOLDER, name: "PLACEHOLDER"); 2289 } 2290 } 2291 2292 public struct SocMgmtRsvd2Type 2293 { 2294 /// <summary> Field "PLACEHOLDER" at 0x0, width: 32 bits </summary> 2295 public IValueRegisterField PLACEHOLDER; 2296 SocMgmtRsvd2TypeAntmicro.Renode.Peripherals.I3C.Caliptra_I3C.SocMgmtRsvd2Type2297 public SocMgmtRsvd2Type(IProvidesRegisterCollection<DoubleWordRegisterCollection> parent) 2298 { 2299 parent.RegistersCollection.DefineRegister(532, 0, true) 2300 .WithValueField(0, 32, out PLACEHOLDER, name: "PLACEHOLDER"); 2301 } 2302 } 2303 2304 public struct SocMgmtRsvd3Type 2305 { 2306 /// <summary> Field "PLACEHOLDER" at 0x0, width: 32 bits </summary> 2307 public IValueRegisterField PLACEHOLDER; 2308 SocMgmtRsvd3TypeAntmicro.Renode.Peripherals.I3C.Caliptra_I3C.SocMgmtRsvd3Type2309 public SocMgmtRsvd3Type(IProvidesRegisterCollection<DoubleWordRegisterCollection> parent) 2310 { 2311 parent.RegistersCollection.DefineRegister(536, 0, true) 2312 .WithValueField(0, 32, out PLACEHOLDER, name: "PLACEHOLDER"); 2313 } 2314 } 2315 2316 public struct SocPadConfType 2317 { 2318 /// <summary> Field "INPUT_ENABLE" at 0x0, width: 1 bits </summary> 2319 public IFlagRegisterField INPUT_ENABLE; 2320 /// <summary> Field "SCHMITT_EN" at 0x1, width: 1 bits </summary> 2321 public IFlagRegisterField SCHMITT_EN; 2322 /// <summary> Field "KEEPER_EN" at 0x2, width: 1 bits </summary> 2323 public IFlagRegisterField KEEPER_EN; 2324 /// <summary> Field "PULL_DIR" at 0x3, width: 1 bits </summary> 2325 public IFlagRegisterField PULL_DIR; 2326 /// <summary> Field "PULL_EN" at 0x4, width: 1 bits </summary> 2327 public IFlagRegisterField PULL_EN; 2328 /// <summary> Field "IO_INVERSION" at 0x5, width: 1 bits </summary> 2329 public IFlagRegisterField IO_INVERSION; 2330 /// <summary> Field "OD_EN" at 0x6, width: 1 bits </summary> 2331 public IFlagRegisterField OD_EN; 2332 /// <summary> Field "VIRTUAL_OD_EN" at 0x7, width: 1 bits </summary> 2333 public IFlagRegisterField VIRTUAL_OD_EN; 2334 /// <summary> Field "PAD_TYPE" at 0x18, width: 8 bits </summary> 2335 public IValueRegisterField PAD_TYPE; 2336 SocPadConfTypeAntmicro.Renode.Peripherals.I3C.Caliptra_I3C.SocPadConfType2337 public SocPadConfType(IProvidesRegisterCollection<DoubleWordRegisterCollection> parent) 2338 { 2339 parent.RegistersCollection.DefineRegister(540, 4278190081, true) 2340 .WithFlag(0, out INPUT_ENABLE, name: "INPUT_ENABLE") 2341 .WithFlag(1, out SCHMITT_EN, name: "SCHMITT_EN") 2342 .WithFlag(2, out KEEPER_EN, name: "KEEPER_EN") 2343 .WithFlag(3, out PULL_DIR, name: "PULL_DIR") 2344 .WithFlag(4, out PULL_EN, name: "PULL_EN") 2345 .WithFlag(5, out IO_INVERSION, name: "IO_INVERSION") 2346 .WithFlag(6, out OD_EN, name: "OD_EN") 2347 .WithFlag(7, out VIRTUAL_OD_EN, name: "VIRTUAL_OD_EN") 2348 .WithValueField(24, 8, out PAD_TYPE, name: "PAD_TYPE"); 2349 } 2350 } 2351 2352 public struct SocPadAttrType 2353 { 2354 /// <summary> Field "DRIVE_SLEW_RATE" at 0x8, width: 8 bits </summary> 2355 public IValueRegisterField DRIVE_SLEW_RATE; 2356 /// <summary> Field "DRIVE_STRENGTH" at 0x18, width: 8 bits </summary> 2357 public IValueRegisterField DRIVE_STRENGTH; 2358 SocPadAttrTypeAntmicro.Renode.Peripherals.I3C.Caliptra_I3C.SocPadAttrType2359 public SocPadAttrType(IProvidesRegisterCollection<DoubleWordRegisterCollection> parent) 2360 { 2361 parent.RegistersCollection.DefineRegister(544, 4278255360, true) 2362 .WithValueField(8, 8, out DRIVE_SLEW_RATE, name: "DRIVE_SLEW_RATE") 2363 .WithValueField(24, 8, out DRIVE_STRENGTH, name: "DRIVE_STRENGTH"); 2364 } 2365 } 2366 2367 public struct SocMgmtFeature2Type 2368 { 2369 /// <summary> Field "PLACEHOLDER" at 0x0, width: 32 bits </summary> 2370 public IValueRegisterField PLACEHOLDER; 2371 SocMgmtFeature2TypeAntmicro.Renode.Peripherals.I3C.Caliptra_I3C.SocMgmtFeature2Type2372 public SocMgmtFeature2Type(IProvidesRegisterCollection<DoubleWordRegisterCollection> parent) 2373 { 2374 parent.RegistersCollection.DefineRegister(548, 0, true) 2375 .WithValueField(0, 32, out PLACEHOLDER, name: "PLACEHOLDER"); 2376 } 2377 } 2378 2379 public struct SocMgmtFeature3Type 2380 { 2381 /// <summary> Field "PLACEHOLDER" at 0x0, width: 32 bits </summary> 2382 public IValueRegisterField PLACEHOLDER; 2383 SocMgmtFeature3TypeAntmicro.Renode.Peripherals.I3C.Caliptra_I3C.SocMgmtFeature3Type2384 public SocMgmtFeature3Type(IProvidesRegisterCollection<DoubleWordRegisterCollection> parent) 2385 { 2386 parent.RegistersCollection.DefineRegister(552, 0, true) 2387 .WithValueField(0, 32, out PLACEHOLDER, name: "PLACEHOLDER"); 2388 } 2389 } 2390 2391 public struct TRRegType 2392 { 2393 /// <summary> Field "T_R" at 0x0, width: 20 bits </summary> 2394 public IValueRegisterField T_R; 2395 TRRegTypeAntmicro.Renode.Peripherals.I3C.Caliptra_I3C.TRRegType2396 public TRRegType(IProvidesRegisterCollection<DoubleWordRegisterCollection> parent) 2397 { 2398 parent.RegistersCollection.DefineRegister(556, 0, true) 2399 .WithValueField(0, 20, out T_R, name: "T_R"); 2400 } 2401 } 2402 2403 public struct TFRegType 2404 { 2405 /// <summary> Field "T_F" at 0x0, width: 20 bits </summary> 2406 public IValueRegisterField T_F; 2407 TFRegTypeAntmicro.Renode.Peripherals.I3C.Caliptra_I3C.TFRegType2408 public TFRegType(IProvidesRegisterCollection<DoubleWordRegisterCollection> parent) 2409 { 2410 parent.RegistersCollection.DefineRegister(560, 0, true) 2411 .WithValueField(0, 20, out T_F, name: "T_F"); 2412 } 2413 } 2414 2415 public struct TSuDatRegType 2416 { 2417 /// <summary> Field "T_SU_DAT" at 0x0, width: 20 bits </summary> 2418 public IValueRegisterField T_SU_DAT; 2419 TSuDatRegTypeAntmicro.Renode.Peripherals.I3C.Caliptra_I3C.TSuDatRegType2420 public TSuDatRegType(IProvidesRegisterCollection<DoubleWordRegisterCollection> parent) 2421 { 2422 parent.RegistersCollection.DefineRegister(564, 0, true) 2423 .WithValueField(0, 20, out T_SU_DAT, name: "T_SU_DAT"); 2424 } 2425 } 2426 2427 public struct THdDatRegType 2428 { 2429 /// <summary> Field "T_HD_DAT" at 0x0, width: 20 bits </summary> 2430 public IValueRegisterField T_HD_DAT; 2431 THdDatRegTypeAntmicro.Renode.Peripherals.I3C.Caliptra_I3C.THdDatRegType2432 public THdDatRegType(IProvidesRegisterCollection<DoubleWordRegisterCollection> parent) 2433 { 2434 parent.RegistersCollection.DefineRegister(568, 0, true) 2435 .WithValueField(0, 20, out T_HD_DAT, name: "T_HD_DAT"); 2436 } 2437 } 2438 2439 public struct THighRegType 2440 { 2441 /// <summary> Field "T_HIGH" at 0x0, width: 20 bits </summary> 2442 public IValueRegisterField T_HIGH; 2443 THighRegTypeAntmicro.Renode.Peripherals.I3C.Caliptra_I3C.THighRegType2444 public THighRegType(IProvidesRegisterCollection<DoubleWordRegisterCollection> parent) 2445 { 2446 parent.RegistersCollection.DefineRegister(572, 0, true) 2447 .WithValueField(0, 20, out T_HIGH, name: "T_HIGH"); 2448 } 2449 } 2450 2451 public struct TLowRegType 2452 { 2453 /// <summary> Field "T_LOW" at 0x0, width: 20 bits </summary> 2454 public IValueRegisterField T_LOW; 2455 TLowRegTypeAntmicro.Renode.Peripherals.I3C.Caliptra_I3C.TLowRegType2456 public TLowRegType(IProvidesRegisterCollection<DoubleWordRegisterCollection> parent) 2457 { 2458 parent.RegistersCollection.DefineRegister(576, 0, true) 2459 .WithValueField(0, 20, out T_LOW, name: "T_LOW"); 2460 } 2461 } 2462 2463 public struct THdStaRegType 2464 { 2465 /// <summary> Field "T_HD_STA" at 0x0, width: 20 bits </summary> 2466 public IValueRegisterField T_HD_STA; 2467 THdStaRegTypeAntmicro.Renode.Peripherals.I3C.Caliptra_I3C.THdStaRegType2468 public THdStaRegType(IProvidesRegisterCollection<DoubleWordRegisterCollection> parent) 2469 { 2470 parent.RegistersCollection.DefineRegister(580, 0, true) 2471 .WithValueField(0, 20, out T_HD_STA, name: "T_HD_STA"); 2472 } 2473 } 2474 2475 public struct TSuStaRegType 2476 { 2477 /// <summary> Field "T_SU_STA" at 0x0, width: 20 bits </summary> 2478 public IValueRegisterField T_SU_STA; 2479 TSuStaRegTypeAntmicro.Renode.Peripherals.I3C.Caliptra_I3C.TSuStaRegType2480 public TSuStaRegType(IProvidesRegisterCollection<DoubleWordRegisterCollection> parent) 2481 { 2482 parent.RegistersCollection.DefineRegister(584, 0, true) 2483 .WithValueField(0, 20, out T_SU_STA, name: "T_SU_STA"); 2484 } 2485 } 2486 2487 public struct TSuStoRegType 2488 { 2489 /// <summary> Field "T_SU_STO" at 0x0, width: 20 bits </summary> 2490 public IValueRegisterField T_SU_STO; 2491 TSuStoRegTypeAntmicro.Renode.Peripherals.I3C.Caliptra_I3C.TSuStoRegType2492 public TSuStoRegType(IProvidesRegisterCollection<DoubleWordRegisterCollection> parent) 2493 { 2494 parent.RegistersCollection.DefineRegister(588, 0, true) 2495 .WithValueField(0, 20, out T_SU_STO, name: "T_SU_STO"); 2496 } 2497 } 2498 2499 public struct TFreeRegType 2500 { 2501 /// <summary> Field "T_FREE" at 0x0, width: 32 bits </summary> 2502 public IValueRegisterField T_FREE; 2503 TFreeRegTypeAntmicro.Renode.Peripherals.I3C.Caliptra_I3C.TFreeRegType2504 public TFreeRegType(IProvidesRegisterCollection<DoubleWordRegisterCollection> parent) 2505 { 2506 parent.RegistersCollection.DefineRegister(592, 4294967295, true) 2507 .WithValueField(0, 32, out T_FREE, name: "T_FREE"); 2508 } 2509 } 2510 2511 public struct TAvalRegType 2512 { 2513 /// <summary> Field "T_AVAL" at 0x0, width: 32 bits </summary> 2514 public IValueRegisterField T_AVAL; 2515 TAvalRegTypeAntmicro.Renode.Peripherals.I3C.Caliptra_I3C.TAvalRegType2516 public TAvalRegType(IProvidesRegisterCollection<DoubleWordRegisterCollection> parent) 2517 { 2518 parent.RegistersCollection.DefineRegister(596, 4294967295, true) 2519 .WithValueField(0, 32, out T_AVAL, name: "T_AVAL"); 2520 } 2521 } 2522 2523 public struct TIdleRegType 2524 { 2525 /// <summary> Field "T_IDLE" at 0x0, width: 32 bits </summary> 2526 public IValueRegisterField T_IDLE; 2527 TIdleRegTypeAntmicro.Renode.Peripherals.I3C.Caliptra_I3C.TIdleRegType2528 public TIdleRegType(IProvidesRegisterCollection<DoubleWordRegisterCollection> parent) 2529 { 2530 parent.RegistersCollection.DefineRegister(600, 4294967295, true) 2531 .WithValueField(0, 32, out T_IDLE, name: "T_IDLE"); 2532 } 2533 } 2534 2535 public struct ControllerConfigType 2536 { 2537 /// <summary> Field "OPERATION_MODE" at 0x4, width: 2 bits </summary> 2538 public IValueRegisterField OPERATION_MODE; 2539 ControllerConfigTypeAntmicro.Renode.Peripherals.I3C.Caliptra_I3C.ControllerConfigType2540 public ControllerConfigType(IProvidesRegisterCollection<DoubleWordRegisterCollection> parent) 2541 { 2542 parent.RegistersCollection.DefineRegister(612, 48, true) 2543 .WithValueField(4, 2, out OPERATION_MODE, mode: FieldMode.Read, name: "OPERATION_MODE"); 2544 } 2545 } 2546 2547 public struct TerminationExtcapHeaderType 2548 { 2549 /// <summary> Field "CAP_ID" at 0x0, width: 8 bits </summary> 2550 public IValueRegisterField CAP_ID; 2551 /// <summary> Field "CAP_LENGTH" at 0x8, width: 16 bits </summary> 2552 public IValueRegisterField CAP_LENGTH; 2553 TerminationExtcapHeaderTypeAntmicro.Renode.Peripherals.I3C.Caliptra_I3C.TerminationExtcapHeaderType2554 public TerminationExtcapHeaderType(IProvidesRegisterCollection<DoubleWordRegisterCollection> parent) 2555 { 2556 parent.RegistersCollection.DefineRegister(616, 16776960, true) 2557 .WithValueField(0, 8, out CAP_ID, mode: FieldMode.Read, name: "CAP_ID") 2558 .WithValueField(8, 16, out CAP_LENGTH, mode: FieldMode.Read, name: "CAP_LENGTH"); 2559 } 2560 } 2561 2562 protected class Dat_DatMemoryContainer 2563 { 2564 private byte[] memory; 2565 2566 public long Size { 2567 get 2568 { 2569 return 1024L; 2570 } 2571 } 2572 public Dat_DatMemoryWrapper this[long index] { 2573 get 2574 { 2575 if(index < 0 || index >= 128) 2576 { 2577 throw new System.IndexOutOfRangeException(); 2578 } 2579 return new Dat_DatMemoryWrapper(memory, index * 8); 2580 } 2581 } 2582 Dat_DatMemoryContainer()2583 public Dat_DatMemoryContainer() 2584 { 2585 memory = new byte[Size]; 2586 } 2587 ReadDoubleWord(long offset)2588 public uint ReadDoubleWord(long offset) 2589 { 2590 return (uint)memory[offset] + ((uint)memory[offset + 1] << 8) + ((uint)memory[offset + 2] << 16) + ((uint)memory[offset + 3] << 24); 2591 } 2592 WriteDoubleWord(long offset, uint value)2593 public void WriteDoubleWord(long offset, uint value) 2594 { 2595 memory[offset] = (byte)value; 2596 memory[offset + 1] = (byte)(value >> 8); 2597 memory[offset + 2] = (byte)(value >> 16); 2598 memory[offset + 3] = (byte)(value >> 24); 2599 } 2600 2601 public class Dat_DatMemoryWrapper 2602 { 2603 private long spanBegin; 2604 private byte[] memory; 2605 2606 /// <summary> Offset: 0x0, Width: 7 bits </summary> 2607 public byte STATIC_ADDRESS { 2608 get 2609 { 2610 byte temp = 0; 2611 temp = (byte)(temp | (byte)(memory[spanBegin + 0] & 0x7f)); 2612 return temp; 2613 } 2614 set 2615 { 2616 memory[spanBegin + 0] = (byte)(memory[spanBegin + 0] & 0x80U | value & 0x7fU); 2617 } 2618 } 2619 /// <summary> Offset: 0xc, Width: 1 bits </summary> 2620 public bool IBI_PAYLOAD { 2621 get 2622 { 2623 bool temp; 2624 temp = (memory[spanBegin + 1] & 0x10) != 0; 2625 return temp; 2626 } 2627 set 2628 { 2629 memory[spanBegin + 1] = (byte)(memory[spanBegin + 1] & 0xefU | (value ? 1U : 0U) << 4); 2630 } 2631 } 2632 /// <summary> Offset: 0xd, Width: 1 bits </summary> 2633 public bool IBI_REJECT { 2634 get 2635 { 2636 bool temp; 2637 temp = (memory[spanBegin + 1] & 0x20) != 0; 2638 return temp; 2639 } 2640 set 2641 { 2642 memory[spanBegin + 1] = (byte)(memory[spanBegin + 1] & 0xdfU | (value ? 1U : 0U) << 5); 2643 } 2644 } 2645 /// <summary> Offset: 0xe, Width: 1 bits </summary> 2646 public bool CRR_REJECT { 2647 get 2648 { 2649 bool temp; 2650 temp = (memory[spanBegin + 1] & 0x40) != 0; 2651 return temp; 2652 } 2653 set 2654 { 2655 memory[spanBegin + 1] = (byte)(memory[spanBegin + 1] & 0xbfU | (value ? 1U : 0U) << 6); 2656 } 2657 } 2658 /// <summary> Offset: 0xf, Width: 1 bits </summary> 2659 public bool TS { 2660 get 2661 { 2662 bool temp; 2663 temp = (memory[spanBegin + 1] & 0x80) != 0; 2664 return temp; 2665 } 2666 set 2667 { 2668 memory[spanBegin + 1] = (byte)(memory[spanBegin + 1] & 0x7fU | (value ? 1U : 0U) << 7); 2669 } 2670 } 2671 /// <summary> Offset: 0x10, Width: 8 bits </summary> 2672 public byte DYNAMIC_ADDRESS { 2673 get 2674 { 2675 byte temp = 0; 2676 temp = (byte)(temp | (byte)memory[spanBegin + 2]); 2677 return temp; 2678 } 2679 set 2680 { 2681 memory[spanBegin + 2] = (byte)value; 2682 } 2683 } 2684 /// <summary> Offset: 0x1a, Width: 3 bits </summary> 2685 public byte RING_ID { 2686 get 2687 { 2688 byte temp = 0; 2689 temp = (byte)(temp | (byte)(memory[spanBegin + 3] & 0x1c) >> 2); 2690 return temp; 2691 } 2692 set 2693 { 2694 memory[spanBegin + 3] = (byte)(memory[spanBegin + 3] & 0xe3U | (value & 0x7U) << 2); 2695 } 2696 } 2697 /// <summary> Offset: 0x1d, Width: 2 bits </summary> 2698 public byte DEV_NACK_RETRY_CNT { 2699 get 2700 { 2701 byte temp = 0; 2702 temp = (byte)(temp | (byte)(memory[spanBegin + 3] & 0x60) >> 5); 2703 return temp; 2704 } 2705 set 2706 { 2707 memory[spanBegin + 3] = (byte)(memory[spanBegin + 3] & 0x9fU | (value & 0x3U) << 5); 2708 } 2709 } 2710 /// <summary> Offset: 0x1f, Width: 1 bits </summary> 2711 public bool DEVICE { 2712 get 2713 { 2714 bool temp; 2715 temp = (memory[spanBegin + 3] & 0x80) != 0; 2716 return temp; 2717 } 2718 set 2719 { 2720 memory[spanBegin + 3] = (byte)(memory[spanBegin + 3] & 0x7fU | (value ? 1U : 0U) << 7); 2721 } 2722 } 2723 /// <summary> Offset: 0x20, Width: 8 bits </summary> 2724 public byte AUTOCMD_MASK { 2725 get 2726 { 2727 byte temp = 0; 2728 temp = (byte)(temp | (byte)memory[spanBegin + 4]); 2729 return temp; 2730 } 2731 set 2732 { 2733 memory[spanBegin + 4] = (byte)value; 2734 } 2735 } 2736 /// <summary> Offset: 0x28, Width: 8 bits </summary> 2737 public byte AUTOCMD_VALUE { 2738 get 2739 { 2740 byte temp = 0; 2741 temp = (byte)(temp | (byte)memory[spanBegin + 5]); 2742 return temp; 2743 } 2744 set 2745 { 2746 memory[spanBegin + 5] = (byte)value; 2747 } 2748 } 2749 /// <summary> Offset: 0x30, Width: 3 bits </summary> 2750 public byte AUTOCMD_MODE { 2751 get 2752 { 2753 byte temp = 0; 2754 temp = (byte)(temp | (byte)(memory[spanBegin + 6] & 0x7)); 2755 return temp; 2756 } 2757 set 2758 { 2759 memory[spanBegin + 6] = (byte)(memory[spanBegin + 6] & 0xf8U | value & 0x7U); 2760 } 2761 } 2762 /// <summary> Offset: 0x33, Width: 8 bits </summary> 2763 public byte AUTOCMD_HDR_CODE { 2764 get 2765 { 2766 byte temp = 0; 2767 temp = (byte)(temp | (byte)(memory[spanBegin + 6] & 0xf8) >> 3); 2768 return temp; 2769 } 2770 set 2771 { 2772 memory[spanBegin + 6] = (byte)(memory[spanBegin + 6] & 0x7U | value << 3); 2773 } 2774 } 2775 Dat_DatMemoryWrapper(byte[] memory, long spanBegin)2776 public Dat_DatMemoryWrapper(byte[] memory, long spanBegin) 2777 { 2778 this.memory = memory; 2779 this.spanBegin = spanBegin; 2780 } 2781 } 2782 } 2783 2784 protected class Dct_DctMemoryContainer 2785 { 2786 private byte[] memory; 2787 2788 public long Size { 2789 get 2790 { 2791 return 2048L; 2792 } 2793 } 2794 public Dct_DctMemoryWrapper this[long index] { 2795 get 2796 { 2797 if(index < 0 || index >= 128) 2798 { 2799 throw new System.IndexOutOfRangeException(); 2800 } 2801 return new Dct_DctMemoryWrapper(memory, index * 16); 2802 } 2803 } 2804 Dct_DctMemoryContainer()2805 public Dct_DctMemoryContainer() 2806 { 2807 memory = new byte[Size]; 2808 } 2809 ReadDoubleWord(long offset)2810 public uint ReadDoubleWord(long offset) 2811 { 2812 return (uint)memory[offset] + ((uint)memory[offset + 1] << 8) + ((uint)memory[offset + 2] << 16) + ((uint)memory[offset + 3] << 24); 2813 } 2814 WriteDoubleWord(long offset, uint value)2815 public void WriteDoubleWord(long offset, uint value) 2816 { 2817 memory[offset] = (byte)value; 2818 memory[offset + 1] = (byte)(value >> 8); 2819 memory[offset + 2] = (byte)(value >> 16); 2820 memory[offset + 3] = (byte)(value >> 24); 2821 } 2822 2823 public class Dct_DctMemoryWrapper 2824 { 2825 private long spanBegin; 2826 private byte[] memory; 2827 2828 /// <summary> Offset: 0x0, Width: 32 bits </summary> 2829 public uint PID_HI { 2830 get 2831 { 2832 uint temp = 0; 2833 temp = (uint)(temp | (uint)memory[spanBegin + 0]); 2834 temp = (uint)(temp | (uint)memory[spanBegin + 1] << 8); 2835 temp = (uint)(temp | (uint)memory[spanBegin + 2] << 16); 2836 temp = (uint)(temp | (uint)memory[spanBegin + 3] << 24); 2837 return temp; 2838 } 2839 set 2840 { 2841 memory[spanBegin + 0] = (byte)value; 2842 memory[spanBegin + 1] = (byte)(value >> 8); 2843 memory[spanBegin + 2] = (byte)(value >> 16); 2844 memory[spanBegin + 3] = (byte)(value >> 24); 2845 } 2846 } 2847 /// <summary> Offset: 0x20, Width: 16 bits </summary> 2848 public ushort PID_LO { 2849 get 2850 { 2851 ushort temp = 0; 2852 temp = (ushort)(temp | (ushort)memory[spanBegin + 4]); 2853 temp = (ushort)(temp | (ushort)memory[spanBegin + 5] << 8); 2854 return temp; 2855 } 2856 set 2857 { 2858 memory[spanBegin + 4] = (byte)value; 2859 memory[spanBegin + 5] = (byte)(value >> 8); 2860 } 2861 } 2862 /// <summary> Offset: 0x40, Width: 8 bits </summary> 2863 public byte DCR { 2864 get 2865 { 2866 byte temp = 0; 2867 temp = (byte)(temp | (byte)memory[spanBegin + 8]); 2868 return temp; 2869 } 2870 set 2871 { 2872 memory[spanBegin + 8] = (byte)value; 2873 } 2874 } 2875 /// <summary> Offset: 0x48, Width: 8 bits </summary> 2876 public byte BCR { 2877 get 2878 { 2879 byte temp = 0; 2880 temp = (byte)(temp | (byte)memory[spanBegin + 9]); 2881 return temp; 2882 } 2883 set 2884 { 2885 memory[spanBegin + 9] = (byte)value; 2886 } 2887 } 2888 /// <summary> Offset: 0x60, Width: 8 bits </summary> 2889 public byte DYNAMIC_ADDRESS { 2890 get 2891 { 2892 byte temp = 0; 2893 temp = (byte)(temp | (byte)memory[spanBegin + 12]); 2894 return temp; 2895 } 2896 set 2897 { 2898 memory[spanBegin + 12] = (byte)value; 2899 } 2900 } 2901 Dct_DctMemoryWrapper(byte[] memory, long spanBegin)2902 public Dct_DctMemoryWrapper(byte[] memory, long spanBegin) 2903 { 2904 this.memory = memory; 2905 this.spanBegin = spanBegin; 2906 } 2907 } 2908 } 2909 } 2910 } 2911
