1 // 2 // Copyright (c) 2010-2024 Antmicro 3 // 4 // This file is licensed under the MIT License. 5 // Full license text is available in 'licenses/MIT.txt'. 6 // 7 using System; 8 using System.Collections.Generic; 9 using Antmicro.Renode.Core; 10 using Antmicro.Renode.Core.Structure.Registers; 11 using Antmicro.Renode.Logging; 12 using Antmicro.Renode.Peripherals; 13 using Antmicro.Renode.Peripherals.Bus; 14 15 namespace Antmicro.Renode.Peripherals.Miscellaneous 16 { 17 public class S32K3XX_MiscellaneousSystemControlModule : BasicDoubleWordPeripheral, IWordPeripheral, IKnownSize, 18 IProvidesRegisterCollection<WordRegisterCollection> 19 20 { S32K3XX_MiscellaneousSystemControlModule(IMachine machine)21 public S32K3XX_MiscellaneousSystemControlModule(IMachine machine) : base(machine) 22 { 23 wordRegisterCollection = new WordRegisterCollection(this); 24 DefineRegisters(); 25 } 26 ReadWord(long offset)27 public ushort ReadWord(long offset) 28 { 29 return wordRegisterCollection.Read(offset); 30 } 31 WriteWord(long offset, ushort value)32 public void WriteWord(long offset, ushort value) 33 { 34 wordRegisterCollection.Write(offset, value); 35 } 36 Reset()37 public override void Reset() 38 { 39 base.Reset(); 40 wordRegisterCollection.Reset(); 41 } 42 43 public long Size => 0x4000; 44 45 WordRegisterCollection IProvidesRegisterCollection<WordRegisterCollection>.RegistersCollection => wordRegisterCollection; 46 DefineRegisters()47 private void DefineRegisters() 48 { 49 IProvidesRegisterCollection<DoubleWordRegisterCollection> asDoubleWordCollection = this; 50 51 var processorConfigurationSize = (uint)Registers.Processor0Type - (uint)Registers.ProcessorXType; 52 Registers.ProcessorXType.DefineMany(asDoubleWordCollection, ProcessorConfigurationCount, stepInBytes: processorConfigurationSize, setup: (reg, index) => 53 { 54 var processorSuffix = index == 0 ? "x" : $"{index - 1}"; 55 reg.WithTag($"PersonalityOfCP{processorSuffix}", 0, 32); 56 } 57 ); 58 Registers.ProcessorXNumber.DefineMany(asDoubleWordCollection, ProcessorConfigurationCount, stepInBytes: processorConfigurationSize, setup: (reg, index) => 59 { 60 var numberSize = index == 0 ? 3 : 2; 61 reg.WithReservedBits(numberSize, 32 - numberSize) 62 .WithTag("ProcessorNumber", 0, numberSize); 63 } 64 ); 65 Registers.ProcessorXRevision.DefineMany(asDoubleWordCollection, ProcessorConfigurationCount, stepInBytes: processorConfigurationSize, setup: (reg, index) => reg 66 .WithReservedBits(8, 24) 67 .WithTag("ProcessorRevision", 0, 8) 68 ); 69 70 Registers.ProcessorXConfiguration0.DefineMany(asDoubleWordCollection, ProcessorConfigurationCount, stepInBytes: processorConfigurationSize, setup: (reg, index) => reg 71 .WithTag("L1InstructionCacheSize", 24, 8) 72 .WithTag("L1InstructionCacheWays", 16, 8) 73 .WithTag("L1DataCacheSize", 8, 8) 74 .WithTag("L1DataCacheWays", 0, 8) 75 ); 76 Registers.ProcessorXConfiguration1.DefineMany(asDoubleWordCollection, ProcessorConfigurationCount, stepInBytes: processorConfigurationSize, setup: (reg, index) => reg 77 .WithTag("L2CacheSize", 24, 8) 78 .WithTag("L2CacheWays", 16, 8) 79 .WithReservedBits(0, 16) 80 ); 81 Registers.ProcessorXConfiguration2.DefineMany(asDoubleWordCollection, ProcessorConfigurationCount, stepInBytes: processorConfigurationSize, setup: (reg, index) => reg 82 .WithTag("TightlyCoupledDataMemorySize", 24, 8) 83 .WithTag("InstructionTightlyCoupledMemorySize", 16, 8) 84 .WithReservedBits(0, 16) 85 ); 86 Registers.ProcessorXConfiguration3.DefineMany(asDoubleWordCollection, ProcessorConfigurationCount, stepInBytes: processorConfigurationSize, setup: (reg, index) => reg 87 .WithReservedBits(5, 27) 88 .WithTaggedFlag("Cryptography", 4) 89 .WithTaggedFlag("CoreMemoryProtectionUnit", 3) 90 .WithTaggedFlag("MemoryManagementUnit", 2) 91 .WithTaggedFlag("NEONInstructionSupport", 1) 92 .WithTaggedFlag("FloatingPointUnit", 0) 93 ); 94 95 var interruptRegisterStep = (uint)Registers.InterruptRouterCP0InterruptStatus1 - (uint)Registers.InterruptRouterCP0InterruptStatus0; 96 Registers.InterruptRouterCP0InterruptStatus0.DefineMany(asDoubleWordCollection, InterruptRouterRegisterCount, stepInBytes: interruptRegisterStep, setup: (reg, index) => 97 { 98 var cpuIndex = index / 4; 99 reg.WithReservedBits(4, 28) 100 .WithTaggedFlag($"CP3ToCP{cpuIndex}", 3) 101 .WithTaggedFlag($"CP2ToCP{cpuIndex}", 2) 102 .WithTaggedFlag($"CP1ToCP{cpuIndex}", 1) 103 .WithTaggedFlag($"CP0ToCP{cpuIndex}", 0); 104 } 105 ); 106 Registers.InterruptRouterCP0InterruptGeneration0.DefineMany(asDoubleWordCollection, InterruptRouterRegisterCount, stepInBytes: interruptRegisterStep, setup: (reg, index) => reg 107 .WithReservedBits(1, 31) 108 .WithTaggedFlag($"InterruptEnable", 0) 109 ); 110 111 Registers.InterruptRouterConfiguration.Define(asDoubleWordCollection) 112 .WithTaggedFlag("Lock", 31) 113 .WithReservedBits(4, 27) 114 .WithTaggedFlag("CP3AsTrustedCore", 3) 115 .WithTaggedFlag("CP2AsTrustedCore", 2) 116 .WithTaggedFlag("CP1AsTrustedCore", 1) 117 .WithTaggedFlag("CP0AsTrustedCore", 0); 118 119 Registers.MemoryExecutionControl.Define(asDoubleWordCollection) 120 .WithTaggedFlag("HardLock", 31) 121 .WithTaggedFlag("SoftLock", 30) 122 .WithReservedBits(24, 6) 123 .WithTaggedFlag("TransactionControlForCortex-M7_3DTCM", 23) 124 .WithTaggedFlag("TransactionControlForCortex-M7_2DTCM", 22) 125 .WithTaggedFlag("TransactionControlForCortex-M7_1DTCM", 21) 126 .WithTaggedFlag("TransactionControlForCortex-M7_0DTCM", 20) 127 .WithTaggedFlag("DisableD0andD1TCMExecutionForCortex-M7_3", 19) 128 .WithTaggedFlag("DisableD0andD1TCMExecutionForCortex-M7_2", 18) 129 .WithTaggedFlag("D0andD1TCMExecutionForCortex-M7_1", 17) 130 .WithTaggedFlag("D0AndD1TCMExecutionForCortex-M7_0", 16) 131 .WithTaggedFlag("TransactionControlForCortex-M7_3ITCM", 15) 132 .WithTaggedFlag("TransactionControlForCortex-M7_2ITCM", 14) 133 .WithTaggedFlag("TransactionControlForCortex-M7_1ITCM", 13) 134 .WithTaggedFlag("TransactionControlForCortex-M7_0ITCM", 12) 135 .WithTaggedFlag("ITCMExecutionForCortex-M7_3", 11) 136 .WithTaggedFlag("ITCMExecutionForCortex-M7_2", 10) 137 .WithTaggedFlag("ITCMExecutionForCortex-M7_1", 9) 138 .WithTaggedFlag("ITCMExecutionForCortex-M7_0", 8) 139 .WithReservedBits(3, 5) 140 .WithTaggedFlag("TransactionControlForPRAM2", 2) 141 .WithTaggedFlag("TransactionControlForPRAM1", 1) 142 .WithTaggedFlag("TransactionControlForPRAM0", 0); 143 144 Registers.EnableInterconnectErrorDetection0.Define(asDoubleWordCollection) 145 .WithReservedBits(30, 2) 146 .WithTaggedFlag("AddressCheckForCortex-M7_1_TCM", 29) 147 .WithTaggedFlag("WriteDataCheckForCortex-M7_1_TCM", 28) 148 .WithTaggedFlag("AddressCheckForCortex-M7_0_TCM", 27) 149 .WithTaggedFlag("WriteDataCheckForCortex-M7_0_TCM", 26) 150 .WithTaggedFlag("AddressCheckForAIPS2", 25) 151 .WithTaggedFlag("WriteDataCheckForAIPS2", 24) 152 .WithTaggedFlag("AddressCheckForAIPS1", 23) 153 .WithTaggedFlag("WriteDataCheckForAIPS1", 22) 154 .WithTaggedFlag("AddressCheckForAIPS0", 21) 155 .WithTaggedFlag("WriteDataCheckForAIPS0", 20) 156 .WithTaggedFlag("AddressCheckForQuadSPI", 19) 157 .WithTaggedFlag("WriteDataCheckForQuadSPI", 18) 158 .WithReservedBits(16, 2) 159 .WithTaggedFlag("AddressCheckForPRAM1", 15) 160 .WithTaggedFlag("WriteDataCheckForPRAM1", 14) 161 .WithTaggedFlag("AddressCheckForPRAM0", 13) 162 .WithTaggedFlag("WriteDataCheckForPRAM0", 12) 163 .WithTaggedFlag("EnableAddressCheckForPF2", 11) 164 .WithTaggedFlag("AddressCheckForPF1", 10) 165 .WithTaggedFlag("AddressCheckForPF0", 9) 166 .WithReservedBits(8, 1) 167 .WithTaggedFlag("ReadDataCheckForCortex-M7_1_AHBP", 7) 168 .WithTaggedFlag("ReadDataCheckForCortex-M7_1_AHBM", 6) 169 .WithTaggedFlag("ReadDataCheckForENET", 5) 170 .WithTaggedFlag("ReadDataCheckForHSE_B", 4) 171 .WithReservedBits(3, 1) 172 .WithTaggedFlag("ReadDataCheckForeDMA", 2) 173 .WithTaggedFlag("ReadDataCheckForCortex-M7_0_AHBP", 1) 174 .WithTaggedFlag("ReadDataCheckForCortex-M7_0_AHBM", 0); 175 176 Registers.EnableInterconnectErrorDetection1.Define(asDoubleWordCollection) 177 .WithReservedBits(25, 7) 178 .WithTaggedFlag("TCMGasketAddressCheck", 24) 179 .WithTaggedFlag("SlaveCheckAcceleratorResultM1GasketAddressCheck", 23) 180 .WithTaggedFlag("SlaveCheckAcceleratorResultM1GasketWriteDataCheck", 22) 181 .WithTaggedFlag("SlaveCheckAcceleratorAddress", 21) 182 .WithTaggedFlag("MasterCheckAcceleratorFeed", 20) 183 .WithTaggedFlag("MasterCheckAcceleratorResult", 19) 184 .WithTaggedFlag("EnableReadDataCheckCortex-M7_3_AHBP", 18) 185 .WithTaggedFlag("EnableReadDataCheckCortex-M7_3_AHBM", 17) 186 .WithReservedBits(16, 1) 187 .WithTaggedFlag("EnableAddressCheckCortex-M7_2_TCM", 15) 188 .WithTaggedFlag("EnableWriteDataCheckCortex-M7_2_TCM", 14) 189 .WithTaggedFlag("EnableAddressCheckCortex-M7_3_TCM", 13) 190 .WithTaggedFlag("EnableWriteDataCheckCortex-M7_3_TCM", 12) 191 .WithTaggedFlag("EnableAddressCheckPRAM2", 11) 192 .WithTaggedFlag("EnableWriteDataCheckPRAM2", 10) 193 .WithReservedBits(8, 2) 194 .WithTaggedFlag("MasterCheckENET1", 7) 195 .WithTaggedFlag("EnableAddressCheckeDMAS1", 6) 196 .WithTaggedFlag("EnableAddressCheckeDMAS0", 5) 197 .WithTaggedFlag("EnableAddressCheckPFlash3", 4) 198 .WithTaggedFlag("EnableReadDataCheckCortex-M7_2_AHBP", 3) 199 .WithTaggedFlag("EnableReadDataCheckCortex-M7_2_AHBM", 2) 200 .WithReservedBits(0, 2); 201 202 IProvidesRegisterCollection<WordRegisterCollection> asWordCollection = this; 203 Registers.InterruptRouterSharedPeripheralRoutingControl0.DefineMany(asWordCollection, InterruptRouterSharedRegisterCount, (reg, index) => reg 204 .WithTaggedFlag("Lock", 15) 205 .WithReservedBits(4, 9) 206 .WithTaggedFlag("EnableCortex-M7_3InterruptSteering", 3) 207 .WithTaggedFlag("EnableCortex-M7_2InterruptSteering", 2) 208 .WithTaggedFlag("EnableCortex-M7_1InterruptSteering", 1) 209 .WithTaggedFlag("EnableCortex-M7_0InterruptSteering", 0) 210 ); 211 } 212 213 private WordRegisterCollection wordRegisterCollection; 214 215 private const uint ProcessorCount = 4; 216 private const uint ProcessorConfigurationCount = ProcessorCount + 1; 217 private const uint InterruptRouterRegisterCount = ProcessorCount * 4; 218 private const uint InterruptRouterSharedRegisterCount = 240; 219 220 public enum Registers 221 { 222 ProcessorXType = 0x0, // CPXTYPE 223 ProcessorXNumber = 0x4, // CPXNUM 224 ProcessorXRevision = 0x8, // CPXREV 225 ProcessorXConfiguration0 = 0xC, // CPXCFG0 226 ProcessorXConfiguration1 = 0x10, // CPXCFG1 227 ProcessorXConfiguration2 = 0x14, // CPXCFG2 228 ProcessorXConfiguration3 = 0x18, // CPXCFG3 229 Processor0Type = 0x20, // CP0TYPE 230 Processor0Number = 0x24, // CP0NUM 231 Processor0Count = 0x28, // CP0REV 232 Processor0Configuration0 = 0x2C, // CP0CFG0 233 Processor0Configuration1 = 0x30, // CP0CFG1 234 Processor0Configuration2 = 0x34, // CP0CFG2 235 Processor0Configuration3 = 0x38, // CP0CFG3 236 Processor1Type = 0x40, // CP1TYPE 237 Processor1Number = 0x44, // CP1NUM 238 Processor1Count = 0x48, // CP1REV 239 Processor1Configuration0 = 0x4C, // CP1CFG0 240 Processor1Configuration1 = 0x50, // CP1CFG1 241 Processor1Configuration2 = 0x54, // CP1CFG2 242 Processor1Configuration3 = 0x58, // CP1CFG3 243 Processor2Type = 0x60, // CP2TYPE 244 Processor2Number = 0x64, // CP2NUM 245 Processor2Count = 0x68, // CP2REV 246 Processor2Configuration0 = 0x6C, // CP2CFG0 247 Processor2Configuration1 = 0x70, // CP2CFG1 248 Processor2Configuration2 = 0x74, // CP2CFG2 249 Processor2Configuration3 = 0x78, // CP2CFG3 250 Processor3Type = 0x80, // CP3TYPE 251 Processor3Number = 0x84, // CP3NUM 252 Processor3Count = 0x88, // CP3REV 253 Processor3Configuration0 = 0x8C, // CP3CFG0 254 Processor3Configuration1 = 0x90, // CP3CFG1 255 Processor3Configuration2 = 0x94, // CP3CFG2 256 Processor3Configuration3 = 0x98, // CP3CFG3 257 InterruptRouterCP0InterruptStatus0 = 0x200, // IRCP0ISR0 258 InterruptRouterCP0InterruptGeneration0 = 0x204, // IRCP0IGR0 259 InterruptRouterCP0InterruptStatus1 = 0x208, // IRCP0ISR1 260 InterruptRouterCP0InterruptGeneration1 = 0x20C, // IRCP0IGR1 261 InterruptRouterCP0InterruptStatus2 = 0x210, // IRCP0ISR2 262 InterruptRouterCP0InterruptGeneration2 = 0x214, // IRCP0IGR2 263 InterruptRouterCP0InterruptStatus3 = 0x218, // IRCP0ISR3 264 InterruptRouterCP0InterruptGeneration3 = 0x21C, // IRCP0IGR3 265 InterruptRouterCP1InterruptStatus0 = 0x220, // IRCP1ISR0 266 InterruptRouterCP1InterruptGeneration0 = 0x224, // IRCP1IGR0 267 InterruptRouterCP1InterruptStatus1 = 0x228, // IRCP1ISR1 268 InterruptRouterCP1InterruptGeneration1 = 0x22C, // IRCP1IGR1 269 InterruptRouterCP1InterruptStatus2 = 0x230, // IRCP1ISR2 270 InterruptRouterCP1InterruptGeneration2 = 0x234, // IRCP1IGR2 271 InterruptRouterCP1InterruptStatus3 = 0x238, // IRCP1ISR3 272 InterruptRouterCP1InterruptGeneration3 = 0x23C, // IRCP1IGR3 273 InterruptRouterCP2InterruptStatus0 = 0x240, // IRCP2ISR0 274 InterruptRouterCP2InterruptGeneration0 = 0x244, // IRCP2IGR0 275 InterruptRouterCP2InterruptStatus1 = 0x248, // IRCP2ISR1 276 InterruptRouterCP2InterruptGeneration1 = 0x24C, // IRCP2IGR1 277 InterruptRouterCP2InterruptStatus2 = 0x250, // IRCP2ISR2 278 InterruptRouterCP2InterruptGeneration2 = 0x254, // IRCP2IGR2 279 InterruptRouterCP2InterruptStatus3 = 0x258, // IRCP2ISR3 280 InterruptRouterCP2InterruptGeneration3 = 0x25C, // IRCP2IGR3 281 InterruptRouterCP3InterruptStatus0 = 0x260, // IRCP3ISR0 282 InterruptRouterCP3InterruptGeneration0 = 0x264, // IRCP3IGR0 283 InterruptRouterCP3InterruptStatus1 = 0x268, // IRCP3ISR1 284 InterruptRouterCP3InterruptGeneration1 = 0x26C, // IRCP3IGR1 285 InterruptRouterCP3InterruptStatus2 = 0x270, // IRCP3ISR2 286 InterruptRouterCP3InterruptGeneration2 = 0x274, // IRCP3IGR2 287 InterruptRouterCP3InterruptStatus3 = 0x278, // IRCP3ISR3 288 InterruptRouterCP3InterruptGeneration3 = 0x27C, // IRCP3IGR3 289 InterruptRouterConfiguration = 0x400, // IRCPCFG 290 MemoryExecutionControl = 0x500, // XNCTRL 291 EnableInterconnectErrorDetection0 = 0x600, // ENEDC 292 EnableInterconnectErrorDetection1 = 0x604, // ENEDC1 293 InterruptRouterSharedPeripheralRoutingControl0 = 0x880, // IRSPRC0 294 InterruptRouterSharedPeripheralRoutingControl239 = 0xA5E // IRSPRC239 295 } 296 } 297 } 298
