Searched refs:MaskedInterruptStatus (Results 1 – 8 of 8) sorted by relevance
| /Renode-Infrastructure-v1.15.3-29f510e/src/Emulator/Peripherals/Peripherals/Timers/ |
| D | PL031.cs | 42 case Offset.MaskedInterruptStatus: in ReadDoubleWord()
121 MaskedInterruptStatus = 0x18, enumerator
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| D | MiV_CoreTimer.cs | 79 {(long)Registers.MaskedInterruptStatus, new DoubleWordRegister(this) in MiV_CoreTimer()
118 MaskedInterruptStatus = 0x18 enumerator
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| /Renode-Infrastructure-v1.15.3-29f510e/src/Emulator/Peripherals/Peripherals/UART/ |
| D | PL011.cs | 258 Registers.MaskedInterruptStatus.Define(this) in DefineRegisters()
259 …FieldMode.Read, name: "Masked interrupt status", valueProviderCallback: _ => MaskedInterruptStatus) in DefineRegisters()
310 IRQ.Set(MaskedInterruptStatus != 0); in UpdateInterrupts()
358 private uint MaskedInterruptStatus => RawInterruptStatus & InterruptMask; field in Antmicro.Renode.Peripherals.UART.PL011
416 MaskedInterruptStatus = 0x040, enumerator
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| D | ESP32_UART.cs | 155 bool flag = MaskedInterruptStatus != 0; in UpdateInterrupts()
164 private uint MaskedInterruptStatus => RawInterruptStatus & InterruptMask; field in Antmicro.Renode.Peripherals.UART.ESP32_UART
204 MaskedInterruptStatus = 0x08, enumerator
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| /Renode-Infrastructure-v1.15.3-29f510e/src/Emulator/Peripherals/Peripherals/SPI/ |
| D | CC2538_SSI.cs | 81 { (long)Registers.MaskedInterruptStatus, new DoubleWordRegister(this) in CC2538_SSI()
207 MaskedInterruptStatus = 0x1C, enumerator
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| /Renode-Infrastructure-v1.15.3-29f510e/src/Emulator/Peripherals/Peripherals/GPIOPort/ |
| D | CC2538_GPIO.cs | 159 {(long)Registers.MaskedInterruptStatus, new DoubleWordRegister(this) in PrepareRegisters()
255 MaskedInterruptStatus = 0x418, enumerator
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| /Renode-Infrastructure-v1.15.3-29f510e/src/Emulator/Peripherals/Peripherals/Miscellaneous/ |
| D | STM32H7_HardwareSemaphore.cs | 138 MaskedInterruptStatus = 0x10c, enumerator
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| /Renode-Infrastructure-v1.15.3-29f510e/src/Emulator/Peripherals/Peripherals/Miscellaneous/Crypto/ |
| D | STM32H7_CRYPTO.cs | 156 Registers.MaskedInterruptStatus.Define(this) in DefineRegisters()
589 MaskedInterruptStatus = 0x1C, enumerator
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