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Searched refs:MachineIrqMask (Results 1 – 1 of 1) sorted by relevance

/Renode-Infrastructure-v1.15.3-29f510e/src/Emulator/Cores/RiscV/
DVexRiscv.cs119 RegisterCSR((ulong)CSRs.MachineIrqMask, () => (ulong)machineInterrupts.Mask, value => in RegisterCustomCSRs()
187 MachineIrqMask = 0xBC0, enumerator