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Searched refs:InterruptEnable (Results 1 – 25 of 129) sorted by relevance

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/Renode-Infrastructure-v1.15.3-29f510e/src/Emulator/Peripherals/Peripherals/UART/
DAtmel91DebugUnit.cs37 if((InterruptEnable & 0x01) != 0) in WriteChar()
58 case Offset.InterruptEnable: in WriteDoubleWord()
59 InterruptEnable |= value; in WriteDoubleWord()
63 InterruptEnable &= ~(value); in WriteDoubleWord()
76 if (BitHelper.IsBitSet(InterruptEnable, 4)) in WriteDoubleWord()
100 return InterruptEnable; in ReadDoubleWord()
147 private uint InterruptEnable = 0x08; field in Antmicro.Renode.Peripherals.UART.Atmel91DebugUnit
157 InterruptEnable = 0x08, enumerator
DLEUART.cs38 case Register.InterruptEnable: in ReadDoubleWord()
67 case Register.InterruptEnable: in WriteDoubleWord()
140 … ((interruptEnable & (uint)InterruptEnable.RxDataAvailable) != 0 && waitingChars.Count > 0) || in UpdateInterrupts()
141 (interruptEnable & (uint)InterruptEnable.TxBufferLevelInterrupt) != 0 || in UpdateInterrupts()
142 (interruptEnable & (uint)InterruptEnable.TxCompleteInterrutpt) != 0 in UpdateInterrupts()
164 private enum InterruptEnable enum in Antmicro.Renode.Peripherals.UART.LEUART
194 InterruptEnable = 0x038, enumerator
DCadence_UART.cs224 {(long)Registers.InterruptEnable, new DoubleWordRegister(this) in BuildRegisterMap()
232 writeCallback: (_, val) => rxTimeoutError.InterruptEnable(val), in BuildRegisterMap()
238 writeCallback: (_, val) => rxFifoOverflow.InterruptEnable(val), in BuildRegisterMap()
243 writeCallback: (_, val) => txFifoEmpty.InterruptEnable(val), in BuildRegisterMap()
247 writeCallback: (_, val) => rxFifoFull.InterruptEnable(val), in BuildRegisterMap()
251 writeCallback: (_, val) => rxFifoEmpty.InterruptEnable(val), in BuildRegisterMap()
255 writeCallback: (_, val) => rxFifoTrigger.InterruptEnable(val), in BuildRegisterMap()
534 InterruptEnable = 0x08, enumerator
DEFM32_UART.cs47 case Registers.InterruptEnable: in WriteDoubleWord()
123 InterruptEnable = 0x04C, // USARTn_IEN enumerator
DEFR32xG22_USART.cs52 {(long)Registers.InterruptEnable, GenerateInterruptEnableRegister()}, in EFR32xG22_USART()
100 InterruptEnable = 0x4C, enumerator
DEFR32_USART.cs42 {(long)Registers.InterruptEnable, GenerateInterruptEnableRegister()}, in EFR32_USART()
117 InterruptEnable = 0x4C, enumerator
/Renode-Infrastructure-v1.15.3-29f510e/src/Emulator/Peripherals/Peripherals/I3C/
DCaliptra_I3C.cs57 InterruptEnable.RX_DESC_STAT_EN); in Init()
62 InterruptEnable.TX_DESC_THLD_STAT_EN); in Init()
67 InterruptEnable.RX_DATA_THLD_STAT_EN); in Init()
72 InterruptEnable.RX_DESC_THLD_STAT_EN); in Init()
77 InterruptEnable.IBI_DONE_EN); in Init()
/Renode-Infrastructure-v1.15.3-29f510e/src/Emulator/Peripherals/Peripherals/SPI/
DXilinxQSPI.cs93 case Offset.InterruptEnable: in WriteDoubleWord()
94 registers.InterruptEnable |= value; in WriteDoubleWord()
97 registers.InterruptEnable &= ~value; in WriteDoubleWord()
156 if((registers.InterruptEnable & (1u << 3)) != 0) in checkInterrupt()
164 if((registers.InterruptEnable & (1u<<4))!=0) //RX FIFO not empty in checkInterrupt()
170 …if(((registers.InterruptEnable & (1u << 2)) != 0) && writeOccured) //TX FIFO not full (always in e… in checkInterrupt()
296 public uint InterruptEnable = 0x00000000; field in Antmicro.Renode.Peripherals.SPI.XilinxQSPI.regs
317 InterruptEnable = 0x08, enumerator
DCadence_SPI.cs316 {(long)Registers.InterruptEnable, new DoubleWordRegister(this) in BuildRegisterMap()
319 writeCallback: (_, val) => txFifoUnderflow.InterruptEnable(val), in BuildRegisterMap()
323 writeCallback: (_, val) => rxFifoFull.InterruptEnable(val), in BuildRegisterMap()
327 writeCallback: (_, val) => rxFifoNotEmpty.InterruptEnable(val), in BuildRegisterMap()
331 writeCallback: (_, val) => txFifoFull.InterruptEnable(val), in BuildRegisterMap()
335 writeCallback: (_, val) => txFifoNotFull.InterruptEnable(val), in BuildRegisterMap()
339 writeCallback: (_, val) => modeFail.InterruptEnable(val), in BuildRegisterMap()
343 writeCallback: (_, val) => rxFifoOverflow.InterruptEnable(val), in BuildRegisterMap()
544 InterruptEnable = 0x08, enumerator
DCadence_xSPI.cs300 {(long)Registers.InterruptEnable, new DoubleWordRegister(this) in BuildRegisterMap()
305 writeCallback: (_, val) => commandCompleted.InterruptEnable(val) in BuildRegisterMap()
309 writeCallback: (_, val) => dmaError.InterruptEnable(val) in BuildRegisterMap()
313 writeCallback: (_, val) => dmaTriggered.InterruptEnable(val) in BuildRegisterMap()
317 writeCallback: (_, val) => commandIgnored.InterruptEnable(val) in BuildRegisterMap()
324 writeCallback: (_, val) => controllerIdle.InterruptEnable(val) in BuildRegisterMap()
469 InterruptEnable = 0x0114, enumerator
/Renode-Infrastructure-v1.15.3-29f510e/src/Emulator/Peripherals/Peripherals/Network/
DGaislerEth.cs245 if(rd.InterruptEnable && ((registers.Control & (1u << 3)) != 0)) in ReceiveFrame()
294 if(td.InterruptEnable && ((registers.Control & (1u << 2)) != 0)) in transmitFrame()
304 td.InterruptEnable = false; in transmitFrame()
377 public bool InterruptEnable; field in Antmicro.Renode.Peripherals.Network.GaislerEth.transmitDescriptor
392 InterruptEnable = (word0 & (1u << 13)) != 0; in Fetch()
402 …ttemptLimitError ? 1u << 15 : 0) | (UnderrunError ? 1u << 14 : 0) | (InterruptEnable ? 1u << 13 : … in WriteBack()
431 public bool InterruptEnable; field in Antmicro.Renode.Peripherals.Network.GaislerEth.receiveDescriptor
449 InterruptEnable = (word0 & (1u << 13)) != 0; in Fetch()
461 …word0 |= (InterruptEnable ? 1u << 13 : 0) | (Wrap ? 1u << 12 : 0) | (Enable ? 1u << 18 : 0) | (Len… in WriteBack()
/Renode-Infrastructure-v1.15.3-29f510e/src/Emulator/Peripherals/Peripherals/GPIOPort/
DQuark_GPIOController.cs26 InterruptEnable = new bool[NumberOfGPIOS]; in Quark_GPIOController()
52 InterruptEnable[i] = false; in Reset()
127 public bool[] InterruptEnable { get; private set; } property in Antmicro.Renode.Peripherals.X86.Quark_GPIOController
156 {(long)Registers.InterruptEnable, new DoubleWordRegister(this) in PrepareRegisters()
158 … Array.Copy(BitHelper.GetBits((uint)val), InterruptEnable, 32); in PrepareRegisters()
161 … valueProviderCallback: _ => BitHelper.GetValueFromBitsArray(InterruptEnable)) in PrepareRegisters()
241 if(!InterruptEnable[i]) in RefreshInterrupts()
320 InterruptEnable = 0x30, enumerator
DCC2538_GPIO.cs144 {(long)Registers.InterruptEnable, new DoubleWordRegister(this) in PrepareRegisters()
150 irqManager.InterruptEnable[i] = bits[i]; in PrepareRegisters()
155 … valueProviderCallback: _ => BitHelper.GetValueFromBitsArray(irqManager.InterruptEnable)) in PrepareRegisters()
253 InterruptEnable = 0x410, enumerator
/Renode-Infrastructure-v1.15.3-29f510e/src/Emulator/Peripherals/Peripherals/Timers/
DS32K3XX_PeriodicInterruptTimer.cs44 …var interrupt = clockChannels.Values.Any(clockChannel => clockChannel.InterruptEnable && clockChan… in UpdateInterrupts()
117 valueProviderCallback: _ => clockChannel.InterruptEnable, in DefineChannelRegisters()
120 clockChannel.InterruptEnable = value; in DefineChannelRegisters()
201 InterruptEnable = false; in Reset()
220 public bool InterruptEnable property in Antmicro.Renode.Peripherals.Timers.S32K3XX_PeriodicInterruptTimer.ClockChannel
DAmbiqApollo4_SystemTimer.cs153 Registers.InterruptEnable.Define(this) in DefineRegisters()
155 …llback: (registerIndex, _, newValue) => compareRegisters[registerIndex].InterruptEnable = newValue, in DefineRegisters()
156 … valueProviderCallback: (registerIndex, _) => compareRegisters[registerIndex].InterruptEnable) in DefineRegisters()
160 …geCallback: (registerIdx, _, newValue) => captureRegisters[registerIdx].InterruptEnable = newValue, in DefineRegisters()
161 … valueProviderCallback: (registerIdx, _) => captureRegisters[registerIdx].InterruptEnable) in DefineRegisters()
201 if(captureRegister.InterruptEnable && captureRegister.InterruptStatus) in UpdateCaptureOverflowIRQ()
319 public bool InterruptEnable property in Antmicro.Renode.Peripherals.Timers.AmbiqApollo4_SystemTimer.CaptureRegister
421 public bool InterruptEnable property in Antmicro.Renode.Peripherals.Timers.AmbiqApollo4_SystemTimer.CompareRegister
500 InterruptEnable = 0x100, enumerator
DPeriodicInterruptTimer.cs67 timers[i].Control = InnerTimer.ControlRegister.InterruptEnable; in Reset()
156 CoreTimer.EventEnabled = (value & ControlRegister.InterruptEnable) != 0;
168 InterruptEnable = (1 << 1), enumerator
DCadence_TTC.cs191 writeCallback: (_, val) => timer.Match[2].InterruptEnable = val, in BuildTimerUnitRegisters()
192 valueProviderCallback: (_) => timer.Match[2].InterruptEnable in BuildTimerUnitRegisters()
195 writeCallback: (_, val) => timer.Match[1].InterruptEnable = val, in BuildTimerUnitRegisters()
196 valueProviderCallback: (_) => timer.Match[1].InterruptEnable in BuildTimerUnitRegisters()
199 writeCallback: (_, val) => timer.Match[0].InterruptEnable = val, in BuildTimerUnitRegisters()
200 valueProviderCallback: (_) => timer.Match[0].InterruptEnable in BuildTimerUnitRegisters()
479 public bool InterruptEnable property in Antmicro.Renode.Peripherals.Timers.Cadence_TTC.TimerUnit.MatchTimerUnit
/Renode-Infrastructure-v1.15.3-29f510e/src/Emulator/Peripherals/Peripherals/I2C/
DCadence_I2C.cs438 {(long)Registers.InterruptEnable, new DoubleWordRegister(this) in BuildRegisterMap()
443 writeCallback: (_, val) => rxFifoUnderflow.InterruptEnable(val), in BuildRegisterMap()
447 writeCallback: (_, val) => txFifoOverflow.InterruptEnable(val), in BuildRegisterMap()
451 writeCallback: (_, val) => rxFifoOverflow.InterruptEnable(val), in BuildRegisterMap()
455 writeCallback: (_, val) => targetReady.InterruptEnable(val), in BuildRegisterMap()
460 writeCallback: (_, val) => transferNotAcknowledged.InterruptEnable(val), in BuildRegisterMap()
464 writeCallback: (_, val) => transferNewData.InterruptEnable(val), in BuildRegisterMap()
468 writeCallback: (_, val) => transferCompleted.InterruptEnable(val), in BuildRegisterMap()
592 InterruptEnable = 0x24, enumerator
DEFR32xG2_I2CController.cs41 {(long)Registers.InterruptEnable, GenerateInterruptEnableRegister()}, in EFR32xG2_I2CController()
83 InterruptEnable = 0x40, enumerator
DEFR32_I2CController.cs36 {(long)Registers.InterruptEnable, GenerateInterruptEnableRegister()}, in EFR32_I2CController()
87 InterruptEnable = 0x40, enumerator
/Renode-Infrastructure-v1.15.3-29f510e/src/Emulator/Peripherals/Peripherals/Miscellaneous/
DQuark_SystemControlSubsystem.cs32 …{(long)Registers.InterruptEnable, CreateAlwaysOnGPIORegister(Quark_GPIOController.Registers.Interr… in Quark_SystemControlSubsystem()
100 InterruptEnable = 0xB30, enumerator
DSAM_TRNG.cs59 Registers.InterruptEnable.Define(this) in DefineRegisters()
92 InterruptEnable = 0x10, enumerator
/Renode-Infrastructure-v1.15.3-29f510e/src/Emulator/Peripherals/Test/PeripheralsTests/
DOpenTitan_SpiDeviceTest.cs91 WriteToPeripheral(SPI.Registers.InterruptEnable, RxFullInterruptMask); in ShouldSetInterruptOnRxFifoFull()
105 WriteToPeripheral(SPI.Registers.InterruptEnable, RxFifoOverflowMask); in ShouldSetInterruptOnRxOverflow()
120 WriteToPeripheral(SPI.Registers.InterruptEnable, RxWatermarkInterruptMask); in ShouldSetInterruptOnRxFifoWatermark()
134 WriteToPeripheral(SPI.Registers.InterruptEnable, TxWatermarkInterruptMask); in ShouldSetInterruptOnTxFifoWatermark()
150 WriteToPeripheral(SPI.Registers.InterruptEnable, TxFifoUnderflowMask); in ShouldSetInterruptOnTxUnderflow()
DCadence_TTCTests.cs37 WriteTimerRegister(index, Registers.InterruptEnable, InterruptMaskAll); in ShouldResetCounter()
78 WriteTimerRegister(index, Registers.InterruptEnable, interruptMask); in ShouldOverflowInOneSecond()
142 InterruptEnable = 0x60, enumerator
/Renode-Infrastructure-v1.15.3-29f510e/src/Emulator/Peripherals/Peripherals/CAN/
DMPFS_CAN.cs30 (long)ControllerRegisters.InterruptEnable, in MPFS_CAN()
132 … writeCallback: (_, val) => txMessageBuffers[index].InterruptEnable = val, in MPFS_CAN()
133 valueProviderCallback: _ => txMessageBuffers[index].InterruptEnable, in MPFS_CAN()
194 … writeCallback: (_, val) => rxMessageBuffers[index].InterruptEnable = val, in MPFS_CAN()
195 valueProviderCallback: _ => rxMessageBuffers[index].InterruptEnable, in MPFS_CAN()
369 … rxInterruptsEnabled.Value && rxMessageBuffers.Any(x => x.IsMessageAvailable && x.InterruptEnable); in UpdateInterrupts()
370 … = txInterruptsEnabled.Value && txMessageBuffers.Any(x => x.IsRequestPending && x.InterruptEnable); in UpdateInterrupts()
406 public bool InterruptEnable { get; set; } property in Antmicro.Renode.Peripherals.CAN.MPFS_CAN.MessageBuffer
548 InterruptEnable = 0x004, enumerator

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