| /Renode-Infrastructure-v1.15.3-29f510e/src/Emulator/Peripherals/Peripherals/I2C/ |
| D | Cadence_I2C.cs | 473 {(long)Registers.InterruptDisable, new DoubleWordRegister(this) in BuildRegisterMap()
478 writeCallback: (_, val) => rxFifoUnderflow.InterruptDisable(val), in BuildRegisterMap()
482 writeCallback: (_, val) => txFifoOverflow.InterruptDisable(val), in BuildRegisterMap()
486 writeCallback: (_, val) => rxFifoOverflow.InterruptDisable(val), in BuildRegisterMap()
490 writeCallback: (_, val) => targetReady.InterruptDisable(val), in BuildRegisterMap()
495 writeCallback: (_, val) => transferNotAcknowledged.InterruptDisable(val), in BuildRegisterMap()
499 writeCallback: (_, val) => transferNewData.InterruptDisable(val), in BuildRegisterMap()
503 writeCallback: (_, val) => transferCompleted.InterruptDisable(val), in BuildRegisterMap()
593 InterruptDisable = 0x28, enumerator
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| D | SAM4S_TWI.cs | 201 Registers.InterruptDisable.Define(this) in DefineRegisters()
604 InterruptDisable = 0x28, enumerator
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| /Renode-Infrastructure-v1.15.3-29f510e/src/Emulator/Peripherals/Peripherals/SPI/ |
| D | Cadence_SPI.cs | 348 {(long)Registers.InterruptDisable, new DoubleWordRegister(this) in BuildRegisterMap()
351 writeCallback: (_, val) => txFifoUnderflow.InterruptDisable(val), in BuildRegisterMap()
355 writeCallback: (_, val) => rxFifoFull.InterruptDisable(val), in BuildRegisterMap()
359 writeCallback: (_, val) => rxFifoNotEmpty.InterruptDisable(val), in BuildRegisterMap()
363 writeCallback: (_, val) => txFifoFull.InterruptDisable(val), in BuildRegisterMap()
367 writeCallback: (_, val) => txFifoNotFull.InterruptDisable(val), in BuildRegisterMap()
371 writeCallback: (_, val) => modeFail.InterruptDisable(val), in BuildRegisterMap()
375 writeCallback: (_, val) => rxFifoOverflow.InterruptDisable(val), in BuildRegisterMap()
545 InterruptDisable = 0x0c, enumerator
|
| D | XilinxQSPI.cs | 96 case Offset.InterruptDisable: in WriteDoubleWord()
318 InterruptDisable = 0x0C, enumerator
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| D | SAM_SPI.cs | 215 RegistersCollection.AddRegister((long)Registers.InterruptDisable, in DefineRegisters()
419 InterruptDisable = 0x18, enumerator
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| /Renode-Infrastructure-v1.15.3-29f510e/src/Emulator/Peripherals/Peripherals/UART/ |
| D | Cadence_UART.cs | 260 {(long)Registers.InterruptDisable, new DoubleWordRegister(this) in BuildRegisterMap()
268 writeCallback: (_, val) => rxTimeoutError.InterruptDisable(val), in BuildRegisterMap()
274 writeCallback: (_, val) => rxFifoOverflow.InterruptDisable(val), in BuildRegisterMap()
279 writeCallback: (_, val) => txFifoEmpty.InterruptDisable(val), in BuildRegisterMap()
283 writeCallback: (_, val) => rxFifoFull.InterruptDisable(val), in BuildRegisterMap()
287 writeCallback: (_, val) => rxFifoEmpty.InterruptDisable(val), in BuildRegisterMap()
291 writeCallback: (_, val) => rxFifoTrigger.InterruptDisable(val), in BuildRegisterMap()
535 InterruptDisable = 0x0c, enumerator
|
| D | Atmel91DebugUnit.cs | 62 case Offset.InterruptDisable: in WriteDoubleWord()
158 InterruptDisable = 0x0C, enumerator
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| D | SAM_USART.cs | 290 Registers.InterruptDisable.Define(this) in DefineRegisters()
641 InterruptDisable = 0x0C, enumerator
|
| /Renode-Infrastructure-v1.15.3-29f510e/src/Emulator/Peripherals/Peripherals/Miscellaneous/ |
| D | SAM_TRNG.cs | 68 Registers.InterruptDisable.Define(this) in DefineRegisters()
93 InterruptDisable = 0x14, enumerator
|
| D | SAM4S_DACC.cs | 169 Registers.InterruptDisable.Define(this) in DefineRegisters()
267 InterruptDisable = 0x28, enumerator
|
| /Renode-Infrastructure-v1.15.3-29f510e/src/Emulator/Peripherals/Peripherals/Helpers/ |
| D | CadenceInterruptFlag.cs | 47 public void InterruptDisable(bool disable) in InterruptDisable() method in Antmicro.Renode.Peripherals.Helpers.CadenceInterruptFlag
|
| /Renode-Infrastructure-v1.15.3-29f510e/src/Emulator/Peripherals/Peripherals/Timers/ |
| D | ZynqMP_RTC.cs | 103 Registers.InterruptDisable.Define(this) in DefineRegisters()
206 InterruptDisable = 0x2C, enumerator
|
| /Renode-Infrastructure-v1.15.3-29f510e/src/Emulator/Peripherals/Test/PeripheralsTests/ |
| D | Cadence_UARTTests.cs | 90 InterruptDisable = 0x0c, enumerator
|
| /Renode-Infrastructure-v1.15.3-29f510e/src/Emulator/Peripherals/Peripherals/CRC/ |
| D | SAM4S_CRCCU.cs | 109 Registers.InterruptDisable.Define(this) in DefineRegisters()
236 InterruptDisable = 0x44, enumerator
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| /Renode-Infrastructure-v1.15.3-29f510e/src/Emulator/Peripherals/Peripherals/Analog/ |
| D | SAM4S_ADC.cs | 251 Registers.InterruptDisable.Define(this) in DefineRegisters()
451 InterruptDisable = 0x28, enumerator
|
| /Renode-Infrastructure-v1.15.3-29f510e/src/Emulator/Peripherals/Peripherals/GPIOPort/ |
| D | XilinxGPIOPS.cs | 272 InterruptDisable = 0x14, enumerator
|
| D | SAM4S_PIO.cs | 234 Registers.InterruptDisable.Define(this) in DefineRegisters()
573 InterruptDisable = 0x0044, // WO enumerator
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| /Renode-Infrastructure-v1.15.3-29f510e/src/Emulator/Peripherals/Peripherals/Wireless/ |
| D | NRF52840_Radio.cs | 172 RegistersCollection.AddRegister((long)Registers.InterruptDisable, in DefineRegisters()
735 InterruptDisable = 0x308, enumerator
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| /Renode-Infrastructure-v1.15.3-29f510e/src/Emulator/Peripherals/Peripherals/Network/ |
| D | CadenceGEM.cs | 290 {(long)Registers.InterruptDisable, interruptManager.GetRegister<DoubleWordRegister>( in CadenceGEM()
1109 InterruptDisable = 0x2C, enumerator
|
