1 // 2 // Copyright (c) 2010-2024 Antmicro 3 // 4 // This file is licensed under the MIT License. 5 // Full license text is available in 'licenses/MIT.txt'. 6 // 7 using Antmicro.Renode.Core; 8 using Antmicro.Renode.Peripherals.CPU; 9 10 namespace Antmicro.Renode.Peripherals.Network 11 { 12 public class S32K3XX_GMAC : SynopsysDWCEthernetQualityOfService 13 { S32K3XX_GMAC(IMachine machine, long systemClockFrequency, ICPU cpuContext = null)14 public S32K3XX_GMAC(IMachine machine, long systemClockFrequency, ICPU cpuContext = null) 15 : base(machine, systemClockFrequency, cpuContext) 16 { 17 Reset(); 18 } 19 ReadDoubleWord(long offset)20 public override uint ReadDoubleWord(long offset) 21 { 22 if(offset < (long)Registers.MTLOperationMode) 23 { 24 return base.ReadDoubleWord(offset); 25 } 26 else if(offset < (long)Registers.DMAMode) 27 { 28 return ReadDoubleWordFromMTL(offset - (long)Registers.MTLOperationMode); 29 } 30 return ReadDoubleWordFromDMA(offset - (long)Registers.DMAMode); 31 } 32 WriteDoubleWord(long offset, uint value)33 public override void WriteDoubleWord(long offset, uint value) 34 { 35 if(offset < (long)Registers.MTLOperationMode) 36 { 37 base.WriteDoubleWord(offset, value); 38 } 39 else if(offset < (long)Registers.DMAMode) 40 { 41 WriteDoubleWordToMTL(offset - (long)Registers.MTLOperationMode, value); 42 } 43 else 44 { 45 WriteDoubleWordToDMA(offset - (long)Registers.DMAMode, value); 46 } 47 } 48 49 public override long Size => 0x1300; 50 51 public GPIO Channel0TX => dmaChannels[0].TxIRQ; 52 public GPIO Channel0RX => dmaChannels[0].RxIRQ; 53 public GPIO Channel1TX => dmaChannels[1].TxIRQ; 54 public GPIO Channel1RX => dmaChannels[1].RxIRQ; 55 public GPIO Channel2TX => dmaChannels[2].TxIRQ; 56 public GPIO Channel2RX => dmaChannels[2].RxIRQ; 57 58 // Base model configuration: 59 protected override long[] DMAChannelOffsets => new long[] 60 { 61 (long)Registers.DMAChannel0Control - (long)Registers.DMAMode, 62 (long)Registers.DMAChannel1Control - (long)Registers.DMAMode, 63 (long)Registers.DMAChannel2Control - (long)Registers.DMAMode, 64 }; 65 protected override BusWidth DMABusWidth => BusWidth.Bits64; 66 protected override int RxQueueSize => 16384; 67 protected override bool SeparateDMAInterrupts => true; 68 69 private enum Registers 70 { 71 Configuration = 0x0, // MAC_Configuration 72 ExtendedConfiguration = 0x4, // MAC_Ext_Configuration 73 PacketFilter = 0x8, // MAC_Packet_Filter 74 WatchdogTimeout = 0xC, // MAC_Watchdog_Timeout 75 HashTable0 = 0x10, // MAC_Hash_Table_Reg0 76 HashTable1 = 0x14, // MAC_Hash_Table_Reg1 77 HashTable2 = 0x18, // MAC_Hash_Table_Reg2 78 HashTable3 = 0x1C, // MAC_Hash_Table_Reg3 79 HashTable4 = 0x20, // MAC_Hash_Table_Reg4 80 HashTable5 = 0x24, // MAC_Hash_Table_Reg5 81 HashTable6 = 0x28, // MAC_Hash_Table_Reg6 82 HashTable7 = 0x2C, // MAC_Hash_Table_Reg7 83 84 VLANTagControl = 0x50, // MAC_VLAN_Tag_Ctrl 85 VLANTagData = 0x54, // MAC_VLAN_Tag_Data 86 VLANTagFilter0 = 0x54, // MAC_VLAN_Tag_Filter0 87 VLANTagFilter1 = 0x54, // MAC_VLAN_Tag_Filter1 88 VLANTagFilter2 = 0x54, // MAC_VLAN_Tag_Filter2 89 VLANTagFilter3 = 0x54, // MAC_VLAN_Tag_Filter3 90 VLANTagFilter4 = 0x54, // MAC_VLAN_Tag_Filter4 91 VLANTagFilter5 = 0x54, // MAC_VLAN_Tag_Filter5 92 VLANTagFilter6 = 0x54, // MAC_VLAN_Tag_Filter6 93 VLANTagFilter7 = 0x54, // MAC_VLAN_Tag_Filter7 94 VLANTagFilter8 = 0x54, // MAC_VLAN_Tag_Filter8 95 VLANTagFilter9 = 0x54, // MAC_VLAN_Tag_Filter9 96 VLANTagFilter10 = 0x54, // MAC_VLAN_Tag_Filter10 97 VLANTagFilter11 = 0x54, // MAC_VLAN_Tag_Filter11 98 VLANTagFilter12 = 0x54, // MAC_VLAN_Tag_Filter12 99 VLANTagFilter13 = 0x54, // MAC_VLAN_Tag_Filter13 100 VLANTagFilter14 = 0x54, // MAC_VLAN_Tag_Filter14 101 VLANTagFilter15 = 0x54, // MAC_VLAN_Tag_Filter15 102 VLANTagFilter16 = 0x54, // MAC_VLAN_Tag_Filter16 103 VLANTagFilter17 = 0x54, // MAC_VLAN_Tag_Filter17 104 VLANTagFilter18 = 0x54, // MAC_VLAN_Tag_Filter18 105 VLANTagFilter19 = 0x54, // MAC_VLAN_Tag_Filter19 106 VLANTagFilter20 = 0x54, // MAC_VLAN_Tag_Filter20 107 VLANTagFilter21 = 0x54, // MAC_VLAN_Tag_Filter21 108 VLANTagFilter22 = 0x54, // MAC_VLAN_Tag_Filter22 109 VLANTagFilter23 = 0x54, // MAC_VLAN_Tag_Filter23 110 VLANTagFilter24 = 0x54, // MAC_VLAN_Tag_Filter24 111 VLANTagFilter25 = 0x54, // MAC_VLAN_Tag_Filter25 112 VLANTagFilter26 = 0x54, // MAC_VLAN_Tag_Filter26 113 VLANTagFilter27 = 0x54, // MAC_VLAN_Tag_Filter27 114 VLANTagFilter28 = 0x54, // MAC_VLAN_Tag_Filter28 115 VLANTagFilter29 = 0x54, // MAC_VLAN_Tag_Filter29 116 VLANTagFilter30 = 0x54, // MAC_VLAN_Tag_Filter30 117 VLANTagFilter31 = 0x54, // MAC_VLAN_Tag_Filter31 118 119 VLANHashTable = 0x58, // MAC_VLAN_Hash_Table 120 121 VLANInclusion = 0x60, // MAC_VLAN_Incl 122 VLANInclusion0 = 0x60, // MAC_VLAN_Incl0 123 VLANInclusion1 = 0x60, // MAC_VLAN_Incl1 124 VLANInclusion2 = 0x60, // MAC_VLAN_Incl2 125 VLANInclusion3 = 0x60, // MAC_VLAN_Incl3 126 VLANInclusion4 = 0x60, // MAC_VLAN_Incl4 127 VLANInclusion5 = 0x60, // MAC_VLAN_Incl5 128 VLANInclusion6 = 0x60, // MAC_VLAN_Incl6 129 VLANInclusion7 = 0x60, // MAC_VLAN_Incl7 130 VLANInclusion8 = 0x60, // MAC_VLAN_Incl8 131 InnerVLANInclusion = 0x64, // MAC_Inner_VLAN_Incl 132 133 Queue0TransmitFlowControl = 0x70, // MAC_Q0_Tx_Flow_Ctrl 134 Queue1TransmitFlowControl = 0x74, // MAC_Q1_Tx_Flow_Ctrl 135 Queue2TransmitFlowControl = 0x78, // MAC_Q2_Tx_Flow_Ctrl 136 137 ReceiveFlowControl = 0x90, // MAC_Rx_Flow_Ctrl 138 ReceiveQueueControl4 = 0x94, // MAC_RxQ_Ctrl4 139 TransmitQueuePriorityMapping0 = 0x98, // MAC_TxQ_Prty_Map0 140 ReceiveQueueControl0 = 0xA0, // MAC_RxQ_Ctrl0 141 ReceiveQueueControl1 = 0xA4, // MAC_RxQ_Ctrl1 142 ReceiveQueueControl2 = 0xA8, // MAC_RxQ_Ctrl2 143 InterruptStatus = 0xB0, // MAC_Interrupt_Status 144 InterruptEnable = 0xB4, // MAC_Interrupt_Enable 145 ReceiveTransmitStatus = 0xB8, // MAC_Rx_Tx_Status 146 PHYInterfaceControlAndStatus = 0xF8, // MAC_PHYIF_Control_Status 147 Version = 0x110, // MAC_Version 148 Debug = 0x114, // MAC_Debug 149 HardwareFeature0 = 0x11C, // MAC_HW_Feature0 150 HardwareFeature1 = 0x120, // MAC_HW_Feature1 151 HardwareFeature2 = 0x124, // MAC_HW_Feature2 152 HardwareFeature3 = 0x128, // MAC_HW_Feature3 153 154 FSMErrorsInterruptStatus = 0x140, // MAC_DPP_FSM_Interrupt_Status 155 FSMControl = 0x148, // MAC_FSM_Control 156 FSMTimeouts = 0x14C, // MAC_FSM_ACT_Timer 157 158 MDIOAddress = 0x200, // MAC_MDIO_Address 159 ARPAddress = 0x210, // MAC_ARP_Address 160 CSRSoftwareControl = 0x230, // MAC_CSR_SW_Ctrl 161 FramePreeptionControl = 0x234, // MAC_FPE_CTRL_STS 162 ExtendedConfiguration1 = 0x238, // MAC_Ext_Cfg1 163 164 PresentationTimeNanoseconds = 0x240, // MAC_Presn_Time_ns 165 PresentationTimeUpdate = 0x244, // MAC_Presn_Time_Updt 166 167 Address0High = 0x300, // MAC_Address0_High 168 Address0Low = 0x304, // MAC_Address0_Low 169 Address1High = 0x308, // MAC_Address1_High 170 Address1Low = 0x30C, // MAC_Address1_Low 171 Address2High = 0x310, // MAC_Address2_High 172 Address2Low = 0x314, // MAC_Address2_Low 173 174 MMCControl = 0x700, // MMC_Control 175 MMCReceiveInterrupt = 0x704, // MMC_Rx_Interrupt 176 MMCTransmitInterrupt = 0x708, // MMC_Tx_Interrupt 177 MMCReceiveInterruptMask = 0x70C, // MMC_Rx_Interrupt_Mask 178 MMCTransmitInterruptMask = 0x710, // MMC_Tx_Interrupt_Mask 179 180 TransmitOctetCount = 0x714, // Tx_Octet_Count_Good_Bad 181 TransmitPacketCount = 0x718, // Tx_Packet_Count_Good_Bad 182 TransmitBroadcastPacketGoodCount = 0x71C, // Tx_Broadcast_Packets_Good 183 TransmitMulticastPacketGoodCount = 0x720, // Tx_Multicast_Packets_Good 184 Transmit64OctetPacketCount = 0x724, // Tx_64Octets_Packets_Good_Bad 185 Transmit64To127OctetPacketCount = 0x728, // Tx_65To127Octets_Packets_Good_Bad 186 Transmit128To255OctetPacketCount = 0x72C, // Tx_128To255Octets_Packets_Good_Bad 187 Transmit256To511OctetPacketCount = 0x730, // Tx_256To511Octets_Packets_Good_Bad 188 Transmit512To1023OctetPacketCount = 0x734, // Tx_512To1023Octets_Packets_Good_Bad 189 Transmit1024ToMaxOctetPacketCount = 0x738, // Tx_1024ToMaxOctets_Packets_Good_Bad 190 TransmitUnicastPacketCount = 0x73C, // Tx_Unicast_Packets_Good_Bad 191 TransmitMulticastPacketCount = 0x740, // Tx_Multicast_Packets_Good_Bad 192 TransmitBroadcastPacketCount = 0x744, // Tx_Broadcast_Packets_Good_Bad 193 TransmitUnderflowErrorPacketCount = 0x748, // Tx_Underflow_Error_Packets 194 TransmitSingleCollisionPacketGoodCount = 0x74C, // Tx_Single_Collision_Good_Packets 195 TransmitMultipleCollisionPacketGoodCount = 0x750, // Tx_Multiple_Collision_Good_Packets 196 TransmitDeferredPacketCount = 0x754, // Tx_Deferred_Packets 197 TransmitLateCollisionPacketCount = 0x758, // Tx_Late_Collision_Packets 198 TransmitExcessiveCollisionPacketCount = 0x75C, // Tx_Late_Collision_Packets 199 TransmitCarrierErrorPacketCount = 0x760, // Tx_Carrier_Error_Packets 200 TransmitOctetGoodCount = 0x764, // Tx_Octet_Count_Good 201 TransmitPacketGoodCount = 0x768, // Tx_Packet_Count_Good 202 TransmitExcessiveDeferralErrorPacketCount = 0x76C, // Tx_Excessive_Deferral_Error 203 TransmitPausePacketCount = 0x770, // Tx_Pause_Packets 204 TransmitVLANPacketGoodCount = 0x774, // Tx_VLAN_Packets_Good 205 TransmitGreaterThanMaxSizePacketGoodCount = 0x778, // Tx_OSize_Packets_Good 206 207 ReceivePacketCount = 0x780, // Rx_Packets_Count_Good_Bad 208 ReceiveOctetCount = 0x784, // Rx_Octet_Count_Good_Bad 209 ReceiveOctetGoodCount = 0x788, // Rx_Octet_Count_Good 210 ReceiveBroadcastPacketGoodCount = 0x78C, // Rx_Broadcast_Packets_Good 211 ReceiveMulticastPacketGoodCount = 0x790, // Rx_Multicast_Packets_Good 212 ReceiveCRCErrorPacketCount = 0x794, // Rx_CRC_Error_Packets 213 ReceiveAlignmentErrorPacketCount = 0x798, // Rx_Alignment_Error_Packets 214 ReceiveRuntErrorPacketCount = 0x79C, // Rx_Runt_Error_Packets 215 ReceiveJabberErrorPacketCount = 0x7A0, // Rx_Jabber_Error_Packets 216 ReceiveUndersizeErrorPacketCount = 0x7A4, // Rx_Undersize_Packets_Good 217 ReceiveOversizeErrorPacketCount = 0x7A8, // Rx_Oversize_Packets_Good 218 Receive64To127OctetPacketCount = 0x7B0, // Rx_65To127Octets_Packets_Good_Bad 219 Receive128To255OctetPacketCount = 0x7B4, // Rx_128To255Octets_Packets_Good_Bad 220 Receive256To511OctetPacketCount = 0x7B8, // Rx_256To511Octets_Packets_Good_Bad 221 Receive512To1023OctetPacketCount = 0x7BC, // Rx_512To1023Octets_Packets_Good_Bad 222 Receive1024ToMaxOctetPacketCount = 0x7C0, // Rx_1024ToMaxOctets_Packets_Good_Bad 223 ReceiveUnicastPacketGoodCount = 0x7C4, // Rx_Unicast_Packets_Good 224 ReceiveLengthErrorPacketCount = 0x7C8, // Rx_Length_Error_Packets 225 ReceiveOutOfRangeTypePacketCount = 0x7CC, // Rx_Out_Of_Range_Type_Packets 226 ReceivePausePacketCount = 0x7D0, // Rx_Pause_Packets 227 ReceiveFIFOOverflowPacketCount = 0x7D4, // Rx_FIFO_Overflow_Packets 228 ReceiveVLANPacketCount = 0x7D8, // Rx_VLAN_Packets_Good_Bad 229 ReceiveWatchdogErrorPacketCount = 0x7DC, // Rx_Watchdog_Error_Packets 230 ReceiveReceiveErrorPacketCount = 0x7E0, // Rx_Receive_Error_Packets 231 ReceiveControlPacketGoodCount = 0x7E4, // Rx_Control_Packets_Good 232 233 MMCFramePreemptionTransmitInterrupt = 0x8A0, // MMC_FPE_Tx_Interrupt 234 MMCFramePreemptionTransmitInterruptMask = 0x8A4, // MMC_FPE_Tx_Interrupt_Mask 235 MMCFramePreemptionTransmitFragmentCount = 0x8A8, // MMC_Tx_FPE_Fragment_Cntr 236 MMCTransmitHoldRequestCount = 0x8AC, // MMC_Tx_Hold_Req_Cntr 237 MMCFramePreemptionReceiveInterrupt = 0x8C0, // MMC_FPE_Rx_Interrupt 238 MMCFramePreemptionReceiveInterruptMask = 0x8C4, // MMC_FPE_Rx_Interrupt_Mask 239 MMCReceivePacketAssemblyErrorCount = 0x8C8, // MMC_Rx_Packet_Assembly_Err_Cntr 240 MMCReceivePacketSMDErrorCount = 0x8CC, // MMC_Rx_Packet_SMD_Err_Cntr 241 MMCReceivePacketAssemblyOkCount = 0x8D0, // MMC_Rx_Packet_Assembly_OK_Cntr 242 MMCFramePreemptionReceiveFragmentCount = 0x8D4, // MMC_Rx_FPE_Fragment_Cntr 243 244 Layer3Layer4Control0 = 0x900, // MAC_L3_L4_Control0 245 Layer4Address0 = 0x904, // MAC_Layer4_Address0 246 Layer3Address0Register0 = 0x910, // MAC_Layer3_Addr0_Reg0 247 Layer3Address1Register0 = 0x914, // MAC_Layer3_Addr1_Reg0 248 Layer3Address2Register0 = 0x918, // MAC_Layer3_Addr2_Reg0 249 Layer3Address3Register0 = 0x91C, // MAC_Layer3_Addr3_Reg0 250 251 Layer3Layer4Control1 = 0x930, // MAC_L3_L4_Control1 252 Layer4Address1 = 0x934, // MAC_Layer4_Address1 253 Layer3Address0Register1 = 0x940, // MAC_Layer3_Addr0_Reg1 254 Layer3Address1Register1 = 0x944, // MAC_Layer3_Addr1_Reg1 255 Layer3Address2Register1 = 0x948, // MAC_Layer3_Addr2_Reg1 256 Layer3Address3Register1 = 0x94C, // MAC_Layer3_Addr3_Reg1 257 258 Layer3Layer4Control2 = 0x960, // MAC_L3_L4_Control2 259 Layer4Address2 = 0x964, // MAC_Layer4_Address2 260 Layer3Address0Register2 = 0x970, // MAC_Layer3_Addr0_Reg2 261 Layer3Address1Register2 = 0x974, // MAC_Layer3_Addr1_Reg2 262 Layer3Address2Register2 = 0x978, // MAC_Layer3_Addr2_Reg2 263 Layer3Address3Register2 = 0x97C, // MAC_Layer3_Addr3_Reg2 264 265 Layer3Layer4Control3 = 0x990, // MAC_L3_L4_Control3 266 Layer4Address3 = 0x994, // MAC_Layer4_Address3 267 Layer3Address0Register3 = 0x9A0, // MAC_Layer3_Addr0_Reg3 268 Layer3Address1Register3 = 0x9A4, // MAC_Layer3_Addr1_Reg3 269 Layer3Address2Register3 = 0x9A8, // MAC_Layer3_Addr2_Reg3 270 Layer3Address3Register3 = 0x9AC, // MAC_Layer3_Addr3_Reg3 271 272 Layer3Layer4Control4 = 0x9C0, // MAC_L3_L4_Control4 273 Layer4Address4 = 0x9C4, // MAC_Layer4_Address4 274 Layer3Address0Register4 = 0x9D0, // MAC_Layer3_Addr0_Reg4 275 Layer3Address1Register4 = 0x9D4, // MAC_Layer3_Addr1_Reg4 276 Layer3Address2Register4 = 0x9D8, // MAC_Layer3_Addr2_Reg4 277 Layer3Address3Register4 = 0x9DC, // MAC_Layer3_Addr3_Reg4 278 279 Layer3Layer4Control5 = 0x9F0, // MAC_L3_L4_Control5 280 Layer4Address5 = 0x9F4, // MAC_Layer4_Address5 281 Layer3Address0Register5 = 0xA00, // MAC_Layer3_Addr0_Reg5 282 Layer3Address1Register5 = 0xA04, // MAC_Layer3_Addr1_Reg5 283 Layer3Address2Register5 = 0xA08, // MAC_Layer3_Addr2_Reg5 284 Layer3Address3Register5 = 0xA0C, // MAC_Layer3_Addr3_Reg5 285 286 Layer3Layer4Control6 = 0xA20, // MAC_L3_L4_Control6 287 Layer4Address6 = 0xA24, // MAC_Layer4_Address6 288 Layer3Address0Register6 = 0xA30, // MAC_Layer3_Addr0_Reg6 289 Layer3Address1Register6 = 0xA34, // MAC_Layer3_Addr1_Reg6 290 Layer3Address2Register6 = 0xA38, // MAC_Layer3_Addr2_Reg6 291 Layer3Address3Register6 = 0xA3C, // MAC_Layer3_Addr3_Reg6 292 293 Layer3Layer4Control7 = 0xA50, // MAC_L3_L4_Control7 294 Layer4Address7 = 0xA54, // MAC_Layer4_Address7 295 Layer3Address0Register7 = 0xA60, // MAC_Layer3_Addr0_Reg7 296 Layer3Address1Register7 = 0xA64, // MAC_Layer3_Addr1_Reg7 297 Layer3Address2Register7 = 0xA68, // MAC_Layer3_Addr2_Reg7 298 Layer3Address3Register7 = 0xA6C, // MAC_Layer3_Addr3_Reg7 299 300 IndirectAccessControl = 0xA70, // MAC_Indir_Access_Ctrl 301 IndirectAccessData = 0xA74, // MAC_Indir_Access_Data 302 303 TypeMatchReceiveQueueRegister0 = 0xA74, // MAC_TMRQ_Regs0 304 TypeMatchReceiveQueueRegister1 = 0xA74, // MAC_TMRQ_Regs1 305 TypeMatchReceiveQueueRegister2 = 0xA74, // MAC_TMRQ_Regs2 306 TypeMatchReceiveQueueRegister3 = 0xA74, // MAC_TMRQ_Regs3 307 TypeMatchReceiveQueueRegister4 = 0xA74, // MAC_TMRQ_Regs4 308 TypeMatchReceiveQueueRegister5 = 0xA74, // MAC_TMRQ_Regs5 309 TypeMatchReceiveQueueRegister6 = 0xA74, // MAC_TMRQ_Regs6 310 TypeMatchReceiveQueueRegister7 = 0xA74, // MAC_TMRQ_Regs7 311 312 TimestampControl = 0xB00, // MAC_Timestamp_Control 313 SubSecondIncrement = 0xB04, // MAC_Sub_Second_Increment 314 SystemTimeSeconds = 0xB08, // MAC_System_Time_Seconds 315 SystemTimeNanoseconds = 0xB0C, // MAC_System_Time_Nanoseconds 316 SystemTimeSecondsUpdate = 0xB10, // MAC_System_Time_Seconds_Update 317 SystemTimeNanosecondsUpdate = 0xB14, // MAC_System_Time_Nanoseconds_Update 318 TimestampAddend = 0xB18, // MAC_Timestamp_Addend 319 SystemTimeHigherWordSeconds = 0xB1C, // MAC_System_Time_Higher_Word_Seconds 320 TimestampStatus = 0xB20, // MAC_Timestamp_Status 321 TransmitTimestampStatusNanoseconds = 0xB30, // MAC_Tx_Timestamp_Status_Nanoseconds 322 TransmitTimestampStatusSeconds = 0xB34, // MAC_Tx_Timestamp_Status_Seconds 323 TimestampIngressAsymmetryCorrection = 0xB50, // MAC_Timestamp_Ingress_Asym_Corr 324 TimestampEgressAsymmetryCorrection = 0xB54, // MAC_Timestamp_Egress_Asym_Corr 325 TimestampIngressCorrectionNanosecond = 0xB58, // MAC_Timestamp_Ingress_Corr_Nanosecond 326 TimestampEgressCorrectionNanosecond = 0xB5C, // MAC_Timestamp_Egress_Corr_Nanosecond 327 TimestampIngressCorrectionSubnanosecond = 0xB60, // MAC_Timestamp_Ingress_Corr_Subnanosec 328 TimestampEgressCorrectionSubnanosecond = 0xB64, // MAC_Timestamp_Egress_Corr_Subnanosec 329 TimestampIngressLatency = 0xB68, // MAC_Timestamp_Ingress_Latency 330 TimestampEgressLatency = 0xB6C, // MAC_Timestamp_Egress_Latency 331 332 PPSControl = 0xB70, // MAC_PPS_Control 333 PPS0TargetTimeSeconds = 0xB80, // MAC_PPS0_Target_Time_Seconds 334 PPS0TargetTimeNanoseconds = 0xB84, // MAC_PPS0_Target_Time_Nanoseconds 335 PPS0Interval = 0xB88, // MAC_PPS0_Interval 336 PPS0Width = 0xB8C, // MAC_PPS0_Width 337 PPS1TargetTimeSeconds = 0xB90, // MAC_PPS1_Target_Time_Seconds 338 PPS1TargetTimeNanoseconds = 0xB94, // MAC_PPS1_Target_Time_Nanoseconds 339 PPS1Interval = 0xB98, // MAC_PPS1_Interval 340 PPS1Width = 0xB9C, // MAC_PPS1_Width 341 PPS2TargetTimeSeconds = 0xBA0, // MAC_PPS2_Target_Time_Seconds 342 PPS2TargetTimeNanoseconds = 0xBA4, // MAC_PPS2_Target_Time_Nanoseconds 343 PPS2Interval = 0xBA8, // MAC_PPS2_Interval 344 PPS2Width = 0xBAC, // MAC_PPS2_Width 345 PPS3TargetTimeSeconds = 0xBB0, // MAC_PPS3_Target_Time_Seconds 346 PPS3TargetTimeNanoseconds = 0xBB4, // MAC_PPS3_Target_Time_Nanoseconds 347 PPS3Interval = 0xBB8, // MAC_PPS3_Interval 348 PPS3Width = 0xBBC, // MAC_PPS3_Width 349 350 MTLOperationMode = 0xC00, // MTL_Operation_Mode 351 MTLDebugControl = 0xC08, // MTL_DBG_CTL 352 MTLDebugStatus = 0xC0C, // MTL_DBG_STS 353 MTLFIFODebugData = 0xC10, // MTL_FIFO_Debug_Data 354 MTLInterruptStatus = 0xC20, // MTL_Interrupt_Status 355 MTLReceiveQueueDMAMap0 = 0xC30, // MTL_RxQ_DMA_Map0 356 MTLTimeBasedSchedulingControl = 0xC40, // MTL_TBS_CTRL 357 MTLEnhancementsToScheduledTransmissionControl = 0xC50, // MTL_EST_Control 358 MTLEnhancementsToScheduledTransmissionExtendedControl = 0xC54, // MTL_EST_Ext_Control 359 MTLEnhancementsToScheduledTransmissionStatus = 0xC58, // MTL_EST_Status 360 MTLEnhancementsToScheduledTransmissionSchedulingError = 0xC60, // MTL_EST_Sch_Error 361 MTLEnhancementsToScheduledTransmissionFrameSizeError = 0xC64, // MTL_EST_Frm_Size_Error 362 MTLEnhancementsToScheduledTransmissionInterruptEnable = 0xC70, // MTL_EST_Intr_Enable 363 MTLEnhancementsToScheduledTransmissionGateControlList = 0xC80, // MTL_EST_GCL_Control 364 MTLEnhancementsToScheduledTransmissionGateControlData = 0xC84, // MTL_EST_GCL_Data 365 MTLFramePreemptionControlStatus = 0xC90, // MTL_FPE_CTRL_STS 366 MTLFramePreemptionAdvanceTime = 0xC94, // MTL_FPE_Advance 367 MTLReceiveParserControlStatus = 0xCA0, // MTL_RXP_Control_Status 368 MTLReceiveParserInterruptControlStatus = 0xCA4, // MTL_RXP_Interrupt_Control_Status 369 MTLReceiveParserDropCount = 0xCA8, // MTL_RXP_Drop_Cnt 370 MTLReceiveParserErrorCount = 0xCAC, // MTL_RXP_Error_Cnt 371 MTLReceiveParserIndirectAccessControlStatus = 0xCB0, // MTL_RXP_Indirect_Acc_Control_Status 372 MTLReceiveParserIndirectAccessData = 0xCB4, // MTL_RXP_Indirect_Acc_Data 373 MTLReceiveParserBypassCount = 0xCB8, // MTL_RXP_Bypass_Cnt 374 MTLErrorCorrectionControl = 0xCC0, // MTL_ECC_Control 375 MTLSafetyInterruptStatus = 0xCC4, // MTL_Safety_Interrupt_Status 376 MTLErrorCorrectionInterruptEnable = 0xCC8, // MTL_ECC_Interrupt_Enable 377 MTLErrorCorrectionInterruptStatus = 0xCCC, // MTL_ECC_Interrupt_Status 378 MTLErrorCorrectionErrorStatusCapture = 0xCD0, // MTL_ECC_Err_Sts_Rctl 379 MTLErrorCorrectionErrorAddressStatus = 0xCD4, // MTL_ECC_Err_Addr_Status 380 MTLErrorCorrectionErrorCountStatus = 0xCD8, // MTL_ECC_Err_Cntr_Status 381 MTLDataParityProtectionControl = 0xCE0, // MTL_DPP_Control 382 MTLDataParityProtectionErrorCorrectionErrorInjection = 0xCE4, // MTL_DPP_ECC_EIC 383 MTLTransmitQueue0OperationMode = 0xD00, // MTL_TxQ0_Operation_Mode 384 MTLTransmitQueue0Underflow = 0xD04, // MTL_TxQ0_Underflow 385 MTLTransmitQueue0Debug = 0xD08, // MTL_TxQ0_Debug 386 MTLTransmitQueue0ETSStatus = 0xD14, // MTL_TxQ0_ETS_Status 387 MTLTransmitQueue0QuantumWeight = 0xD18, // MTL_TxQ0_Quantum_Weight 388 MTLQueue0InterruptControlStatus = 0xD2C, // MTL_Q0_Interrupt_Control_Status 389 MTLReceiveQueue0OperationMode = 0xD30, // MTL_RxQ0_Operation_Mode 390 MTLReceiveQueue0MissedPacketOverflowCount = 0xD34, // MTL_RxQ0_Missed_Packet_Overflow_Cnt 391 MTLReceiveQueue0Debug = 0xD38, // MTL_RxQ0_Debug 392 MTLReceiveQueue0Control = 0xD3C, // MTL_RxQ0_Control 393 MTLTransmitQueue1OperationMode = 0xD40, // MTL_TxQ1_Operation_Mode 394 MTLTransmitQueue1Underflow = 0xD44, // MTL_TxQ1_Underflow 395 MTLTransmitQueue1Debug = 0xD48, // MTL_TxQ1_Debug 396 MTLTransmitQueue1ETSControl = 0xD50, // MTL_TxQ1_ETS_Control 397 MTLTransmitQueue1ETSStatus = 0xD54, // MTL_TxQ1_ETS_Status 398 MTLTransmitQueue1QuantumWeight = 0xD58, // MTL_TxQ1_Quantum_Weight 399 MTLTransmitQueue1SendSlopeCredit = 0xD5C, // MTL_TxQ1_SendSlopeCredit 400 MTLTransmitQueue1HighCredit = 0xD60, // MTL_TxQ1_HiCredit 401 MTLTransmitQueue1LowCredit = 0xD64, // MTL_TxQ1_LoCredit 402 MTLQueue1InterruptControlStatus = 0xD6C, // MTL_Q1_Interrupt_Control_Status 403 MTLReceiveQueue1OperationMode = 0xD70, // MTL_RxQ1_Operation_Mode 404 MTLReceiveQueue1MissedPacketOverflowCount = 0xD74, // MTL_RxQ1_Missed_Packet_Overflow_Cnt 405 MTLReceiveQueue1Debug = 0xD78, // MTL_RxQ1_Debug 406 MTLReceiveQueue1Control = 0xD7C, // MTL_RxQ1_Control 407 MTLTransmitQueue2OperationMode = 0xD80, // MTL_TxQ2_Operation_Mode 408 MTLTransmitQueue2Underflow = 0xD84, // MTL_TxQ2_Underflow 409 MTLTransmitQueue2Debug = 0xD88, // MTL_TxQ2_Debug 410 MTLTransmitQueue2ETSControl = 0xD90, // MTL_TxQ2_ETS_Control 411 MTLTransmitQueue2ETSStatus = 0xD94, // MTL_TxQ2_ETS_Status 412 MTLTransmitQueue2QuantumWeight = 0xD98, // MTL_TxQ2_Quantum_Weight 413 MTLTransmitQueue2SendSlopeCredit = 0xD9C, // MTL_TxQ2_SendSlopeCredit 414 MTLTransmitQueue2HighCredit = 0xDA0, // MTL_TxQ2_HiCredit 415 MTLTransmitQueue2LowCredit = 0xDA4, // MTL_TxQ2_LoCredit 416 MTLQueue2InterruptControlStatus = 0xDAC, // MTL_Q2_Interrupt_Control_Status 417 MTLReceiveQueue2OperationMode = 0xDB0, // MTL_RxQ2_Operation_Mode 418 MTLReceiveQueue2MissedPacketOverflowCount = 0xDB4, // MTL_RxQ2_Missed_Packet_Overflow_Cnt 419 MTLReceiveQueue2Debug = 0xDB8, // MTL_RxQ2_Debug 420 MTLReceiveQueue2Control = 0xDBC, // MTL_RxQ2_Control 421 422 DMAMode = 0x1000, // DMA_Mode 423 DMASystemBusMode = 0x1004, // DMA_SysBus_Mode 424 DMAInterruptStatus = 0x1008, // DMA_Interrupt_Status 425 DMADebugStatus0 = 0x100C, // DMA_Debug_Status0 426 DMATBSControl0 = 0x1050, // DMA_TBS_CTRL0 427 DMATBSControl1 = 0x1054, // DMA_TBS_CTRL1 428 DMATBSControl2 = 0x1058, // DMA_TBS_CTRL2 429 DMATBSControl3 = 0x105C, // DMA_TBS_CTRL3 430 DMASafetyInterruptStatus = 0x1080, // DMA_Safety_Interrupt_Status 431 432 DMAChannel0Control = 0x1100, // DMA_CH0_Control 433 DMAChannel0TransmitControl = 0x1104, // DMA_CH0_Tx_Control 434 DMAChannel0ReceiveControl = 0x1108, // DMA_CH0_Rx_Control 435 DMAChannel0TransmitDescriptorListAddress = 0x1114, // DMA_CH0_TxDesc_List_Address 436 DMAChannel0ReceiveDescriptorListAddress = 0x111C, // DMA_CH0_RxDesc_List_Address 437 DMAChannel0TransmitDescriptorTailPointer = 0x1120, // DMA_CH0_TxDesc_Tail_Pointer 438 DMAChannel0ReceiveDescriptorTailPointer = 0x1128, // DMA_CH0_RxDesc_Tail_Pointer 439 DMAChannel0TransmitDescriptorRingLength = 0x112C, // DMA_CH0_TxDesc_Ring_Length 440 DMAChannel0ReceiveControl2 = 0x1130, // DMA_CH0_Rx_Control2 441 DMAChannel0InterruptEnable = 0x1134, // DMA_CH0_Interrupt_Enable 442 DMAChannel0ReceiveInterruptWatchdogTimer = 0x1138, // DMA_CH0_Rx_Interrupt_Watchdog_Timer 443 DMAChannel0SlotFunctionControlStatus = 0x113C, // DMA_CH0_Slot_Function_Control_Status 444 DMAChannel0CurrentApplicationTransmitDescriptor = 0x1144, // DMA_CH0_Current_App_TxDesc 445 DMAChannel0CurrentApplicationReceiveDescriptor = 0x114C, // DMA_CH0_Current_App_RxDesc 446 DMAChannel0CurrentApplicationTransmitBuffer = 0x1154, // DMA_CH0_Current_App_TxBuffer 447 DMAChannel0CurrentApplicationReceiveBuffer = 0x115C, // DMA_CH0_Current_App_RxBuffer 448 DMAChannel0Status = 0x1160, // DMA_CH0_Status 449 DMAChannel0MissedFrameCount = 0x1164, // DMA_CH0_Miss_Frame_Cnt 450 DMAChannel0ReceiveParserAcceptCount = 0x1168, // DMA_CH0_RXP_Accept_Cnt 451 DMAChannel0ReceiveERICount = 0x116C, // DMA_CH0_RX_ERI_Cnt 452 453 DMAChannel1Control = 0x1180, // DMA_CH1_Control 454 DMAChannel1TransmitControl = 0x1184, // DMA_CH1_Tx_Control 455 DMAChannel1ReceiveControl = 0x1188, // DMA_CH1_Rx_Control 456 DMAChannel1TransmitDescriptorListAddress = 0x1194, // DMA_CH1_TxDesc_List_Address 457 DMAChannel1ReceiveDescriptorListAddress = 0x119C, // DMA_CH1_RxDesc_List_Address 458 DMAChannel1TransmitDescriptorTailPointer = 0x11A0, // DMA_CH1_TxDesc_Tail_Pointer 459 DMAChannel1ReceiveDescriptorTailPointer = 0x11A8, // DMA_CH1_RxDesc_Tail_Pointer 460 DMAChannel1TransmitDescriptorRingLength = 0x11AC, // DMA_CH1_TxDesc_Ring_Length 461 DMAChannel1ReceiveControl2 = 0x11B0, // DMA_CH1_Rx_Control2 462 DMAChannel1InterruptEnable = 0x11B4, // DMA_CH1_Interrupt_Enable 463 DMAChannel1ReceiveInterruptWatchdogTimer = 0x11B8, // DMA_CH1_Rx_Interrupt_Watchdog_Timer 464 DMAChannel1SlotFunctionControlStatus = 0x11BC, // DMA_CH1_Slot_Function_Control_Status 465 DMAChannel1CurrentApplicationTransmitDescriptor = 0x11C4, // DMA_CH1_Current_App_TxDesc 466 DMAChannel1CurrentApplicationReceiveDescriptor = 0x11CC, // DMA_CH1_Current_App_RxDesc 467 DMAChannel1CurrentApplicationTransmitBuffer = 0x11D4, // DMA_CH1_Current_App_TxBuffer 468 DMAChannel1CurrentApplicationReceiveBuffer = 0x11DC, // DMA_CH1_Current_App_RxBuffer 469 DMAChannel1Status = 0x11E0, // DMA_CH1_Status 470 DMAChannel1MissedFrameCount = 0x11E4, // DMA_CH1_Miss_Frame_Cnt 471 DMAChannel1ReceiveParserAcceptCount = 0x11E8, // DMA_CH1_RXP_Accept_Cnt 472 DMAChannel1ReceiveERICount = 0x11EC, // DMA_CH1_RX_ERI_Cnt 473 474 DMAChannel2Control = 0x1200, // DMA_CH2_Control 475 DMAChannel2TransmitControl = 0x1204, // DMA_CH2_Tx_Control 476 DMAChannel2ReceiveControl = 0x1208, // DMA_CH2_Rx_Control 477 DMAChannel2TransmitDescriptorListAddress = 0x1214, // DMA_CH2_TxDesc_List_Address 478 DMAChannel2ReceiveDescriptorListAddress = 0x1218, // DMA_CH2_RxDesc_List_Address 479 DMAChannel2TransmitDescriptorTailPointer = 0x1220, // DMA_CH2_TxDesc_Tail_Pointer 480 DMAChannel2ReceiveDescriptorTailPointer = 0x1228, // DMA_CH2_RxDesc_Tail_Pointer 481 DMAChannel2TransmitDescriptorRingLength = 0x122C, // DMA_CH2_TxDesc_Ring_Length 482 DMAChannel2ReceiveControl2 = 0x1230, // DMA_CH2_Rx_Control2 483 DMAChannel2InterruptEnable = 0x1234, // DMA_CH2_Interrupt_Enable 484 DMAChannel2ReceiveInterruptWatchdogTimer = 0x1238, // DMA_CH2_Rx_Interrupt_Watchdog_Timer 485 DMAChannel2SlotFunctionControlStatus = 0x123C, // DMA_CH2_Slot_Function_Control_Status 486 DMAChannel2CurrentApplicationTransmitDescriptor = 0x1244, // DMA_CH2_Current_App_TxDesc 487 DMAChannel2CurrentApplicationReceiveDescriptor = 0x124C, // DMA_CH2_Current_App_RxDesc 488 DMAChannel2CurrentApplicationTransmitBuffer = 0x1254, // DMA_CH2_Current_App_TxBuffer 489 DMAChannel2CurrentApplicationReceiveBuffer = 0x125C, // DMA_CH2_Current_App_RxBuffer 490 DMAChannel2Status = 0x1260, // DMA_CH2_Status 491 DMAChannel2MissedFrameCount = 0x1264, // DMA_CH2_Miss_Frame_Cnt 492 DMAChannel2ReceiveParserAcceptCount = 0x1268, // DMA_CH2_RXP_Accept_Cnt 493 DMAChannel2ReceiveERICount = 0x126C, // DMA_CH2_RX_ERI_Cnt 494 } 495 } 496 } 497
