1 // 2 // Copyright (c) 2010-2023 Antmicro 3 // 4 // This file is licensed under the MIT License. 5 // Full license text is available in 'licenses/MIT.txt'. 6 // 7 using System; 8 using System.Collections.Generic; 9 using System.Linq; 10 using Antmicro.Renode.Core; 11 using Antmicro.Renode.Core.Structure; 12 using Antmicro.Renode.Core.Structure.Registers; 13 using Antmicro.Renode.Logging; 14 using Antmicro.Renode.Peripherals.Bus; 15 using Antmicro.Renode.Utilities; 16 17 using Range = Antmicro.Renode.Core.Range; 18 19 namespace Antmicro.Renode.Peripherals.PCI 20 { 21 [AllowedTranslations(AllowedTranslation.ByteToDoubleWord | AllowedTranslation.WordToDoubleWord)] 22 public class MPFS_PCIe : SimpleContainer<IPCIePeripheral>, IDoubleWordPeripheral, IKnownSize, IPCIeRouter, IAbsoluteAddressAware 23 { MPFS_PCIe(IMachine machine)24 public MPFS_PCIe(IMachine machine) : base(machine) 25 { 26 var registersDictionary = new Dictionary<long, DoubleWordRegister> 27 { 28 //this register is not documented. It seems it contains the enabled flag, it may contain the port type, number of lanes, lane rate etc 29 {(long)Registers.GEN_SETTINGS, new DoubleWordRegister(this) 30 .WithFlag(0, FieldMode.Read, valueProviderCallback: _ => true, name: "ROOT_PORT_ENABLE") 31 }, 32 {(long)Registers.ECC_CONTROL, new DoubleWordRegister(this) 33 .WithTag("TX_RAM_INJ_ERR", 0, 4) 34 .WithTag("RX_RAM_INJ_ERR", 4, 4) 35 .WithTag("PCIe2AXI_RAM_INJ_ERR", 8, 4) 36 .WithTag("AXI2PCIe_RAM_INJ_ERR", 12, 4) 37 .WithReservedBits(16, 8) 38 .WithTag("TX_RAM_ECC_BYPASS", 24, 1) 39 .WithTag("RX_RAM_ECC_BYPASS", 25, 1) 40 .WithTag("PCIe2AXI_RAM_ECC_BYPASS", 26, 1) 41 .WithTag("AXI2PCIe_RAM_ECC_BYPASS", 27, 1) 42 .WithReservedBits(28, 4) 43 }, 44 //most likely w1c, unclear from the docs 45 {(long)Registers.PCIE_EVENT_INT, new DoubleWordRegister(this) 46 .WithTag("L2_EXIT_INT", 0, 1) 47 .WithTag("HOTRST_EXIT_INT", 1, 1) 48 .WithTag("DLUP_EXIT_INT", 2, 1) 49 .WithReservedBits(3, 13) 50 .WithTag("L2_EXIT_INT_MASK", 16, 1) 51 .WithTag("HOTRST_EXIT_INT_MASK", 17, 1) 52 .WithTag("DLUP_EXIT_INT_MASK", 18, 1) 53 .WithReservedBits(19, 13) 54 }, 55 //correctable ecc-related memory errors, probably w1c 56 {(long)Registers.SEC_ERROR_INT, new DoubleWordRegister(this) 57 .WithTag("TX_RAM_SEC_ERR_INT", 0, 4) 58 .WithTag("RX_RAM_SEC_ERR_INT", 4, 4) 59 .WithTag("PCIE2AXI_RAM_SEC_ERR_INT", 8, 4) 60 .WithTag("AXI2PCIE_RAM_SEC_ERR_INT", 12, 4) 61 .WithReservedBits(16, 16) 62 }, 63 //uncorrectable ecc-related memory errors, probably w1c 64 {(long)Registers.DED_ERROR_INT, new DoubleWordRegister(this) 65 .WithTag("TX_RAM_DED_ERR_INT", 0, 4) 66 .WithTag("RX_RAM_DED_ERR_INT", 4, 4) 67 .WithTag("PCIE2AXI_RAM_DED_ERR_INT", 8, 4) 68 .WithTag("AXI2PCIE_RAM_DED_ERR_INT", 12, 4) 69 .WithReservedBits(16, 16) 70 }, 71 //this is the "standard" interrupt mask register, 1 to enable interrupt source 72 {(long)Registers.IMASK_LOCAL, new DoubleWordRegister(this) 73 .WithTag("IMASK_DMA_END_ENGINE_0", 0, 1) 74 .WithTag("IMASK_DMA_END_ENGINE_1", 1, 1) 75 .WithReservedBits(2, 6) 76 .WithTag("IMASK_DMA_ERROR_ENGINE_0", 8, 1) 77 .WithTag("IMASK_DMA_ERROR_ENGINE_1", 9, 1) 78 .WithReservedBits(10, 6) 79 .WithTag("IMASK_A_ATR_EVT_POST_ERR", 16, 1) 80 .WithTag("IMASK_A_ATR_EVT_FETCH_ERR", 17, 1) 81 .WithTag("IMASK_A_ATR_EVT_DISCARD_ERR", 18, 1) 82 .WithTag("IMASK_A_ATR_EVT_DOORBELL", 19, 1) 83 .WithTag("IMASK_P_ATR_EVT_POST_ERR", 20, 1) 84 .WithTag("IMASK_P_ATR_EVT_FETCH_ERR", 21, 1) 85 .WithTag("IMASK_P_ATR_EVT_DISCARD_ERR", 22, 1) 86 .WithTag("IMASK_P_ATR_EVT_DOORBELL", 23, 1) 87 .WithTag("IMASK_PM_MSI_INT_INTA", 24, 1) 88 .WithTag("IMASK_PM_MSI_INT_INTB", 25, 1) 89 .WithTag("IMASK_PM_MSI_INT_INTC", 26, 1) 90 .WithTag("IMASK_PM_MSI_INT_INTD", 27, 1) 91 .WithTag("IMASK_PM_MSI_INT_MSI", 28, 1) 92 .WithTag("IMASK_PM_MSI_INT_AER_EVT", 29, 1) 93 .WithTag("IMASK_PM_MSI_INT_EVENTS", 30, 1) 94 .WithTag("IMASK_PM_MSI_INT_SYS_ERR", 31, 1) 95 }, 96 //this is the "standard" interrupt status register, w1c 97 {(long)Registers.ISTATUS_LOCAL, new DoubleWordRegister(this) 98 .WithTag("DMA_END_ENGINE_0", 0, 1) 99 .WithTag("DMA_END_ENGINE_1", 1, 1) 100 .WithReservedBits(2, 6) 101 .WithTag("DMA_ERROR_ENGINE_0", 8, 1) 102 .WithTag("DMA_ERROR_ENGINE_1", 9, 1) 103 .WithReservedBits(10, 6) 104 .WithTag("A_ATR_EVT_POST_ERR", 16, 1) 105 .WithTag("A_ATR_EVT_FETCH_ERR", 17, 1) 106 .WithTag("A_ATR_EVT_DISCARD_ERR", 18, 1) 107 .WithTag("A_ATR_EVT_DOORBELL", 19, 1) 108 .WithTag("P_ATR_EVT_POST_ERR", 20, 1) 109 .WithTag("P_ATR_EVT_FETCH_ERR", 21, 1) 110 .WithTag("P_ATR_EVT_DISCARD_ERR", 22, 1) 111 .WithTag("P_ATR_EVT_DOORBELL", 23, 1) 112 .WithTag("PM_MSI_INT_INTA", 24, 1) 113 .WithTag("PM_MSI_INT_INTB", 25, 1) 114 .WithTag("PM_MSI_INT_INTC", 26, 1) 115 .WithTag("PM_MSI_INT_INTD", 27, 1) 116 .WithTag("PM_MSI_INT_MSI", 28, 1) 117 .WithTag("PM_MSI_INT_AER_EVT", 29, 1) 118 .WithTag("PM_MSI_INT_EVENTS", 30, 1) 119 .WithTag("PM_MSI_INT_SYS_ERR", 31, 1) 120 }, 121 //this should reflect bits in ISTATUS_HOST, but it's described as a one field 122 {(long)Registers.IMASK_HOST, new DoubleWordRegister(this) 123 .WithTag("INT_MASK_HOST", 0, 32) 124 }, 125 //this should reflect bits in ISTATUS_LOCAL. The docs say that the host processor monitors and clears these bits (w1c), but the software writes it anyway) 126 {(long)Registers.ISTATUS_HOST, new DoubleWordRegister(this) 127 .WithTag("DMA_END", 0, 8) 128 .WithTag("DMA_ERROR", 8, 2) 129 .WithTag("A_ATR_EVT", 10, 10) 130 .WithTag("P_ATR_EVT", 20, 4) 131 .WithTag("INT_REQUEST", 24, 8) 132 }, 133 }; 134 for(var i = 0; i < NumberOfTranslationTables; i++) 135 { 136 pcieAddressTables[i] = new AddressTranslationTable(this); 137 axiAddressTables[i] = new AddressTranslationTable(this); 138 CreateAddressTranslationRegisters(registersDictionary, i, true); 139 CreateAddressTranslationRegisters(registersDictionary, i, false); 140 } 141 registers = new DoubleWordRegisterCollection(this, registersDictionary); 142 } 143 ReadDoubleWord(long offset)144 public uint ReadDoubleWord(long offset) 145 { 146 return registers.Read(offset); 147 } 148 WriteDoubleWord(long offset, uint value)149 public void WriteDoubleWord(long offset, uint value) 150 { 151 registers.Write(offset, value); 152 } 153 154 [ConnectionRegion("ecam")] WriteDoubleWordEcam(long offset, uint value)155 public void WriteDoubleWordEcam(long offset, uint value) 156 { 157 158 var table = axiAddressTables.SingleOrDefault(x => x.DoesAddressHit(currentAccessAbsoluteAddress)); 159 if(table == null) 160 { 161 this.Log(LogLevel.Warning, "Trying to access memory at 0x{0:X} writing 0x{1:X} without address translation configured.", currentAccessAbsoluteAddress, value); 162 this.LogUnhandledWrite(offset, value); 163 return; 164 } 165 var translatedAddress = table.Translate(currentAccessAbsoluteAddress); 166 if(table.TargetSpace == PCIeSpace.Configuration) 167 { 168 if(!TryDoEcamLookup(offset, out var result)) 169 { 170 this.LogUnhandledWrite(offset, value); 171 return; 172 } 173 result.Endpoint.ConfigurationWriteDoubleWord(result.EcamAddress.Offset, value); 174 } 175 else if(table.TargetSpace == PCIeSpace.TxRx) 176 { 177 var barCandidates = memoryMap.Where(x => x.Key.Contains(translatedAddress)); 178 if(!barCandidates.Any()) 179 { 180 this.Log(LogLevel.Warning, "Trying to write to a BAR at 0x{0:X}, but nothing is registered there, value 0x{1:X}.", translatedAddress, value); 181 return; 182 } 183 //This should not be required, but we need to improve RegisterBar first 184 var targetBarEntry = barCandidates.Single(); 185 targetBarEntry.Value.TargetPeripheral.MemoryWriteDoubleWord(targetBarEntry.Value.BarNumber, (long)(translatedAddress - targetBarEntry.Key.StartAddress), value); 186 } 187 else 188 { 189 this.Log(LogLevel.Warning, "Trying to write to the PCIe space at 0x{0:X} in an unsupported mode {1}, value 0x{2:X}.", offset, table.TargetSpace, value); 190 return; 191 } 192 } 193 194 [ConnectionRegion("ecam")] ReadDoubleWordEcam(long offset)195 public uint ReadDoubleWordEcam(long offset) 196 { 197 var table = axiAddressTables.SingleOrDefault(x => x.DoesAddressHit(currentAccessAbsoluteAddress)); 198 if(table == null) 199 { 200 this.Log(LogLevel.Warning, "Trying to access memory at 0x{0:X} without address translation configured.", currentAccessAbsoluteAddress); 201 this.LogUnhandledRead(offset); 202 return 0; 203 } 204 var translatedAddress = table.Translate(currentAccessAbsoluteAddress); 205 if(table.TargetSpace == PCIeSpace.Configuration) 206 { 207 if(!TryDoEcamLookup(offset, out var result)) 208 { 209 this.LogUnhandledRead(offset); 210 return FunctionNotImplemented; 211 } 212 return result.Endpoint.ConfigurationReadDoubleWord(result.EcamAddress.Offset); 213 } 214 else if(table.TargetSpace == PCIeSpace.TxRx) 215 { 216 var barCandidates = memoryMap.Where(x => x.Key.Contains(translatedAddress)); 217 if(!barCandidates.Any()) 218 { 219 this.Log(LogLevel.Warning, "Trying to read from a BAR at 0x{0:X}, but nothing is registered there.", translatedAddress); 220 return 0; 221 } 222 //This should not be required, but we need to improve RegisterBar first 223 var targetBarEntry = barCandidates.Single(); 224 return targetBarEntry.Value.TargetPeripheral.MemoryReadDoubleWord(targetBarEntry.Value.BarNumber, (long)(translatedAddress - targetBarEntry.Key.StartAddress)); 225 } 226 else 227 { 228 this.Log(LogLevel.Warning, "Trying to read from the PCIe space at 0x{0:X} in an unsupported mode {1}.", offset, table.TargetSpace); 229 return 0; 230 } 231 } 232 Reset()233 public override void Reset() 234 { 235 registers.Reset(); 236 } 237 SetAbsoluteAddress(ulong address)238 public void SetAbsoluteAddress(ulong address) 239 { 240 currentAccessAbsoluteAddress = address & ~3ul; 241 } 242 243 public long Size => 0x4000; 244 TryDoEcamLookup(long offset, out EcamLookupResult result)245 private bool TryDoEcamLookup(long offset, out EcamLookupResult result) 246 { 247 result = new EcamLookupResult(); 248 result.EcamAddress = new EcamAddress((uint)offset); // the case is safe as we are interested in lower 28 bits 249 return result.EcamAddress.Device == 0 && TryGetByAddress(result.EcamAddress.Bus, out result.Endpoint); // this works if we have a flat structure only! 250 } 251 CreateAddressTranslationRegisters(Dictionary<long, DoubleWordRegister> registers, int tableNumber, bool isPcieTable)252 private void CreateAddressTranslationRegisters(Dictionary<long, DoubleWordRegister> registers, int tableNumber, bool isPcieTable) 253 { 254 var table = isPcieTable ? pcieAddressTables[tableNumber] : axiAddressTables[tableNumber]; 255 var baseOffset = (long)(isPcieTable ? Registers.ATR0_PCIE_WIN0_SRCADDR_PARAM : Registers.ATR0_AXI4_SLV0_SRCADDR_PARAM) 256 + tableNumber * (Registers.ATR1_AXI4_SLV0_SRCADDR_PARAM - Registers.ATR0_AXI4_SLV0_SRCADDR_PARAM); 257 registers.Add(baseOffset + (long)AddressTranslationRegisters.SourceAddressLowAndParameters, new DoubleWordRegister(this) 258 .WithFlag(0, changeCallback: (_, value) => table.Enabled = value, 259 valueProviderCallback: _ => table.Enabled, name: "ATR_IMPL") 260 .WithValueField(1, 6, changeCallback: (_, value) => table.SizePower = (uint)value, 261 valueProviderCallback: _ => table.SizePower, name: "ATR_SIZE") 262 .WithReservedBits(7, 5) 263 .WithValueField(12, 20, changeCallback: (_, value) => BitHelper.UpdateWithShifted(ref table.SourceAddress, value, 12, 20), 264 valueProviderCallback: _ => (uint)BitHelper.GetValue(table.SourceAddress, 12, 20), name: "SRC_ADDR[31:12]") 265 ); 266 registers.Add(baseOffset + (long)AddressTranslationRegisters.SourceAddressHigh, new DoubleWordRegister(this) 267 .WithValueField(0, 32, changeCallback: (_, value) => BitHelper.UpdateWithShifted(ref table.SourceAddress, value, 32, 32), 268 valueProviderCallback: _ => (uint)BitHelper.GetValue(table.SourceAddress, 32, 32), name: "SRC_ADDR[63:32]") 269 ); 270 registers.Add(baseOffset + (long)AddressTranslationRegisters.DestinationAddressLow, new DoubleWordRegister(this) 271 .WithReservedBits(0, 12) 272 .WithValueField(12, 20, changeCallback: (_, value) => BitHelper.UpdateWithShifted(ref table.DestinationAddress, value, 12, 20), 273 valueProviderCallback: _ => (uint)BitHelper.GetValue(table.DestinationAddress, 12, 20), name: "TRSL_ADDR_LSB") 274 ); 275 registers.Add(baseOffset + (long)AddressTranslationRegisters.DestinationAddressHigh, new DoubleWordRegister(this) 276 .WithValueField(0, 32, changeCallback: (_, value) => BitHelper.UpdateWithShifted(ref table.SourceAddress, value, 32, 32), 277 valueProviderCallback: _ => (uint)BitHelper.GetValue(table.SourceAddress, 32, 32), name: "TRSL_ADDR_UDW") 278 ); 279 registers.Add(baseOffset + (long)AddressTranslationRegisters.TranslationParametersLow, new DoubleWordRegister(this) 280 .WithEnumField(0, 4, changeCallback: (_, value) => table.TargetSpace = value, 281 valueProviderCallback: (PCIeSpace _) => table.TargetSpace, name: "TRSL_ID") 282 .WithReservedBits(4, 12) 283 .WithTag("TRSF_PARAM", 16, 12) 284 .WithReservedBits(28, 4) 285 ); 286 registers.Add(baseOffset + (long)AddressTranslationRegisters.TranslationMaskLow, new DoubleWordRegister(this) 287 .WithValueField(0, 32, valueProviderCallback: _ => (uint)BitHelper.GetValue(table.TranslationMask, 0, 32), name: "TRSL_MASK") 288 ); 289 registers.Add(baseOffset + (long)AddressTranslationRegisters.TranslationMaskHigh, new DoubleWordRegister(this) 290 .WithValueField(0, 32, valueProviderCallback: _ => (uint)BitHelper.GetValue(table .TranslationMask, 32, 32), name: "TRSL_MASK") 291 ); 292 } 293 RegisterBar(Range range, IPCIePeripheral peripheral, uint bar)294 public void RegisterBar(Range range, IPCIePeripheral peripheral, uint bar) 295 { 296 //This has to be improved greatly. 297 //1. have fast search 298 //2. invalidate overlaps 299 var previousRegistration = memoryMap.Where(x => x.Value.BarNumber == bar && x.Value.TargetPeripheral == peripheral).Select(x => x.Key); 300 if(previousRegistration.Any()) 301 { 302 memoryMap.Remove(previousRegistration.SingleOrDefault()); 303 } 304 memoryMap[range] = new TargetBar { BarNumber = bar, TargetPeripheral = peripheral }; 305 } 306 307 private ulong currentAccessAbsoluteAddress; 308 private readonly DoubleWordRegisterCollection registers; 309 310 private readonly AddressTranslationTable[] pcieAddressTables = new AddressTranslationTable[NumberOfTranslationTables]; 311 private readonly AddressTranslationTable[] axiAddressTables = new AddressTranslationTable[NumberOfTranslationTables]; 312 private readonly Dictionary<Range, TargetBar> memoryMap = new Dictionary<Range, TargetBar>(); 313 314 private const int NumberOfTranslationTables = 6; 315 316 private const uint FunctionNotImplemented = 0xFFFF; 317 318 protected struct TargetBar 319 { 320 public IPCIePeripheral TargetPeripheral; 321 public uint BarNumber; 322 } 323 324 private struct EcamLookupResult 325 { 326 public IPCIePeripheral Endpoint; 327 public EcamAddress EcamAddress; 328 } 329 330 private struct EcamAddress 331 { EcamAddressAntmicro.Renode.Peripherals.PCI.MPFS_PCIe.EcamAddress332 public EcamAddress(uint address) : this() 333 { 334 Bus = (int)BitHelper.GetValue(address, 20, 8); 335 Device = (int)BitHelper.GetValue(address, 15, 5); 336 Function = (int)BitHelper.GetValue(address, 12, 3); 337 Offset = BitHelper.GetValue(address, 0, 12); 338 } 339 340 public int Bus; 341 public int Device; 342 public int Function; 343 public uint Offset; 344 } 345 346 private class AddressTranslationTable 347 { AddressTranslationTable(MPFS_PCIe parent)348 public AddressTranslationTable(MPFS_PCIe parent) 349 { 350 this.parent = parent; 351 this.size = MinSize; 352 } 353 Translate(ulong address)354 public ulong Translate(ulong address) 355 { 356 return address - SourceAddress + DestinationAddress; 357 } 358 DoesAddressHit(ulong address)359 public bool DoesAddressHit(ulong address) 360 { 361 return Enabled && address >= SourceAddress && ((address - SourceAddress) & TranslationMask) == 0; 362 } 363 364 public uint SizePower 365 { 366 get 367 { 368 return size; 369 } 370 set 371 { 372 if(value > MaxSize || value < MinSize) 373 { 374 parent.Log(LogLevel.Warning, "Trying to set address translation table size out of bounds: writing {0} when should be between {1} and {2}. Ignoring.", value, MinSize, MaxSize); 375 } 376 size = value; 377 } 378 } 379 380 public bool Enabled; 381 public ulong SourceAddress; 382 public ulong DestinationAddress; 383 384 public PCIeSpace TargetSpace; 385 386 // we handle 63 separately as it would overflow the ulong. The result is correct. 387 public ulong TranslationMask => size == MaxSize ? 0ul : 0ul - (2ul << ((int)SizePower + 1)); 388 389 private uint size; 390 private MPFS_PCIe parent; 391 392 private const int MinSize = 11; 393 private const int MaxSize = 63; 394 } 395 396 private enum AddressTranslationRegisters 397 { 398 SourceAddressLowAndParameters = 0x0, 399 SourceAddressHigh = 0x4, 400 DestinationAddressLow = 0x8, 401 DestinationAddressHigh = 0xC, 402 TranslationParametersLow = 0x10, 403 Reserved = 0x14, 404 TranslationMaskLow = 0x18, 405 TranslationMaskHigh = 0x1C, 406 } 407 408 private enum Registers 409 { 410 /* PCIE Bridge Control Registers */ 411 BRIDGE_VER = 0x0, 412 BRIDGE_BUS = 0x4, 413 BRIDGE_IMPL_IF = 0x8, 414 /* reserved */ 415 PCIE_IF_CONF = 0x10, 416 PCIE_BASIC_CONF = 0x14, 417 PCIE_BASIC_STATUS = 0x18, 418 /* reserved */ 419 AXI_SLVL_CONF = 0x24, 420 /* reserved */ 421 AXI_MST0_CONF = 0x30, 422 AXI_SLV0_CONF = 0x34, 423 /* reserved */ 424 GEN_SETTINGS = 0x80, 425 PCIE_CFGCTRL = 0x84, 426 PCIE_PIPE_DW0 = 0x88, 427 PCIE_PIPE_DW1 = 0x8C, 428 PCIE_VC_CRED_DW0 = 0x90, 429 PCIE_VC_CRED_DW1 = 0x94, 430 PCIE_PCI_IDS_DW0 = 0x98, 431 PCIE_PCI_IDS_DW1 = 0x9C, 432 PCIE_PCI_IDS_DW2 = 0xA0, 433 PCIE_PCI_LPM = 0xA4, 434 PCIE_PCI_IRQ_DW0 = 0xA8, 435 PCIE_PCI_IRQ_DW1 = 0xAC, 436 PCIE_PCI_IRQ_DW2 = 0xB0, 437 PCIE_PCI_IOV_DW0 = 0xB4, 438 PCIE_PCI_IOV_DW1 = 0xB8, 439 /* reserved */ 440 PCIE_PEX_DEV = 0xC0, 441 PCIE_PEX_DEV2 = 0xC4, 442 PCIE_PEX_LINK = 0xC8, 443 PCIE_PEX_SLOT = 0xCC, 444 PCIE_PEX_ROOT_VC = 0xD0, 445 PCIE_PEX_SPC = 0xD4, 446 PCIE_PEX_SPC2 = 0xD8, 447 PCIE_PEX_NFTS = 0xDC, 448 PCIE_PEX_L1SS = 0xE0, 449 PCIE_BAR_01_DW0 = 0xE4, 450 PCIE_BAR_01_DW1 = 0xE8, 451 PCIE_BAR_23_DW0 = 0xEC, 452 PCIE_BAR_23_DW1 = 0xF0, 453 PCIE_BAR_45_DW0 = 0xF4, 454 PCIE_BAR_45_DW1 = 0xF8, 455 PCIE_BAR_WIN = 0xFC, 456 PCIE_EQ_PRESET_DW0 = 0x100, 457 PCIE_EQ_PRESET_DW1 = 0x104, 458 PCIE_EQ_PRESET_DW2 = 0x108, 459 PCIE_EQ_PRESET_DW3 = 0x10C, 460 PCIE_EQ_PRESET_DW4 = 0x110, 461 PCIE_EQ_PRESET_DW5 = 0x114, 462 PCIE_EQ_PRESET_DW6 = 0x118, 463 PCIE_EQ_PRESET_DW7 = 0x11C, 464 PCIE_SRIOV_DW0 = 0x120, 465 PCIE_SRIOV_DW1 = 0x124, 466 PCIE_SRIOV_DW2 = 0x128, 467 PCIE_SRIOV_DW3 = 0x12C, 468 PCIE_SRIOV_DW4 = 0x130, 469 PCIE_SRIOV_DW5 = 0x134, 470 PCIE_SRIOV_DW6 = 0x138, 471 PCIE_SRIOV_DW7 = 0x13C, 472 PCIE_CFGNUM = 0x140, 473 /* reserved */ 474 PM_CONF_DW0 = 0x174, 475 PM_CONF_DW1 = 0x178, 476 PM_CONF_DW2 = 0x17C, 477 IMASK_LOCAL = 0x180, 478 ISTATUS_LOCAL = 0x184, 479 IMASK_HOST = 0x188, 480 ISTATUS_HOST = 0x18C, 481 IMSI_ADDR = 0x190, 482 ISTATUS_MSI = 0x194, 483 ICMD_PM = 0x198, 484 ISTATUS_PM = 0x19C, 485 ATS_PRI_REPORT = 0x1A0, 486 LTR_VALUES = 0x1A4, 487 /* reserved */ 488 ISTATUS_DMA0 = 0x1B0, 489 ISTATUS_DMA1 = 0x1B4, 490 /* reserved */ 491 ISTATUS_P_ADT_WIN0 = 0x1D8, 492 ISTATUS_P_ADT_WIN1 = 0x1DC, 493 ISTATUS_A_ADT_SLV0 = 0x1E0, 494 ISTATUS_A_ADT_SLV1 = 0x1E4, 495 ISTATUS_A_ADT_SLV2 = 0x1E8, 496 ISTATUS_A_ADT_SLV3 = 0x1EC, 497 /* reserved */ 498 ROUTING_RULES_R_DW0 = 0x200, 499 ROUTING_RULES_R_DW1 = 0x204, 500 ROUTING_RULES_R_DW2 = 0x208, 501 ROUTING_RULES_R_DW3 = 0x20C, 502 ROUTING_RULES_R_DW4 = 0x210, 503 ROUTING_RULES_R_DW5 = 0x214, 504 ROUTING_RULES_R_DW6 = 0x218, 505 ROUTING_RULES_R_DW7 = 0x21C, 506 ROUTING_RULES_R_DW8 = 0x220, 507 ROUTING_RULES_R_DW9 = 0x224, 508 ROUTING_RULES_R_DW10 = 0x228, 509 ROUTING_RULES_R_DW11 = 0x22C, 510 ROUTING_RULES_R_DW12 = 0x230, 511 ROUTING_RULES_R_DW13 = 0x234, 512 ROUTING_RULES_R_DW14 = 0x238, 513 ROUTING_RULES_R_DW15 = 0x23C, 514 ROUTING_RULES_W_DW0 = 0x240, 515 ROUTING_RULES_W_DW1 = 0x244, 516 ROUTING_RULES_W_DW2 = 0x248, 517 ROUTING_RULES_W_DW3 = 0x24C, 518 ROUTING_RULES_W_DW4 = 0x250, 519 ROUTING_RULES_W_DW5 = 0x254, 520 ROUTING_RULES_W_DW6 = 0x258, 521 ROUTING_RULES_W_DW7 = 0x25C, 522 ROUTING_RULES_W_DW8 = 0x260, 523 ROUTING_RULES_W_DW9 = 0x264, 524 ROUTING_RULES_W_DW10 = 0x268, 525 ROUTING_RULES_W_DW11 = 0x26C, 526 ROUTING_RULES_W_DW12 = 0x270, 527 ROUTING_RULES_W_DW13 = 0x274, 528 ROUTING_RULES_W_DW14 = 0x278, 529 ROUTING_RULES_W_DW15 = 0x27C, 530 ARBITRATION_RULES_DW0 = 0x280, 531 ARBITRATION_RULES_DW1 = 0x284, 532 ARBITRATION_RULES_DW2 = 0x288, 533 ARBITRATION_RULES_DW3 = 0x28C, 534 ARBITRATION_RULES_DW4 = 0x290, 535 ARBITRATION_RULES_DW5 = 0x294, 536 ARBITRATION_RULES_DW6 = 0x298, 537 ARBITRATION_RULES_DW7 = 0x29C, 538 ARBITRATION_RULES_DW8 = 0x2A0, 539 ARBITRATION_RULES_DW9 = 0x2A4, 540 ARBITRATION_RULES_DW10 = 0x2A8, 541 ARBITRATION_RULES_DW11 = 0x2AC, 542 ARBITRATION_RULES_DW12 = 0x2B0, 543 ARBITRATION_RULES_DW13 = 0x2B4, 544 ARBITRATION_RULES_DW14 = 0x2B8, 545 ARBITRATION_RULES_DW15 = 0x2BC, 546 PRIORITY_RULES_DW0 = 0x2C0, 547 PRIORITY_RULES_DW1 = 0x2C4, 548 PRIORITY_RULES_DW2 = 0x2C8, 549 PRIORITY_RULES_DW3 = 0x2CC, 550 PRIORITY_RULES_DW4 = 0x2D0, 551 PRIORITY_RULES_DW5 = 0x2D4, 552 PRIORITY_RULES_DW6 = 0x2D8, 553 PRIORITY_RULES_DW7 = 0x2DC, 554 PRIORITY_RULES_DW8 = 0x2E0, 555 PRIORITY_RULES_DW9 = 0x2E4, 556 PRIORITY_RULES_DW10 = 0x2E8, 557 PRIORITY_RULES_DW11 = 0x2EC, 558 PRIORITY_RULES_DW12 = 0x2F0, 559 PRIORITY_RULES_DW13 = 0x2F4, 560 PRIORITY_RULES_DW14 = 0x2F8, 561 PRIORITY_RULES_DW15 = 0x2FC, 562 /* reserved */ 563 P2A_TC_QOS_CONV = 0x3C0, 564 P2A_ATTR_CACHE_CONV = 0x3C4, 565 P2A_NC_BASE_ADDR_DW0 = 0x3C8, 566 P2A_NC_BASE_ADDR_DW1 = 0x3CC, 567 /* reserved */ 568 DMA0_SRC_PARAM = 0x400, 569 DMA0_DESTPARAM = 0x404, 570 DMA0_SRCADDR_LDW = 0x408, 571 DMA0_SRCADDR_UDW = 0x40C, 572 DMA0_DESTADDR_LDW = 0x410, 573 DMA0_DESTADDR_UDW = 0x414, 574 DMA0_LENGTH = 0x418, 575 DMA0_CONTROL = 0x41C, 576 DMA0_STATUS = 0x420, 577 DMA0_PRC_LENGTH = 0x424, 578 DMA0_SHARE_ACCESS = 0x428, 579 /* reserved */ 580 DMA1_SRC_PARAM = 0x440, 581 DMA1_DESTPARAM = 0x444, 582 DMA1_SRCADDR_LDW = 0x448, 583 DMA1_SRCADDR_UDW = 0x44C, 584 DMA1_DESTADDR_LDW = 0x450, 585 DMA1_DESTADDR_UDW = 0x454, 586 DMA1_LENGTH = 0x458, 587 DMA1_CONTROL = 0x45C, 588 DMA1_STATUS = 0x460, 589 DMA1_PRC_LENGTH = 0x464, 590 DMA1_SHARE_ACCESS = 0x468, 591 /* reserved */ 592 ATR0_PCIE_WIN0_SRCADDR_PARAM = 0x600, 593 ATR0_PCIE_WIN0_SRC_ADDR = 0x604, 594 ATR0_PCIE_WIN0_TRSL_ADDR_LSB = 0x608, 595 ATR0_PCIE_WIN0_TRSL_ADDR_UDW = 0x60C, 596 ATR0_PCIE_WIN0_TRSL_PARAM = 0x610, 597 /* reserved */ 598 ATR0_PCIE_WIN0_TRSL_MASK_DW0 = 0x618, 599 ATR0_PCIE_WIN0_TRSL_MASK_DW1 = 0x61C, 600 ATR1_PCIE_WIN0_SRCADDR_PARAM = 0x620, 601 ATR1_PCIE_WIN0_SRC_ADDR = 0x624, 602 ATR1_PCIE_WIN0_TRSL_ADDR_LSB = 0x628, 603 ATR1_PCIE_WIN0_TRSL_ADDR_UDW = 0x62C, 604 ATR1_PCIE_WIN0_TRSL_PARAM = 0x630, 605 /* reserved */ 606 ATR1_PCIE_WIN0_TRSL_MASK_DW0 = 0x638, 607 ATR1_PCIE_WIN0_TRSL_MASK_DW1 = 0x63C, 608 ATR2_PCIE_WIN0_SRCADDR_PARAM = 0x640, 609 ATR2_PCIE_WIN0_SRC_ADDR = 0x644, 610 ATR2_PCIE_WIN0_TRSL_ADDR_LSB = 0x648, 611 ATR2_PCIE_WIN0_TRSL_ADDR_UDW = 0x64C, 612 ATR2_PCIE_WIN0_TRSL_PARAM = 0x650, 613 /* reserved */ 614 ATR2_PCIE_WIN0_TRSL_MASK_DW0 = 0x658, 615 ATR2_PCIE_WIN0_TRSL_MASK_DW1 = 0x65C, 616 ATR3_PCIE_WIN0_SRCADDR_PARAM = 0x660, 617 ATR3_PCIE_WIN0_SRC_ADDR = 0x664, 618 ATR3_PCIE_WIN0_TRSL_ADDR_LSB = 0x668, 619 ATR3_PCIE_WIN0_TRSL_ADDR_UDW = 0x66C, 620 ATR3_PCIE_WIN0_TRSL_PARAM = 0x670, 621 /* reserved */ 622 ATR3_PCIE_WIN0_TRSL_MASK_DW0 = 0x678, 623 ATR3_PCIE_WIN0_TRSL_MASK_DW1 = 0x67C, 624 ATR4_PCIE_WIN0_SRCADDR_PARAM = 0x680, 625 ATR4_PCIE_WIN0_SRC_ADDR = 0x684, 626 ATR4_PCIE_WIN0_TRSL_ADDR_LSB = 0x688, 627 ATR4_PCIE_WIN0_TRSL_ADDR_UDW = 0x68C, 628 ATR4_PCIE_WIN0_TRSL_PARAM = 0x690, 629 /* reserved */ 630 ATR4_PCIE_WIN0_TRSL_MASK_DW0 = 0x698, 631 ATR4_PCIE_WIN0_TRSL_MASK_DW1 = 0x69C, 632 ATR5_PCIE_WIN0_SRCADDR_PARAM = 0x6A0, 633 ATR5_PCIE_WIN0_SRC_ADDR = 0x6A4, 634 ATR5_PCIE_WIN0_TRSL_ADDR_LSB = 0x6A8, 635 ATR5_PCIE_WIN0_TRSL_ADDR_UDW = 0x6AC, 636 ATR5_PCIE_WIN0_TRSL_PARAM = 0x6B0, 637 /* reserved */ 638 ATR5_PCIE_WIN0_TRSL_MASK_DW0 = 0x6B8, 639 ATR5_PCIE_WIN0_TRSL_MASK_DW1 = 0x6BC, 640 ATR6_PCIE_WIN0_SRCADDR_PARAM = 0x6C0, 641 ATR6_PCIE_WIN0_SRC_ADDR = 0x6C4, 642 ATR6_PCIE_WIN0_TRSL_ADDR_LSB = 0x6C8, 643 ATR6_PCIE_WIN0_TRSL_ADDR_UDW = 0x6CC, 644 ATR6_PCIE_WIN0_TRSL_PARAM = 0x6D0, 645 /* reserved */ 646 ATR6_PCIE_WIN0_TRSL_MASK_DW0 = 0x6D8, 647 ATR6_PCIE_WIN0_TRSL_MASK_DW1 = 0x6DC, 648 ATR7_PCIE_WIN0_SRCADDR_PARAM = 0x6E0, 649 ATR7_PCIE_WIN0_SRC_ADDR = 0x6E4, 650 ATR7_PCIE_WIN0_TRSL_ADDR_LSB = 0x6E8, 651 ATR7_PCIE_WIN0_TRSL_ADDR_UDW = 0x6EC, 652 ATR7_PCIE_WIN0_TRSL_PARAM = 0x6F0, 653 /* reserved */ 654 ATR7_PCIE_WIN0_TRSL_MASK_DW0 = 0x6F8, 655 ATR7_PCIE_WIN0_TRSL_MASK_DW1 = 0x6FC, 656 657 ATR0_PCIE_WIN1_SRCADDR_PARAM = 0x700, 658 ATR0_PCIE_WIN1_SRC_ADDR = 0x704, 659 ATR0_PCIE_WIN1_TRSL_ADDR_LSB = 0x708, 660 ATR0_PCIE_WIN1_TRSL_ADDR_UDW = 0x70C, 661 ATR0_PCIE_WIN1_TRSL_PARAM = 0x710, 662 /* reserved */ 663 ATR0_PCIE_WIN1_TRSL_MASK_DW0 = 0x718, 664 ATR0_PCIE_WIN1_TRSL_MASK_DW1 = 0x71C, 665 ATR1_PCIE_WIN1_SRCADDR_PARAM = 0x720, 666 ATR1_PCIE_WIN1_SRC_ADDR = 0x724, 667 ATR1_PCIE_WIN1_TRSL_ADDR_LSB = 0x728, 668 ATR1_PCIE_WIN1_TRSL_ADDR_UDW = 0x72C, 669 ATR1_PCIE_WIN1_TRSL_PARAM = 0x730, 670 /* reserved */ 671 ATR1_PCIE_WIN1_TRSL_MASK_DW0 = 0x738, 672 ATR1_PCIE_WIN1_TRSL_MASK_DW1 = 0x73C, 673 ATR2_PCIE_WIN1_SRCADDR_PARAM = 0x740, 674 ATR2_PCIE_WIN1_SRC_ADDR = 0x744, 675 ATR2_PCIE_WIN1_TRSL_ADDR_LSB = 0x748, 676 ATR2_PCIE_WIN1_TRSL_ADDR_UDW = 0x74C, 677 ATR2_PCIE_WIN1_TRSL_PARAM = 0x750, 678 /* reserved */ 679 ATR2_PCIE_WIN1_TRSL_MASK_DW0 = 0x758, 680 ATR2_PCIE_WIN1_TRSL_MASK_DW1 = 0x75C, 681 ATR3_PCIE_WIN1_SRCADDR_PARAM = 0x760, 682 ATR3_PCIE_WIN1_SRC_ADDR = 0x764, 683 ATR3_PCIE_WIN1_TRSL_ADDR_LSB = 0x768, 684 ATR3_PCIE_WIN1_TRSL_ADDR_UDW = 0x76C, 685 ATR3_PCIE_WIN1_TRSL_PARAM = 0x770, 686 /* reserved */ 687 ATR3_PCIE_WIN1_TRSL_MASK_DW0 = 0x778, 688 ATR3_PCIE_WIN1_TRSL_MASK_DW1 = 0x77C, 689 ATR4_PCIE_WIN1_SRCADDR_PARAM = 0x780, 690 ATR4_PCIE_WIN1_SRC_ADDR = 0x784, 691 ATR4_PCIE_WIN1_TRSL_ADDR_LSB = 0x788, 692 ATR4_PCIE_WIN1_TRSL_ADDR_UDW = 0x78C, 693 ATR4_PCIE_WIN1_TRSL_PARAM = 0x790, 694 /* reserved */ 695 ATR4_PCIE_WIN1_TRSL_MASK_DW0 = 0x798, 696 ATR4_PCIE_WIN1_TRSL_MASK_DW1 = 0x79C, 697 ATR5_PCIE_WIN1_SRCADDR_PARAM = 0x7A0, 698 ATR5_PCIE_WIN1_SRC_ADDR = 0x7A4, 699 ATR5_PCIE_WIN1_TRSL_ADDR_LSB = 0x7A8, 700 ATR5_PCIE_WIN1_TRSL_ADDR_UDW = 0x7AC, 701 ATR5_PCIE_WIN1_TRSL_PARAM = 0x7B0, 702 /* reserved */ 703 ATR5_PCIE_WIN1_TRSL_MASK_DW0 = 0x7B8, 704 ATR5_PCIE_WIN1_TRSL_MASK_DW1 = 0x7BC, 705 ATR6_PCIE_WIN1_SRCADDR_PARAM = 0x7C0, 706 ATR6_PCIE_WIN1_SRC_ADDR = 0x7C4, 707 ATR6_PCIE_WIN1_TRSL_ADDR_LSB = 0x7C8, 708 ATR6_PCIE_WIN1_TRSL_ADDR_UDW = 0x7CC, 709 ATR6_PCIE_WIN1_TRSL_PARAM = 0x7D0, 710 /* reserved */ 711 ATR6_PCIE_WIN1_TRSL_MASK_DW0 = 0x7D8, 712 ATR6_PCIE_WIN1_TRSL_MASK_DW1 = 0x7DC, 713 ATR7_PCIE_WIN1_SRCADDR_PARAM = 0x7E0, 714 ATR7_PCIE_WIN1_SRC_ADDR = 0x7E4, 715 ATR7_PCIE_WIN1_TRSL_ADDR_LSB = 0x7E8, 716 ATR7_PCIE_WIN1_TRSL_ADDR_UDW = 0x7EC, 717 ATR7_PCIE_WIN1_TRSL_PARAM = 0x7F0, 718 /* reserved */ 719 ATR7_PCIE_WIN1_TRSL_MASK_DW0 = 0x7F8, 720 ATR7_PCIE_WIN1_TRSL_MASK_DW1 = 0x7FC, 721 722 ATR0_AXI4_SLV0_SRCADDR_PARAM = 0x800, 723 ATR0_AXI4_SLV0_SRC_ADDR = 0x804, 724 ATR0_AXI4_SLV0_TRSL_ADDR_LSB = 0x808, 725 ATR0_AXI4_SLV0_TRSL_ADDR_UDW = 0x80C, 726 ATR0_AXI4_SLV0_TRSL_PARAM = 0x810, 727 /* reserved */ 728 ATR0_AXI4_SLV0_TRSL_MASK_DW0 = 0x818, 729 ATR0_AXI4_SLV0_TRSL_MASK_DW1 = 0x81C, 730 ATR1_AXI4_SLV0_SRCADDR_PARAM = 0x820, 731 ATR1_AXI4_SLV0_SRC_ADDR = 0x824, 732 ATR1_AXI4_SLV0_TRSL_ADDR_LSB = 0x828, 733 ATR1_AXI4_SLV0_TRSL_ADDR_UDW = 0x82C, 734 ATR1_AXI4_SLV0_TRSL_PARAM = 0x830, 735 /* reserved */ 736 ATR1_AXI4_SLV0_TRSL_MASK_DW0 = 0x838, 737 ATR1_AXI4_SLV0_TRSL_MASK_DW1 = 0x83C, 738 ATR2_AXI4_SLV0_SRCADDR_PARAM = 0x840, 739 ATR2_AXI4_SLV0_SRC_ADDR = 0x844, 740 ATR2_AXI4_SLV0_TRSL_ADDR_LSB = 0x848, 741 ATR2_AXI4_SLV0_TRSL_ADDR_UDW = 0x84C, 742 ATR2_AXI4_SLV0_TRSL_PARAM = 0x850, 743 /* reserved */ 744 ATR2_AXI4_SLV0_TRSL_MASK_DW0 = 0x858, 745 ATR2_AXI4_SLV0_TRSL_MASK_DW1 = 0x85C, 746 ATR3_AXI4_SLV0_SRCADDR_PARAM = 0x860, 747 ATR3_AXI4_SLV0_SRC_ADDR = 0x864, 748 ATR3_AXI4_SLV0_TRSL_ADDR_LSB = 0x868, 749 ATR3_AXI4_SLV0_TRSL_ADDR_UDW = 0x86C, 750 ATR3_AXI4_SLV0_TRSL_PARAM = 0x870, 751 /* reserved */ 752 ATR3_AXI4_SLV0_TRSL_MASK_DW0 = 0x878, 753 ATR3_AXI4_SLV0_TRSL_MASK_DW1 = 0x87C, 754 ATR4_AXI4_SLV0_SRCADDR_PARAM = 0x880, 755 ATR4_AXI4_SLV0_SRC_ADDR = 0x884, 756 ATR4_AXI4_SLV0_TRSL_ADDR_LSB = 0x888, 757 ATR4_AXI4_SLV0_TRSL_ADDR_UDW = 0x88C, 758 ATR4_AXI4_SLV0_TRSL_PARAM = 0x890, 759 /* reserved */ 760 ATR4_AXI4_SLV0_TRSL_MASK_DW0 = 0x898, 761 ATR4_AXI4_SLV0_TRSL_MASK_DW1 = 0x89C, 762 ATR5_AXI4_SLV0_SRCADDR_PARAM = 0x8A0, 763 ATR5_AXI4_SLV0_SRC_ADDR = 0x8A4, 764 ATR5_AXI4_SLV0_TRSL_ADDR_LSB = 0x8A8, 765 ATR5_AXI4_SLV0_TRSL_ADDR_UDW = 0x8AC, 766 ATR5_AXI4_SLV0_TRSL_PARAM = 0x8B0, 767 /* reserved */ 768 ATR5_AXI4_SLV0_TRSL_MASK_DW0 = 0x8B8, 769 ATR5_AXI4_SLV0_TRSL_MASK_DW1 = 0x8BC, 770 ATR6_AXI4_SLV0_SRCADDR_PARAM = 0x8C0, 771 ATR6_AXI4_SLV0_SRC_ADDR = 0x8C4, 772 ATR6_AXI4_SLV0_TRSL_ADDR_LSB = 0x8C8, 773 ATR6_AXI4_SLV0_TRSL_ADDR_UDW = 0x8CC, 774 ATR6_AXI4_SLV0_TRSL_PARAM = 0x8D0, 775 /* reserved */ 776 ATR6_AXI4_SLV0_TRSL_MASK_DW0 = 0x8D8, 777 ATR6_AXI4_SLV0_TRSL_MASK_DW1 = 0x8DC, 778 ATR7_AXI4_SLV0_SRCADDR_PARAM = 0x8E0, 779 ATR7_AXI4_SLV0_SRC_ADDR = 0x8E4, 780 ATR7_AXI4_SLV0_TRSL_ADDR_LSB = 0x8E8, 781 ATR7_AXI4_SLV0_TRSL_ADDR_UDW = 0x8EC, 782 ATR7_AXI4_SLV0_TRSL_PARAM = 0x8F0, 783 /* reserved */ 784 ATR7_AXI4_SLV0_TRSL_MASK_DW0 = 0x8F8, 785 ATR7_AXI4_SLV0_TRSL_MASK_DW1 = 0x8FC, 786 787 /* PCIE Control Registers */ 788 SEC_ERROR_EVENT_CNT = 0x2020, 789 DED_ERROR_EVENT_CNT = 0x2024, 790 SEC_ERROR_INT = 0x2028, 791 SEC_ERROR_INT_MASK = 0x202C, // 0x220C according to the docs. A typo? 792 DED_ERROR_INT = 0x2030, 793 DED_ERROR_INT_MASK = 0x2034, 794 ECC_CONTROL = 0x2038, 795 ECC_ERR_LOC = 0x203C, 796 RAM_MARGIN_1 = 0x2040, 797 RAM_MARGIN_2 = 0x2044, 798 RAM_POWER_CONTROL = 0x2048, 799 /* reserved */ 800 DEBUG_SEL = 0x2050, 801 /* reserved */ 802 LTSSM_STATE = 0x205C, 803 PHY_COMMON_INTERFACE = 0x2060, 804 PL_TX_LANEIF_0 = 0x2064, 805 PL_RX_LANEIF_0 = 0x2068, 806 PL_WAKECLKREQ = 0x206C, 807 /* reserved */ 808 PCICONF_PCI_IDS_OVERRIDE = 0x2080, 809 PCICONF_PCI_IDS_31_0 = 0x2084, 810 PCICONF_PCI_IDS_63_32 = 0x2088, 811 PCICONF_PCI_IDS_95_64 = 0x208C, 812 /* reserved */ 813 PCIE_PEX_DEV_LINK_SPC2 = 0x20A0, 814 //PCIE_PEX_SPC = 0x20A4, <-- available in the header, but not in the docs. The same name occurs under 0xD4 815 /* reserved */ 816 PCIE_AXI_MASTER_ATR_CFG0 = 0x2100, 817 PCIE_AXI_MASTER_ATR_CFG1 = 0x2104, 818 PCIE_AXI_MASTER_ATR_CFG2 = 0x2108, 819 /* reserved */ 820 AXI_SLAVE_PCIE_ATR_CFG0 = 0x2120, 821 AXI_SLAVE_PCIE_ATR_CFG1 = 0x2124, 822 AXI_SLAVE_PCIE_ATR_CFG2 = 0x2128, 823 /* reserved */ 824 PCIE_BAR_01 = 0x2140, 825 PCIE_BAR_23 = 0x2144, 826 PCIE_BAR_45 = 0x2148, 827 PCIE_EVENT_INT = 0x214C, 828 } 829 } 830 }
