1 // 2 // Copyright (c) 2010-2024 Antmicro 3 // 4 // This file is licensed under the MIT License. 5 // Full license text is available in 'licenses/MIT.txt'. 6 // 7 using System; 8 using Antmicro.Renode.Core; 9 using Antmicro.Renode.Core.Structure; 10 using Antmicro.Renode.Core.Structure.Registers; 11 using Antmicro.Renode.Logging; 12 using Antmicro.Renode.Network; 13 using Antmicro.Renode.Peripherals.Bus; 14 using Antmicro.Renode.Peripherals.CPU; 15 16 namespace Antmicro.Renode.Peripherals.Network 17 { 18 public class S32K3XX_EMAC : SynopsysDWCEthernetQualityOfService 19 { S32K3XX_EMAC(IMachine machine, long systemClockFrequency, ICPU cpuContext = null)20 public S32K3XX_EMAC(IMachine machine, long systemClockFrequency, ICPU cpuContext = null) 21 :base(machine, systemClockFrequency, cpuContext) 22 { 23 Reset(); 24 } 25 ReadDoubleWord(long offset)26 public override uint ReadDoubleWord(long offset) 27 { 28 if(offset < (long)Registers.MTLOperationMode) 29 { 30 return base.ReadDoubleWord(offset); 31 } 32 else if(offset < (long)Registers.DMAMode) 33 { 34 return ReadDoubleWordFromMTL(offset - (long)Registers.MTLOperationMode); 35 } 36 return ReadDoubleWordFromDMA(offset - (long)Registers.DMAMode); 37 } 38 WriteDoubleWord(long offset, uint value)39 public override void WriteDoubleWord(long offset, uint value) 40 { 41 if(offset < (long)Registers.MTLOperationMode) 42 { 43 base.WriteDoubleWord(offset, value); 44 } 45 else if(offset < (long)Registers.DMAMode) 46 { 47 WriteDoubleWordToMTL(offset - (long)Registers.MTLOperationMode, value); 48 } 49 else 50 { 51 WriteDoubleWordToDMA(offset - (long)Registers.DMAMode, value); 52 } 53 } 54 55 public override long Size => 0x1200; 56 57 public GPIO Channel0TX => dmaChannels[0].TxIRQ; 58 public GPIO Channel0RX => dmaChannels[0].RxIRQ; 59 public GPIO Channel1TX => dmaChannels[1].TxIRQ; 60 public GPIO Channel1RX => dmaChannels[1].RxIRQ; 61 62 // Base model configuration: 63 protected override long[] DMAChannelOffsets => new long[] 64 { 65 (long)Registers.DMAChannel0Control - (long)Registers.DMAMode, 66 (long)Registers.DMAChannel1Control - (long)Registers.DMAMode, 67 }; 68 protected override BusWidth DMABusWidth => BusWidth.Bits32; 69 protected override int RxQueueSize => 8192; 70 protected override bool SeparateDMAInterrupts => true; 71 72 private enum Registers 73 { 74 Configuration = 0x0, // MAC_Configuration 75 ExtendedConfiguration = 0x4, // MAC_Ext_Configuration 76 PacketFilter = 0x8, // MAC_Packet_Filter 77 WatchdogTimeout = 0xC, // MAC_Watchdog_Timeout 78 HashTable0 = 0x10, // MAC_Hash_Table_Reg0 79 HashTable1 = 0x14, // MAC_Hash_Table_Reg1 80 81 VLANTag = 0x50, // MAC_VLAN_Tag_Ctrl 82 VLANTagControl = 0x50, // MAC_VLAN_Tag_Ctrl 83 VLANTagData = 0x54, // MAC_VLAN_Tag_Data 84 VLANTagFilter0 = 0x54, // MAC_VLAN_Tag_Filter0 85 VLANTagFilter1 = 0x54, // MAC_VLAN_Tag_Filter1 86 VLANTagFilter2 = 0x54, // MAC_VLAN_Tag_Filter2 87 VLANTagFilter3 = 0x54, // MAC_VLAN_Tag_Filter3 88 VLANTagFilter4 = 0x54, // MAC_VLAN_Tag_Filter4 89 90 VLANHashTable = 0x58, // MAC_VLAN_Hash_Table 91 92 VLANInclusion = 0x60, // MAC_VLAN_Incl 93 VLANInclusion0 = 0x60, // MAC_VLAN_Incl0 94 VLANInclusion1 = 0x60, // MAC_VLAN_Incl1 95 VLANInclusion2 = 0x60, // MAC_VLAN_Incl2 96 VLANInclusion3 = 0x60, // MAC_VLAN_Incl3 97 VLANInclusion4 = 0x60, // MAC_VLAN_Incl4 98 VLANInclusion5 = 0x60, // MAC_VLAN_Incl5 99 VLANInclusion6 = 0x60, // MAC_VLAN_Incl6 100 VLANInclusion7 = 0x60, // MAC_VLAN_Incl7 101 InnerVLANInclusion = 0x64, // MAC_Inner_VLAN_Incl 102 103 Queue0TransmitFlowControl = 0x70, // MAC_Q0_Tx_Flow_Ctrl 104 105 ReceiveFlowControl = 0x90, // MAC_Rx_Flow_Ctrl 106 ReceiveQueueControl4 = 0x94, // MAC_RxQ_Ctrl4 107 ReceiveQueueControl0 = 0xA0, // MAC_RxQ_Ctrl0 108 ReceiveQueueControl1 = 0xA4, // MAC_RxQ_Ctrl1 109 ReceiveQueueControl2 = 0xA8, // MAC_RxQ_Ctrl2 110 InterruptStatus = 0xB0, // MAC_Interrupt_Status 111 InterruptEnable = 0xB4, // MAC_Interrupt_Enable 112 ReceiveTransmitStatus = 0xB8, // MAC_Rx_Tx_Status 113 PHYInterfaceControlAndStatus = 0xF8, // MAC_PHYIF_Control_Status 114 Version = 0x110, // MAC_Version 115 Debug = 0x114, // MAC_Debug 116 HardwareFeature0 = 0x11C, // MAC_HW_Feature0 117 HardwareFeature1 = 0x120, // MAC_HW_Feature1 118 HardwareFeature2 = 0x124, // MAC_HW_Feature2 119 HardwareFeature3 = 0x128, // MAC_HW_Feature3 120 121 FSMErrorsInterruptStatus = 0x140, // MAC_DPP_FSM_Interrupt_Status 122 FSMControl = 0x148, // MAC_FSM_Control 123 FSMTimeouts = 0x14C, // MAC_FSM_ACT_Timer 124 125 MDIOAddress = 0x200, // MAC_MDIO_Address 126 ARPAddress = 0x210, // MAC_ARP_Address 127 CSRSoftwareControl = 0x230, // MAC_CSR_SW_Ctrl 128 FramePreeptionControl = 0x234, // MAC_FPE_CTRL_STS 129 ExtendedConfiguration1 = 0x238, // MAC_Ext_Cfg1 130 131 PresentationTimeNanoseconds = 0x240, // MAC_Presn_Time_ns 132 PresentationTimeUpdate = 0x244, // MAC_Presn_Time_Updt 133 134 Address0High = 0x300, // MAC_Address0_High 135 Address0Low = 0x304, // MAC_Address0_Low 136 Address1High = 0x308, // MAC_Address1_High 137 Address1Low = 0x30C, // MAC_Address1_Low 138 Address2High = 0x310, // MAC_Address2_High 139 Address2Low = 0x314, // MAC_Address2_Low 140 141 MMCControl = 0x700, // MMC_Control 142 MMCReceiveInterrupt = 0x704, // MMC_Rx_Interrupt 143 MMCTransmitInterrupt = 0x708, // MMC_Tx_Interrupt 144 MMCReceiveInterruptMask = 0x70C, // MMC_Rx_Interrupt_Mask 145 MMCTransmitInterruptMask = 0x710, // MMC_Tx_Interrupt_Mask 146 147 TransmitOctetCount = 0x714, // Tx_Octet_Count_Good_Bad 148 TransmitPacketCount = 0x718, // Tx_Packet_Count_Good_Bad 149 TransmitBroadcastPacketGoodCount = 0x71C, // Tx_Broadcast_Packets_Good 150 TransmitMulticastPacketGoodCount = 0x720, // Tx_Multicast_Packets_Good 151 Transmit64OctetPacketCount = 0x724, // Tx_64Octets_Packets_Good_Bad 152 Transmit64To127OctetPacketCount = 0x728, // Tx_65To127Octets_Packets_Good_Bad 153 Transmit128To255OctetPacketCount = 0x72C, // Tx_128To255Octets_Packets_Good_Bad 154 Transmit256To511OctetPacketCount = 0x730, // Tx_256To511Octets_Packets_Good_Bad 155 Transmit512To1023OctetPacketCount = 0x734, // Tx_512To1023Octets_Packets_Good_Bad 156 Transmit1024ToMaxOctetPacketCount = 0x738, // Tx_1024ToMaxOctets_Packets_Good_Bad 157 TransmitUnicastPacketCount = 0x73C, // Tx_Unicast_Packets_Good_Bad 158 TransmitMulticastPacketCount = 0x740, // Tx_Multicast_Packets_Good_Bad 159 TransmitBroadcastPacketCount = 0x744, // Tx_Broadcast_Packets_Good_Bad 160 TransmitUnderflowErrorPacketCount = 0x748, // Tx_Underflow_Error_Packets 161 TransmitSingleCollisionPacketGoodCount = 0x74C, // Tx_Single_Collision_Good_Packets 162 TransmitMultipleCollisionPacketGoodCount = 0x750, // Tx_Multiple_Collision_Good_Packets 163 TransmitDeferredPacketCount = 0x754, // Tx_Deferred_Packets 164 TransmitLateCollisionPacketCount = 0x758, // Tx_Late_Collision_Packets 165 TransmitExcessiveCollisionPacketCount = 0x75C, // Tx_Late_Collision_Packets 166 TransmitCarrierErrorPacketCount = 0x760, // Tx_Carrier_Error_Packets 167 TransmitOctetGoodCount = 0x764, // Tx_Octet_Count_Good 168 TransmitPacketGoodCount = 0x768, // Tx_Packet_Count_Good 169 TransmitExcessiveDeferralErrorPacketCount = 0x76C, // Tx_Excessive_Deferral_Error 170 TransmitPausePacketCount = 0x770, // Tx_Pause_Packets 171 TransmitVLANPacketGoodCount = 0x774, // Tx_VLAN_Packets_Good 172 TransmitGreaterThanMaxSizePacketGoodCount = 0x778, // Tx_OSize_Packets_Good 173 174 ReceivePacketCount = 0x780, // Rx_Packets_Count_Good_Bad 175 ReceiveOctetCount = 0x784, // Rx_Octet_Count_Good_Bad 176 ReceiveOctetGoodCount = 0x788, // Rx_Octet_Count_Good 177 ReceiveBroadcastPacketGoodCount = 0x78C, // Rx_Broadcast_Packets_Good 178 ReceiveMulticastPacketGoodCount = 0x790, // Rx_Multicast_Packets_Good 179 ReceiveCRCErrorPacketCount = 0x794, // Rx_CRC_Error_Packets 180 ReceiveAlignmentErrorPacketCount = 0x798, // Rx_Alignment_Error_Packets 181 ReceiveRuntErrorPacketCount = 0x79C, // Rx_Runt_Error_Packets 182 ReceiveJabberErrorPacketCount = 0x7A0, // Rx_Jabber_Error_Packets 183 ReceiveUndersizeErrorPacketCount = 0x7A4, // Rx_Undersize_Packets_Good 184 ReceiveOversizeErrorPacketCount = 0x7A8, // Rx_Oversize_Packets_Good 185 Receive64To127OctetPacketCount = 0x7B0, // Rx_65To127Octets_Packets_Good_Bad 186 Receive128To255OctetPacketCount = 0x7B4, // Rx_128To255Octets_Packets_Good_Bad 187 Receive256To511OctetPacketCount = 0x7B8, // Rx_256To511Octets_Packets_Good_Bad 188 Receive512To1023OctetPacketCount = 0x7BC, // Rx_512To1023Octets_Packets_Good_Bad 189 Receive1024ToMaxOctetPacketCount = 0x7C0, // Rx_1024ToMaxOctets_Packets_Good_Bad 190 ReceiveUnicastPacketGoodCount = 0x7C4, // Rx_Unicast_Packets_Good 191 ReceiveLengthErrorPacketCount = 0x7C8, // Rx_Length_Error_Packets 192 ReceiveOutOfRangeTypePacketCount = 0x7CC, // Rx_Out_Of_Range_Type_Packets 193 ReceivePausePacketCount = 0x7D0, // Rx_Pause_Packets 194 ReceiveFIFOOverflowPacketCount = 0x7D4, // Rx_FIFO_Overflow_Packets 195 ReceiveVLANPacketCount = 0x7D8, // Rx_VLAN_Packets_Good_Bad 196 ReceiveWatchdogErrorPacketCount = 0x7DC, // Rx_Watchdog_Error_Packets 197 ReceiveReceiveErrorPacketCount = 0x7E0, // Rx_Receive_Error_Packets 198 ReceiveControlPacketGoodCount = 0x7E4, // Rx_Control_Packets_Good 199 200 MMCFramePreemptionTransmitInterrupt = 0x8A0, // MMC_FPE_Tx_Interrupt 201 MMCFramePreemptionTransmitInterruptMask = 0x8A4, // MMC_FPE_Tx_Interrupt_Mask 202 MMCFramePreemptionTransmitFragmentCount = 0x8A8, // MMC_Tx_FPE_Fragment_Cntr 203 MMCTransmitHoldRequestCount = 0x8AC, // MMC_Tx_Hold_Req_Cntr 204 MMCFramePreemptionReceiveInterrupt = 0x8C0, // MMC_FPE_Rx_Interrupt 205 MMCFramePreemptionReceiveInterruptMask = 0x8C4, // MMC_FPE_Rx_Interrupt_Mask 206 MMCReceivePacketAssemblyErrorCount = 0x8C8, // MMC_Rx_Packet_Assembly_Err_Cntr 207 MMCReceivePacketSMDErrorCount = 0x8CC, // MMC_Rx_Packet_SMD_Err_Cntr 208 MMCReceivePacketAssemblyOkCount = 0x8D0, // MMC_Rx_Packet_Assembly_OK_Cntr 209 MMCFramePreemptionReceiveFragmentCount = 0x8D4, // MMC_Rx_FPE_Fragment_Cntr 210 211 Layer3Layer4Control0 = 0x900, // MAC_L3_L4_Control0 212 Layer4Address0 = 0x904, // MAC_Layer4_Address0 213 Layer3Address0Register0 = 0x910, // MAC_Layer3_Addr0_Reg0 214 Layer3Address1Register0 = 0x914, // MAC_Layer3_Addr1_Reg0 215 Layer3Address2Register0 = 0x918, // MAC_Layer3_Addr2_Reg0 216 Layer3Address3Register0 = 0x91C, // MAC_Layer3_Addr3_Reg0 217 218 Layer3Layer4Control1 = 0x930, // MAC_L3_L4_Control1 219 Layer4Address1 = 0x934, // MAC_Layer4_Address1 220 Layer3Address0Register1 = 0x940, // MAC_Layer3_Addr0_Reg1 221 Layer3Address1Register1 = 0x944, // MAC_Layer3_Addr1_Reg1 222 Layer3Address2Register1 = 0x948, // MAC_Layer3_Addr2_Reg1 223 Layer3Address3Register1 = 0x94C, // MAC_Layer3_Addr3_Reg1 224 225 Layer3Layer4Control2 = 0x960, // MAC_L3_L4_Control2 226 Layer4Address2 = 0x964, // MAC_Layer4_Address2 227 Layer3Address0Register2 = 0x970, // MAC_Layer3_Addr0_Reg2 228 Layer3Address1Register2 = 0x974, // MAC_Layer3_Addr1_Reg2 229 Layer3Address2Register2 = 0x978, // MAC_Layer3_Addr2_Reg2 230 Layer3Address3Register2 = 0x97C, // MAC_Layer3_Addr3_Reg2 231 232 Layer3Layer4Control3 = 0x990, // MAC_L3_L4_Control3 233 Layer4Address3 = 0x994, // MAC_Layer4_Address3 234 Layer3Address0Register3 = 0x9A0, // MAC_Layer3_Addr0_Reg3 235 Layer3Address1Register3 = 0x9A4, // MAC_Layer3_Addr1_Reg3 236 Layer3Address2Register3 = 0x9A8, // MAC_Layer3_Addr2_Reg3 237 Layer3Address3Register3 = 0x9AC, // MAC_Layer3_Addr3_Reg3 238 239 TimestampControl = 0xB00, // MAC_Timestamp_Control 240 SubSecondIncrement = 0xB04, // MAC_Sub_Second_Increment 241 SystemTimeSeconds = 0xB08, // MAC_System_Time_Seconds 242 SystemTimeNanoseconds = 0xB0C, // MAC_System_Time_Nanoseconds 243 SystemTimeSecondsUpdate = 0xB10, // MAC_System_Time_Seconds_Update 244 SystemTimeNanosecondsUpdate = 0xB14, // MAC_System_Time_Nanoseconds_Update 245 TimestampAddend = 0xB18, // MAC_Timestamp_Addend 246 SystemTimeHigherWordSeconds = 0xB1C, // MAC_System_Time_Higher_Word_Seconds 247 TimestampStatus = 0xB20, // MAC_Timestamp_Status 248 TransmitTimestampStatusNanoseconds = 0xB30, // MAC_Tx_Timestamp_Status_Nanoseconds 249 TransmitTimestampStatusSeconds = 0xB34, // MAC_Tx_Timestamp_Status_Seconds 250 TimestampIngressAsymmetryCorrection = 0xB50, // MAC_Timestamp_Ingress_Asym_Corr 251 TimestampEgressAsymmetryCorrection = 0xB54, // MAC_Timestamp_Egress_Asym_Corr 252 TimestampIngressCorrectionNanosecond = 0xB58, // MAC_Timestamp_Ingress_Corr_Nanosecond 253 TimestampEgressCorrectionNanosecond = 0xB5C, // MAC_Timestamp_Egress_Corr_Nanosecond 254 TimestampIngressCorrectionSubnanosecond = 0xB60, // MAC_Timestamp_Ingress_Corr_Subnanosec 255 TimestampEgressCorrectionSubnanosecond = 0xB64, // MAC_Timestamp_Egress_Corr_Subnanosec 256 TimestampIngressLatency = 0xB68, // MAC_Timestamp_Ingress_Latency 257 TimestampEgressLatency = 0xB6C, // MAC_Timestamp_Egress_Latency 258 259 PPSControl = 0xB70, // MAC_PPS_Control 260 PPS0TargetTimeSeconds = 0xB80, // MAC_PPS0_Target_Time_Seconds 261 PPS0TargetTimeNanoseconds = 0xB84, // MAC_PPS0_Target_Time_Nanoseconds 262 PPS0Interval = 0xB88, // MAC_PPS0_Interval 263 PPS0Width = 0xB8C, // MAC_PPS0_Width 264 PPS1TargetTimeSeconds = 0xB90, // MAC_PPS1_Target_Time_Seconds 265 PPS1TargetTimeNanoseconds = 0xB94, // MAC_PPS1_Target_Time_Nanoseconds 266 PPS1Interval = 0xB98, // MAC_PPS1_Interval 267 PPS1Width = 0xB9C, // MAC_PPS1_Width 268 PPS2TargetTimeSeconds = 0xBA0, // MAC_PPS2_Target_Time_Seconds 269 PPS2TargetTimeNanoseconds = 0xBA4, // MAC_PPS2_Target_Time_Nanoseconds 270 PPS2Interval = 0xBA8, // MAC_PPS2_Interval 271 PPS2Width = 0xBAC, // MAC_PPS2_Width 272 PPS3TargetTimeSeconds = 0xBB0, // MAC_PPS3_Target_Time_Seconds 273 PPS3TargetTimeNanoseconds = 0xBB4, // MAC_PPS3_Target_Time_Nanoseconds 274 PPS3Interval = 0xBB8, // MAC_PPS3_Interval 275 PPS3Width = 0xBBC, // MAC_PPS3_Width 276 277 MTLOperationMode = 0xC00, // MTL_Operation_Mode 278 MTLDebugControl = 0xC08, // MTL_DBG_CTL 279 MTLDebugStatus = 0xC0C, // MTL_DBG_STS 280 MTLFIFODebugData = 0xC10, // MTL_FIFO_Debug_Data 281 MTLInterruptStatus = 0xC20, // MTL_Interrupt_Status 282 MTLReceiveQueueDMAMap0 = 0xC30, // MTL_RxQ_DMA_Map0 283 MTLTimeBasedSchedulingControl = 0xC40, // MTL_TBS_CTRL 284 MTLEnhancementsToScheduledTransmissionControl = 0xC50, // MTL_EST_Control 285 MTLEnhancementsToScheduledTransmissionExtendedControl = 0xC54, // MTL_EST_Ext_Control 286 MTLEnhancementsToScheduledTransmissionStatus = 0xC58, // MTL_EST_Status 287 MTLEnhancementsToScheduledTransmissionSchedulingError = 0xC60, // MTL_EST_Sch_Error 288 MTLEnhancementsToScheduledTransmissionFrameSizeError = 0xC64, // MTL_EST_Frm_Size_Error 289 MTLEnhancementsToScheduledTransmissionInterruptEnable = 0xC70, // MTL_EST_Intr_Enable 290 MTLEnhancementsToScheduledTransmissionGateControlList = 0xC80, // MTL_EST_GCL_Control 291 MTLEnhancementsToScheduledTransmissionGateControlData = 0xC84, // MTL_EST_GCL_Data 292 MTLFramePreemptionControlStatus = 0xC90, // MTL_FPE_CTRL_STS 293 MTLFramePreemptionAdvanceTime = 0xC94, // MTL_FPE_Advance 294 MTLReceiveParserControlStatus = 0xCA0, // MTL_RXP_Control_Status 295 MTLReceiveParserInterruptControlStatus = 0xCA4, // MTL_RXP_Interrupt_Control_Status 296 MTLReceiveParserDropCount = 0xCA8, // MTL_RXP_Drop_Cnt 297 MTLReceiveParserErrorCount = 0xCAC, // MTL_RXP_Error_Cnt 298 MTLReceiveParserIndirectAccessControlStatus = 0xCB0, // MTL_RXP_Indirect_Acc_Control_Status 299 MTLReceiveParserIndirectAccessData = 0xCB4, // MTL_RXP_Indirect_Acc_Data 300 MTLReceiveParserBypassCount = 0xCB8, // MTL_RXP_Bypass_Cnt 301 MTLErrorCorrectionControl = 0xCC0, // MTL_ECC_Control 302 MTLSafetyInterruptStatus = 0xCC4, // MTL_Safety_Interrupt_Status 303 MTLErrorCorrectionInterruptEnable = 0xCC8, // MTL_ECC_Interrupt_Enable 304 MTLErrorCorrectionInterruptStatus = 0xCCC, // MTL_ECC_Interrupt_Status 305 MTLErrorCorrectionErrorStatusCapture = 0xCD0, // MTL_ECC_Err_Sts_Rctl 306 MTLErrorCorrectionErrorAddressStatus = 0xCD4, // MTL_ECC_Err_Addr_Status 307 MTLErrorCorrectionErrorCountStatus = 0xCD8, // MTL_ECC_Err_Cntr_Status 308 MTLDataParityProtectionControl = 0xCE0, // MTL_DPP_Control 309 MTLTransmitQueue0OperationMode = 0xD00, // MTL_TxQ0_Operation_Mode 310 MTLTransmitQueue0Underflow = 0xD04, // MTL_TxQ0_Underflow 311 MTLTransmitQueue0Debug = 0xD08, // MTL_TxQ0_Debug 312 MTLTransmitQueue0ETSStatus = 0xD14, // MTL_TxQ0_ETS_Status 313 MTLTransmitQueue0QuantumWeight = 0xD18, // MTL_TxQ0_Quantum_Weight 314 MTLQueue0InterruptControlStatus = 0xD2C, // MTL_Q0_Interrupt_Control_Status 315 MTLReceiveQueue0OperationMode = 0xD30, // MTL_RxQ0_Operation_Mode 316 MTLReceiveQueue0MissedPacketOverflowCount = 0xD34, // MTL_RxQ0_Missed_Packet_Overflow_Cnt 317 MTLReceiveQueue0Debug = 0xD38, // MTL_RxQ0_Debug 318 MTLReceiveQueue0Control = 0xD3C, // MTL_RxQ0_Control 319 MTLTransmitQueue1OperationMode = 0xD40, // MTL_TxQ1_Operation_Mode 320 MTLTransmitQueue1Underflow = 0xD44, // MTL_TxQ1_Underflow 321 MTLTransmitQueue1Debug = 0xD48, // MTL_TxQ1_Debug 322 MTLTransmitQueue1ETSControl = 0xD50, // MTL_TxQ1_ETS_Control 323 MTLTransmitQueue1ETSStatus = 0xD54, // MTL_TxQ1_ETS_Status 324 MTLTransmitQueue1QuantumWeight = 0xD58, // MTL_TxQ1_Quantum_Weight 325 MTLTransmitQueue1SendSlopeCredit = 0xD5C, // MTL_TxQ1_SendSlopeCredit 326 MTLTransmitQueue1HighCredit = 0xD60, // MTL_TxQ1_HiCredit 327 MTLTransmitQueue1LowCredit = 0xD64, // MTL_TxQ1_LoCredit 328 MTLQueue1InterruptControlStatus = 0xD6C, // MTL_Q1_Interrupt_Control_Status 329 MTLReceiveQueue1OperationMode = 0xD70, // MTL_RxQ1_Operation_Mode 330 MTLReceiveQueue1MissedPacketOverflowCount = 0xD74, // MTL_RxQ1_Missed_Packet_Overflow_Cnt 331 MTLReceiveQueue1Debug = 0xD78, // MTL_RxQ1_Debug 332 MTLReceiveQueue1Control = 0xD7C, // MTL_RxQ1_Control 333 334 DMAMode = 0x1000, // DMA_Mode 335 DMASystemBusMode = 0x1004, // DMA_SysBus_Mode 336 DMAInterruptStatus = 0x1008, // DMA_Interrupt_Status 337 DMADebugStatus0 = 0x100C, // DMA_Debug_Status0 338 DMATBSControl0 = 0x1050, // DMA_TBS_CTRL0 339 DMASafetyInterruptStatus = 0x1080, // DMA_Safety_Interrupt_Status 340 341 DMAChannel0Control = 0x1100, // DMA_CH0_Control 342 DMAChannel0TransmitControl = 0x1104, // DMA_CH0_Tx_Control 343 DMAChannel0ReceiveControl = 0x1108, // DMA_CH0_Rx_Control 344 DMAChannel0TransmitDescriptorListAddress = 0x1114, // DMA_CH0_TxDesc_List_Address 345 DMAChannel0ReceiveDescriptorListAddress = 0x111C, // DMA_CH0_RxDesc_List_Address 346 DMAChannel0TransmitDescriptorTailPointer = 0x1120, // DMA_CH0_TxDesc_Tail_Pointer 347 DMAChannel0ReceiveDescriptorTailPointer = 0x1128, // DMA_CH0_RxDesc_Tail_Pointer 348 DMAChannel0TransmitDescriptorRingLength = 0x112C, // DMA_CH0_TxDesc_Ring_Length 349 DMAChannel0ReceiveDescriptorRingLength = 0x1130, // DMA_CH0_RxDesc_Ring_Length 350 DMAChannel0InterruptEnable = 0x1134, // DMA_CH0_Interrupt_Enable 351 DMAChannel0ReceiveInterruptWatchdogTimer = 0x1138, // DMA_CH0_Rx_Interrupt_Watchdog_Timer 352 DMAChannel0SlotFunctionControlStatus = 0x113C, // DMA_CH0_Slot_Function_Control_Status 353 DMAChannel0CurrentApplicationTransmitDescriptor = 0x1144, // DMA_CH0_Current_App_TxDesc 354 DMAChannel0CurrentApplicationReceiveDescriptor = 0x114C, // DMA_CH0_Current_App_RxDesc 355 DMAChannel0CurrentApplicationTransmitBuffer = 0x1154, // DMA_CH0_Current_App_TxBuffer 356 DMAChannel0CurrentApplicationReceiveBuffer = 0x115C, // DMA_CH0_Current_App_RxBuffer 357 DMAChannel0Status = 0x1160, // DMA_CH0_Status 358 DMAChannel0MissedFrameCount = 0x1164, // DMA_CH0_Miss_Frame_Cnt 359 DMAChannel0ReceiveParserAcceptCount = 0x1168, // DMA_CH0_RXP_Accept_Cnt 360 DMAChannel0ReceiveERICount = 0x116C, // DMA_CH0_RX_ERI_Cnt 361 362 DMAChannel1Control = 0x1180, // DMA_CH1_Control 363 DMAChannel1TransmitControl = 0x1184, // DMA_CH1_Tx_Control 364 DMAChannel1ReceiveControl = 0x1188, // DMA_CH1_Rx_Control 365 DMAChannel1TransmitDescriptorListAddress = 0x1194, // DMA_CH1_TxDesc_List_Address 366 DMAChannel1ReceiveDescriptorListAddress = 0x119C, // DMA_CH1_RxDesc_List_Address 367 DMAChannel1TransmitDescriptorTailPointer = 0x11A0, // DMA_CH1_TxDesc_Tail_Pointer 368 DMAChannel1ReceiveDescriptorTailPointer = 0x11A8, // DMA_CH1_RxDesc_Tail_Pointer 369 DMAChannel1TransmitDescriptorRingLength = 0x11AC, // DMA_CH1_TxDesc_Ring_Length 370 DMAChannel1ReceiveDescriptorRingLength = 0x11B0, // DMA_CH0_RxDesc_Ring_Length 371 DMAChannel1InterruptEnable = 0x11B4, // DMA_CH1_Interrupt_Enable 372 DMAChannel1ReceiveInterruptWatchdogTimer = 0x11B8, // DMA_CH1_Rx_Interrupt_Watchdog_Timer 373 DMAChannel1SlotFunctionControlStatus = 0x11BC, // DMA_CH1_Slot_Function_Control_Status 374 DMAChannel1CurrentApplicationTransmitDescriptor = 0x11C4, // DMA_CH1_Current_App_TxDesc 375 DMAChannel1CurrentApplicationReceiveDescriptor = 0x11CC, // DMA_CH1_Current_App_RxDesc 376 DMAChannel1CurrentApplicationTransmitBuffer = 0x11D4, // DMA_CH1_Current_App_TxBuffer 377 DMAChannel1CurrentApplicationReceiveBuffer = 0x11DC, // DMA_CH1_Current_App_RxBuffer 378 DMAChannel1Status = 0x11E0, // DMA_CH1_Status 379 DMAChannel1MissedFrameCount = 0x11E4, // DMA_CH1_Miss_Frame_Cnt 380 DMAChannel1ReceiveParserAcceptCount = 0x11E8, // DMA_CH1_RXP_Accept_Cnt 381 DMAChannel1ReceiveERICount = 0x11EC, // DMA_CH1_RX_ERI_Cnt 382 } 383 } 384 }
