1 //
2 // Copyright (c) 2010-2024 Antmicro
3 // Copyright (c) 2020-2023 Microchip
4 //
5 // This file is licensed under the MIT License.
6 // Full license text is available in 'licenses/MIT.txt'.
7 //
8 
9 using Antmicro.Renode.Peripherals.Bus;
10 using Antmicro.Renode.Logging;
11 
12 namespace Antmicro.Renode.Peripherals.Miscellaneous
13 {
14     /*
15      * This class is a mock designed to allow DDR training software to pass.
16      * All writes are ignored.
17      */
18     public class MPFS_DDRMock : IDoubleWordPeripheral, IBytePeripheral, IKnownSize
19     {
ReadDoubleWord(long offset)20         public uint ReadDoubleWord(long offset)
21         {
22             var value = 0x0u;
23             switch(offset)
24             {
25                 case 0x08: /* DDRPHY_STARTUP */
26                     value = 0x200;
27                     break;
28                 case 0x010: /* PLL_DI_0_1 */
29                     value = 0x200;
30                     break;
31                 case 0x02C: /* SSCG_REG_2 */
32                     value = 0xFFFFFFFF;
33                     break;
34                 case 0x0B4: /* RPC_RESET_MAIN_PLL */
35                     value = 0x52454E44; //In HW, this would return 0x00, returning this signature instead.
36                     break;
37                 case 0x864: /* ADDCMD_STATUS0 */
38                     value = 0x44332211;
39                     break;
40                 case 0x868: /* ADDCMD_STATUS_1 */
41                     value = 0xDDCCBBAA;
42                     break;
43                 case 0x81C: /* GT_ERR_COMB */
44                     value = 0x0;
45                     break;
46                 case 0x820: /* GT_CLK_SEL */
47                     value = 0x0;
48                     break;
49                 case 0x824: /* GT_TXDLY */
50                     value = 0xFFFFFFFF;
51                     break;
52                 case 0x834: /* DQ_DQS_ERR_DONE */
53                     value = 0x8;
54                     break;
55                 case 0x84C: /* DQDQS_STATUS1 */
56                     value = 0xFF;
57                     break;
58                 case 0x850: /* DQDQS_STATUS2 */
59                     value = 0xFF;
60                     break;
61                 case 0xC08: /* PLL_CNTL */
62                     value = 0xFF;
63                     break;
64                 default:
65                     value = 0xFFFFFFFF * readToggle;
66                     readToggle = 1 - readToggle;
67                     break;
68             }
69             this.Log(LogLevel.Noisy, "Reading double word from DDR controller - offset: 0x{0:X}, value: 0x{1:X}", offset, value);
70             return value;
71         }
72 
WriteDoubleWord(long offset, uint value)73         public void WriteDoubleWord(long offset, uint value)
74         {
75             // intentionally left blank
76         }
77 
ReadByte(long offset)78         public byte ReadByte(long offset)
79         {
80             byte value = 0x0;
81 
82             switch(offset)
83             {
84                 case 0x814:
85                     value = (byte)(1 << byteRead);
86                     byteRead = (byteRead + 1) % 5;
87                     break;
88                 case 0x834:
89                     value = 0x8;
90                     break;
91                 case 0x84C:
92                 case 0x84D:
93                 case 0x84E:
94                 case 0x84F:
95                     value = 0xFF;
96                     break;
97                 default:
98                     value = 0x0;
99                     break;
100             }
101             this.Log(LogLevel.Noisy, "Read byte from DDR controller - offset: 0x{0:X}, value 0x{1:X}", offset, value);
102             return value;
103         }
104 
WriteByte(long offset, byte value)105         public void WriteByte(long offset, byte value)
106         {
107             // intentionally left blank
108         }
109 
Reset()110         public void Reset()
111         {
112             byteRead = 0x0;
113             readToggle = 0x0;
114         }
115 
116         public long Size => 0x1000; // Size is address space on sysbus
117 
118         private uint readToggle = 0x0;
119         private int byteRead = 0x0;
120     }
121 }
122