1 // 2 // Copyright (c) 2010-2023 Antmicro 3 // 4 // This file is licensed under the MIT License. 5 // Full license text is available in 'licenses/MIT.txt'. 6 // 7 using Antmicro.Renode.Core; 8 using Antmicro.Renode.Core.Structure.Registers; 9 10 namespace Antmicro.Renode.Peripherals.MemoryControllers 11 { 12 public class OpenTitan_SRAMController: BasicDoubleWordPeripheral, IKnownSize 13 { OpenTitan_SRAMController(IMachine machine)14 public OpenTitan_SRAMController(IMachine machine): base(machine) 15 { 16 FatalError = new GPIO(); 17 DefineRegisters(); 18 Reset(); 19 } 20 21 public long Size => 0x20; 22 23 public GPIO FatalError { get; } 24 DefineRegisters()25 public void DefineRegisters() 26 { 27 Registers.AlertTest.Define(this) 28 .WithFlag(0, FieldMode.Write, writeCallback: (_, val) => { if(val) FatalError.Blink(); }, name: "FATAL_ERROR") 29 .WithReservedBits(1, 31); 30 31 Registers.Status.Define(this) 32 .WithTaggedFlag("BUS_INTEG_ERROR", 0) 33 .WithTaggedFlag("INIT_ERROR", 1) 34 .WithTaggedFlag("ESCALATED", 2) 35 .WithTaggedFlag("SCR_KEY_VALID", 3) 36 .WithTaggedFlag("SCR_KEY_SEED_VALID", 4) 37 .WithTaggedFlag("INIT_DONE", 5) 38 .WithReservedBits(6, 26); 39 40 Registers.ExecutionEnableWriteEnable.Define(this, 0x1) 41 .WithTaggedFlag("EXEC_REGWEN", 0) 42 .WithReservedBits(1, 31); 43 44 Registers.ExecutionEnable.Define(this, 0x9) 45 .WithTag("EN", 0, 4) 46 .WithReservedBits(4, 28); 47 48 Registers.ControlWriteEnable.Define(this, 0x1) 49 .WithTaggedFlag("CTRL_REGWEN", 0) 50 .WithReservedBits(1, 31); 51 52 Registers.Control.Define(this) 53 .WithTaggedFlag("RENEW_SCR_KEY", 0) 54 .WithTaggedFlag("INIT", 1) 55 .WithReservedBits(2, 30); 56 } 57 58 public enum Registers 59 { 60 AlertTest = 0x0, 61 Status = 0x4, 62 ExecutionEnableWriteEnable = 0x8, 63 ExecutionEnable = 0xc, 64 ControlWriteEnable = 0x10, 65 Control = 0x14, 66 } 67 } 68 }