1 // 2 // Copyright (c) 2010-2018 Antmicro 3 // Copyright (c) 2011-2015 Realtime Embedded 4 // 5 // This file is licensed under the MIT License. 6 // Full license text is available in 'licenses/MIT.txt'. 7 // 8 using System; 9 using Antmicro.Renode.Core; 10 using Antmicro.Renode.Logging; 11 12 namespace Antmicro.Renode.Peripherals.I2C 13 { 14 public class TegraDVC : TegraI2CController 15 { TegraDVC(IMachine machine)16 public TegraDVC(IMachine machine) : base(machine) 17 { 18 } 19 ReadDoubleWord(long offset)20 public override uint ReadDoubleWord (long offset) 21 { 22 if (offset < 0x40) { 23 switch ((Registers)offset) { 24 case Registers.Control1: 25 return control [0]; 26 case Registers.Control2: 27 return control [1]; 28 case Registers.Control3: 29 return control [2]; 30 case Registers.Status: 31 return status; 32 default: 33 this.LogUnhandledRead(offset); 34 return 0; 35 } 36 } 37 return base.ReadDoubleWord ((offset >= 0x60) ? offset - 0x10 : offset - 0x40); 38 } 39 WriteDoubleWord(long offset, uint value)40 public override void WriteDoubleWord (long offset, uint value) 41 { 42 if (offset < 0x40) { 43 switch ((Registers)offset) { 44 case Registers.Control1: 45 control [0] = value; 46 break; 47 case Registers.Control2: 48 control [1] = value; 49 break; 50 case Registers.Control3: 51 control [2] = value; 52 break; 53 case Registers.Status: 54 status = value; 55 break; 56 default: 57 this.LogUnhandledWrite(offset, value); 58 break; 59 } 60 return; 61 } 62 base.WriteDoubleWord ((offset >= 0x60) ? offset - 0x10 : offset - 0x40 , value); 63 } 64 65 private uint status; 66 private uint[] control = new uint[3]; 67 private enum Registers 68 { 69 Control1 = 0x0, 70 Control2 = 0x4, 71 Control3 = 0x8, 72 Status = 0xC, 73 } 74 } 75 } 76 77