1 // 2 // Copyright (c) 2010-2024 Antmicro 3 // 4 // This file is licensed under the MIT License. 5 // Full license text is available in 'licenses/MIT.txt'. 6 // 7 8 using System.Collections.Generic; 9 using Antmicro.Renode.Core; 10 11 namespace Antmicro.Renode.Peripherals.GPIOPort 12 { 13 public class RenesasRA8_GPIO : RenesasRA_GPIO 14 { RenesasRA8_GPIO(IMachine machine, int portNumber, int numberOfConnections, RenesasRA_GPIOMisc pfsMisc)15 public RenesasRA8_GPIO(IMachine machine, int portNumber, int numberOfConnections, RenesasRA_GPIOMisc pfsMisc) 16 : base(machine, portNumber, numberOfConnections, pfsMisc) 17 { 18 // Intentionally left blank 19 } 20 21 protected override List<InterruptOutput>[] PinInterruptOutputs => new List<InterruptOutput>[] 22 { 23 /* PORT0 */ new List<InterruptOutput> 24 { 25 new InterruptOutput(0, IRQ6), 26 new InterruptOutput(1, IRQ7), 27 new InterruptOutput(2, IRQ8), 28 new InterruptOutput(4, IRQ9), 29 new InterruptOutput(5, IRQ10), 30 new InterruptOutput(6, IRQ11), 31 new InterruptOutput(8, IRQ12), 32 new InterruptOutput(9, IRQ13), 33 new InterruptOutput(10, IRQ14), 34 new InterruptOutput(15, IRQ13), 35 }, 36 /* PORT1 */ new List<InterruptOutput> 37 { 38 new InterruptOutput(0, IRQ2), 39 new InterruptOutput(1, IRQ1), 40 new InterruptOutput(4, IRQ1), 41 new InterruptOutput(5, IRQ0), 42 }, 43 /* PORT2 */ new List<InterruptOutput> 44 { 45 new InterruptOutput(2, IRQ3), 46 new InterruptOutput(3, IRQ2), 47 new InterruptOutput(5, IRQ1), 48 new InterruptOutput(6, IRQ0), 49 new InterruptOutput(8, IRQ3), 50 new InterruptOutput(12, IRQ3), 51 new InterruptOutput(13, IRQ2), 52 }, 53 /* PORT3 */ new List<InterruptOutput> 54 { 55 new InterruptOutput(0, IRQ4), 56 new InterruptOutput(1, IRQ6), 57 new InterruptOutput(2, IRQ5), 58 new InterruptOutput(4, IRQ9), 59 new InterruptOutput(5, IRQ8), 60 }, 61 /* PORT4 */ new List<InterruptOutput> 62 { 63 new InterruptOutput(0, IRQ0), 64 new InterruptOutput(1, IRQ5), 65 new InterruptOutput(2, IRQ4), 66 new InterruptOutput(3, IRQ14), 67 new InterruptOutput(4, IRQ15), 68 new InterruptOutput(8, IRQ7), 69 new InterruptOutput(9, IRQ6), 70 new InterruptOutput(10, IRQ5), 71 new InterruptOutput(11, IRQ4), 72 new InterruptOutput(14, IRQ9), 73 new InterruptOutput(15, IRQ8), 74 }, 75 /* PORT5 */ new List<InterruptOutput> 76 { 77 new InterruptOutput(8, IRQ1), 78 new InterruptOutput(9, IRQ2), 79 new InterruptOutput(10, IRQ3), 80 new InterruptOutput(11, IRQ15), 81 new InterruptOutput(12, IRQ14), 82 }, 83 /* PORT6 */ new List<InterruptOutput> 84 { 85 new InterruptOutput(15, IRQ7), 86 }, 87 /* PORT7 */ new List<InterruptOutput> 88 { 89 new InterruptOutput(6, IRQ7), 90 new InterruptOutput(7, IRQ8), 91 new InterruptOutput(8, IRQ11), 92 new InterruptOutput(9, IRQ10), 93 }, 94 /* PORT8 */ new List<InterruptOutput> 95 { 96 new InterruptOutput(0, IRQ11), 97 new InterruptOutput(1, IRQ12), 98 new InterruptOutput(4, IRQ14), 99 new InterruptOutput(6, IRQ0), 100 new InterruptOutput(8, IRQ15), 101 }, 102 /* PORT9 */ new List<InterruptOutput> 103 { 104 new InterruptOutput(5, IRQ8), 105 new InterruptOutput(6, IRQ9), 106 new InterruptOutput(7, IRQ10), 107 new InterruptOutput(8, IRQ11), 108 }, 109 /* PORTA */ new List<InterruptOutput> 110 { 111 new InterruptOutput(8, IRQ6), 112 new InterruptOutput(9, IRQ5), 113 new InterruptOutput(10, IRQ4), 114 }, 115 /* PORTB */ new List<InterruptOutput> 116 { 117 // Intentionally left blank 118 }, 119 }; 120 } 121 } 122