1 // 2 // Copyright (c) 2010-2025 Antmicro 3 // Copyright (c) 2022-2025 Silicon Labs 4 // 5 // This file is licensed under the MIT License. 6 // Full license text is available in 'licenses/MIT.txt'. 7 // 8 9 using System.Collections.Generic; 10 using System.IO; 11 using System; 12 using Antmicro.Renode.Core; 13 using Antmicro.Renode.Core.Structure.Registers; 14 using Antmicro.Renode.Exceptions; 15 using Antmicro.Renode.Logging; 16 using Antmicro.Renode.Peripherals.Bus; 17 using Antmicro.Renode.Time; 18 using Antmicro.Renode.Peripherals.GPIOPort; 19 20 namespace Antmicro.Renode.Peripherals.GPIOPort 21 { 22 public class EFR32xG2_GPIO_3 : BaseGPIOPort, IDoubleWordPeripheral, IKnownSize 23 { EFR32xG2_GPIO_3(Machine machine)24 public EFR32xG2_GPIO_3(Machine machine) : base(machine, NumberOfPins * NumberOfPorts) 25 { 26 OddIRQ = new GPIO(); 27 EvenIRQ = new GPIO(); 28 29 registersCollection = BuildRegistersCollection(); 30 InnerReset(); 31 } 32 Reset()33 public override void Reset() 34 { 35 lock(internalLock) 36 { 37 base.Reset(); 38 InnerReset(); 39 } 40 } 41 ReadDoubleWord(long offset)42 public uint ReadDoubleWord(long offset) 43 { 44 return ReadRegister(offset); 45 } 46 ReadByte(long offset)47 public byte ReadByte(long offset) 48 { 49 int byteOffset = (int)(offset & 0x3); 50 uint registerValue = ReadRegister(offset, true); 51 byte result = (byte)((registerValue >> byteOffset*8) & 0xFF); 52 return result; 53 } 54 ReadRegister(long offset, bool internal_read = false)55 private uint ReadRegister(long offset, bool internal_read = false) 56 { 57 var result = 0U; 58 long internal_offset = offset; 59 60 lock(internalLock) 61 { 62 // Set, Clear, Toggle registers should only be used for write operations. But just in case we convert here as well. 63 if (offset >= SetRegisterOffset && offset < ClearRegisterOffset) 64 { 65 // Set register 66 internal_offset = offset - SetRegisterOffset; 67 if(!internal_read) 68 { 69 this.Log(LogLevel.Noisy, "SET Operation on {0}, offset=0x{1:X}, internal_offset=0x{2:X}", (Registers)internal_offset, offset, internal_offset); 70 } 71 } else if (offset >= ClearRegisterOffset && offset < ToggleRegisterOffset) 72 { 73 // Clear register 74 internal_offset = offset - ClearRegisterOffset; 75 if(!internal_read) 76 { 77 this.Log(LogLevel.Noisy, "CLEAR Operation on {0}, offset=0x{1:X}, internal_offset=0x{2:X}", (Registers)internal_offset, offset, internal_offset); 78 } 79 } else if (offset >= ToggleRegisterOffset) 80 { 81 // Toggle register 82 internal_offset = offset - ToggleRegisterOffset; 83 if(!internal_read) 84 { 85 this.Log(LogLevel.Noisy, "TOGGLE Operation on {0}, offset=0x{1:X}, internal_offset=0x{2:X}", (Registers)internal_offset, offset, internal_offset); 86 } 87 } 88 89 if(!registersCollection.TryRead(internal_offset, out result)) 90 { 91 if(!internal_read) 92 { 93 this.Log(LogLevel.Noisy, "Unhandled read at offset 0x{0:X} ({1}).", internal_offset, (Registers)internal_offset); 94 } 95 } 96 else 97 { 98 if(!internal_read) 99 { 100 this.Log(LogLevel.Noisy, "Read at offset 0x{0:X} ({1}), returned 0x{2:X}.", internal_offset, (Registers)internal_offset, result); 101 } 102 } 103 104 return result; 105 } 106 } 107 WriteDoubleWord(long offset, uint value)108 public void WriteDoubleWord(long offset, uint value) 109 { 110 // TODO: A subset of registers is lockable: if the lock is on (see LockStatus register), these registers should not be accessible. 111 WriteRegister(offset, value); 112 } 113 WriteRegister(long offset, uint value, bool internal_write = false)114 private void WriteRegister(long offset, uint value, bool internal_write = false) 115 { 116 lock(internalLock) 117 { 118 long internal_offset = offset; 119 uint internal_value = value; 120 121 if (offset >= SetRegisterOffset && offset < ClearRegisterOffset) 122 { 123 // Set register 124 internal_offset = offset - SetRegisterOffset; 125 uint old_value = ReadRegister(internal_offset, true); 126 internal_value = old_value | value; 127 this.Log(LogLevel.Noisy, "SET Operation on {0}, offset=0x{1:X}, internal_offset=0x{2:X}, SET_value=0x{3:X}, old_value=0x{4:X}, new_value=0x{5:X}", (Registers)internal_offset, offset, internal_offset, value, old_value, internal_value); 128 } else if (offset >= ClearRegisterOffset && offset < ToggleRegisterOffset) 129 { 130 // Clear register 131 internal_offset = offset - ClearRegisterOffset; 132 uint old_value = ReadRegister(internal_offset, true); 133 internal_value = old_value & ~value; 134 this.Log(LogLevel.Noisy, "CLEAR Operation on {0}, offset=0x{1:X}, internal_offset=0x{2:X}, CLEAR_value=0x{3:X}, old_value=0x{4:X}, new_value=0x{5:X}", (Registers)internal_offset, offset, internal_offset, value, old_value, internal_value); 135 } else if (offset >= ToggleRegisterOffset) 136 { 137 // Toggle register 138 internal_offset = offset - ToggleRegisterOffset; 139 uint old_value = ReadRegister(internal_offset, true); 140 internal_value = old_value ^ value; 141 this.Log(LogLevel.Noisy, "TOGGLE Operation on {0}, offset=0x{1:X}, internal_offset=0x{2:X}, TOGGLE_value=0x{3:X}, old_value=0x{4:X}, new_value=0x{5:X}", (Registers)internal_offset, offset, internal_offset, value, old_value, internal_value); 142 } 143 144 this.Log(LogLevel.Noisy, "Write at offset 0x{0:X} ({1}), value 0x{2:X}.", internal_offset, (Registers)internal_offset, internal_value); 145 146 if(!registersCollection.TryWrite(internal_offset, internal_value)) 147 { 148 this.Log(LogLevel.Noisy, "Unhandled write at offset 0x{0:X} ({1}), value 0x{2:X}.", internal_offset, (Registers)internal_offset, internal_value); 149 return; 150 } 151 } 152 } 153 BuildRegistersCollection()154 private DoubleWordRegisterCollection BuildRegistersCollection() 155 { 156 var registerDictionary = new Dictionary<long, DoubleWordRegister> 157 { 158 {(long)Registers.ExternalInterruptPortSelectLow, new DoubleWordRegister(this) 159 .WithEnumField<DoubleWordRegister, Port>(0, 2, out externalInterruptPortSelect[0], name: "EXTIPSEL0") 160 .WithReservedBits(2, 2) 161 .WithEnumField<DoubleWordRegister, Port>(4, 2, out externalInterruptPortSelect[1], name: "EXTIPSEL1") 162 .WithReservedBits(6, 2) 163 .WithEnumField<DoubleWordRegister, Port>(8, 2, out externalInterruptPortSelect[2], name: "EXTIPSEL2") 164 .WithReservedBits(10, 2) 165 .WithEnumField<DoubleWordRegister, Port>(12, 2, out externalInterruptPortSelect[3], name: "EXTIPSEL3") 166 .WithReservedBits(14, 2) 167 .WithEnumField<DoubleWordRegister, Port>(16, 2, out externalInterruptPortSelect[4], name: "EXTIPSEL4") 168 .WithReservedBits(18, 2) 169 .WithEnumField<DoubleWordRegister, Port>(20, 2, out externalInterruptPortSelect[5], name: "EXTIPSEL5") 170 .WithReservedBits(22, 2) 171 .WithEnumField<DoubleWordRegister, Port>(24, 2, out externalInterruptPortSelect[6], name: "EXTIPSEL6") 172 .WithReservedBits(26, 2) 173 .WithEnumField<DoubleWordRegister, Port>(28, 2, out externalInterruptPortSelect[7], name: "EXTIPSEL7") 174 .WithReservedBits(30, 2) 175 .WithChangeCallback((_, __) => UpdateRouting()) 176 }, 177 {(long)Registers.ExternalInterruptPortSelectHigh, new DoubleWordRegister(this) 178 .WithEnumField<DoubleWordRegister, Port>(0, 2, out externalInterruptPortSelect[8], name: "EXTIPSEL8") 179 .WithReservedBits(2, 2) 180 .WithEnumField<DoubleWordRegister, Port>(4, 2, out externalInterruptPortSelect[9], name: "EXTIPSEL9") 181 .WithReservedBits(6, 2) 182 .WithEnumField<DoubleWordRegister, Port>(8, 2, out externalInterruptPortSelect[10], name: "EXTIPSEL10") 183 .WithReservedBits(10, 2) 184 .WithEnumField<DoubleWordRegister, Port>(12, 2, out externalInterruptPortSelect[11], name: "EXTIPSEL11") 185 .WithReservedBits(14, 2) 186 .WithEnumField<DoubleWordRegister, Port>(16, 2, out externalInterruptPortSelect[12], name: "EXTIPSEL12") 187 .WithReservedBits(18, 2) 188 .WithEnumField<DoubleWordRegister, Port>(20, 2, out externalInterruptPortSelect[13], name: "EXTIPSEL13") 189 .WithReservedBits(22, 2) 190 .WithEnumField<DoubleWordRegister, Port>(24, 2, out externalInterruptPortSelect[14], name: "EXTIPSEL14") 191 .WithReservedBits(26, 2) 192 .WithEnumField<DoubleWordRegister, Port>(28, 2, out externalInterruptPortSelect[15], name: "EXTIPSEL15") 193 .WithReservedBits(30, 2) 194 .WithChangeCallback((_, __) => UpdateRouting()) 195 }, 196 {(long)Registers.ExternalInterruptPinSelectLow, new DoubleWordRegister(this) 197 .WithValueField(0, 2, out externalInterruptPinSelect[0], name: "EXTIPINSEL0") 198 .WithReservedBits(2, 2) 199 .WithValueField(4, 2, out externalInterruptPinSelect[1], name: "EXTIPINSEL1") 200 .WithReservedBits(6, 2) 201 .WithValueField(8, 2, out externalInterruptPinSelect[2], name: "EXTIPINSEL2") 202 .WithReservedBits(10, 2) 203 .WithValueField(12, 2, out externalInterruptPinSelect[3], name: "EXTIPINSEL3") 204 .WithReservedBits(14, 2) 205 .WithValueField(16, 2, out externalInterruptPinSelect[4], name: "EXTIPINSEL4") 206 .WithReservedBits(18, 2) 207 .WithValueField(20, 2, out externalInterruptPinSelect[5], name: "EXTIPINSEL5") 208 .WithReservedBits(22, 2) 209 .WithValueField(24, 2, out externalInterruptPinSelect[6], name: "EXTIPINSEL6") 210 .WithReservedBits(26, 2) 211 .WithValueField(28, 2, out externalInterruptPinSelect[7], name: "EXTIPINSEL7") 212 .WithReservedBits(30, 2) 213 .WithChangeCallback((_, __) => UpdateRouting()) 214 }, 215 {(long)Registers.ExternalInterruptPinSelectHigh, new DoubleWordRegister(this) 216 .WithValueField(0, 2, out externalInterruptPinSelect[8], name: "EXTIPINSEL8") 217 .WithReservedBits(2, 2) 218 .WithValueField(4, 2, out externalInterruptPinSelect[9], name: "EXTIPINSEL9") 219 .WithReservedBits(6, 2) 220 .WithValueField(8, 2, out externalInterruptPinSelect[10], name: "EXTIPINSEL10") 221 .WithReservedBits(10, 2) 222 .WithValueField(12, 2, out externalInterruptPinSelect[11], name: "EXTIPINSEL11") 223 .WithReservedBits(14, 2) 224 .WithValueField(16, 2, out externalInterruptPinSelect[12], name: "EXTIPINSEL12") 225 .WithReservedBits(18, 2) 226 .WithValueField(20, 2, out externalInterruptPinSelect[13], name: "EXTIPINSEL13") 227 .WithReservedBits(22, 2) 228 .WithValueField(24, 2, out externalInterruptPinSelect[14], name: "EXTIPINSEL14") 229 .WithReservedBits(26, 2) 230 .WithValueField(28, 2, out externalInterruptPinSelect[15], name: "EXTIPINSEL15") 231 .WithReservedBits(30, 2) 232 .WithChangeCallback((_, __) => UpdateRouting()) 233 }, 234 {(long)Registers.ExternalInterruptRisingEdgeTrigger, new DoubleWordRegister(this) 235 .WithFlags(0, 16, 236 writeCallback: (i, _, value) => 237 { 238 if (value) 239 { 240 interruptTrigger[i] |= (uint)InterruptTrigger.RisingEdge; 241 } 242 else 243 { 244 interruptTrigger[i] ^= (uint)InterruptTrigger.RisingEdge; 245 } 246 }, 247 valueProviderCallback: (i, _) => ((interruptTrigger[i] & (uint)InterruptTrigger.RisingEdge) > 0), 248 name: "EXTIRISE") 249 .WithReservedBits(16, 16) 250 }, 251 {(long)Registers.ExternalInterruptFallingEdgeTrigger, new DoubleWordRegister(this) 252 .WithFlags(0, 16, 253 writeCallback: (i, _, value) => 254 { 255 if (value) 256 { 257 interruptTrigger[i] |= (uint)InterruptTrigger.FallingEdge; 258 } 259 else 260 { 261 interruptTrigger[i] ^= (uint)InterruptTrigger.FallingEdge; 262 } 263 }, 264 valueProviderCallback: (i, _) => ((interruptTrigger[i] & (uint)InterruptTrigger.FallingEdge) > 0), 265 name: "EXTIFALL") 266 .WithReservedBits(16, 16) 267 }, 268 {(long)Registers.InterruptFlag, new DoubleWordRegister(this) 269 .WithFlag(0, out externalInterrupt[0], name: "EXTIF0") 270 .WithFlag(1, out externalInterrupt[1], name: "EXTIF1") 271 .WithFlag(2, out externalInterrupt[2], name: "EXTIF2") 272 .WithFlag(3, out externalInterrupt[3], name: "EXTIF3") 273 .WithFlag(4, out externalInterrupt[4], name: "EXTIF4") 274 .WithFlag(5, out externalInterrupt[5], name: "EXTIF5") 275 .WithFlag(6, out externalInterrupt[6], name: "EXTIF6") 276 .WithFlag(7, out externalInterrupt[7], name: "EXTIF7") 277 .WithFlag(8, out externalInterrupt[8], name: "EXTIF8") 278 .WithFlag(9, out externalInterrupt[9], name: "EXTIF9") 279 .WithFlag(10, out externalInterrupt[10], name: "EXTIF10") 280 .WithFlag(11, out externalInterrupt[11], name: "EXTIF11") 281 .WithFlag(12, out externalInterrupt[12], name: "EXTIF12") 282 .WithFlag(13, out externalInterrupt[13], name: "EXTIF13") 283 .WithFlag(14, out externalInterrupt[14], name: "EXTIF14") 284 .WithFlag(15, out externalInterrupt[15], name: "EXTIF15") 285 .WithTaggedFlag("EM4WUIF0", 16) 286 .WithTaggedFlag("EM4WUIF1", 17) 287 .WithTaggedFlag("EM4WUIF2", 18) 288 .WithTaggedFlag("EM4WUIF3", 19) 289 .WithTaggedFlag("EM4WUIF4", 20) 290 .WithTaggedFlag("EM4WUIF5", 21) 291 .WithTaggedFlag("EM4WUIF6", 22) 292 .WithTaggedFlag("EM4WUIF7", 23) 293 .WithTaggedFlag("EM4WUIF8", 24) 294 .WithTaggedFlag("EM4WUIF9", 25) 295 .WithTaggedFlag("EM4WUIF10", 26) 296 .WithTaggedFlag("EM4WUIF11", 27) 297 .WithTaggedFlag("EM4WUIF12", 28) 298 .WithTaggedFlag("EM4WUIF13", 29) 299 .WithTaggedFlag("EM4WUIF14", 30) 300 .WithTaggedFlag("EM4WUIF15", 31) 301 .WithWriteCallback((_, __) => UpdateInterrupts()) 302 }, 303 {(long)Registers.InterruptEnable, new DoubleWordRegister(this) 304 .WithFlag(0, out externalInterruptEnable[0], name: "EXTIEN0") 305 .WithFlag(1, out externalInterruptEnable[1], name: "EXTIEN1") 306 .WithFlag(2, out externalInterruptEnable[2], name: "EXTIEN2") 307 .WithFlag(3, out externalInterruptEnable[3], name: "EXTIEN3") 308 .WithFlag(4, out externalInterruptEnable[4], name: "EXTIEN4") 309 .WithFlag(5, out externalInterruptEnable[5], name: "EXTIEN5") 310 .WithFlag(6, out externalInterruptEnable[6], name: "EXTIEN6") 311 .WithFlag(7, out externalInterruptEnable[7], name: "EXTIEN7") 312 .WithFlag(8, out externalInterruptEnable[8], name: "EXTIEN8") 313 .WithFlag(9, out externalInterruptEnable[9], name: "EXTIEN9") 314 .WithFlag(10, out externalInterruptEnable[10], name: "EXTIEN10") 315 .WithFlag(11, out externalInterruptEnable[11], name: "EXTIEN11") 316 .WithFlag(12, out externalInterruptEnable[12], name: "EXTIEN12") 317 .WithFlag(13, out externalInterruptEnable[13], name: "EXTIEN13") 318 .WithFlag(14, out externalInterruptEnable[14], name: "EXTIEN14") 319 .WithFlag(15, out externalInterruptEnable[15], name: "EXTIEN15") 320 .WithTaggedFlag("EM4WUIEN0", 16) 321 .WithTaggedFlag("EM4WUIEN1", 17) 322 .WithTaggedFlag("EM4WUIEN2", 18) 323 .WithTaggedFlag("EM4WUIEN3", 19) 324 .WithTaggedFlag("EM4WUIEN4", 20) 325 .WithTaggedFlag("EM4WUIEN5", 21) 326 .WithTaggedFlag("EM4WUIEN6", 22) 327 .WithTaggedFlag("EM4WUIEN7", 23) 328 .WithTaggedFlag("EM4WUIEN8", 24) 329 .WithTaggedFlag("EM4WUIEN9", 25) 330 .WithTaggedFlag("EM4WUIEN10", 26) 331 .WithTaggedFlag("EM4WUIEN11", 27) 332 .WithTaggedFlag("EM4WUIEN12", 28) 333 .WithTaggedFlag("EM4WUIEN13", 29) 334 .WithTaggedFlag("EM4WUIEN14", 30) 335 .WithTaggedFlag("EM4WUIEN15", 31) 336 .WithWriteCallback((_, __) => UpdateInterrupts()) 337 }, 338 {(long)Registers.Lock, new DoubleWordRegister(this) 339 .WithValueField(0, 16, writeCallback: (_, value) => configurationLocked = (value != UnlockCode), name: "LOCKKEY") 340 .WithReservedBits(16, 16) 341 }, 342 {(long)Registers.LockStatus, new DoubleWordRegister(this) 343 .WithFlag(0, FieldMode.Read, valueProviderCallback: _ => configurationLocked, name: "LOCK") 344 .WithReservedBits(1, 31) 345 }, 346 {(long)Registers.USART0_RouteEnable, new DoubleWordRegister(this) 347 .WithFlag(0, out USART0_RouteEnable_CsPin, name: "CSPEN") 348 .WithFlag(1, out USART0_RouteEnable_RtsPin, name: "RTSPEN") 349 .WithFlag(2, out USART0_RouteEnable_RxPin, name: "RXPEN") 350 .WithFlag(3, out USART0_RouteEnable_SclkPin, name: "SCLKPEN") 351 .WithFlag(4, out USART0_RouteEnable_TxPin, name: "TXPEN") 352 }, 353 {(long)Registers.USART0_RX_Route, new DoubleWordRegister(this) 354 .WithEnumField<DoubleWordRegister, Port>(0, 2, out USART0_RxRoutePort, name: "PORT") 355 .WithReservedBits(2, 14) 356 .WithValueField(16, 4, out USART0_RxRoutePin, name: "PIN") 357 .WithReservedBits(20, 12) 358 }, 359 {(long)Registers.USART0_TX_Route, new DoubleWordRegister(this) 360 .WithEnumField<DoubleWordRegister, Port>(0, 2, out USART0_TxRoutePort, name: "PORT") 361 .WithReservedBits(2, 14) 362 .WithValueField(16, 4, out USART0_TxRoutePin, name: "PIN") 363 .WithReservedBits(20, 12) 364 }, 365 {(long)Registers.EUSART0_RouteEnable, new DoubleWordRegister(this) 366 .WithFlag(0, out EUSART0_RouteEnable_CsPin, name: "CSPEN") 367 .WithFlag(1, out EUSART0_RouteEnable_RtsPin, name: "RTSPEN") 368 .WithFlag(2, out EUSART0_RouteEnable_RxPin, name: "RXPEN") 369 .WithFlag(3, out EUSART0_RouteEnable_SclkPin, name: "SCLKPEN") 370 .WithFlag(4, out EUSART0_RouteEnable_TxPin, name: "TXPEN") 371 }, 372 {(long)Registers.EUSART0_RX_Route, new DoubleWordRegister(this) 373 .WithEnumField<DoubleWordRegister, Port>(0, 2, out EUSART0_RxRoutePort, name: "PORT") 374 .WithReservedBits(2, 14) 375 .WithValueField(16, 4, out EUSART0_RxRoutePin, name: "PIN") 376 .WithReservedBits(20, 12) 377 }, 378 {(long)Registers.EUSART0_TX_Route, new DoubleWordRegister(this) 379 .WithEnumField<DoubleWordRegister, Port>(0, 2, out EUSART0_TxRoutePort, name: "PORT") 380 .WithReservedBits(2, 14) 381 .WithValueField(16, 4, out EUSART0_TxRoutePin, name: "PIN") 382 .WithReservedBits(20, 12) 383 }, 384 {(long)Registers.EUSART1_RouteEnable, new DoubleWordRegister(this) 385 .WithFlag(0, out EUSART1_RouteEnable_CsPin, name: "CSPEN") 386 .WithFlag(1, out EUSART1_RouteEnable_RtsPin, name: "RTSPEN") 387 .WithFlag(2, out EUSART1_RouteEnable_RxPin, name: "RXPEN") 388 .WithFlag(3, out EUSART1_RouteEnable_SclkPin, name: "SCLKPEN") 389 .WithFlag(4, out EUSART1_RouteEnable_TxPin, name: "TXPEN") 390 }, 391 {(long)Registers.EUSART1_RX_Route, new DoubleWordRegister(this) 392 .WithEnumField<DoubleWordRegister, Port>(0, 2, out EUSART1_RxRoutePort, name: "PORT") 393 .WithReservedBits(2, 14) 394 .WithValueField(16, 4, out EUSART1_RxRoutePin, name: "PIN") 395 .WithReservedBits(20, 12) 396 }, 397 {(long)Registers.EUSART1_TX_Route, new DoubleWordRegister(this) 398 .WithEnumField<DoubleWordRegister, Port>(0, 2, out EUSART1_TxRoutePort, name: "PORT") 399 .WithReservedBits(2, 14) 400 .WithValueField(16, 4, out EUSART1_TxRoutePin, name: "PIN") 401 .WithReservedBits(20, 12) 402 }, 403 }; 404 405 for(var i = 0; i < NumberOfPorts; ++i) 406 { 407 BuildPortRegisters(registerDictionary, i); 408 } 409 410 return new DoubleWordRegisterCollection(this, registerDictionary); 411 } 412 BuildPortRegisters(Dictionary<long, DoubleWordRegister> regs, int portNumber)413 private void BuildPortRegisters(Dictionary<long, DoubleWordRegister> regs, int portNumber) 414 { 415 var regOffset = PortOffset * portNumber; 416 var pinOffset = portNumber * NumberOfPins; 417 418 regs.Add((long)Registers.PortAControl + regOffset, new DoubleWordRegister(this) 419 .WithReservedBits(0, 4) 420 .WithTag("SLEWRATE", 4, 3) 421 .WithReservedBits(7, 5) 422 .WithTaggedFlag("DINDIS", 12) 423 .WithReservedBits(13, 7) 424 .WithTag("SLEWRATEALT", 20, 3) 425 .WithReservedBits(23, 5) 426 .WithTaggedFlag("DINDISALT", 28) 427 .WithReservedBits(29, 3) 428 ); 429 regs.Add((long)Registers.PortAModeLow + regOffset, new DoubleWordRegister(this) 430 .WithEnumField<DoubleWordRegister, PinMode>(0, 4, out pinMode[pinOffset], name: "MODE0") 431 .WithEnumField<DoubleWordRegister, PinMode>(4, 4, out pinMode[pinOffset + 1], name: "MODE1") 432 .WithEnumField<DoubleWordRegister, PinMode>(8, 4, out pinMode[pinOffset + 2], name: "MODE2") 433 .WithEnumField<DoubleWordRegister, PinMode>(12, 4, out pinMode[pinOffset + 3], name: "MODE3") 434 .WithEnumField<DoubleWordRegister, PinMode>(16, 4, out pinMode[pinOffset + 4], name: "MODE4") 435 .WithEnumField<DoubleWordRegister, PinMode>(20, 4, out pinMode[pinOffset + 5], name: "MODE5") 436 .WithEnumField<DoubleWordRegister, PinMode>(24, 4, out pinMode[pinOffset + 6], name: "MODE6") 437 .WithEnumField<DoubleWordRegister, PinMode>(28, 4, out pinMode[pinOffset + 7], name: "MODE7") 438 ); 439 regs.Add((long)Registers.PortAModeHigh + regOffset, new DoubleWordRegister(this) 440 .WithEnumField<DoubleWordRegister, PinMode>(0, 4, out pinMode[pinOffset + 8], name: "MODE8") 441 .WithEnumField<DoubleWordRegister, PinMode>(4, 4, out pinMode[pinOffset + 9], name: "MODE9") 442 .WithEnumField<DoubleWordRegister, PinMode>(8, 4, out pinMode[pinOffset + 10], name: "MODE10") 443 .WithEnumField<DoubleWordRegister, PinMode>(12, 4, out pinMode[pinOffset + 11], name: "MODE11") 444 .WithEnumField<DoubleWordRegister, PinMode>(16, 4, out pinMode[pinOffset + 12], name: "MODE12") 445 .WithEnumField<DoubleWordRegister, PinMode>(20, 4, out pinMode[pinOffset + 13], name: "MODE13") 446 .WithEnumField<DoubleWordRegister, PinMode>(24, 4, out pinMode[pinOffset + 14], name: "MODE14") 447 .WithEnumField<DoubleWordRegister, PinMode>(28, 4, out pinMode[pinOffset + 15], name: "MODE15") 448 ); 449 regs.Add((long)Registers.PortADataOut + regOffset, new DoubleWordRegister(this) 450 .WithFlags(0, 16, 451 writeCallback: (i, _, value) => 452 { 453 var pin = pinOffset + i; 454 if (IsOutput(pinMode[pin].Value)) 455 { 456 Connections[pin].Set(value); 457 } 458 }, 459 valueProviderCallback: (i, _) => 460 { 461 var pin = pinOffset + i; 462 return Connections[pin].IsSet; 463 }, 464 name: "DOUT") 465 .WithReservedBits(16, 16) 466 ); 467 regs.Add((long)Registers.PortADataIn + regOffset, new DoubleWordRegister(this) 468 .WithFlags(0, 16, FieldMode.Read, 469 valueProviderCallback: (i, _) => 470 { 471 var pin = pinOffset + i; 472 return State[pin]; 473 }, 474 name: "DIN") 475 .WithReservedBits(16, 16) 476 ); 477 } 478 479 public long Size => 0x4000; 480 public GPIO OddIRQ { get; } 481 public GPIO EvenIRQ { get; } 482 private readonly DoubleWordRegisterCollection registersCollection; 483 private readonly object internalLock = new object(); 484 private const uint SetRegisterOffset = 0x1000; 485 private const uint ClearRegisterOffset = 0x2000; 486 private const uint ToggleRegisterOffset = 0x3000; 487 private const int NumberOfPorts = 4; 488 private const int NumberOfPins = 16; 489 private const int NumberOfExternalInterrupts = 16; 490 private const int UnlockCode = 0xA534; 491 private const int PortOffset = 0x30; 492 #region register fields 493 private readonly IEnumRegisterField<Port>[] externalInterruptPortSelect = new IEnumRegisterField<Port>[NumberOfExternalInterrupts]; 494 private readonly IValueRegisterField[] externalInterruptPinSelect = new IValueRegisterField[NumberOfExternalInterrupts]; 495 private readonly IEnumRegisterField<PinMode>[] pinMode = new IEnumRegisterField<PinMode>[NumberOfPins * NumberOfPorts]; 496 private readonly IFlagRegisterField[] externalInterrupt = new IFlagRegisterField[NumberOfExternalInterrupts]; 497 private readonly IFlagRegisterField[] externalInterruptEnable = new IFlagRegisterField[NumberOfExternalInterrupts]; 498 private readonly uint[] interruptTrigger = new uint[NumberOfExternalInterrupts]; 499 private readonly bool[] previousState = new bool[NumberOfExternalInterrupts]; 500 private readonly uint[] targetExternalPins = new uint[NumberOfPins * NumberOfPorts]; 501 private bool configurationLocked; 502 // USART0 503 private IFlagRegisterField USART0_RouteEnable_TxPin; 504 private IFlagRegisterField USART0_RouteEnable_SclkPin; 505 private IFlagRegisterField USART0_RouteEnable_RxPin; 506 private IFlagRegisterField USART0_RouteEnable_RtsPin; 507 private IFlagRegisterField USART0_RouteEnable_CsPin; 508 private IEnumRegisterField<Port> USART0_RxRoutePort; 509 private IValueRegisterField USART0_RxRoutePin; 510 private IEnumRegisterField<Port> USART0_TxRoutePort; 511 private IValueRegisterField USART0_TxRoutePin; 512 // EUSART0 513 private IFlagRegisterField EUSART0_RouteEnable_TxPin; 514 private IFlagRegisterField EUSART0_RouteEnable_SclkPin; 515 private IFlagRegisterField EUSART0_RouteEnable_RxPin; 516 private IFlagRegisterField EUSART0_RouteEnable_RtsPin; 517 private IFlagRegisterField EUSART0_RouteEnable_CsPin; 518 private IEnumRegisterField<Port> EUSART0_RxRoutePort; 519 private IValueRegisterField EUSART0_RxRoutePin; 520 private IEnumRegisterField<Port> EUSART0_TxRoutePort; 521 private IValueRegisterField EUSART0_TxRoutePin; 522 // EUSART1 523 private IFlagRegisterField EUSART1_RouteEnable_TxPin; 524 private IFlagRegisterField EUSART1_RouteEnable_SclkPin; 525 private IFlagRegisterField EUSART1_RouteEnable_RxPin; 526 private IFlagRegisterField EUSART1_RouteEnable_RtsPin; 527 private IFlagRegisterField EUSART1_RouteEnable_CsPin; 528 private IEnumRegisterField<Port> EUSART1_RxRoutePort; 529 private IValueRegisterField EUSART1_RxRoutePin; 530 private IEnumRegisterField<Port> EUSART1_TxRoutePort; 531 private IValueRegisterField EUSART1_TxRoutePin; 532 #endregion 533 534 #region methods InnerReset()535 public void InnerReset() 536 { 537 registersCollection.Reset(); 538 configurationLocked = false; 539 EvenIRQ.Unset(); 540 OddIRQ.Unset(); 541 for(var i = 0; i < NumberOfExternalInterrupts; i++) 542 { 543 interruptTrigger[i] = (uint)InterruptTrigger.None; 544 previousState[i] = false; 545 } 546 for(var i = 0; i < NumberOfPins * NumberOfPorts; i++) 547 { 548 targetExternalPins[i] = 0; 549 } 550 } 551 OnGPIO(int number, bool value)552 public override void OnGPIO(int number, bool value) 553 { 554 bool internalSignal = ((number & 0x1000) > 0); 555 556 // Override the GPIO number if this is an internal signal. 557 if (internalSignal) 558 { 559 SignalSource signalSource = (SignalSource)(number & 0xFF); 560 SignalType signalType = (SignalType)((number & 0xF00) >> 8); 561 562 number = GetPinNumberFromInternalSignal(signalSource, signalType); 563 564 if (number < 0) 565 { 566 this.Log(LogLevel.Warning, "Pin number not found for internal signal (source={0} signal={1})", signalSource, signalType); 567 return; 568 } 569 } 570 571 if(number < 0 || number >= State.Length) 572 { 573 this.Log(LogLevel.Error, string.Format("Gpio #{0} called, but only {1} lines are available", number, State.Length)); 574 return; 575 } 576 577 lock(internalLock) 578 { 579 if(IsOutput(pinMode[number].Value)) 580 { 581 this.Log(LogLevel.Warning, "Writing to an output GPIO pin #{0}", number); 582 return; 583 } 584 585 base.OnGPIO(number, value); 586 UpdateInterrupts(); 587 } 588 } 589 GetPinNumberFromInternalSignal(SignalSource signalSource, SignalType signalType)590 int GetPinNumberFromInternalSignal(SignalSource signalSource, SignalType signalType) 591 { 592 int pinNumber = -1; 593 594 switch(signalSource) 595 { 596 case SignalSource.USART0: 597 { 598 switch(signalType) 599 { 600 case SignalType.USART0_RX: 601 { 602 if (USART0_RouteEnable_RxPin.Value) 603 { 604 pinNumber = GetPinNumber(USART0_RxRoutePort.Value, (uint)USART0_RxRoutePin.Value); 605 } 606 break; 607 } 608 default: 609 this.Log(LogLevel.Error, string.Format("GPIO Signal type {0} for USART0 not supported", signalType)); 610 return pinNumber; 611 } 612 break; 613 } 614 case SignalSource.EUSART0: 615 { 616 switch(signalType) 617 { 618 case SignalType.EUSART0_RX: 619 { 620 if (EUSART0_RouteEnable_RxPin.Value) 621 { 622 pinNumber = GetPinNumber(EUSART0_RxRoutePort.Value, (uint)EUSART0_RxRoutePin.Value); 623 } 624 break; 625 } 626 default: 627 this.Log(LogLevel.Error, string.Format("GPIO Signal type {0} for EUSART0 not supported", signalType)); 628 return pinNumber; 629 } 630 break; 631 } 632 case SignalSource.EUSART1: 633 { 634 switch(signalType) 635 { 636 case SignalType.EUSART1_RX: 637 { 638 if (EUSART1_RouteEnable_RxPin.Value) 639 { 640 pinNumber = GetPinNumber(EUSART1_RxRoutePort.Value, (uint)EUSART1_RxRoutePin.Value); 641 } 642 break; 643 } 644 default: 645 this.Log(LogLevel.Error, string.Format("GPIO Signal type {0} for EUSART1 not supported", signalType)); 646 return pinNumber; 647 } 648 break; 649 } 650 default: 651 this.Log(LogLevel.Error, string.Format("GPIO Signal source {0} not supported", signalSource)); 652 return pinNumber; 653 } 654 655 return pinNumber; 656 } 657 UpdateInterrupts()658 private void UpdateInterrupts() 659 { 660 machine.ClockSource.ExecuteInLock(delegate { 661 for(var i = 0; i < NumberOfPorts*NumberOfPins; ++i) 662 { 663 var externalInterruptIndex = targetExternalPins[i]; 664 665 if (!externalInterruptEnable[externalInterruptIndex].Value) 666 { 667 continue; 668 } 669 670 var isEdge = (State[i] != previousState[externalInterruptIndex]); 671 previousState[externalInterruptIndex] = State[i]; 672 673 if(isEdge 674 && ((State[i] && ((interruptTrigger[externalInterruptIndex] & (uint)InterruptTrigger.RisingEdge) > 0)) 675 || (!State[i] && ((interruptTrigger[externalInterruptIndex] & (uint)InterruptTrigger.FallingEdge) > 0)))) 676 { 677 externalInterrupt[externalInterruptIndex].Value = true; 678 } 679 } 680 681 // Set even and/or odd interrupt as needed 682 var even = false; 683 var odd = false; 684 for(var i = 0; i < NumberOfExternalInterrupts; i += 2) 685 { 686 even |= externalInterrupt[i].Value; 687 } 688 for(var i = 1; i < NumberOfExternalInterrupts; i += 2) 689 { 690 odd |= externalInterrupt[i].Value; 691 } 692 OddIRQ.Set(odd); 693 EvenIRQ.Set(even); 694 }); 695 } 696 UpdateRouting()697 private void UpdateRouting() 698 { 699 for(uint i=0; i<NumberOfPins * NumberOfPorts; i++) 700 { 701 targetExternalPins[i] = 0; 702 } 703 704 for(uint i=0; i<NumberOfExternalInterrupts; i++) 705 { 706 Port port = externalInterruptPortSelect[i].Value; 707 uint pin = (uint)externalInterruptPinSelect[i].Value; 708 709 uint pinGroup = i / 4; 710 uint pinNumber = ((uint)port * NumberOfPins) + (pinGroup * 4) + pin; 711 712 targetExternalPins[pinNumber] = i; 713 } 714 715 UpdateInterrupts(); 716 } 717 GetPinNumber(Port port, uint pinSelect)718 private int GetPinNumber(Port port, uint pinSelect) 719 { 720 return (int)(((uint)port)*NumberOfPins + pinSelect); 721 } 722 IsOutput(PinMode mode)723 private bool IsOutput(PinMode mode) 724 { 725 return mode >= PinMode.PushPull; 726 } 727 TrySyncTime()728 private bool TrySyncTime() 729 { 730 if(machine.SystemBus.TryGetCurrentCPU(out var cpu)) 731 { 732 cpu.SyncTime(); 733 return true; 734 } 735 return false; 736 } 737 GetTime()738 private TimeInterval GetTime() => machine.LocalTimeSource.ElapsedVirtualTime; 739 #endregion 740 741 #region enums 742 private enum Port 743 { 744 PortA = 0, 745 PortB = 1, 746 PortC = 2, 747 PortD = 3, 748 } 749 750 private enum PinMode 751 { 752 Disabled = 0, 753 Input = 1, 754 InputPull = 2, 755 InputPullFilter = 3, 756 PushPull = 4, 757 PushPullAlt = 5, 758 WiredOr = 6, 759 WiredOrPullDown = 7, 760 WiredAnd = 8, 761 WiredAndFilter = 9, 762 WiredAndPullUp = 10, 763 WiredAndPullUpFilter = 11, 764 WiredAndAlt = 12, 765 WiredAndAltFilter = 13, 766 WiredAndAltPullUp = 14, 767 WiredAndAltPullUpFilter = 15, 768 } 769 770 private enum InterruptTrigger 771 { 772 None = 0x0, 773 FallingEdge = 0x1, 774 RisingEdge = 0x2, 775 } 776 777 private enum SignalSource 778 { 779 None = 0, 780 USART0 = 1, 781 EUSART0 = 2, 782 EUSART1 = 3, 783 } 784 785 private enum SignalType 786 { 787 // If SignalSource is USART0 788 USART0_CTS = 0, 789 USART0_RTS = 1, 790 USART0_RX = 2, 791 USART0_SCLK = 3, 792 USART0_TX = 4, 793 // If SignalSource is EUSART0 794 EUSART0_CTS = 0, 795 EUSART0_RTS = 1, 796 EUSART0_RX = 2, 797 EUSART0_SCLK = 3, 798 EUSART0_TX = 4, 799 // If SignalSource is EUSART1 800 EUSART1_CTS = 0, 801 EUSART1_RTS = 1, 802 EUSART1_RX = 2, 803 EUSART1_SCLK = 3, 804 EUSART1_TX = 4, 805 } 806 807 private enum Registers 808 { 809 IpVersion = 0x0000, 810 PortAControl = 0x0030, 811 PortAModeLow = 0x0034, 812 PortAModeHigh = 0x003C, 813 PortADataOut = 0x0040, 814 PortADataIn = 0x0044, 815 PortBControl = 0x0060, 816 PortBModeLow = 0x0064, 817 PortBModeHigh = 0x006C, 818 PortBDataOut = 0x0070, 819 PortBDataIn = 0x0074, 820 PortCControl = 0x0090, 821 PortCModeLow = 0x0094, 822 PortCModeHigh = 0x009C, 823 PortCDataOut = 0x00A0, 824 PortCDataIn = 0x00A4, 825 PortDControl = 0x00C0, 826 PortDModeLow = 0x00C4, 827 PortDModeHigh = 0x00CC, 828 PortDDataOut = 0x00D0, 829 PortDDataIn = 0x00D4, 830 Lock = 0x0300, 831 LockStatus = 0x0310, 832 ABusAllocation = 0x0320, 833 BBusAllocation = 0x0324, 834 CDBusAllocation = 0x0328, 835 AOdd0Switch = 0x0330, 836 AOdd1Switch = 0x0334, 837 AEven0Switch = 0x0338, 838 AEven1Switch = 0x033C, 839 BOdd0Switch = 0x0340, 840 BOdd1Switch = 0x0344, 841 BEven0Switch = 0x0348, 842 BEven1Switch = 0x034C, 843 CDOdd0Switch = 0x0350, 844 CDOdd1Switch = 0x0354, 845 CDEven0Switch = 0x0358, 846 CDEven1Switch = 0x035C, 847 ExternalInterruptPortSelectLow = 0x0400, 848 ExternalInterruptPortSelectHigh = 0x0404, 849 ExternalInterruptPinSelectLow = 0x0408, 850 ExternalInterruptPinSelectHigh = 0x040C, 851 ExternalInterruptRisingEdgeTrigger = 0x0410, 852 ExternalInterruptFallingEdgeTrigger = 0x0414, 853 InterruptFlag = 0x0420, 854 InterruptEnable = 0x0424, 855 EM4WakeUpEnable = 0x042C, 856 EM4WakeUpPolarity = 0x0430, 857 DebugRoutePinEn = 0x0440, 858 TraceRoutePinEn = 0x0444, 859 ACMP0_RouteEnable = 0x0450, 860 ACMP0_ACMPOUT_Route = 0x0454, 861 ACMP1_RouteEnable = 0x045C, 862 ACMP1_ACMPOUT_Route = 0x0460, 863 CMU_RouteEnable = 0x0468, 864 CMU_CLKIN0_Route = 0x046C, 865 CMU_CLKOUT0_Route = 0x0470, 866 CMU_CLKOUT1_Route = 0x0474, 867 CMU_CLKOUT2_Route = 0x0478, 868 CMU_CLKOUTHIDDEN_Route = 0x047C, 869 DCDC_RouteEnable = 0x0484, 870 DCDC_COREHIDDEN_Route = 0x0488, 871 DCDC_VCMPHIDDEN_Route = 0x048C, 872 EUSART0_RouteEnable = 0x0494, 873 EUSART0_CS_Route = 0x0498, 874 EUSART0_CTS_Route = 0x049C, 875 EUSART0_RTS_Route = 0x04A0, 876 EUSART0_RX_Route = 0x04A4, 877 EUSART0_SCLK_Route = 0x04A8, 878 EUSART0_TX_Route = 0x04AC, 879 EUSART1_RouteEnable = 0x04B4, 880 EUSART1_CS_Route = 0x04B8, 881 EUSART1_CTS_Route = 0x04BC, 882 EUSART1_RTS_Route = 0x04C0, 883 EUSART1_RX_Route = 0x04C4, 884 EUSART1_SCLK_Route = 0x04C8, 885 EUSART1_TX_Route = 0x04CC, 886 FRC_RouteEnable = 0x04D4, 887 FRC_DCLK_Route = 0x04D8, 888 FRC_DFRAME_Route = 0x04DC, 889 FRC_DOUT_Route = 0x04E0, 890 I2C0_RouteEnable = 0x04E8, 891 I2C0_SCL_Route = 0x04EC, 892 I2C0_SDA_Route = 0x04F0, 893 I2C1_RouteEnable = 0x04F8, 894 I2C1_SCL_Route = 0x04FC, 895 I2C1_SDA_Route = 0x0500, 896 KEYSCAN_RouteEnable = 0x0508, 897 KEYSCAN_COLOUT0_Route = 0x050C, 898 KEYSCAN_COLOUT1_Route = 0x0510, 899 KEYSCAN_COLOUT2_Route = 0x0514, 900 KEYSCAN_COLOUT3_Route = 0x0518, 901 KEYSCAN_COLOUT4_Route = 0x051C, 902 KEYSCAN_COLOUT5_Route = 0x0520, 903 KEYSCAN_COLOUT6_Route = 0x0524, 904 KEYSCAN_COLOUT7_Route = 0x0528, 905 KEYSCAN_ROWSENSE0_Route = 0x052C, 906 KEYSCAN_ROWSENSE1_Route = 0x0530, 907 KEYSCAN_ROWSENSE2_Route = 0x0534, 908 KEYSCAN_ROWSENSE3_Route = 0x0538, 909 KEYSCAN_ROWSENSE4_Route = 0x053C, 910 KEYSCAN_ROWSENSE5_Route = 0x0540, 911 LETIMER_RouteEnable = 0x0548, 912 LETIMER_OUT0_Route = 0x054C, 913 LETIMER_OUT1_Route = 0x0550, 914 MODEM_RouteEnable = 0x0558, 915 MODEM_ANT0_Route = 0x055C, 916 MODEM_ANT1_Route = 0x0560, 917 MODEM_ANTROLLOVER_Route = 0x0564, 918 MODEM_ANTRR0_Route = 0x0568, 919 MODEM_ANTRR1_Route = 0x056C, 920 MODEM_ANTRR2_Route = 0x0570, 921 MODEM_ANTRR3_Route = 0x0574, 922 MODEM_ANTRR4_Route = 0x0578, 923 MODEM_ANTRR5_Route = 0x057C, 924 MODEM_ANTSWEN_Route = 0x0580, 925 MODEM_ANTSWUS_Route = 0x0584, 926 MODEM_ANTTRIG_Route = 0x0588, 927 MODEM_ANTTRIGSTOP_Route = 0x058C, 928 MODEM_DCLK_Route = 0x0590, 929 MODEM_DIN_Route = 0x0594, 930 MODEM_DOUT_Route = 0x0598, 931 MODEM_S0IN_Route = 0x05A4, 932 MODEM_S1IN_Route = 0x05A8, 933 PRS0_RouteEnable = 0x05B0, 934 PRS0_ASYNCH0_Route = 0x05B4, 935 PRS0_ASYNCH1_Route = 0x05B8, 936 PRS0_ASYNCH2_Route = 0x05BC, 937 PRS0_ASYNCH3_Route = 0x05C0, 938 PRS0_ASYNCH4_Route = 0x05C4, 939 PRS0_ASYNCH5_Route = 0x05C8, 940 PRS0_ASYNCH6_Route = 0x05CC, 941 PRS0_ASYNCH7_Route = 0x05D0, 942 PRS0_ASYNCH8_Route = 0x05D4, 943 PRS0_ASYNCH9_Route = 0x05D8, 944 PRS0_ASYNCH10_Route = 0x05DC, 945 PRS0_ASYNCH11_Route = 0x05E0, 946 PRS0_ASYNCH12_Route = 0x05E4, 947 PRS0_ASYNCH13_Route = 0x05E8, 948 PRS0_ASYNCH14_Route = 0x05EC, 949 PRS0_ASYNCH15_Route = 0x05F0, 950 PRS0_SYNCH0_Route = 0x05F4, 951 PRS0_SYNCH1_Route = 0x05F8, 952 PRS0_SYNCH2_Route = 0x05FC, 953 PRS0_SYNCH3_Route = 0x0600, 954 RAC_RouteEnable = 0x0608, 955 RAC_LNAEN_Route = 0x060C, 956 RAC_PAEN_Route = 0x0610, 957 RFECA0_RouteEnable = 0x0618, 958 RFECA0_DATAOUT0_Route = 0x061C, 959 RFECA0_DATAOUT1_Route = 0x0620, 960 RFECA0_DATAOUT2_Route = 0x0624, 961 RFECA0_DATAOUT3_Route = 0x0628, 962 RFECA0_DATAOUT4_Route = 0x062C, 963 RFECA0_DATAOUT5_Route = 0x0630, 964 RFECA0_DATAOUT6_Route = 0x0634, 965 RFECA0_DATAOUT7_Route = 0x0638, 966 RFECA0_DATAOUT8_Route = 0x063C, 967 RFECA0_DATAOUT9_Route = 0x0640, 968 RFECA0_DATAOUT10_Route = 0x0644, 969 RFECA0_DATAOUT11_Route = 0x0648, 970 RFECA0_DATAOUT12_Route = 0x064C, 971 RFECA0_DATAOUT13_Route = 0x0650, 972 RFECA0_DATAOUT14_Route = 0x0654, 973 RFECA0_DATAOUT15_Route = 0x0658, 974 RFECA0_DATAOUT16_Route = 0x065C, 975 RFECA0_DATAOUT17_Route = 0x0660, 976 RFECA0_DATAOUT18_Route = 0x0664, 977 RFECA0_DATAVALID_Route = 0x0668, 978 RFECA0_TRIGGERIN_Route = 0x066C, 979 SYXO0_BUFOUTREQINASYNC_Route = 0x0678, 980 TIMER0_RouteEnable = 0x0680, 981 TIMER0_CC0_Route = 0x0684, 982 TIMER0_CC1_Route = 0x0688, 983 TIMER0_CC2_Route = 0x068C, 984 TIMER0_CDTI0_Route = 0x0690, 985 TIMER0_CDTI1_Route = 0x0694, 986 TIMER0_CDTI2_Route = 0x0698, 987 TIMER1_RouteEnable = 0x06A0, 988 TIMER1_CC0_Route = 0x06A4, 989 TIMER1_CC1_Route = 0x06A8, 990 TIMER1_CC2_Route = 0x06AC, 991 TIMER1_CDTI0_Route = 0x06B0, 992 TIMER1_CDTI1_Route = 0x06B4, 993 TIMER1_CDTI2_Route = 0x06B8, 994 TIMER2_RouteEnable = 0x06C0, 995 TIMER2_CC0_Route = 0x06C4, 996 TIMER2_CC1_Route = 0x06C8, 997 TIMER2_CC2_Route = 0x06CC, 998 TIMER2_CDTI0_Route = 0x06D0, 999 TIMER2_CDTI1_Route = 0x06D4, 1000 TIMER2_CDTI2_Route = 0x06D8, 1001 TIMER3_RouteEnable = 0x06E0, 1002 TIMER3_CC0_Route = 0x06E4, 1003 TIMER3_CC1_Route = 0x06E8, 1004 TIMER3_CC2_Route = 0x06EC, 1005 TIMER3_CDTI0_Route = 0x06F0, 1006 TIMER3_CDTI1_Route = 0x06F4, 1007 TIMER3_CDTI2_Route = 0x06F8, 1008 TIMER4_RouteEnable = 0x0700, 1009 TIMER4_CC0_Route = 0x0704, 1010 TIMER4_CC1_Route = 0x0708, 1011 TIMER4_CC2_Route = 0x070C, 1012 TIMER4_CDTI0_Route = 0x0710, 1013 TIMER4_CDTI1_Route = 0x0714, 1014 TIMER4_CDTI2_Route = 0x0718, 1015 USART0_RouteEnable = 0x0720, 1016 USART0_CS_Route = 0x0724, 1017 USART0_CTS_Route = 0x0728, 1018 USART0_RTS_Route = 0x072C, 1019 USART0_RX_Route = 0x0730, 1020 USART0_CLK_Route = 0x0734, 1021 USART0_TX_Route = 0x0738, 1022 RootAccessTypeDescriptor0 = 0x0740, 1023 RootAccessTypeDescriptor1 = 0x0744, 1024 RootAccessTypeDescriptor6 = 0x0758, 1025 RootAccessTypeDescriptor8 = 0x0760, 1026 RootAccessTypeDescriptor9 = 0x0764, 1027 RootAccessTypeDescriptor10 = 0x0768, 1028 RootAccessTypeDescriptor11 = 0x076C, 1029 RootAccessTypeDescriptor12 = 0x0770, 1030 RootAccessTypeDescriptor13 = 0x0774, 1031 RootAccessTypeDescriptor14 = 0x0778, 1032 // Set registers 1033 IpVersion_Set = 0x1000, 1034 PortAControl_Set = 0x1030, 1035 PortAModeLow_Set = 0x1034, 1036 PortAModeHigh_Set = 0x103C, 1037 PortADataOut_Set = 0x1040, 1038 PortADataIn_Set = 0x1044, 1039 PortBControl_Set = 0x1060, 1040 PortBModeLow_Set = 0x1064, 1041 PortBModeHigh_Set = 0x106C, 1042 PortBDataOut_Set = 0x1070, 1043 PortBDataIn_Set = 0x1074, 1044 PortCControl_Set = 0x1090, 1045 PortCModeLow_Set = 0x1094, 1046 PortCModeHigh_Set = 0x109C, 1047 PortCDataOut_Set = 0x10A0, 1048 PortCDataIn_Set = 0x10A4, 1049 PortDControl_Set = 0x10C0, 1050 PortDModeLow_Set = 0x10C4, 1051 PortDModeHigh_Set = 0x10CC, 1052 PortDDataOut_Set = 0x10D0, 1053 PortDDataIn_Set = 0x10D4, 1054 Lock_Set = 0x1300, 1055 LockStatus_Set = 0x1310, 1056 ABusAllocation_Set = 0x1320, 1057 BBusAllocation_Set = 0x1324, 1058 CDBusAllocation_Set = 0x1328, 1059 AOdd0Switch_Set = 0x1330, 1060 AOdd1Switch_Set = 0x1334, 1061 AEven0Switch_Set = 0x1338, 1062 AEven1Switch_Set = 0x133C, 1063 BOdd0Switch_Set = 0x1340, 1064 BOdd1Switch_Set = 0x1344, 1065 BEven0Switch_Set = 0x1348, 1066 BEven1Switch_Set = 0x134C, 1067 CDOdd0Switch_Set = 0x1350, 1068 CDOdd1Switch_Set = 0x1354, 1069 CDEven0Switch_Set = 0x1358, 1070 CDEven1Switch_Set = 0x135C, 1071 ExternalInterruptPortSelectLow_Set = 0x1400, 1072 ExternalInterruptPortSelectHigh_Set = 0x1404, 1073 ExternalInterruptPinSelectLow_Set = 0x1408, 1074 ExternalInterruptPinSelectHigh_Set = 0x140C, 1075 ExternalInterruptRisingEdgeTrigger_Set = 0x1410, 1076 ExternalInterruptFallingEdgeTrigger_Set = 0x1414, 1077 InterruptFlag_Set = 0x1420, 1078 InterruptEnable_Set = 0x1424, 1079 EM4WakeUpEnable_Set = 0x142C, 1080 EM4WakeUpPolarity_Set = 0x1430, 1081 DebugRoutePinEn_Set = 0x1440, 1082 TraceRoutePinEn_Set = 0x1444, 1083 ACMP0_RouteEnable_Set = 0x1450, 1084 ACMP0_ACMPOUT_Route_Set = 0x1454, 1085 ACMP1_RouteEnable_Set = 0x145C, 1086 ACMP1_ACMPOUT_Route_Set = 0x1460, 1087 CMU_RouteEnable_Set = 0x1468, 1088 CMU_CLKIN0_Route_Set = 0x146C, 1089 CMU_CLKOUT0_Route_Set = 0x1470, 1090 CMU_CLKOUT1_Route_Set = 0x1474, 1091 CMU_CLKOUT2_Route_Set = 0x1478, 1092 CMU_CLKOUTHIDDEN_Route_Set = 0x147C, 1093 DCDC_RouteEnable_Set = 0x1484, 1094 DCDC_COREHIDDEN_Route_Set = 0x1488, 1095 DCDC_VCMPHIDDEN_Route_Set = 0x148C, 1096 EUSART0_RouteEnable_Set = 0x1494, 1097 EUSART0_CS_Route_Set = 0x1498, 1098 EUSART0_CTS_Route_Set = 0x149C, 1099 EUSART0_RTS_Route_Set = 0x14A0, 1100 EUSART0_RX_Route_Set = 0x14A4, 1101 EUSART0_SCLK_Route_Set = 0x14A8, 1102 EUSART0_TX_Route_Set = 0x14AC, 1103 EUSART1_RouteEnable_Set = 0x14B4, 1104 EUSART1_CS_Route_Set = 0x14B8, 1105 EUSART1_CTS_Route_Set = 0x14BC, 1106 EUSART1_RTS_Route_Set = 0x14C0, 1107 EUSART1_RX_Route_Set = 0x14C4, 1108 EUSART1_SCLK_Route_Set = 0x14C8, 1109 EUSART1_TX_Route_Set = 0x14CC, 1110 FRC_RouteEnable_Set = 0x14D4, 1111 FRC_DCLK_Route_Set = 0x14D8, 1112 FRC_DFRAME_Route_Set = 0x14DC, 1113 FRC_DOUT_Route_Set = 0x14E0, 1114 I2C0_RouteEnable_Set = 0x14E8, 1115 I2C0_SCL_Route_Set = 0x14EC, 1116 I2C0_SDA_Route_Set = 0x14F0, 1117 I2C1_RouteEnable_Set = 0x14F8, 1118 I2C1_SCL_Route_Set = 0x14FC, 1119 I2C1_SDA_Route_Set = 0x1500, 1120 KEYSCAN_RouteEnable_Set = 0x1508, 1121 KEYSCAN_COLOUT0_Route_Set = 0x150C, 1122 KEYSCAN_COLOUT1_Route_Set = 0x1510, 1123 KEYSCAN_COLOUT2_Route_Set = 0x1514, 1124 KEYSCAN_COLOUT3_Route_Set = 0x1518, 1125 KEYSCAN_COLOUT4_Route_Set = 0x151C, 1126 KEYSCAN_COLOUT5_Route_Set = 0x1520, 1127 KEYSCAN_COLOUT6_Route_Set = 0x1524, 1128 KEYSCAN_COLOUT7_Route_Set = 0x1528, 1129 KEYSCAN_ROWSENSE0_Route_Set = 0x152C, 1130 KEYSCAN_ROWSENSE1_Route_Set = 0x1530, 1131 KEYSCAN_ROWSENSE2_Route_Set = 0x1534, 1132 KEYSCAN_ROWSENSE3_Route_Set = 0x1538, 1133 KEYSCAN_ROWSENSE4_Route_Set = 0x153C, 1134 KEYSCAN_ROWSENSE5_Route_Set = 0x1540, 1135 LETIMER_RouteEnable_Set = 0x1548, 1136 LETIMER_OUT0_Route_Set = 0x154C, 1137 LETIMER_OUT1_Route_Set = 0x1550, 1138 MODEM_RouteEnable_Set = 0x1558, 1139 MODEM_ANT0_Route_Set = 0x155C, 1140 MODEM_ANT1_Route_Set = 0x1560, 1141 MODEM_ANTROLLOVER_Route_Set = 0x1564, 1142 MODEM_ANTRR0_Route_Set = 0x1568, 1143 MODEM_ANTRR1_Route_Set = 0x156C, 1144 MODEM_ANTRR2_Route_Set = 0x1570, 1145 MODEM_ANTRR3_Route_Set = 0x1574, 1146 MODEM_ANTRR4_Route_Set = 0x1578, 1147 MODEM_ANTRR5_Route_Set = 0x157C, 1148 MODEM_ANTSWEN_Route_Set = 0x1580, 1149 MODEM_ANTSWUS_Route_Set = 0x1584, 1150 MODEM_ANTTRIG_Route_Set = 0x1588, 1151 MODEM_ANTTRIGSTOP_Route_Set = 0x158C, 1152 MODEM_DCLK_Route_Set = 0x1590, 1153 MODEM_DIN_Route_Set = 0x1594, 1154 MODEM_DOUT_Route_Set = 0x1598, 1155 MODEM_S0IN_Route_Set = 0x15A4, 1156 MODEM_S1IN_Route_Set = 0x15A8, 1157 PRS0_RouteEnable_Set = 0x15B0, 1158 PRS0_ASYNCH0_Route_Set = 0x15B4, 1159 PRS0_ASYNCH1_Route_Set = 0x15B8, 1160 PRS0_ASYNCH2_Route_Set = 0x15BC, 1161 PRS0_ASYNCH3_Route_Set = 0x15C0, 1162 PRS0_ASYNCH4_Route_Set = 0x15C4, 1163 PRS0_ASYNCH5_Route_Set = 0x15C8, 1164 PRS0_ASYNCH6_Route_Set = 0x15CC, 1165 PRS0_ASYNCH7_Route_Set = 0x15D0, 1166 PRS0_ASYNCH8_Route_Set = 0x15D4, 1167 PRS0_ASYNCH9_Route_Set = 0x15D8, 1168 PRS0_ASYNCH10_Route_Set = 0x15DC, 1169 PRS0_ASYNCH11_Route_Set = 0x15E0, 1170 PRS0_ASYNCH12_Route_Set = 0x15E4, 1171 PRS0_ASYNCH13_Route_Set = 0x15E8, 1172 PRS0_ASYNCH14_Route_Set = 0x15EC, 1173 PRS0_ASYNCH15_Route_Set = 0x15F0, 1174 PRS0_SYNCH0_Route_Set = 0x15F4, 1175 PRS0_SYNCH1_Route_Set = 0x15F8, 1176 PRS0_SYNCH2_Route_Set = 0x15FC, 1177 PRS0_SYNCH3_Route_Set = 0x1600, 1178 RAC_RouteEnable_Set = 0x1608, 1179 RAC_LNAEN_Route_Set = 0x160C, 1180 RAC_PAEN_Route_Set = 0x1610, 1181 RFECA0_RouteEnable_Set = 0x1618, 1182 RFECA0_DATAOUT0_Route_Set = 0x161C, 1183 RFECA0_DATAOUT1_Route_Set = 0x1620, 1184 RFECA0_DATAOUT2_Route_Set = 0x1624, 1185 RFECA0_DATAOUT3_Route_Set = 0x1628, 1186 RFECA0_DATAOUT4_Route_Set = 0x162C, 1187 RFECA0_DATAOUT5_Route_Set = 0x1630, 1188 RFECA0_DATAOUT6_Route_Set = 0x1634, 1189 RFECA0_DATAOUT7_Route_Set = 0x1638, 1190 RFECA0_DATAOUT8_Route_Set = 0x163C, 1191 RFECA0_DATAOUT9_Route_Set = 0x1640, 1192 RFECA0_DATAOUT10_Route_Set = 0x1644, 1193 RFECA0_DATAOUT11_Route_Set = 0x1648, 1194 RFECA0_DATAOUT12_Route_Set = 0x164C, 1195 RFECA0_DATAOUT13_Route_Set = 0x1650, 1196 RFECA0_DATAOUT14_Route_Set = 0x1654, 1197 RFECA0_DATAOUT15_Route_Set = 0x1658, 1198 RFECA0_DATAOUT16_Route_Set = 0x165C, 1199 RFECA0_DATAOUT17_Route_Set = 0x1660, 1200 RFECA0_DATAOUT18_Route_Set = 0x1664, 1201 RFECA0_DATAVALID_Route_Set = 0x1668, 1202 RFECA0_TRIGGERIN_Route_Set = 0x166C, 1203 SYXO0_BUFOUTREQINASYNC_Route_Set = 0x1678, 1204 TIMER0_RouteEnable_Set = 0x1680, 1205 TIMER0_CC0_Route_Set = 0x1684, 1206 TIMER0_CC1_Route_Set = 0x1688, 1207 TIMER0_CC2_Route_Set = 0x168C, 1208 TIMER0_CDTI0_Route_Set = 0x1690, 1209 TIMER0_CDTI1_Route_Set = 0x1694, 1210 TIMER0_CDTI2_Route_Set = 0x1698, 1211 TIMER1_RouteEnable_Set = 0x16A0, 1212 TIMER1_CC0_Route_Set = 0x16A4, 1213 TIMER1_CC1_Route_Set = 0x16A8, 1214 TIMER1_CC2_Route_Set = 0x16AC, 1215 TIMER1_CDTI0_Route_Set = 0x16B0, 1216 TIMER1_CDTI1_Route_Set = 0x16B4, 1217 TIMER1_CDTI2_Route_Set = 0x16B8, 1218 TIMER2_RouteEnable_Set = 0x16C0, 1219 TIMER2_CC0_Route_Set = 0x16C4, 1220 TIMER2_CC1_Route_Set = 0x16C8, 1221 TIMER2_CC2_Route_Set = 0x16CC, 1222 TIMER2_CDTI0_Route_Set = 0x16D0, 1223 TIMER2_CDTI1_Route_Set = 0x16D4, 1224 TIMER2_CDTI2_Route_Set = 0x16D8, 1225 TIMER3_RouteEnable_Set = 0x16E0, 1226 TIMER3_CC0_Route_Set = 0x16E4, 1227 TIMER3_CC1_Route_Set = 0x16E8, 1228 TIMER3_CC2_Route_Set = 0x16EC, 1229 TIMER3_CDTI0_Route_Set = 0x16F0, 1230 TIMER3_CDTI1_Route_Set = 0x16F4, 1231 TIMER3_CDTI2_Route_Set = 0x16F8, 1232 TIMER4_RouteEnable_Set = 0x1700, 1233 TIMER4_CC0_Route_Set = 0x1704, 1234 TIMER4_CC1_Route_Set = 0x1708, 1235 TIMER4_CC2_Route_Set = 0x170C, 1236 TIMER4_CDTI0_Route_Set = 0x1710, 1237 TIMER4_CDTI1_Route_Set = 0x1714, 1238 TIMER4_CDTI2_Route_Set = 0x1718, 1239 USART0_RouteEnable_Set = 0x1720, 1240 USART0_CS_Route_Set = 0x1724, 1241 USART0_CTS_Route_Set = 0x1728, 1242 USART0_RTS_Route_Set = 0x172C, 1243 USART0_RX_Route_Set = 0x1730, 1244 USART0_CLK_Route_Set = 0x1734, 1245 USART0_TX_Route_Set = 0x1738, 1246 RootAccessTypeDescriptor0_Set = 0x1740, 1247 RootAccessTypeDescriptor1_Set = 0x1744, 1248 RootAccessTypeDescriptor6_Set = 0x1758, 1249 RootAccessTypeDescriptor8_Set = 0x1760, 1250 RootAccessTypeDescriptor9_Set = 0x1764, 1251 RootAccessTypeDescriptor10_Set = 0x1768, 1252 RootAccessTypeDescriptor11_Set = 0x176C, 1253 RootAccessTypeDescriptor12_Set = 0x1770, 1254 RootAccessTypeDescriptor13_Set = 0x1774, 1255 RootAccessTypeDescriptor14_Set = 0x1778, 1256 // Clear registers 1257 IpVersion_Clr = 0x2000, 1258 PortAControl_Clr = 0x2030, 1259 PortAModeLow_Clr = 0x2034, 1260 PortAModeHigh_Clr = 0x203C, 1261 PortADataOut_Clr = 0x2040, 1262 PortADataIn_Clr = 0x2044, 1263 PortBControl_Clr = 0x2060, 1264 PortBModeLow_Clr = 0x2064, 1265 PortBModeHigh_Clr = 0x206C, 1266 PortBDataOut_Clr = 0x2070, 1267 PortBDataIn_Clr = 0x2074, 1268 PortCControl_Clr = 0x2090, 1269 PortCModeLow_Clr = 0x2094, 1270 PortCModeHigh_Clr = 0x209C, 1271 PortCDataOut_Clr = 0x20A0, 1272 PortCDataIn_Clr = 0x20A4, 1273 PortDControl_Clr = 0x20C0, 1274 PortDModeLow_Clr = 0x20C4, 1275 PortDModeHigh_Clr = 0x20CC, 1276 PortDDataOut_Clr = 0x20D0, 1277 PortDDataIn_Clr = 0x20D4, 1278 Lock_Clr = 0x2300, 1279 LockStatus_Clr = 0x2310, 1280 ABusAllocation_Clr = 0x2320, 1281 BBusAllocation_Clr = 0x2324, 1282 CDBusAllocation_Clr = 0x2328, 1283 AOdd0Switch_Clr = 0x2330, 1284 AOdd1Switch_Clr = 0x2334, 1285 AEven0Switch_Clr = 0x2338, 1286 AEven1Switch_Clr = 0x233C, 1287 BOdd0Switch_Clr = 0x2340, 1288 BOdd1Switch_Clr = 0x2344, 1289 BEven0Switch_Clr = 0x2348, 1290 BEven1Switch_Clr = 0x234C, 1291 CDOdd0Switch_Clr = 0x2350, 1292 CDOdd1Switch_Clr = 0x2354, 1293 CDEven0Switch_Clr = 0x2358, 1294 CDEven1Switch_Clr = 0x235C, 1295 ExternalInterruptPortSelectLow_Clr = 0x2400, 1296 ExternalInterruptPortSelectHigh_Clr = 0x2404, 1297 ExternalInterruptPinSelectLow_Clr = 0x2408, 1298 ExternalInterruptPinSelectHigh_Clr = 0x240C, 1299 ExternalInterruptRisingEdgeTrigger_Clr = 0x2410, 1300 ExternalInterruptFallingEdgeTrigger_Clr = 0x2414, 1301 InterruptFlag_Clr = 0x2420, 1302 InterruptEnable_Clr = 0x2424, 1303 EM4WakeUpEnable_Clr = 0x242C, 1304 EM4WakeUpPolarity_Clr = 0x2430, 1305 DebugRoutePinEn_Clr = 0x2440, 1306 TraceRoutePinEn_Clr = 0x2444, 1307 ACMP0_RouteEnable_Clr = 0x2450, 1308 ACMP0_ACMPOUT_Route_Clr = 0x2454, 1309 ACMP1_RouteEnable_Clr = 0x245C, 1310 ACMP1_ACMPOUT_Route_Clr = 0x2460, 1311 CMU_RouteEnable_Clr = 0x2468, 1312 CMU_CLKIN0_Route_Clr = 0x246C, 1313 CMU_CLKOUT0_Route_Clr = 0x2470, 1314 CMU_CLKOUT1_Route_Clr = 0x2474, 1315 CMU_CLKOUT2_Route_Clr = 0x2478, 1316 CMU_CLKOUTHIDDEN_Route_Clr = 0x247C, 1317 DCDC_RouteEnable_Clr = 0x2484, 1318 DCDC_COREHIDDEN_Route_Clr = 0x2488, 1319 DCDC_VCMPHIDDEN_Route_Clr = 0x248C, 1320 EUSART0_RouteEnable_Clr = 0x2494, 1321 EUSART0_CS_Route_Clr = 0x2498, 1322 EUSART0_CTS_Route_Clr = 0x249C, 1323 EUSART0_RTS_Route_Clr = 0x24A0, 1324 EUSART0_RX_Route_Clr = 0x24A4, 1325 EUSART0_SCLK_Route_Clr = 0x24A8, 1326 EUSART0_TX_Route_Clr = 0x24AC, 1327 EUSART1_RouteEnable_Clr = 0x24B4, 1328 EUSART1_CS_Route_Clr = 0x24B8, 1329 EUSART1_CTS_Route_Clr = 0x24BC, 1330 EUSART1_RTS_Route_Clr = 0x24C0, 1331 EUSART1_RX_Route_Clr = 0x24C4, 1332 EUSART1_SCLK_Route_Clr = 0x24C8, 1333 EUSART1_TX_Route_Clr = 0x24CC, 1334 FRC_RouteEnable_Clr = 0x24D4, 1335 FRC_DCLK_Route_Clr = 0x24D8, 1336 FRC_DFRAME_Route_Clr = 0x24DC, 1337 FRC_DOUT_Route_Clr = 0x24E0, 1338 I2C0_RouteEnable_Clr = 0x24E8, 1339 I2C0_SCL_Route_Clr = 0x24EC, 1340 I2C0_SDA_Route_Clr = 0x24F0, 1341 I2C1_RouteEnable_Clr = 0x24F8, 1342 I2C1_SCL_Route_Clr = 0x24FC, 1343 I2C1_SDA_Route_Clr = 0x2500, 1344 KEYSCAN_RouteEnable_Clr = 0x2508, 1345 KEYSCAN_COLOUT0_Route_Clr = 0x250C, 1346 KEYSCAN_COLOUT1_Route_Clr = 0x2510, 1347 KEYSCAN_COLOUT2_Route_Clr = 0x2514, 1348 KEYSCAN_COLOUT3_Route_Clr = 0x2518, 1349 KEYSCAN_COLOUT4_Route_Clr = 0x251C, 1350 KEYSCAN_COLOUT5_Route_Clr = 0x2520, 1351 KEYSCAN_COLOUT6_Route_Clr = 0x2524, 1352 KEYSCAN_COLOUT7_Route_Clr = 0x2528, 1353 KEYSCAN_ROWSENSE0_Route_Clr = 0x252C, 1354 KEYSCAN_ROWSENSE1_Route_Clr = 0x2530, 1355 KEYSCAN_ROWSENSE2_Route_Clr = 0x2534, 1356 KEYSCAN_ROWSENSE3_Route_Clr = 0x2538, 1357 KEYSCAN_ROWSENSE4_Route_Clr = 0x253C, 1358 KEYSCAN_ROWSENSE5_Route_Clr = 0x2540, 1359 LETIMER_RouteEnable_Clr = 0x2548, 1360 LETIMER_OUT0_Route_Clr = 0x254C, 1361 LETIMER_OUT1_Route_Clr = 0x2550, 1362 MODEM_RouteEnable_Clr = 0x2558, 1363 MODEM_ANT0_Route_Clr = 0x255C, 1364 MODEM_ANT1_Route_Clr = 0x2560, 1365 MODEM_ANTROLLOVER_Route_Clr = 0x2564, 1366 MODEM_ANTRR0_Route_Clr = 0x2568, 1367 MODEM_ANTRR1_Route_Clr = 0x256C, 1368 MODEM_ANTRR2_Route_Clr = 0x2570, 1369 MODEM_ANTRR3_Route_Clr = 0x2574, 1370 MODEM_ANTRR4_Route_Clr = 0x2578, 1371 MODEM_ANTRR5_Route_Clr = 0x257C, 1372 MODEM_ANTSWEN_Route_Clr = 0x2580, 1373 MODEM_ANTSWUS_Route_Clr = 0x2584, 1374 MODEM_ANTTRIG_Route_Clr = 0x2588, 1375 MODEM_ANTTRIGSTOP_Route_Clr = 0x258C, 1376 MODEM_DCLK_Route_Clr = 0x2590, 1377 MODEM_DIN_Route_Clr = 0x2594, 1378 MODEM_DOUT_Route_Clr = 0x2598, 1379 MODEM_S0IN_Route_Clr = 0x25A4, 1380 MODEM_S1IN_Route_Clr = 0x25A8, 1381 PRS0_RouteEnable_Clr = 0x25B0, 1382 PRS0_ASYNCH0_Route_Clr = 0x25B4, 1383 PRS0_ASYNCH1_Route_Clr = 0x25B8, 1384 PRS0_ASYNCH2_Route_Clr = 0x25BC, 1385 PRS0_ASYNCH3_Route_Clr = 0x25C0, 1386 PRS0_ASYNCH4_Route_Clr = 0x25C4, 1387 PRS0_ASYNCH5_Route_Clr = 0x25C8, 1388 PRS0_ASYNCH6_Route_Clr = 0x25CC, 1389 PRS0_ASYNCH7_Route_Clr = 0x25D0, 1390 PRS0_ASYNCH8_Route_Clr = 0x25D4, 1391 PRS0_ASYNCH9_Route_Clr = 0x25D8, 1392 PRS0_ASYNCH10_Route_Clr = 0x25DC, 1393 PRS0_ASYNCH11_Route_Clr = 0x25E0, 1394 PRS0_ASYNCH12_Route_Clr = 0x25E4, 1395 PRS0_ASYNCH13_Route_Clr = 0x25E8, 1396 PRS0_ASYNCH14_Route_Clr = 0x25EC, 1397 PRS0_ASYNCH15_Route_Clr = 0x25F0, 1398 PRS0_SYNCH0_Route_Clr = 0x25F4, 1399 PRS0_SYNCH1_Route_Clr = 0x25F8, 1400 PRS0_SYNCH2_Route_Clr = 0x25FC, 1401 PRS0_SYNCH3_Route_Clr = 0x2600, 1402 RAC_RouteEnable_Clr = 0x2608, 1403 RAC_LNAEN_Route_Clr = 0x260C, 1404 RAC_PAEN_Route_Clr = 0x2610, 1405 RFECA0_RouteEnable_Clr = 0x2618, 1406 RFECA0_DATAOUT0_Route_Clr = 0x261C, 1407 RFECA0_DATAOUT1_Route_Clr = 0x2620, 1408 RFECA0_DATAOUT2_Route_Clr = 0x2624, 1409 RFECA0_DATAOUT3_Route_Clr = 0x2628, 1410 RFECA0_DATAOUT4_Route_Clr = 0x262C, 1411 RFECA0_DATAOUT5_Route_Clr = 0x2630, 1412 RFECA0_DATAOUT6_Route_Clr = 0x2634, 1413 RFECA0_DATAOUT7_Route_Clr = 0x2638, 1414 RFECA0_DATAOUT8_Route_Clr = 0x263C, 1415 RFECA0_DATAOUT9_Route_Clr = 0x2640, 1416 RFECA0_DATAOUT10_Route_Clr = 0x2644, 1417 RFECA0_DATAOUT11_Route_Clr = 0x2648, 1418 RFECA0_DATAOUT12_Route_Clr = 0x264C, 1419 RFECA0_DATAOUT13_Route_Clr = 0x2650, 1420 RFECA0_DATAOUT14_Route_Clr = 0x2654, 1421 RFECA0_DATAOUT15_Route_Clr = 0x2658, 1422 RFECA0_DATAOUT16_Route_Clr = 0x265C, 1423 RFECA0_DATAOUT17_Route_Clr = 0x2660, 1424 RFECA0_DATAOUT18_Route_Clr = 0x2664, 1425 RFECA0_DATAVALID_Route_Clr = 0x2668, 1426 RFECA0_TRIGGERIN_Route_Clr = 0x266C, 1427 SYXO0_BUFOUTREQINASYNC_Route_Clr = 0x2678, 1428 TIMER0_RouteEnable_Clr = 0x2680, 1429 TIMER0_CC0_Route_Clr = 0x2684, 1430 TIMER0_CC1_Route_Clr = 0x2688, 1431 TIMER0_CC2_Route_Clr = 0x268C, 1432 TIMER0_CDTI0_Route_Clr = 0x2690, 1433 TIMER0_CDTI1_Route_Clr = 0x2694, 1434 TIMER0_CDTI2_Route_Clr = 0x2698, 1435 TIMER1_RouteEnable_Clr = 0x26A0, 1436 TIMER1_CC0_Route_Clr = 0x26A4, 1437 TIMER1_CC1_Route_Clr = 0x26A8, 1438 TIMER1_CC2_Route_Clr = 0x26AC, 1439 TIMER1_CDTI0_Route_Clr = 0x26B0, 1440 TIMER1_CDTI1_Route_Clr = 0x26B4, 1441 TIMER1_CDTI2_Route_Clr = 0x26B8, 1442 TIMER2_RouteEnable_Clr = 0x26C0, 1443 TIMER2_CC0_Route_Clr = 0x26C4, 1444 TIMER2_CC1_Route_Clr = 0x26C8, 1445 TIMER2_CC2_Route_Clr = 0x26CC, 1446 TIMER2_CDTI0_Route_Clr = 0x26D0, 1447 TIMER2_CDTI1_Route_Clr = 0x26D4, 1448 TIMER2_CDTI2_Route_Clr = 0x26D8, 1449 TIMER3_RouteEnable_Clr = 0x26E0, 1450 TIMER3_CC0_Route_Clr = 0x26E4, 1451 TIMER3_CC1_Route_Clr = 0x26E8, 1452 TIMER3_CC2_Route_Clr = 0x26EC, 1453 TIMER3_CDTI0_Route_Clr = 0x26F0, 1454 TIMER3_CDTI1_Route_Clr = 0x26F4, 1455 TIMER3_CDTI2_Route_Clr = 0x26F8, 1456 TIMER4_RouteEnable_Clr = 0x2700, 1457 TIMER4_CC0_Route_Clr = 0x2704, 1458 TIMER4_CC1_Route_Clr = 0x2708, 1459 TIMER4_CC2_Route_Clr = 0x270C, 1460 TIMER4_CDTI0_Route_Clr = 0x2710, 1461 TIMER4_CDTI1_Route_Clr = 0x2714, 1462 TIMER4_CDTI2_Route_Clr = 0x2718, 1463 USART0_RouteEnable_Clr = 0x2720, 1464 USART0_CS_Route_Clr = 0x2724, 1465 USART0_CTS_Route_Clr = 0x2728, 1466 USART0_RTS_Route_Clr = 0x272C, 1467 USART0_RX_Route_Clr = 0x2730, 1468 USART0_CLK_Route_Clr = 0x2734, 1469 USART0_TX_Route_Clr = 0x2738, 1470 RootAccessTypeDescriptor0_Clr = 0x2740, 1471 RootAccessTypeDescriptor1_Clr = 0x2744, 1472 RootAccessTypeDescriptor6_Clr = 0x2758, 1473 RootAccessTypeDescriptor8_Clr = 0x2760, 1474 RootAccessTypeDescriptor9_Clr = 0x2764, 1475 RootAccessTypeDescriptor10_Clr = 0x2768, 1476 RootAccessTypeDescriptor11_Clr = 0x276C, 1477 RootAccessTypeDescriptor12_Clr = 0x2770, 1478 RootAccessTypeDescriptor13_Clr = 0x2774, 1479 RootAccessTypeDescriptor14_Clr = 0x2778, 1480 // Toggle registers 1481 IpVersion_Tgl = 0x3000, 1482 PortAControl_Tgl = 0x3030, 1483 PortAModeLow_Tgl = 0x3034, 1484 PortAModeHigh_Tgl = 0x303C, 1485 PortADataOut_Tgl = 0x3040, 1486 PortADataIn_Tgl = 0x3044, 1487 PortBControl_Tgl = 0x3060, 1488 PortBModeLow_Tgl = 0x3064, 1489 PortBModeHigh_Tgl = 0x306C, 1490 PortBDataOut_Tgl = 0x3070, 1491 PortBDataIn_Tgl = 0x3074, 1492 PortCControl_Tgl = 0x3090, 1493 PortCModeLow_Tgl = 0x3094, 1494 PortCModeHigh_Tgl = 0x309C, 1495 PortCDataOut_Tgl = 0x30A0, 1496 PortCDataIn_Tgl = 0x30A4, 1497 PortDControl_Tgl = 0x30C0, 1498 PortDModeLow_Tgl = 0x30C4, 1499 PortDModeHigh_Tgl = 0x30CC, 1500 PortDDataOut_Tgl = 0x30D0, 1501 PortDDataIn_Tgl = 0x30D4, 1502 Lock_Tgl = 0x3300, 1503 LockStatus_Tgl = 0x3310, 1504 ABusAllocation_Tgl = 0x3320, 1505 BBusAllocation_Tgl = 0x3324, 1506 CDBusAllocation_Tgl = 0x3328, 1507 AOdd0Switch_Tgl = 0x3330, 1508 AOdd1Switch_Tgl = 0x3334, 1509 AEven0Switch_Tgl = 0x3338, 1510 AEven1Switch_Tgl = 0x333C, 1511 BOdd0Switch_Tgl = 0x3340, 1512 BOdd1Switch_Tgl = 0x3344, 1513 BEven0Switch_Tgl = 0x3348, 1514 BEven1Switch_Tgl = 0x334C, 1515 CDOdd0Switch_Tgl = 0x3350, 1516 CDOdd1Switch_Tgl = 0x3354, 1517 CDEven0Switch_Tgl = 0x3358, 1518 CDEven1Switch_Tgl = 0x335C, 1519 ExternalInterruptPortSelectLow_Tgl = 0x3400, 1520 ExternalInterruptPortSelectHigh_Tgl = 0x3404, 1521 ExternalInterruptPinSelectLow_Tgl = 0x3408, 1522 ExternalInterruptPinSelectHigh_Tgl = 0x340C, 1523 ExternalInterruptRisingEdgeTrigger_Tgl = 0x3410, 1524 ExternalInterruptFallingEdgeTrigger_Tgl = 0x3414, 1525 InterruptFlag_Tgl = 0x3420, 1526 InterruptEnable_Tgl = 0x3424, 1527 EM4WakeUpEnable_Tgl = 0x342C, 1528 EM4WakeUpPolarity_Tgl = 0x3430, 1529 DebugRoutePinEn_Tgl = 0x3440, 1530 TraceRoutePinEn_Tgl = 0x3444, 1531 ACMP0_RouteEnable_Tgl = 0x3450, 1532 ACMP0_ACMPOUT_Route_Tgl = 0x3454, 1533 ACMP1_RouteEnable_Tgl = 0x345C, 1534 ACMP1_ACMPOUT_Route_Tgl = 0x3460, 1535 CMU_RouteEnable_Tgl = 0x3468, 1536 CMU_CLKIN0_Route_Tgl = 0x346C, 1537 CMU_CLKOUT0_Route_Tgl = 0x3470, 1538 CMU_CLKOUT1_Route_Tgl = 0x3474, 1539 CMU_CLKOUT2_Route_Tgl = 0x3478, 1540 CMU_CLKOUTHIDDEN_Route_Tgl = 0x347C, 1541 DCDC_RouteEnable_Tgl = 0x3484, 1542 DCDC_COREHIDDEN_Route_Tgl = 0x3488, 1543 DCDC_VCMPHIDDEN_Route_Tgl = 0x348C, 1544 EUSART0_RouteEnable_Tgl = 0x3494, 1545 EUSART0_CS_Route_Tgl = 0x3498, 1546 EUSART0_CTS_Route_Tgl = 0x349C, 1547 EUSART0_RTS_Route_Tgl = 0x34A0, 1548 EUSART0_RX_Route_Tgl = 0x34A4, 1549 EUSART0_SCLK_Route_Tgl = 0x34A8, 1550 EUSART0_TX_Route_Tgl = 0x34AC, 1551 EUSART1_RouteEnable_Tgl = 0x34B4, 1552 EUSART1_CS_Route_Tgl = 0x34B8, 1553 EUSART1_CTS_Route_Tgl = 0x34BC, 1554 EUSART1_RTS_Route_Tgl = 0x34C0, 1555 EUSART1_RX_Route_Tgl = 0x34C4, 1556 EUSART1_SCLK_Route_Tgl = 0x34C8, 1557 EUSART1_TX_Route_Tgl = 0x34CC, 1558 FRC_RouteEnable_Tgl = 0x34D4, 1559 FRC_DCLK_Route_Tgl = 0x34D8, 1560 FRC_DFRAME_Route_Tgl = 0x34DC, 1561 FRC_DOUT_Route_Tgl = 0x34E0, 1562 I2C0_RouteEnable_Tgl = 0x34E8, 1563 I2C0_SCL_Route_Tgl = 0x34EC, 1564 I2C0_SDA_Route_Tgl = 0x34F0, 1565 I2C1_RouteEnable_Tgl = 0x34F8, 1566 I2C1_SCL_Route_Tgl = 0x34FC, 1567 I2C1_SDA_Route_Tgl = 0x3500, 1568 KEYSCAN_RouteEnable_Tgl = 0x3508, 1569 KEYSCAN_COLOUT0_Route_Tgl = 0x350C, 1570 KEYSCAN_COLOUT1_Route_Tgl = 0x3510, 1571 KEYSCAN_COLOUT2_Route_Tgl = 0x3514, 1572 KEYSCAN_COLOUT3_Route_Tgl = 0x3518, 1573 KEYSCAN_COLOUT4_Route_Tgl = 0x351C, 1574 KEYSCAN_COLOUT5_Route_Tgl = 0x3520, 1575 KEYSCAN_COLOUT6_Route_Tgl = 0x3524, 1576 KEYSCAN_COLOUT7_Route_Tgl = 0x3528, 1577 KEYSCAN_ROWSENSE0_Route_Tgl = 0x352C, 1578 KEYSCAN_ROWSENSE1_Route_Tgl = 0x3530, 1579 KEYSCAN_ROWSENSE2_Route_Tgl = 0x3534, 1580 KEYSCAN_ROWSENSE3_Route_Tgl = 0x3538, 1581 KEYSCAN_ROWSENSE4_Route_Tgl = 0x353C, 1582 KEYSCAN_ROWSENSE5_Route_Tgl = 0x3540, 1583 LETIMER_RouteEnable_Tgl = 0x3548, 1584 LETIMER_OUT0_Route_Tgl = 0x354C, 1585 LETIMER_OUT1_Route_Tgl = 0x3550, 1586 MODEM_RouteEnable_Tgl = 0x3558, 1587 MODEM_ANT0_Route_Tgl = 0x355C, 1588 MODEM_ANT1_Route_Tgl = 0x3560, 1589 MODEM_ANTROLLOVER_Route_Tgl = 0x3564, 1590 MODEM_ANTRR0_Route_Tgl = 0x3568, 1591 MODEM_ANTRR1_Route_Tgl = 0x356C, 1592 MODEM_ANTRR2_Route_Tgl = 0x3570, 1593 MODEM_ANTRR3_Route_Tgl = 0x3574, 1594 MODEM_ANTRR4_Route_Tgl = 0x3578, 1595 MODEM_ANTRR5_Route_Tgl = 0x357C, 1596 MODEM_ANTSWEN_Route_Tgl = 0x3580, 1597 MODEM_ANTSWUS_Route_Tgl = 0x3584, 1598 MODEM_ANTTRIG_Route_Tgl = 0x3588, 1599 MODEM_ANTTRIGSTOP_Route_Tgl = 0x358C, 1600 MODEM_DCLK_Route_Tgl = 0x3590, 1601 MODEM_DIN_Route_Tgl = 0x3594, 1602 MODEM_DOUT_Route_Tgl = 0x3598, 1603 MODEM_S0IN_Route_Tgl = 0x35A4, 1604 MODEM_S1IN_Route_Tgl = 0x35A8, 1605 PRS0_RouteEnable_Tgl = 0x35B0, 1606 PRS0_ASYNCH0_Route_Tgl = 0x35B4, 1607 PRS0_ASYNCH1_Route_Tgl = 0x35B8, 1608 PRS0_ASYNCH2_Route_Tgl = 0x35BC, 1609 PRS0_ASYNCH3_Route_Tgl = 0x35C0, 1610 PRS0_ASYNCH4_Route_Tgl = 0x35C4, 1611 PRS0_ASYNCH5_Route_Tgl = 0x35C8, 1612 PRS0_ASYNCH6_Route_Tgl = 0x35CC, 1613 PRS0_ASYNCH7_Route_Tgl = 0x35D0, 1614 PRS0_ASYNCH8_Route_Tgl = 0x35D4, 1615 PRS0_ASYNCH9_Route_Tgl = 0x35D8, 1616 PRS0_ASYNCH10_Route_Tgl = 0x35DC, 1617 PRS0_ASYNCH11_Route_Tgl = 0x35E0, 1618 PRS0_ASYNCH12_Route_Tgl = 0x35E4, 1619 PRS0_ASYNCH13_Route_Tgl = 0x35E8, 1620 PRS0_ASYNCH14_Route_Tgl = 0x35EC, 1621 PRS0_ASYNCH15_Route_Tgl = 0x35F0, 1622 PRS0_SYNCH0_Route_Tgl = 0x35F4, 1623 PRS0_SYNCH1_Route_Tgl = 0x35F8, 1624 PRS0_SYNCH2_Route_Tgl = 0x35FC, 1625 PRS0_SYNCH3_Route_Tgl = 0x3600, 1626 RAC_RouteEnable_Tgl = 0x3608, 1627 RAC_LNAEN_Route_Tgl = 0x360C, 1628 RAC_PAEN_Route_Tgl = 0x3610, 1629 RFECA0_RouteEnable_Tgl = 0x3618, 1630 RFECA0_DATAOUT0_Route_Tgl = 0x361C, 1631 RFECA0_DATAOUT1_Route_Tgl = 0x3620, 1632 RFECA0_DATAOUT2_Route_Tgl = 0x3624, 1633 RFECA0_DATAOUT3_Route_Tgl = 0x3628, 1634 RFECA0_DATAOUT4_Route_Tgl = 0x362C, 1635 RFECA0_DATAOUT5_Route_Tgl = 0x3630, 1636 RFECA0_DATAOUT6_Route_Tgl = 0x3634, 1637 RFECA0_DATAOUT7_Route_Tgl = 0x3638, 1638 RFECA0_DATAOUT8_Route_Tgl = 0x363C, 1639 RFECA0_DATAOUT9_Route_Tgl = 0x3640, 1640 RFECA0_DATAOUT10_Route_Tgl = 0x3644, 1641 RFECA0_DATAOUT11_Route_Tgl = 0x3648, 1642 RFECA0_DATAOUT12_Route_Tgl = 0x364C, 1643 RFECA0_DATAOUT13_Route_Tgl = 0x3650, 1644 RFECA0_DATAOUT14_Route_Tgl = 0x3654, 1645 RFECA0_DATAOUT15_Route_Tgl = 0x3658, 1646 RFECA0_DATAOUT16_Route_Tgl = 0x365C, 1647 RFECA0_DATAOUT17_Route_Tgl = 0x3660, 1648 RFECA0_DATAOUT18_Route_Tgl = 0x3664, 1649 RFECA0_DATAVALID_Route_Tgl = 0x3668, 1650 RFECA0_TRIGGERIN_Route_Tgl = 0x366C, 1651 SYXO0_BUFOUTREQINASYNC_Route_Tgl = 0x3678, 1652 TIMER0_RouteEnable_Tgl = 0x3680, 1653 TIMER0_CC0_Route_Tgl = 0x3684, 1654 TIMER0_CC1_Route_Tgl = 0x3688, 1655 TIMER0_CC2_Route_Tgl = 0x368C, 1656 TIMER0_CDTI0_Route_Tgl = 0x3690, 1657 TIMER0_CDTI1_Route_Tgl = 0x3694, 1658 TIMER0_CDTI2_Route_Tgl = 0x3698, 1659 TIMER1_RouteEnable_Tgl = 0x36A0, 1660 TIMER1_CC0_Route_Tgl = 0x36A4, 1661 TIMER1_CC1_Route_Tgl = 0x36A8, 1662 TIMER1_CC2_Route_Tgl = 0x36AC, 1663 TIMER1_CDTI0_Route_Tgl = 0x36B0, 1664 TIMER1_CDTI1_Route_Tgl = 0x36B4, 1665 TIMER1_CDTI2_Route_Tgl = 0x36B8, 1666 TIMER2_RouteEnable_Tgl = 0x36C0, 1667 TIMER2_CC0_Route_Tgl = 0x36C4, 1668 TIMER2_CC1_Route_Tgl = 0x36C8, 1669 TIMER2_CC2_Route_Tgl = 0x36CC, 1670 TIMER2_CDTI0_Route_Tgl = 0x36D0, 1671 TIMER2_CDTI1_Route_Tgl = 0x36D4, 1672 TIMER2_CDTI2_Route_Tgl = 0x36D8, 1673 TIMER3_RouteEnable_Tgl = 0x36E0, 1674 TIMER3_CC0_Route_Tgl = 0x36E4, 1675 TIMER3_CC1_Route_Tgl = 0x36E8, 1676 TIMER3_CC2_Route_Tgl = 0x36EC, 1677 TIMER3_CDTI0_Route_Tgl = 0x36F0, 1678 TIMER3_CDTI1_Route_Tgl = 0x36F4, 1679 TIMER3_CDTI2_Route_Tgl = 0x36F8, 1680 TIMER4_RouteEnable_Tgl = 0x3700, 1681 TIMER4_CC0_Route_Tgl = 0x3704, 1682 TIMER4_CC1_Route_Tgl = 0x3708, 1683 TIMER4_CC2_Route_Tgl = 0x370C, 1684 TIMER4_CDTI0_Route_Tgl = 0x3710, 1685 TIMER4_CDTI1_Route_Tgl = 0x3714, 1686 TIMER4_CDTI2_Route_Tgl = 0x3718, 1687 USART0_RouteEnable_Tgl = 0x3720, 1688 USART0_CS_Route_Tgl = 0x3724, 1689 USART0_CTS_Route_Tgl = 0x3728, 1690 USART0_RTS_Route_Tgl = 0x372C, 1691 USART0_RX_Route_Tgl = 0x3730, 1692 USART0_CLK_Route_Tgl = 0x3734, 1693 USART0_TX_Route_Tgl = 0x3738, 1694 RootAccessTypeDescriptor0_Tgl = 0x3740, 1695 RootAccessTypeDescriptor1_Tgl = 0x3744, 1696 RootAccessTypeDescriptor6_Tgl = 0x3758, 1697 RootAccessTypeDescriptor8_Tgl = 0x3760, 1698 RootAccessTypeDescriptor9_Tgl = 0x3764, 1699 RootAccessTypeDescriptor10_Tgl = 0x3768, 1700 RootAccessTypeDescriptor11_Tgl = 0x376C, 1701 RootAccessTypeDescriptor12_Tgl = 0x3770, 1702 RootAccessTypeDescriptor13_Tgl = 0x3774, 1703 RootAccessTypeDescriptor14_Tgl = 0x3778, 1704 } 1705 #endregion 1706 } 1707 }