1 // 2 // Copyright (c) 2010-2022 Antmicro 3 // 4 // This file is licensed under the MIT License. 5 // Full license text is available in 'licenses/MIT.txt'. 6 // 7 using Antmicro.Renode.Core; 8 using Antmicro.Renode.Core.Structure.Registers; 9 using Antmicro.Renode.Logging; 10 using Antmicro.Renode.Peripherals.Bus; 11 using System; 12 13 namespace Antmicro.Renode.Peripherals.GPIOPort 14 { 15 [AllowedTranslations(AllowedTranslation.ByteToDoubleWord | AllowedTranslation.WordToDoubleWord)] 16 public class AmbiqApollo4_GPIO : BaseGPIOPort, IProvidesRegisterCollection<DoubleWordRegisterCollection>, IDoubleWordPeripheral, IKnownSize 17 { AmbiqApollo4_GPIO(IMachine machine)18 public AmbiqApollo4_GPIO(IMachine machine) : base(machine, NumberOfPins) 19 { 20 RegistersCollection = new DoubleWordRegisterCollection(this); 21 22 DefineRegisters(); 23 Reset(); 24 } 25 Reset()26 public override void Reset() 27 { 28 base.Reset(); 29 RegistersCollection.Reset(); 30 31 outputPinValues.Initialize(); 32 tristatePinOutputEnabled.Initialize(); 33 } 34 OnGPIO(int number, bool value)35 public override void OnGPIO(int number, bool value) 36 { 37 if(!CheckPinNumber(number)) 38 { 39 return; 40 } 41 42 var oldState = State[number]; 43 base.OnGPIO(number, value); 44 45 if(inputEnable[number].Value && oldState != value) 46 { 47 HandlePinStateChangeInterrupt(number, risingEdge: value); 48 } 49 } 50 ReadDoubleWord(long offset)51 public uint ReadDoubleWord(long offset) 52 { 53 return RegistersCollection.Read(offset); 54 } 55 WriteDoubleWord(long offset, uint value)56 public void WriteDoubleWord(long offset, uint value) 57 { 58 if(offset >= (long)Registers.PinConfiguration0 && offset <= (long)Registers.PinConfiguration127) 59 { 60 if(padKey.Value != PadKeyUnlockValue) 61 { 62 this.Log(LogLevel.Warning, "Tried to change pin configuration register which is locked. PADKEY value: {0:X}", padKey.Value); 63 return; 64 } 65 } 66 RegistersCollection.Write(offset, value); 67 } 68 69 public long Size => 0x440; 70 71 public GPIO McuN0IrqBank0 => irq[(int)IrqType.McuN0IrqBank0]; 72 public GPIO McuN0IrqBank1 => irq[(int)IrqType.McuN0IrqBank1]; 73 public GPIO McuN0IrqBank2 => irq[(int)IrqType.McuN0IrqBank2]; 74 public GPIO McuN0IrqBank3 => irq[(int)IrqType.McuN0IrqBank3]; 75 public GPIO McuN1IrqBank0 => irq[(int)IrqType.McuN1IrqBank0]; 76 public GPIO McuN1IrqBank1 => irq[(int)IrqType.McuN1IrqBank1]; 77 public GPIO McuN1IrqBank2 => irq[(int)IrqType.McuN1IrqBank2]; 78 public GPIO McuN1IrqBank3 => irq[(int)IrqType.McuN1IrqBank3]; 79 80 public DoubleWordRegisterCollection RegistersCollection { get; } 81 DefineRegisters()82 private void DefineRegisters() 83 { 84 Registers.PinConfiguration0.DefineMany(this, NumberOfPins, (register, regIdx) => 85 { 86 register 87 .WithValueField(0, 4, name: $"FUNCSEL{regIdx} - Function select for GPIO pin {regIdx}") 88 .WithFlag(4, out inputEnable[regIdx], name: $"INPEN{regIdx} - Input enable for GPIO {regIdx}", 89 changeCallback: (_, newValue) => { if(State[regIdx]) HandlePinStateChangeInterrupt(regIdx, risingEdge: newValue); }) 90 .WithFlag(5, out readZero[regIdx], name: $"RDZERO{regIdx} - Return 0 for read data on GPIO {regIdx}") 91 .WithEnumField(6, 2, out interruptMode[regIdx], name: $"IRPTEN{regIdx} - Interrupt enable for GPIO {regIdx}") 92 .WithEnumField(8, 2, out ioMode[regIdx], name: $"OUTCFG{regIdx} - Pin IO mode selection for GPIO pin {regIdx}", 93 changeCallback: (_, __) => UpdateOutputPinState(regIdx)) 94 .WithWriteCallback((_, __) => 95 { 96 this.Log(LogLevel.Noisy, "Pin #{0} configured to IO mode {1}, input enable: {2}", regIdx, ioMode[regIdx].Value, inputEnable[regIdx].Value); 97 }); 98 99 if(regIdx < FirstVirtualPinIndex) 100 { 101 register 102 .WithEnumField<DoubleWordRegister, DriveStrength>(10, 2, name: $"DS{regIdx} - Drive strength selection for GPIO {regIdx}") 103 .WithFlag(12, name: $"SR{regIdx} - Configure the slew rate") 104 .WithEnumField<DoubleWordRegister, PullUpDownConfiguration>(13, 3, name: $"PULLCFG30 - Pullup/Pulldown configuration for GPIO {regIdx}") 105 .WithEnumField<DoubleWordRegister, ChipSelectConfiguration>(16, 6, name: $"NCESRC{regIdx} - IOMSTR/MSPI N Chip Select {regIdx}, DISP control signals DE, CSX, and CS") 106 .WithEnumField<DoubleWordRegister, PolarityConfiguration>(22, 1, name: $"NCEPOL{regIdx} - Polarity select for NCE for GPIO {regIdx}") 107 .WithReservedBits(23, 2) 108 .WithFlag(25, name: $"VDDPWRSWEN{regIdx} - VDD power switch enable") 109 .WithFlag(26, name: $"FIEN{regIdx} - Force input enable active regardless of function selected") 110 .WithFlag(27, name: $"FOEN{regIdx} - Force output enable active regardless of function selected") 111 .WithReservedBits(28, 4); 112 } 113 else 114 { 115 register.WithReservedBits(10, 22); 116 } 117 }, resetValue: 0x3 /* FUNCSEL: GPIO */); 118 119 Registers.OutputWrite0.DefineMany(this, NumberOfBanks, (register, regIdx) => 120 { 121 register.WithFlags(0, PinsPerBank, name: $"WT{regIdx} - GPIO Output {regIdx}", writeCallback: (bitIdx, _, value) => 122 { 123 var pinIdx = regIdx * PinsPerBank + bitIdx; 124 125 // Let's only call the method if the pins value is really changed. 126 if(outputPinValues[pinIdx] != value) 127 { 128 SetOutputPinValue(pinIdx, value); 129 } 130 }, valueProviderCallback: (bitIdx, _) => 131 { 132 var pinIdx = regIdx * PinsPerBank + bitIdx; 133 return outputPinValues[pinIdx]; 134 }); 135 }); 136 137 Registers.OutputSet0.DefineMany(this, NumberOfBanks, (register, regIdx) => 138 { 139 register.WithFlags(0, PinsPerBank, name: $"WTS{regIdx} - GPIO Output Set {regIdx}", writeCallback: (bitIdx, _, value) => 140 { 141 if(value) 142 { 143 SetOutputPinValue(regIdx * PinsPerBank + bitIdx, true); 144 } 145 }); 146 }); 147 148 Registers.OutputClear0.DefineMany(this, NumberOfBanks, (register, regIdx) => 149 { 150 register.WithFlags(0, PinsPerBank, name: $"WTC{regIdx} - GPIO Output Clear {regIdx}", writeCallback: (bitIdx, _, value) => 151 { 152 if(value) 153 { 154 SetOutputPinValue(regIdx * PinsPerBank + bitIdx, false); 155 } 156 }); 157 }); 158 159 Registers.GPIOOutputEnable0.DefineMany(this, NumberOfBanks, (register, regIdx) => 160 { 161 register.WithFlags(0, PinsPerBank, name: $"EN{regIdx} - GPIO Enable {regIdx}", 162 valueProviderCallback: (bitIdx, _) => tristatePinOutputEnabled[regIdx * PinsPerBank + bitIdx], 163 writeCallback: (bitIdx, _, value) => 164 { 165 EnableTristatePinOutputState(regIdx * PinsPerBank + bitIdx, value); 166 }); 167 }); 168 169 Registers.GPIOOutputEnableSet0.DefineMany(this, NumberOfBanks, (register, regIdx) => 170 { 171 register.WithFlags(0, PinsPerBank, name: $"ENS{regIdx} - GPIO Enable Set {regIdx}", 172 valueProviderCallback: (bitIdx, _) => tristatePinOutputEnabled[regIdx * PinsPerBank + bitIdx], 173 writeCallback: (bitIdx, _, value) => 174 { 175 if(!value) 176 { 177 return; 178 } 179 180 EnableTristatePinOutputState(regIdx * PinsPerBank + bitIdx, true); 181 }); 182 }); 183 184 Registers.GPIOOutputEnableClear0.DefineMany(this, NumberOfBanks, (register, regIdx) => 185 { 186 register.WithFlags(0, PinsPerBank, name: $"ENC{regIdx} - GPIO Enable Clear {regIdx}", 187 valueProviderCallback: (bitIdx, _) => tristatePinOutputEnabled[regIdx * PinsPerBank + bitIdx], 188 writeCallback: (bitIdx, _, value) => 189 { 190 if(!value) 191 { 192 return; 193 } 194 195 EnableTristatePinOutputState(regIdx * PinsPerBank + bitIdx, false); 196 }); 197 }); 198 199 Registers.InputRead0.DefineMany(this, NumberOfBanks, (register, regIdx) => 200 { 201 register.WithFlags(0, PinsPerBank, FieldMode.Read, name: $"RD{regIdx} - Pin {regIdx} state", valueProviderCallback: (bitIdx, _) => 202 { 203 var pinIdx = regIdx * PinsPerBank + bitIdx; 204 205 return readZero[pinIdx].Value || !inputEnable[pinIdx].Value 206 ? false 207 : State[pinIdx]; 208 }); 209 }); 210 211 foreach(var descriptor in new[] 212 { 213 new { Register = Registers.MCUPriorityN0InterruptEnable0, Type = IrqType.McuN0IrqBank0 }, 214 new { Register = Registers.MCUPriorityN0InterruptEnable1, Type = IrqType.McuN0IrqBank1 }, 215 new { Register = Registers.MCUPriorityN0InterruptEnable2, Type = IrqType.McuN0IrqBank2 }, 216 new { Register = Registers.MCUPriorityN0InterruptEnable3, Type = IrqType.McuN0IrqBank3 }, 217 218 new { Register = Registers.MCUPriorityN1InterruptEnable0, Type = IrqType.McuN1IrqBank0 }, 219 new { Register = Registers.MCUPriorityN1InterruptEnable1, Type = IrqType.McuN1IrqBank1 }, 220 new { Register = Registers.MCUPriorityN1InterruptEnable2, Type = IrqType.McuN1IrqBank2 }, 221 new { Register = Registers.MCUPriorityN1InterruptEnable3, Type = IrqType.McuN1IrqBank3 }, 222 }) 223 { 224 descriptor.Register.Define(this) 225 .WithFlags(0, PinsPerBank, out irqEnabled[(int)descriptor.Type]) 226 .WithWriteCallback((_, __) => UpdateInterrupt(descriptor.Type)); 227 } 228 229 foreach(var descriptor in new[] 230 { 231 new { Register = Registers.MCUPriorityN0InterruptStatus0, Type = IrqType.McuN0IrqBank0 }, 232 new { Register = Registers.MCUPriorityN0InterruptStatus1, Type = IrqType.McuN0IrqBank1 }, 233 new { Register = Registers.MCUPriorityN0InterruptStatus2, Type = IrqType.McuN0IrqBank2 }, 234 new { Register = Registers.MCUPriorityN0InterruptStatus3, Type = IrqType.McuN0IrqBank3 }, 235 236 new { Register = Registers.MCUPriorityN1InterruptStatus0, Type = IrqType.McuN1IrqBank0 }, 237 new { Register = Registers.MCUPriorityN1InterruptStatus1, Type = IrqType.McuN1IrqBank1 }, 238 new { Register = Registers.MCUPriorityN1InterruptStatus2, Type = IrqType.McuN1IrqBank2 }, 239 new { Register = Registers.MCUPriorityN1InterruptStatus3, Type = IrqType.McuN1IrqBank3 }, 240 }) 241 { 242 descriptor.Register.Define(this) 243 .WithFlags(0, PinsPerBank, out irqStatus[(int)descriptor.Type], FieldMode.Read); 244 } 245 246 foreach(var descriptor in new[] 247 { 248 new { Register = Registers.MCUPriorityN0InterruptClear0, Type = IrqType.McuN0IrqBank0 }, 249 new { Register = Registers.MCUPriorityN0InterruptClear1, Type = IrqType.McuN0IrqBank1 }, 250 new { Register = Registers.MCUPriorityN0InterruptClear2, Type = IrqType.McuN0IrqBank2 }, 251 new { Register = Registers.MCUPriorityN0InterruptClear3, Type = IrqType.McuN0IrqBank3 }, 252 253 new { Register = Registers.MCUPriorityN1InterruptClear0, Type = IrqType.McuN1IrqBank0 }, 254 new { Register = Registers.MCUPriorityN1InterruptClear1, Type = IrqType.McuN1IrqBank1 }, 255 new { Register = Registers.MCUPriorityN1InterruptClear2, Type = IrqType.McuN1IrqBank2 }, 256 new { Register = Registers.MCUPriorityN1InterruptClear3, Type = IrqType.McuN1IrqBank3 }, 257 }) 258 { 259 descriptor.Register.Define(this) 260 .WithFlags(0, PinsPerBank, writeCallback: (bitIdx, _, value) => 261 { 262 if(!value) 263 { 264 return; 265 } 266 267 irqStatus[(int)descriptor.Type][bitIdx].Value = false; 268 }) 269 .WithWriteCallback((_, __) => UpdateInterrupt(descriptor.Type)); 270 } 271 272 foreach(var descriptor in new[] 273 { 274 new { Register = Registers.MCUPriorityN0InterruptSet0, Type = IrqType.McuN0IrqBank0 }, 275 new { Register = Registers.MCUPriorityN0InterruptSet1, Type = IrqType.McuN0IrqBank1 }, 276 new { Register = Registers.MCUPriorityN0InterruptSet2, Type = IrqType.McuN0IrqBank2 }, 277 new { Register = Registers.MCUPriorityN0InterruptSet3, Type = IrqType.McuN0IrqBank3 }, 278 279 new { Register = Registers.MCUPriorityN1InterruptSet0, Type = IrqType.McuN1IrqBank0 }, 280 new { Register = Registers.MCUPriorityN1InterruptSet1, Type = IrqType.McuN1IrqBank1 }, 281 new { Register = Registers.MCUPriorityN1InterruptSet2, Type = IrqType.McuN1IrqBank2 }, 282 new { Register = Registers.MCUPriorityN1InterruptSet3, Type = IrqType.McuN1IrqBank3 }, 283 }) 284 { 285 descriptor.Register.Define(this) 286 .WithFlags(0, PinsPerBank, writeCallback: (bitIdx, _, value) => 287 { 288 if(!value) 289 { 290 return; 291 } 292 293 irqStatus[(int)descriptor.Type][bitIdx].Value = true; 294 }) 295 .WithWriteCallback((_, __) => UpdateInterrupt(descriptor.Type)); 296 } 297 298 Registers.PadKey.Define(this) 299 .WithValueField(0, 32, out padKey, name: "PADKEY") 300 ; 301 } 302 EnableTristatePinOutputState(int pinIdx, bool enabled)303 private void EnableTristatePinOutputState(int pinIdx, bool enabled) 304 { 305 tristatePinOutputEnabled[pinIdx] = enabled; 306 this.Log(LogLevel.Debug, "GPIO #{0} tri-state {1}", pinIdx, enabled ? "enabled" : "disabled"); 307 308 UpdateOutputPinState(pinIdx); 309 } 310 HandlePinStateChangeInterrupt(int pinIdx, bool risingEdge)311 private void HandlePinStateChangeInterrupt(int pinIdx, bool risingEdge) 312 { 313 var mode = interruptMode[pinIdx].Value; 314 if(mode == InterruptEnable.EnabledOnAnyTransition 315 || (risingEdge && mode == InterruptEnable.EnabledOnRisingEdgeTransition) 316 || (!risingEdge && mode == InterruptEnable.EnabledOnFallingEdgeTransition)) 317 { 318 this.Log(LogLevel.Noisy, "Triggering IRQ #{0} on the {1} edge", pinIdx, risingEdge ? "rising" : "falling"); 319 TriggerInterrupt(pinIdx); 320 } 321 } 322 IsPinOutputEnabled(int pinIdx)323 private bool IsPinOutputEnabled(int pinIdx) 324 { 325 switch(ioMode[pinIdx].Value) 326 { 327 case IOMode.OutputDisabled: 328 return false; 329 330 case IOMode.PushPullOutputMode: 331 return true; 332 333 case IOMode.OpenDrainOutputMode: 334 return false; 335 336 case IOMode.TristatePushPullOutputMode: 337 return tristatePinOutputEnabled[pinIdx]; 338 339 default: 340 throw new ArgumentException($"Unexpected IOMode: {ioMode[pinIdx].Value}"); 341 } 342 } 343 SetOutputPinValue(int pinIdx, bool state)344 private void SetOutputPinValue(int pinIdx, bool state) 345 { 346 outputPinValues[pinIdx] = state; 347 UpdateOutputPinState(pinIdx); 348 } 349 TriggerInterrupt(int pinIdx)350 private void TriggerInterrupt(int pinIdx) 351 { 352 var irqBank = pinIdx / PinsPerBank; 353 var banksPinOffset = pinIdx % PinsPerBank; 354 355 TriggerInterruptInner(irqBank, banksPinOffset); 356 TriggerInterruptInner(irqBank, banksPinOffset, n1Priority: true); 357 } 358 TriggerInterruptInner(int irqBank, int banksPinOffset, bool n1Priority = false)359 private void TriggerInterruptInner(int irqBank, int banksPinOffset, bool n1Priority = false) 360 { 361 var irqType = n1Priority ? irqBank + NumberOfBanks : irqBank; 362 if(irqEnabled[irqType][banksPinOffset].Value) 363 { 364 irqStatus[irqType][banksPinOffset].Value = true; 365 UpdateInterrupt((IrqType)irqType); 366 } 367 } 368 UpdateInterrupt(IrqType irqType)369 private void UpdateInterrupt(IrqType irqType) 370 { 371 var flag = false; 372 for(var banksPinOffset = 0; banksPinOffset < PinsPerBank; banksPinOffset++) 373 { 374 if(irqEnabled[(int)irqType][banksPinOffset].Value && irqStatus[(int)irqType][banksPinOffset].Value) 375 { 376 flag = true; 377 break; 378 } 379 } 380 381 this.Log(LogLevel.Debug, "{0} {1} interrupt", flag ? "Setting" : "Clearing", irqType); 382 irq[(int)irqType].Set(flag); 383 } 384 UpdateOutputPinState(int pinIdx)385 private void UpdateOutputPinState(int pinIdx) 386 { 387 var newPinState = IsPinOutputEnabled(pinIdx) && outputPinValues[pinIdx]; 388 if(Connections[pinIdx].IsSet != newPinState) 389 { 390 Connections[pinIdx].Set(newPinState); 391 this.Log(LogLevel.Debug, "{0} output pin #{1}", newPinState ? "Setting" : "Clearing", pinIdx); 392 } 393 } 394 395 private IValueRegisterField padKey; 396 397 private readonly IFlagRegisterField[] inputEnable = new IFlagRegisterField[NumberOfPins]; 398 private readonly IEnumRegisterField<InterruptEnable>[] interruptMode = new IEnumRegisterField<InterruptEnable>[NumberOfPins]; 399 private readonly IEnumRegisterField<IOMode>[] ioMode = new IEnumRegisterField<IOMode>[NumberOfPins]; 400 private readonly IFlagRegisterField[][] irqEnabled = new IFlagRegisterField[NumberOfExternalInterrupts][]; 401 private readonly IFlagRegisterField[][] irqStatus = new IFlagRegisterField[NumberOfExternalInterrupts][]; 402 private readonly IFlagRegisterField[] readZero = new IFlagRegisterField[NumberOfPins]; 403 404 private readonly GPIO[] irq = new [] { new GPIO(), new GPIO(), new GPIO(), new GPIO(), new GPIO(), new GPIO(), new GPIO(), new GPIO() }; 405 private readonly bool[] outputPinValues = new bool[NumberOfPins]; 406 private readonly bool[] tristatePinOutputEnabled = new bool[NumberOfPins]; 407 408 private const int FirstVirtualPinIndex = 105; 409 private const int NumberOfBanks = NumberOfPins / PinsPerBank; 410 private const int NumberOfExternalInterrupts = 8; 411 private const int NumberOfPins = 128; 412 private const uint PadKeyUnlockValue = 0x73; 413 private const int PinsPerBank = 32; 414 415 private enum ChipSelectConfiguration 416 { 417 IOM0CE0 = 0x0, // IOM 0 NCE 0 module 418 IOM0CE1 = 0x1, // IOM 0 NCE 1 module 419 IOM0CE2 = 0x2, // IOM 0 NCE 2 module 420 IOM0CE3 = 0x3, // IOM 0 NCE 3 module 421 IOM1CE0 = 0x4, // IOM 1 NCE 0 module 422 IOM1CE1 = 0x5, // IOM 1 NCE 1 module 423 IOM1CE2 = 0x6, // IOM 1 NCE 2 module 424 IOM1CE3 = 0x7, // IOM 1 NCE 3 module 425 IOM2CE0 = 0x8, // IOM 2 NCE 0 module 426 IOM2CE1 = 0x9, // IOM 2 NCE 1 module 427 IOM2CE2 = 0xA, // IOM 2 NCE 2 module 428 IOM2CE3 = 0xB, // IOM 2 NCE 3 module 429 IOM3CE0 = 0xC, // IOM 3 NCE 0 module 430 IOM3CE1 = 0xD, // IOM 3 NCE 1 module 431 IOM3CE2 = 0xE, // IOM 3 NCE 2 module 432 IOM3CE3 = 0xF, // IOM 3 NCE 3 module 433 IOM4CE0 = 0x10, // IOM 4 NCE 0 module 434 IOM4CE1 = 0x11, // IOM 4 NCE 1 module 435 IOM4CE2 = 0x12, // IOM 4 NCE 2 module 436 IOM4CE3 = 0x13, // IOM 4 NCE 3 module 437 IOM5CE0 = 0x14, // IOM 5 NCE 0 module 438 IOM5CE1 = 0x15, // IOM 5 NCE 1 module 439 IOM5CE2 = 0x16, // IOM 5 NCE 2 module 440 IOM5CE3 = 0x17, // IOM 5 NCE 3 module 441 IOM6CE0 = 0x18, // IOM 6 NCE 0 module 442 IOM6CE1 = 0x19, // IOM 6 NCE 1 module 443 IOM6CE2 = 0x1A, // IOM 6 NCE 2 module 444 IOM6CE3 = 0x1B, // IOM 6 NCE 3 module 445 IOM7CE0 = 0x1C, // IOM 7 NCE 0 module 446 IOM7CE1 = 0x1D, // IOM 7 NCE 1 module 447 IOM7CE2 = 0x1E, // IOM 7 NCE 2 module 448 IOM7CE3 = 0x1F, // IOM 7 NCE 3 module 449 MSPI0CEN0 = 0x20, // MSPI 0 NCE 0 module 450 MSPI0CEN1 = 0x21, // MSPI 0 NCE 1 module 451 MSPI1CEN0 = 0x22, // MSPI 1 NCE 0 module 452 MSPI1CEN1 = 0x23, // MSPI 1 NCE 1 module 453 MSPI2CEN0 = 0x24, // MSPI 2 NCE 0 module 454 MSPI2CEN1 = 0x25, // MSPI 2 NCE 1 module 455 DC_DPI_DE = 0x26, // DC DPI DE module 456 DISP_CONT_CSX = 0x27, // DISP CONT CSX module 457 DC_SPI_CS_N = 0x28, // DC SPI CS_N module 458 DC_QSPI_CS_N = 0x29, // DC QSPI CS_N module 459 DC_RESX = 0x2A, // DC module RESX 460 } 461 462 private enum DriveStrength 463 { 464 OutputDriver0_1x = 0x0, // 0.1x output driver selected 465 OutputDriver0_5x = 0x1, // 0.5x output driver selected 466 } 467 468 private enum InterruptEnable 469 { 470 Disabled = 0x0, // Interrupts are disabled for this GPIO 471 EnabledOnFallingEdgeTransition = 0x1, // Interrupts are enabled for falling edge transition on this GPIO 472 EnabledOnRisingEdgeTransition = 0x2, // Interrupts are enabled for rising edge transitions on this GPIO 473 EnabledOnAnyTransition = 0x3, // Interrupts are enabled for any edge transition on this GPIO 474 } 475 476 private enum IOMode 477 { 478 OutputDisabled = 0x0, // Output Disabled 479 PushPullOutputMode = 0x1, // Output configured in push pull mode. Will drive 0 and 1 values on pin. 480 OpenDrainOutputMode = 0x2, // Output configured in open drain mode. Will only drive pin low, tristate otherwise. 481 TristatePushPullOutputMode = 0x3, // Output configured in Tristate-able push pull mode. Will drive 0, 1 of HiZ on pin. 482 } 483 484 private enum IrqType 485 { 486 McuN0IrqBank0, 487 McuN0IrqBank1, 488 McuN0IrqBank2, 489 McuN0IrqBank3, 490 McuN1IrqBank0, 491 McuN1IrqBank1, 492 McuN1IrqBank2, 493 McuN1IrqBank3 494 } 495 496 private enum PolarityConfiguration 497 { 498 ActiveLow = 0x0, // Polarity is active low 499 ActiveHigh = 0x1, // Polarity is active high 500 } 501 502 private enum PullUpDownConfiguration 503 { 504 None = 0x0, // No pullup or pulldown selected 505 Pulldown50K = 0x1, // 50K Pulldown selected 506 Pullup1_5K = 0x2, // 1.5K Pullup selected 507 Pullup6K = 0x3, // 6K Pullup selected 508 Pullup12K = 0x4, // 12K Pullup selected 509 Pullup24K = 0x5, // 24K Pullup selected 510 Pullup50K = 0x6, // 50K Pullup selected 511 Pullup100K = 0x7, // 100K Pullup selected 512 } 513 514 private enum Registers : long 515 { 516 PinConfiguration0 = 0x000, // Configuration control for GPIO pin 0 517 PinConfiguration1 = 0x004, // Configuration control for GPIO pin 1 518 PinConfiguration2 = 0x008, // Configuration control for GPIO pin 2 519 PinConfiguration3 = 0x00C, // Configuration control for GPIO pin 3 520 PinConfiguration4 = 0x010, // Configuration control for GPIO pin 4 521 PinConfiguration5 = 0x014, // Configuration control for GPIO pin 5 522 PinConfiguration6 = 0x018, // Configuration control for GPIO pin 6 523 PinConfiguration7 = 0x01C, // Configuration control for GPIO pin 7 524 PinConfiguration8 = 0x020, // Configuration control for GPIO pin 8 525 PinConfiguration9 = 0x024, // Configuration control for GPIO pin 9 526 PinConfiguration10 = 0x028, // Configuration control for GPIO pin 10 527 PinConfiguration11 = 0x02C, // Configuration control for GPIO pin 11 528 PinConfiguration12 = 0x030, // Configuration control for GPIO pin 12 529 PinConfiguration13 = 0x034, // Configuration control for GPIO pin 13 530 PinConfiguration14 = 0x038, // Configuration control for GPIO pin 14 531 PinConfiguration15 = 0x03C, // Configuration control for GPIO pin 15 532 PinConfiguration16 = 0x040, // Configuration control for GPIO pin 16 533 PinConfiguration17 = 0x044, // Configuration control for GPIO pin 17 534 PinConfiguration18 = 0x048, // Configuration control for GPIO pin 18 535 PinConfiguration19 = 0x04C, // Configuration control for GPIO pin 19 536 PinConfiguration20 = 0x050, // Configuration control for GPIO pin 20 537 PinConfiguration21 = 0x054, // Configuration control for GPIO pin 21 538 PinConfiguration22 = 0x058, // Configuration control for GPIO pin 22 539 PinConfiguration23 = 0x05C, // Configuration control for GPIO pin 23 540 PinConfiguration24 = 0x060, // Configuration control for GPIO pin 24 541 PinConfiguration25 = 0x064, // Configuration control for GPIO pin 25 542 PinConfiguration26 = 0x068, // Configuration control for GPIO pin 26 543 PinConfiguration27 = 0x06C, // Configuration control for GPIO pin 27 544 PinConfiguration28 = 0x070, // Configuration control for GPIO pin 28 545 PinConfiguration29 = 0x074, // Configuration control for GPIO pin 29 546 PinConfiguration30 = 0x078, // Configuration control for GPIO pin 30 547 PinConfiguration31 = 0x07C, // Configuration control for GPIO pin 31 548 PinConfiguration32 = 0x080, // Configuration control for GPIO pin 32 549 PinConfiguration33 = 0x084, // Configuration control for GPIO pin 33 550 PinConfiguration34 = 0x088, // Configuration control for GPIO pin 34 551 PinConfiguration35 = 0x08C, // Configuration control for GPIO pin 35 552 PinConfiguration36 = 0x090, // Configuration control for GPIO pin 36 553 PinConfiguration37 = 0x094, // Configuration control for GPIO pin 37 554 PinConfiguration38 = 0x098, // Configuration control for GPIO pin 38 555 PinConfiguration39 = 0x09C, // Configuration control for GPIO pin 39 556 PinConfiguration40 = 0x0A0, // Configuration control for GPIO pin 40 557 PinConfiguration41 = 0x0A4, // Configuration control for GPIO pin 41 558 PinConfiguration42 = 0x0A8, // Configuration control for GPIO pin 42 559 PinConfiguration43 = 0x0AC, // Configuration control for GPIO pin 43 560 PinConfiguration44 = 0x0B0, // Configuration control for GPIO pin 44 561 PinConfiguration45 = 0x0B4, // Configuration control for GPIO pin 45 562 PinConfiguration46 = 0x0B8, // Configuration control for GPIO pin 46 563 PinConfiguration47 = 0x0BC, // Configuration control for GPIO pin 47 564 PinConfiguration48 = 0x0C0, // Configuration control for GPIO pin 48 565 PinConfiguration49 = 0x0C4, // Configuration control for GPIO pin 49 566 PinConfiguration50 = 0x0C8, // Configuration control for GPIO pin 50 567 PinConfiguration51 = 0x0CC, // Configuration control for GPIO pin 51 568 PinConfiguration52 = 0x0D0, // Configuration control for GPIO pin 52 569 PinConfiguration53 = 0x0D4, // Configuration control for GPIO pin 53 570 PinConfiguration54 = 0x0D8, // Configuration control for GPIO pin 54 571 PinConfiguration55 = 0x0DC, // Configuration control for GPIO pin 55 572 PinConfiguration56 = 0x0E0, // Configuration control for GPIO pin 56 573 PinConfiguration57 = 0x0E4, // Configuration control for GPIO pin 57 574 PinConfiguration58 = 0x0E8, // Configuration control for GPIO pin 58 575 PinConfiguration59 = 0x0EC, // Configuration control for GPIO pin 59 576 PinConfiguration60 = 0x0F0, // Configuration control for GPIO pin 60 577 PinConfiguration61 = 0x0F4, // Configuration control for GPIO pin 61 578 PinConfiguration62 = 0x0F8, // Configuration control for GPIO pin 62 579 PinConfiguration63 = 0x0FC, // Configuration control for GPIO pin 63 580 PinConfiguration64 = 0x100, // Configuration control for GPIO pin 64 581 PinConfiguration65 = 0x104, // Configuration control for GPIO pin 65 582 PinConfiguration66 = 0x108, // Configuration control for GPIO pin 66 583 PinConfiguration67 = 0x10C, // Configuration control for GPIO pin 67 584 PinConfiguration68 = 0x110, // Configuration control for GPIO pin 68 585 PinConfiguration69 = 0x114, // Configuration control for GPIO pin 69 586 PinConfiguration70 = 0x118, // Configuration control for GPIO pin 70 587 PinConfiguration71 = 0x11C, // Configuration control for GPIO pin 71 588 PinConfiguration72 = 0x120, // Configuration control for GPIO pin 72 589 PinConfiguration73 = 0x124, // Configuration control for GPIO pin 73 590 PinConfiguration74 = 0x128, // Configuration control for GPIO pin 74 591 PinConfiguration75 = 0x12C, // Configuration control for GPIO pin 75 592 PinConfiguration76 = 0x130, // Configuration control for GPIO pin 76 593 PinConfiguration77 = 0x134, // Configuration control for GPIO pin 77 594 PinConfiguration78 = 0x138, // Configuration control for GPIO pin 78 595 PinConfiguration79 = 0x13C, // Configuration control for GPIO pin 79 596 PinConfiguration80 = 0x140, // Configuration control for GPIO pin 80 597 PinConfiguration81 = 0x144, // Configuration control for GPIO pin 81 598 PinConfiguration82 = 0x148, // Configuration control for GPIO pin 82 599 PinConfiguration83 = 0x14C, // Configuration control for GPIO pin 83 600 PinConfiguration84 = 0x150, // Configuration control for GPIO pin 84 601 PinConfiguration85 = 0x154, // Configuration control for GPIO pin 85 602 PinConfiguration86 = 0x158, // Configuration control for GPIO pin 86 603 PinConfiguration87 = 0x15C, // Configuration control for GPIO pin 87 604 PinConfiguration88 = 0x160, // Configuration control for GPIO pin 88 605 PinConfiguration89 = 0x164, // Configuration control for GPIO pin 89 606 PinConfiguration90 = 0x168, // Configuration control for GPIO pin 90 607 PinConfiguration91 = 0x16C, // Configuration control for GPIO pin 91 608 PinConfiguration92 = 0x170, // Configuration control for GPIO pin 92 609 PinConfiguration93 = 0x174, // Configuration control for GPIO pin 93 610 PinConfiguration94 = 0x178, // Configuration control for GPIO pin 94 611 PinConfiguration95 = 0x17C, // Configuration control for GPIO pin 95 612 PinConfiguration96 = 0x180, // Configuration control for GPIO pin 96 613 PinConfiguration97 = 0x184, // Configuration control for GPIO pin 97 614 PinConfiguration98 = 0x188, // Configuration control for GPIO pin 98 615 PinConfiguration99 = 0x18C, // Configuration control for GPIO pin 99 616 PinConfiguration100 = 0x190, // Configuration control for GPIO pin 100 617 PinConfiguration101 = 0x194, // Configuration control for GPIO pin 101 618 PinConfiguration102 = 0x198, // Configuration control for GPIO pin 102 619 PinConfiguration103 = 0x19C, // Configuration control for GPIO pin 103 620 PinConfiguration104 = 0x1A0, // Configuration control for GPIO pin 104 621 PinConfiguration105 = 0x1A4, // Configuration control for Virtual GPIO pin 105 622 PinConfiguration106 = 0x1A8, // Configuration control for Virtual GPIO pin 106 623 PinConfiguration107 = 0x1AC, // Configuration control for Virtual GPIO pin 107 624 PinConfiguration108 = 0x1B0, // Configuration control for Virtual GPIO pin 108 625 PinConfiguration109 = 0x1B4, // Configuration control for Virtual GPIO pin 109 626 PinConfiguration110 = 0x1B8, // Configuration control for Virtual GPIO pin 110 627 PinConfiguration111 = 0x1BC, // Configuration control for Virtual GPIO pin 111 628 PinConfiguration112 = 0x1C0, // Configuration control for Virtual GPIO pin 112 629 PinConfiguration113 = 0x1C4, // Configuration control for Virtual GPIO pin 113 630 PinConfiguration114 = 0x1C8, // Configuration control for Virtual GPIO pin 114 631 PinConfiguration115 = 0x1CC, // Configuration control for Virtual GPIO pin 115 632 PinConfiguration116 = 0x1D0, // Configuration control for Virtual GPIO pin 116 633 PinConfiguration117 = 0x1D4, // Configuration control for Virtual GPIO pin 117 634 PinConfiguration118 = 0x1D8, // Configuration control for Virtual GPIO pin 118 635 PinConfiguration119 = 0x1DC, // Configuration control for Virtual GPIO pin 119 636 PinConfiguration120 = 0x1E0, // Configuration control for Virtual GPIO pin 120 637 PinConfiguration121 = 0x1E4, // Configuration control for Virtual GPIO pin 121 638 PinConfiguration122 = 0x1E8, // Configuration control for Virtual GPIO pin 122 639 PinConfiguration123 = 0x1EC, // Configuration control for Virtual GPIO pin 123 640 PinConfiguration124 = 0x1F0, // Configuration control for Virtual GPIO pin 124 641 PinConfiguration125 = 0x1F4, // Configuration control for Virtual GPIO pin 125 642 PinConfiguration126 = 0x1F8, // Configuration control for Virtual GPIO pin 126 643 PinConfiguration127 = 0x1FC, // Configuration control for Virtual GPIO pin 127 644 PadKey = 0x200, // Key Register for all pad configuration registers 645 InputRead0 = 0x204, // GPIO Input 0 (31-0) 646 InputRead1 = 0x208, // GPIO Input 1 (63-32) 647 InputRead2 = 0x20C, // GPIO Input 2 (95-64) 648 InputRead3 = 0x210, // GPIO Input 3 (127-96) 649 OutputWrite0 = 0x214, // GPIO Output 0 (31-0) 650 OutputWrite1 = 0x218, // GPIO Output 1 (63-32) 651 OutputWrite2 = 0x21C, // GPIO Output 2 (95-64) 652 OutputWrite3 = 0x220, // GPIO Output 3 (127-96) 653 OutputSet0 = 0x224, // GPIO Output Set 0 (31-0) 654 OutputSet1 = 0x228, // GPIO Output Set 1 (63-32) 655 OutputSet2 = 0x22C, // GPIO Output Set 2 (95-64) 656 OutputSet3 = 0x230, // GPIO Output Set 3 (127-96) 657 OutputClear0 = 0x234, // GPIO Output Clear 0 (31-0) 658 OutputClear1 = 0x238, // GPIO Output Clear 1 (63-32) 659 OutputClear2 = 0x23C, // GPIO Output Clear 2 (95-64) 660 OutputClear3 = 0x240, // GPIO Output Clear 3 (127-96) 661 GPIOOutputEnable0 = 0x244, // GPIO Enable 0 (31-0) 662 GPIOOutputEnable1 = 0x248, // GPIO Enable 1 (63-32) 663 GPIOOutputEnable2 = 0x24C, // GPIO Enable 2 (95-64) 664 GPIOOutputEnable3 = 0x250, // GPIO Enable 3 (127-96) 665 GPIOOutputEnableSet0 = 0x254, // GPIO Enable Set 0 (31-0) 666 GPIOOutputEnableSet1 = 0x258, // GPIO Enable Set 1 (63-32) 667 GPIOOutputEnableSet2 = 0x25C, // GPIO Enable Set 2 (95-64) 668 GPIOOutputEnableSet3 = 0x260, // GPIO Enable Set 3 (127-96) 669 GPIOOutputEnableClear0 = 0x264, // GPIO Enable Clear 0 (31-0) 670 GPIOOutputEnableClear1 = 0x268, // GPIO Enable Clear 1 (63-32) 671 GPIOOutputEnableClear2 = 0x26C, // GPIO Enable Clear 2 (95-64) 672 GPIOOutputEnableClear3 = 0x270, // GPIO Enable Clear 3 (127-96) 673 IOM0FlowControlIRQSelect = 0x274, // IOM0 Flow Control IRQ Select 674 IOM1FlowControlIRQSelect = 0x278, // IOM1 Flow Control IRQ Select 675 IOM2FlowControlIRQSelect = 0x27C, // IOM2 Flow Control IRQ Select 676 IOM3FlowControlIRQSelect = 0x280, // IOM3 Flow Control IRQ Select 677 IOM4FlowControlIRQSelect = 0x284, // IOM4 Flow Control IRQ Select 678 IOM5FlowControlIRQSelect = 0x288, // IOM5 Flow Control IRQ Select 679 IOM6FlowControlIRQSelect = 0x28C, // IOM6 Flow Control IRQ Select 680 IOM7FlowControlIRQSelect = 0x290, // IOM7 Flow Control IRQ Select 681 SDIFCDWPPadSelect = 0x294, // SDIF CD and WP Select 682 ObservationModeSample = 0x298, // GPIO Observation Mode Sample 683 InputEnableSignals0 = 0x29C, // Read only. Reflects the value of the input enable signals for pads 31-0 sent to the pad. 684 InputEnableSignals1 = 0x2A0, // Read only. Reflects the value of the input enable signals for pads 63-32 sent to the pad. 685 InputEnableSignals2 = 0x2A4, // Read only. Reflects the value of the input enable signals for pads 95-64 sent to the pad. 686 InputEnableSignals3 = 0x2A8, // Read only. Reflects the value of the input enable signals for pads 127-96 sent to the pad. 687 OutputEnableSignals0 = 0x2AC, // Read only. Reflects the value of the output enable signals for pads 31-0 sent to the pad. 688 OutputEnableSignals1 = 0x2B0, // Read only. Reflects the value of the output enable signals for pads 63-32 sent to the pad. 689 OutputEnableSignals2 = 0x2B4, // Read only. Reflects the value of the output enable signals for pads 95-64 sent to the pad. 690 OutputEnableSignals3 = 0x2B8, // Read only. Reflects the value of the output enable signals for pads 127-96 sent to the pad. 691 MCUPriorityN0InterruptEnable0 = 0x2C0, // GPIO MCU Interrupts N0 31-0: Enable 692 MCUPriorityN0InterruptStatus0 = 0x2C4, // GPIO MCU Interrupts N0 31-0: Status 693 MCUPriorityN0InterruptClear0 = 0x2C8, // GPIO MCU Interrupts N0 31-0: Clear 694 MCUPriorityN0InterruptSet0 = 0x2CC, // GPIO MCU Interrupts N0 31-0: Set 695 MCUPriorityN0InterruptEnable1 = 0x2D0, // GPIO MCU Interrupts N0 63-32: Enable 696 MCUPriorityN0InterruptStatus1 = 0x2D4, // GPIO MCU Interrupts N0 63-32: Status 697 MCUPriorityN0InterruptClear1 = 0x2D8, // GPIO MCU Interrupts N0 63-32: Clear 698 MCUPriorityN0InterruptSet1 = 0x2DC, // GPIO MCU Interrupts N0 63-32: Set 699 MCUPriorityN0InterruptEnable2 = 0x2E0, // GPIO MCU Interrupts N0 95-64: Enable 700 MCUPriorityN0InterruptStatus2 = 0x2E4, // GPIO MCU Interrupts N0 95-64: Status 701 MCUPriorityN0InterruptClear2 = 0x2E8, // GPIO MCU Interrupts N0 95-64: Clear 702 MCUPriorityN0InterruptSet2 = 0x2EC, // GPIO MCU Interrupts N0 95-64: Set 703 MCUPriorityN0InterruptEnable3 = 0x2F0, // GPIO MCU Interrupts N0 127-96: Enable 704 MCUPriorityN0InterruptStatus3 = 0x2F4, // GPIO MCU Interrupts N0 127-96: Status 705 MCUPriorityN0InterruptClear3 = 0x2F8, // GPIO MCU Interrupts N0 127-96: Clear 706 MCUPriorityN0InterruptSet3 = 0x2FC, // GPIO MCU Interrupts N0 127-96: Set 707 MCUPriorityN1InterruptEnable0 = 0x300, // GPIO MCU Interrupts N1 31-0: Enable 708 MCUPriorityN1InterruptStatus0 = 0x304, // GPIO MCU Interrupts N1 31-0: Status 709 MCUPriorityN1InterruptClear0 = 0x308, // GPIO MCU Interrupts N1 31-0: Clear 710 MCUPriorityN1InterruptSet0 = 0x30C, // GPIO MCU Interrupts N1 31-0: Set 711 MCUPriorityN1InterruptEnable1 = 0x310, // GPIO MCU Interrupts N1 63-32: Enable 712 MCUPriorityN1InterruptStatus1 = 0x314, // GPIO MCU Interrupts N1 63-32: Status 713 MCUPriorityN1InterruptClear1 = 0x318, // GPIO MCU Interrupts N1 63-32: Clear 714 MCUPriorityN1InterruptSet1 = 0x31C, // GPIO MCU Interrupts N1 63-32: Set 715 MCUPriorityN1InterruptEnable2 = 0x320, // GPIO MCU Interrupts N1 95-64: Enable 716 MCUPriorityN1InterruptStatus2 = 0x324, // GPIO MCU Interrupts N1 95-64: Status 717 MCUPriorityN1InterruptClear2 = 0x328, // GPIO MCU Interrupts N1 95-64: Clear 718 MCUPriorityN1InterruptSet2 = 0x32C, // GPIO MCU Interrupts N1 95-64: Set 719 MCUPriorityN1InterruptEnable3 = 0x330, // GPIO MCU Interrupts N1 127-96: Enable 720 MCUPriorityN1InterruptStatus3 = 0x334, // GPIO MCU Interrupts N1 127-96: Status 721 MCUPriorityN1InterruptClear3 = 0x338, // GPIO MCU Interrupts N1 127-96: Clear 722 MCUPriorityN1InterruptSet3 = 0x33C, // GPIO MCU Interrupts N1 127-96: Set 723 DSP0PriorityN0InterruptEnable0 = 0x340, // GPIO DSP0 Interrupts N0 31-0: Enable 724 DSP0PriorityN0InterruptStatus0 = 0x344, // GPIO DSP0 Interrupts N0 31-0: Status 725 DSP0PriorityN0InterruptClear0 = 0x348, // GPIO DSP0 Interrupts N0 31-0: Clear 726 DSP0PriorityN0InterruptSet0 = 0x34C, // GPIO DSP0 Interrupts N0 31-0: Set 727 DSP0PriorityN0InterruptEnable1 = 0x350, // GPIO DSP0 Interrupts N0 63-32: Enable 728 DSP0PriorityN0InterruptStatus1 = 0x354, // GPIO DSP0 Interrupts N0 63-32: Status 729 DSP0PriorityN0InterruptClear1 = 0x358, // GPIO DSP0 Interrupts N0 63-32: Clear 730 DSP0PriorityN0InterruptSet1 = 0x35C, // GPIO DSP0 Interrupts N0 63-32: Set 731 DSP0PriorityN0InterruptEnable2 = 0x360, // GPIO DSP0 Interrupts N0 95-64: Enable 732 DSP0PriorityN0InterruptStatus2 = 0x364, // GPIO DSP0 Interrupts N0 95-64: Status 733 DSP0PriorityN0InterruptClear2 = 0x368, // GPIO DSP0 Interrupts N0 95-64: Clear 734 DSP0PriorityN0InterruptSet2 = 0x36C, // GPIO DSP0 Interrupts N0 95-64: Set 735 DSP0PriorityN0InterruptEnable3 = 0x370, // GPIO DSP0 Interrupts N0 127-96: Enable 736 DSP0PriorityN0InterruptStatus3 = 0x374, // GPIO DSP0 Interrupts N0 127-96: Status 737 DSP0PriorityN0InterruptClear3 = 0x378, // GPIO DSP0 Interrupts N0 127-96: Clear 738 DSP0PriorityN0InterruptSet3 = 0x37C, // GPIO DSP0 Interrupts N0 127-96: Set 739 DSP0PriorityN1InterruptEnable0 = 0x380, // GPIO DSP0 Interrupts N1 31-0: Enable 740 DSP0PriorityN1InterruptStatus0 = 0x384, // GPIO DSP0 Interrupts N1 31-0: Status 741 DSP0PriorityN1InterruptClear0 = 0x388, // GPIO DSP0 Interrupts N1 31-0: Clear 742 DSP0PriorityN1InterruptSet0 = 0x38C, // GPIO DSP0 Interrupts N1 31-0: Set 743 DSP0PriorityN1InterruptEnable1 = 0x390, // GPIO DSP0 Interrupts N1 63-32: Enable 744 DSP0PriorityN1InterruptStatus1 = 0x394, // GPIO DSP0 Interrupts N1 63-32: Status 745 DSP0PriorityN1InterruptClear1 = 0x398, // GPIO DSP0 Interrupts N1 63-32: Clear 746 DSP0PriorityN1InterruptSet1 = 0x39C, // GPIO DSP0 Interrupts N1 63-32: Set 747 DSP0PriorityN1InterruptEnable2 = 0x3A0, // GPIO DSP0 Interrupts N1 95-64: Enable 748 DSP0PriorityN1InterruptStatus2 = 0x3A4, // GPIO DSP0 Interrupts N1 95-64: Status 749 DSP0PriorityN1InterruptClear2 = 0x3A8, // GPIO DSP0 Interrupts N1 95-64: Clear 750 DSP0PriorityN1InterruptSet2 = 0x3AC, // GPIO DSP0 Interrupts N1 95-64: Set 751 DSP0PriorityN1InterruptEnable3 = 0x3B0, // GPIO DSP0 Interrupts N1 127-96: Enable 752 DSP0PriorityN1InterruptStatus3 = 0x3B4, // GPIO DSP0 Interrupts N1 127-96: Status 753 DSP0PriorityN1InterruptClear3 = 0x3B8, // GPIO DSP0 Interrupts N1 127-96: Clear 754 DSP0PriorityN1InterruptSet3 = 0x3BC, // GPIO DSP0 Interrupts N1 127-96: Set 755 DSP1PriorityN0InterruptEnable0 = 0x3C0, // GPIO DSP1 Interrupts N0 31-0: Enable 756 DSP1PriorityN0InterruptStatus0 = 0x3C4, // GPIO DSP1 Interrupts N0 31-0: Status 757 DSP1PriorityN0InterruptClear0 = 0x3C8, // GPIO DSP1 Interrupts N0 31-0: Clear 758 DSP1PriorityN0InterruptSet0 = 0x3CC, // GPIO DSP1 Interrupts N0 31-0: Set 759 DSP1PriorityN0InterruptEnable1 = 0x3D0, // GPIO DSP1 Interrupts N0 63-32: Enable 760 DSP1PriorityN0InterruptStatus1 = 0x3D4, // GPIO DSP1 Interrupts N0 63-32: Status 761 DSP1PriorityN0InterruptClear1 = 0x3D8, // GPIO DSP1 Interrupts N0 63-32: Clear 762 DSP1PriorityN0InterruptSet1 = 0x3DC, // GPIO DSP1 Interrupts N0 63-32: Set 763 DSP1PriorityN0InterruptEnable2 = 0x3E0, // GPIO DSP1 Interrupts N0 95-64: Enable 764 DSP1PriorityN0InterruptStatus2 = 0x3E4, // GPIO DSP1 Interrupts N0 95-64: Status 765 DSP1PriorityN0InterruptClear2 = 0x3E8, // GPIO DSP1 Interrupts N0 95-64: Clear 766 DSP1PriorityN0InterruptSet2 = 0x3EC, // GPIO DSP1 Interrupts N0 95-64: Set 767 DSP1PriorityN0InterruptEnable3 = 0x3F0, // GPIO DSP1 Interrupts N0 127-96: Enable 768 DSP1PriorityN0InterruptStatus3 = 0x3F4, // GPIO DSP1 Interrupts N0 127-96: Status 769 DSP1PriorityN0InterruptClear3 = 0x3F8, // GPIO DSP1 Interrupts N0 127-96: Clear 770 DSP1PriorityN0InterruptSet3 = 0x3FC, // GPIO DSP1 Interrupts N0 127-96: Set 771 DSP1PriorityN1InterruptEnable0 = 0x400, // GPIO DSP1 Interrupts N1 31-0: Enable 772 DSP1PriorityN1InterruptStatus0 = 0x404, // GPIO DSP1 Interrupts N1 31-0: Status 773 DSP1PriorityN1InterruptClear0 = 0x408, // GPIO DSP1 Interrupts N1 31-0: Clear 774 DSP1PriorityN1InterruptSet0 = 0x40C, // GPIO DSP1 Interrupts N1 31-0: Set 775 DSP1PriorityN1InterruptEnable1 = 0x410, // GPIO DSP1 Interrupts N1 63-32: Enable 776 DSP1PriorityN1InterruptStatus1 = 0x414, // GPIO DSP1 Interrupts N1 63-32: Status 777 DSP1PriorityN1InterruptClear1 = 0x418, // GPIO DSP1 Interrupts N1 63-32: Clear 778 DSP1PriorityN1InterruptSet1 = 0x41C, // GPIO DSP1 Interrupts N1 63-32: Set 779 DSP1PriorityN1InterruptEnable2 = 0x420, // GPIO DSP1 Interrupts N1 95-64: Enable 780 DSP1PriorityN1InterruptStatus2 = 0x424, // GPIO DSP1 Interrupts N1 95-64: Status 781 DSP1PriorityN1InterruptClear2 = 0x428, // GPIO DSP1 Interrupts N1 95-64: Clear 782 DSP1PriorityN1InterruptSet2 = 0x42C, // GPIO DSP1 Interrupts N1 95-64: Set 783 DSP1PriorityN1InterruptEnable3 = 0x430, // GPIO DSP1 Interrupts N1 127-96: Enable 784 DSP1PriorityN1InterruptStatus3 = 0x434, // GPIO DSP1 Interrupts N1 127-96: Status 785 DSP1PriorityN1InterruptClear3 = 0x438, // GPIO DSP1 Interrupts N1 127-96: Clear 786 DSP1PriorityN1InterruptSet3 = 0x43C, // GPIO DSP1 Interrupts N1 127-96: Set 787 } 788 } 789 } 790
