1 // 2 // Copyright (c) 2010-2020 Antmicro 3 // 4 // This file is licensed under the MIT License. 5 // Full license text is available in 'licenses/MIT.txt'. 6 // 7 using Antmicro.Renode.Core; 8 using Antmicro.Renode.Core.Structure.Registers; 9 using Antmicro.Renode.Utilities; 10 11 namespace Antmicro.Renode.Peripherals.DMA 12 { 13 public class EOSS3_SystemDMABridge : BasicDoubleWordPeripheral, IKnownSize 14 { EOSS3_SystemDMABridge(IMachine machine, UDMA systemDma)15 public EOSS3_SystemDMABridge(IMachine machine, UDMA systemDma) : base(machine) 16 { 17 this.systemDma = systemDma; 18 DefineRegisters(); 19 } 20 21 public long Size => 0x1000; 22 DefineRegisters()23 private void DefineRegisters() 24 { 25 Registers.Request.Define(this) 26 .WithValueField(0, 10, FieldMode.Write, writeCallback: (_, value) => BitHelper.ForeachActiveBit(value, x => systemDma.InitTransfer(x, true)), name: "dma_req") 27 .WithReservedBits(11, 5) 28 .WithValueField(16, 10, FieldMode.Write, writeCallback: (_, value) => BitHelper.ForeachActiveBit(value, x => systemDma.InitTransfer(x, false)), name: "dma_req") 29 .WithReservedBits(27, 5) 30 ; 31 32 Registers.Active.Define(this) 33 .WithValueField(0, 10, FieldMode.Read, name: "dma_active") //it always returns 0, as the transfer is instant. Keeping this field for possible future latching etc 34 .WithReservedBits(11, 21) 35 ; 36 37 // this register is effectively a scratchpad 38 Registers.SramTimingAdjust.Define(this) 39 .WithReservedBits(0, 1) 40 .WithFlag(1, name: "sdma_sram_rme") 41 .WithValueField(2, 4, name: "sdma_sram_rm") 42 .WithReservedBits(6, 26) 43 ; 44 } 45 46 private readonly UDMA systemDma; 47 48 private enum Registers 49 { 50 Request = 0x0, 51 WaitOnRequest = 0x4, 52 Active = 0x8, 53 PowerDownEventThreshold = 0xC, 54 SramTimingAdjust = 0x10, 55 } 56 } 57 } 58
