1  /* SPDX-License-Identifier: GPL-2.0-or-later */
2  /*
3   * include/linux/mfd/wm8994/registers.h -- Register definitions for WM8994
4   *
5   * Copyright 2009 Wolfson Microelectronics PLC.
6   *
7   * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
8   */
9  
10  #ifndef __MFD_WM8994_REGISTERS_H__
11  #define __MFD_WM8994_REGISTERS_H__
12  
13  /*
14   * Register values.
15   */
16  #define WM8994_SOFTWARE_RESET                   0x00
17  #define WM8994_POWER_MANAGEMENT_1               0x01
18  #define WM8994_POWER_MANAGEMENT_2               0x02
19  #define WM8994_POWER_MANAGEMENT_3               0x03
20  #define WM8994_POWER_MANAGEMENT_4               0x04
21  #define WM8994_POWER_MANAGEMENT_5               0x05
22  #define WM8994_POWER_MANAGEMENT_6               0x06
23  #define WM8994_INPUT_MIXER_1                    0x15
24  #define WM8994_LEFT_LINE_INPUT_1_2_VOLUME       0x18
25  #define WM8994_LEFT_LINE_INPUT_3_4_VOLUME       0x19
26  #define WM8994_RIGHT_LINE_INPUT_1_2_VOLUME      0x1A
27  #define WM8994_RIGHT_LINE_INPUT_3_4_VOLUME      0x1B
28  #define WM8994_LEFT_OUTPUT_VOLUME               0x1C
29  #define WM8994_RIGHT_OUTPUT_VOLUME              0x1D
30  #define WM8994_LINE_OUTPUTS_VOLUME              0x1E
31  #define WM8994_HPOUT2_VOLUME                    0x1F
32  #define WM8994_LEFT_OPGA_VOLUME                 0x20
33  #define WM8994_RIGHT_OPGA_VOLUME                0x21
34  #define WM8994_SPKMIXL_ATTENUATION              0x22
35  #define WM8994_SPKMIXR_ATTENUATION              0x23
36  #define WM8994_SPKOUT_MIXERS                    0x24
37  #define WM8994_CLASSD                           0x25
38  #define WM8994_SPEAKER_VOLUME_LEFT              0x26
39  #define WM8994_SPEAKER_VOLUME_RIGHT             0x27
40  #define WM8994_INPUT_MIXER_2                    0x28
41  #define WM8994_INPUT_MIXER_3                    0x29
42  #define WM8994_INPUT_MIXER_4                    0x2A
43  #define WM8994_INPUT_MIXER_5                    0x2B
44  #define WM8994_INPUT_MIXER_6                    0x2C
45  #define WM8994_OUTPUT_MIXER_1                   0x2D
46  #define WM8994_OUTPUT_MIXER_2                   0x2E
47  #define WM8994_OUTPUT_MIXER_3                   0x2F
48  #define WM8994_OUTPUT_MIXER_4                   0x30
49  #define WM8994_OUTPUT_MIXER_5                   0x31
50  #define WM8994_OUTPUT_MIXER_6                   0x32
51  #define WM8994_HPOUT2_MIXER                     0x33
52  #define WM8994_LINE_MIXER_1                     0x34
53  #define WM8994_LINE_MIXER_2                     0x35
54  #define WM8994_SPEAKER_MIXER                    0x36
55  #define WM8994_ADDITIONAL_CONTROL               0x37
56  #define WM8994_ANTIPOP_1                        0x38
57  #define WM8994_ANTIPOP_2                        0x39
58  #define WM8994_MICBIAS                          0x3A
59  #define WM8994_LDO_1                            0x3B
60  #define WM8994_LDO_2                            0x3C
61  #define WM8958_MICBIAS1				0x3D
62  #define WM8958_MICBIAS2				0x3E
63  #define WM8994_CHARGE_PUMP_1                    0x4C
64  #define WM8958_CHARGE_PUMP_2                    0x4D
65  #define WM8994_CLASS_W_1                        0x51
66  #define WM8994_DC_SERVO_1                       0x54
67  #define WM8994_DC_SERVO_2                       0x55
68  #define WM8994_DC_SERVO_4                       0x57
69  #define WM8994_DC_SERVO_READBACK                0x58
70  #define WM8994_DC_SERVO_4E			0x59
71  #define WM8994_ANALOGUE_HP_1                    0x60
72  #define WM8958_MIC_DETECT_1                     0xD0
73  #define WM8958_MIC_DETECT_2                     0xD1
74  #define WM8958_MIC_DETECT_3                     0xD2
75  #define WM8994_CHIP_REVISION                    0x100
76  #define WM8994_CONTROL_INTERFACE                0x101
77  #define WM8994_WRITE_SEQUENCER_CTRL_1           0x110
78  #define WM8994_WRITE_SEQUENCER_CTRL_2           0x111
79  #define WM8994_AIF1_CLOCKING_1                  0x200
80  #define WM8994_AIF1_CLOCKING_2                  0x201
81  #define WM8994_AIF2_CLOCKING_1                  0x204
82  #define WM8994_AIF2_CLOCKING_2                  0x205
83  #define WM8994_CLOCKING_1                       0x208
84  #define WM8994_CLOCKING_2                       0x209
85  #define WM8994_AIF1_RATE                        0x210
86  #define WM8994_AIF2_RATE                        0x211
87  #define WM8994_RATE_STATUS                      0x212
88  #define WM8994_FLL1_CONTROL_1                   0x220
89  #define WM8994_FLL1_CONTROL_2                   0x221
90  #define WM8994_FLL1_CONTROL_3                   0x222
91  #define WM8994_FLL1_CONTROL_4                   0x223
92  #define WM8994_FLL1_CONTROL_5                   0x224
93  #define WM8958_FLL1_EFS_1                       0x226
94  #define WM8958_FLL1_EFS_2                       0x227
95  #define WM8994_FLL2_CONTROL_1                   0x240
96  #define WM8994_FLL2_CONTROL_2                   0x241
97  #define WM8994_FLL2_CONTROL_3                   0x242
98  #define WM8994_FLL2_CONTROL_4                   0x243
99  #define WM8994_FLL2_CONTROL_5                   0x244
100  #define WM8958_FLL2_EFS_1                       0x246
101  #define WM8958_FLL2_EFS_2                       0x247
102  #define WM8994_AIF1_CONTROL_1                   0x300
103  #define WM8994_AIF1_CONTROL_2                   0x301
104  #define WM8994_AIF1_MASTER_SLAVE                0x302
105  #define WM8994_AIF1_BCLK                        0x303
106  #define WM8994_AIF1ADC_LRCLK                    0x304
107  #define WM8994_AIF1DAC_LRCLK                    0x305
108  #define WM8994_AIF1DAC_DATA                     0x306
109  #define WM8994_AIF1ADC_DATA                     0x307
110  #define WM8994_AIF2_CONTROL_1                   0x310
111  #define WM8994_AIF2_CONTROL_2                   0x311
112  #define WM8994_AIF2_MASTER_SLAVE                0x312
113  #define WM8994_AIF2_BCLK                        0x313
114  #define WM8994_AIF2ADC_LRCLK                    0x314
115  #define WM8994_AIF2DAC_LRCLK                    0x315
116  #define WM8994_AIF2DAC_DATA                     0x316
117  #define WM8994_AIF2ADC_DATA                     0x317
118  #define WM1811_AIF2TX_CONTROL                   0x318
119  #define WM8958_AIF3_CONTROL_1                   0x320
120  #define WM8958_AIF3_CONTROL_2                   0x321
121  #define WM8958_AIF3DAC_DATA                     0x322
122  #define WM8958_AIF3ADC_DATA                     0x323
123  #define WM8994_AIF1_ADC1_LEFT_VOLUME            0x400
124  #define WM8994_AIF1_ADC1_RIGHT_VOLUME           0x401
125  #define WM8994_AIF1_DAC1_LEFT_VOLUME            0x402
126  #define WM8994_AIF1_DAC1_RIGHT_VOLUME           0x403
127  #define WM8994_AIF1_ADC2_LEFT_VOLUME            0x404
128  #define WM8994_AIF1_ADC2_RIGHT_VOLUME           0x405
129  #define WM8994_AIF1_DAC2_LEFT_VOLUME            0x406
130  #define WM8994_AIF1_DAC2_RIGHT_VOLUME           0x407
131  #define WM8994_AIF1_ADC1_FILTERS                0x410
132  #define WM8994_AIF1_ADC2_FILTERS                0x411
133  #define WM8994_AIF1_DAC1_FILTERS_1              0x420
134  #define WM8994_AIF1_DAC1_FILTERS_2              0x421
135  #define WM8994_AIF1_DAC2_FILTERS_1              0x422
136  #define WM8994_AIF1_DAC2_FILTERS_2              0x423
137  #define WM8958_AIF1_DAC1_NOISE_GATE             0x430
138  #define WM8958_AIF1_DAC2_NOISE_GATE             0x431
139  #define WM8994_AIF1_DRC1_1                      0x440
140  #define WM8994_AIF1_DRC1_2                      0x441
141  #define WM8994_AIF1_DRC1_3                      0x442
142  #define WM8994_AIF1_DRC1_4                      0x443
143  #define WM8994_AIF1_DRC1_5                      0x444
144  #define WM8994_AIF1_DRC2_1                      0x450
145  #define WM8994_AIF1_DRC2_2                      0x451
146  #define WM8994_AIF1_DRC2_3                      0x452
147  #define WM8994_AIF1_DRC2_4                      0x453
148  #define WM8994_AIF1_DRC2_5                      0x454
149  #define WM8994_AIF1_DAC1_EQ_GAINS_1             0x480
150  #define WM8994_AIF1_DAC1_EQ_GAINS_2             0x481
151  #define WM8994_AIF1_DAC1_EQ_BAND_1_A            0x482
152  #define WM8994_AIF1_DAC1_EQ_BAND_1_B            0x483
153  #define WM8994_AIF1_DAC1_EQ_BAND_1_PG           0x484
154  #define WM8994_AIF1_DAC1_EQ_BAND_2_A            0x485
155  #define WM8994_AIF1_DAC1_EQ_BAND_2_B            0x486
156  #define WM8994_AIF1_DAC1_EQ_BAND_2_C            0x487
157  #define WM8994_AIF1_DAC1_EQ_BAND_2_PG           0x488
158  #define WM8994_AIF1_DAC1_EQ_BAND_3_A            0x489
159  #define WM8994_AIF1_DAC1_EQ_BAND_3_B            0x48A
160  #define WM8994_AIF1_DAC1_EQ_BAND_3_C            0x48B
161  #define WM8994_AIF1_DAC1_EQ_BAND_3_PG           0x48C
162  #define WM8994_AIF1_DAC1_EQ_BAND_4_A            0x48D
163  #define WM8994_AIF1_DAC1_EQ_BAND_4_B            0x48E
164  #define WM8994_AIF1_DAC1_EQ_BAND_4_C            0x48F
165  #define WM8994_AIF1_DAC1_EQ_BAND_4_PG           0x490
166  #define WM8994_AIF1_DAC1_EQ_BAND_5_A            0x491
167  #define WM8994_AIF1_DAC1_EQ_BAND_5_B            0x492
168  #define WM8994_AIF1_DAC1_EQ_BAND_5_PG           0x493
169  #define WM8994_AIF1_DAC1_EQ_BAND_1_C            0x494
170  #define WM8994_AIF1_DAC2_EQ_GAINS_1             0x4A0
171  #define WM8994_AIF1_DAC2_EQ_GAINS_2             0x4A1
172  #define WM8994_AIF1_DAC2_EQ_BAND_1_A            0x4A2
173  #define WM8994_AIF1_DAC2_EQ_BAND_1_B            0x4A3
174  #define WM8994_AIF1_DAC2_EQ_BAND_1_PG           0x4A4
175  #define WM8994_AIF1_DAC2_EQ_BAND_2_A            0x4A5
176  #define WM8994_AIF1_DAC2_EQ_BAND_2_B            0x4A6
177  #define WM8994_AIF1_DAC2_EQ_BAND_2_C            0x4A7
178  #define WM8994_AIF1_DAC2_EQ_BAND_2_PG           0x4A8
179  #define WM8994_AIF1_DAC2_EQ_BAND_3_A            0x4A9
180  #define WM8994_AIF1_DAC2_EQ_BAND_3_B            0x4AA
181  #define WM8994_AIF1_DAC2_EQ_BAND_3_C            0x4AB
182  #define WM8994_AIF1_DAC2_EQ_BAND_3_PG           0x4AC
183  #define WM8994_AIF1_DAC2_EQ_BAND_4_A            0x4AD
184  #define WM8994_AIF1_DAC2_EQ_BAND_4_B            0x4AE
185  #define WM8994_AIF1_DAC2_EQ_BAND_4_C            0x4AF
186  #define WM8994_AIF1_DAC2_EQ_BAND_4_PG           0x4B0
187  #define WM8994_AIF1_DAC2_EQ_BAND_5_A            0x4B1
188  #define WM8994_AIF1_DAC2_EQ_BAND_5_B            0x4B2
189  #define WM8994_AIF1_DAC2_EQ_BAND_5_PG           0x4B3
190  #define WM8994_AIF1_DAC2_EQ_BAND_1_C            0x4B4
191  #define WM8994_AIF2_ADC_LEFT_VOLUME             0x500
192  #define WM8994_AIF2_ADC_RIGHT_VOLUME            0x501
193  #define WM8994_AIF2_DAC_LEFT_VOLUME             0x502
194  #define WM8994_AIF2_DAC_RIGHT_VOLUME            0x503
195  #define WM8994_AIF2_ADC_FILTERS                 0x510
196  #define WM8994_AIF2_DAC_FILTERS_1               0x520
197  #define WM8994_AIF2_DAC_FILTERS_2               0x521
198  #define WM8958_AIF2_DAC_NOISE_GATE              0x530
199  #define WM8994_AIF2_DRC_1                       0x540
200  #define WM8994_AIF2_DRC_2                       0x541
201  #define WM8994_AIF2_DRC_3                       0x542
202  #define WM8994_AIF2_DRC_4                       0x543
203  #define WM8994_AIF2_DRC_5                       0x544
204  #define WM8994_AIF2_EQ_GAINS_1                  0x580
205  #define WM8994_AIF2_EQ_GAINS_2                  0x581
206  #define WM8994_AIF2_EQ_BAND_1_A                 0x582
207  #define WM8994_AIF2_EQ_BAND_1_B                 0x583
208  #define WM8994_AIF2_EQ_BAND_1_PG                0x584
209  #define WM8994_AIF2_EQ_BAND_2_A                 0x585
210  #define WM8994_AIF2_EQ_BAND_2_B                 0x586
211  #define WM8994_AIF2_EQ_BAND_2_C                 0x587
212  #define WM8994_AIF2_EQ_BAND_2_PG                0x588
213  #define WM8994_AIF2_EQ_BAND_3_A                 0x589
214  #define WM8994_AIF2_EQ_BAND_3_B                 0x58A
215  #define WM8994_AIF2_EQ_BAND_3_C                 0x58B
216  #define WM8994_AIF2_EQ_BAND_3_PG                0x58C
217  #define WM8994_AIF2_EQ_BAND_4_A                 0x58D
218  #define WM8994_AIF2_EQ_BAND_4_B                 0x58E
219  #define WM8994_AIF2_EQ_BAND_4_C                 0x58F
220  #define WM8994_AIF2_EQ_BAND_4_PG                0x590
221  #define WM8994_AIF2_EQ_BAND_5_A                 0x591
222  #define WM8994_AIF2_EQ_BAND_5_B                 0x592
223  #define WM8994_AIF2_EQ_BAND_5_PG                0x593
224  #define WM8994_AIF2_EQ_BAND_1_C                 0x594
225  #define WM8994_DAC1_MIXER_VOLUMES               0x600
226  #define WM8994_DAC1_LEFT_MIXER_ROUTING          0x601
227  #define WM8994_DAC1_RIGHT_MIXER_ROUTING         0x602
228  #define WM8994_DAC2_MIXER_VOLUMES               0x603
229  #define WM8994_DAC2_LEFT_MIXER_ROUTING          0x604
230  #define WM8994_DAC2_RIGHT_MIXER_ROUTING         0x605
231  #define WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING     0x606
232  #define WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING    0x607
233  #define WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING     0x608
234  #define WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING    0x609
235  #define WM8994_DAC1_LEFT_VOLUME                 0x610
236  #define WM8994_DAC1_RIGHT_VOLUME                0x611
237  #define WM8994_DAC2_LEFT_VOLUME                 0x612
238  #define WM8994_DAC2_RIGHT_VOLUME                0x613
239  #define WM8994_DAC_SOFTMUTE                     0x614
240  #define WM8994_OVERSAMPLING                     0x620
241  #define WM8994_SIDETONE                         0x621
242  #define WM8994_GPIO_1                           0x700
243  #define WM8994_GPIO_2                           0x701
244  #define WM8994_GPIO_3                           0x702
245  #define WM8994_GPIO_4                           0x703
246  #define WM8994_GPIO_5                           0x704
247  #define WM8994_GPIO_6                           0x705
248  #define WM1811_JACKDET_CTRL			0x705
249  #define WM8994_GPIO_7                           0x706
250  #define WM8994_GPIO_8                           0x707
251  #define WM8994_GPIO_9                           0x708
252  #define WM8994_GPIO_10                          0x709
253  #define WM8994_GPIO_11                          0x70A
254  #define WM8994_PULL_CONTROL_1                   0x720
255  #define WM8994_PULL_CONTROL_2                   0x721
256  #define WM8994_INTERRUPT_STATUS_1               0x730
257  #define WM8994_INTERRUPT_STATUS_2               0x731
258  #define WM8994_INTERRUPT_RAW_STATUS_2           0x732
259  #define WM8994_INTERRUPT_STATUS_1_MASK          0x738
260  #define WM8994_INTERRUPT_STATUS_2_MASK          0x739
261  #define WM8994_INTERRUPT_CONTROL                0x740
262  #define WM8994_IRQ_DEBOUNCE                     0x748
263  #define WM8958_DSP2_PROGRAM                     0x900
264  #define WM8958_DSP2_CONFIG                      0x901
265  #define WM8958_DSP2_MAGICNUM                    0xA00
266  #define WM8958_DSP2_RELEASEYEAR                 0xA01
267  #define WM8958_DSP2_RELEASEMONTHDAY             0xA02
268  #define WM8958_DSP2_RELEASETIME                 0xA03
269  #define WM8958_DSP2_VERMAJMIN                   0xA04
270  #define WM8958_DSP2_VERBUILD                    0xA05
271  #define WM8958_DSP2_TESTREG                     0xA06
272  #define WM8958_DSP2_XORREG                      0xA07
273  #define WM8958_DSP2_SHIFTMAXX                   0xA08
274  #define WM8958_DSP2_SHIFTMAXY                   0xA09
275  #define WM8958_DSP2_SHIFTMAXZ                   0xA0A
276  #define WM8958_DSP2_SHIFTMAXEXTLO               0xA0B
277  #define WM8958_DSP2_AESSELECT                   0xA0C
278  #define WM8958_DSP2_EXECCONTROL                 0xA0D
279  #define WM8958_DSP2_SAMPLEBREAK                 0xA0E
280  #define WM8958_DSP2_COUNTBREAK                  0xA0F
281  #define WM8958_DSP2_INTSTATUS                   0xA10
282  #define WM8958_DSP2_EVENTSTATUS                 0xA11
283  #define WM8958_DSP2_INTMASK                     0xA12
284  #define WM8958_DSP2_CONFIGDWIDTH                0xA13
285  #define WM8958_DSP2_CONFIGINSTR                 0xA14
286  #define WM8958_DSP2_CONFIGDMEM                  0xA15
287  #define WM8958_DSP2_CONFIGDELAYS                0xA16
288  #define WM8958_DSP2_CONFIGNUMIO                 0xA17
289  #define WM8958_DSP2_CONFIGEXTDEPTH              0xA18
290  #define WM8958_DSP2_CONFIGMULTIPLIER            0xA19
291  #define WM8958_DSP2_CONFIGCTRLDWIDTH            0xA1A
292  #define WM8958_DSP2_CONFIGPIPELINE              0xA1B
293  #define WM8958_DSP2_SHIFTMAXEXTHI               0xA1C
294  #define WM8958_DSP2_SWVERSIONREG                0xA1D
295  #define WM8958_DSP2_CONFIGXMEM                  0xA1E
296  #define WM8958_DSP2_CONFIGYMEM                  0xA1F
297  #define WM8958_DSP2_CONFIGZMEM                  0xA20
298  #define WM8958_FW_BUILD_1                       0x2000
299  #define WM8958_FW_BUILD_0                       0x2001
300  #define WM8958_FW_ID_1                          0x2002
301  #define WM8958_FW_ID_0                          0x2003
302  #define WM8958_FW_MAJOR_1                       0x2004
303  #define WM8958_FW_MAJOR_0                       0x2005
304  #define WM8958_FW_MINOR_1                       0x2006
305  #define WM8958_FW_MINOR_0                       0x2007
306  #define WM8958_FW_PATCH_1                       0x2008
307  #define WM8958_FW_PATCH_0                       0x2009
308  #define WM8958_MBC_BAND_2_LOWER_CUTOFF_C1_1     0x2200
309  #define WM8958_MBC_BAND_2_LOWER_CUTOFF_C1_2     0x2201
310  #define WM8958_MBC_BAND_2_LOWER_CUTOFF_C2_1     0x2202
311  #define WM8958_MBC_BAND_2_LOWER_CUTOFF_C2_2     0x2203
312  #define WM8958_MBC_BAND_2_LOWER_CUTOFF_C3_1     0x2204
313  #define WM8958_MBC_BAND_2_LOWER_CUTOFF_C3_2     0x2205
314  #define WM8958_MBC_BAND_2_UPPER_CUTOFF_C2_1     0x2206
315  #define WM8958_MBC_BAND_2_UPPER_CUTOFF_C2_2     0x2207
316  #define WM8958_MBC_BAND_2_UPPER_CUTOFF_C3_1     0x2208
317  #define WM8958_MBC_BAND_2_UPPER_CUTOFF_C3_2     0x2209
318  #define WM8958_MBC_BAND_2_UPPER_CUTOFF_C1_1     0x220A
319  #define WM8958_MBC_BAND_2_UPPER_CUTOFF_C1_2     0x220B
320  #define WM8958_MBC_BAND_1_UPPER_CUTOFF_C1_1     0x220C
321  #define WM8958_MBC_BAND_1_UPPER_CUTOFF_C1_2     0x220D
322  #define WM8958_MBC_BAND_1_UPPER_CUTOFF_C2_1     0x220E
323  #define WM8958_MBC_BAND_1_UPPER_CUTOFF_C2_2     0x220F
324  #define WM8958_MBC_BAND_1_UPPER_CUTOFF_C3_1     0x2210
325  #define WM8958_MBC_BAND_1_UPPER_CUTOFF_C3_2     0x2211
326  #define WM8958_MBC_BAND_1_LOWER_CUTOFF_1        0x2212
327  #define WM8958_MBC_BAND_1_LOWER_CUTOFF_2        0x2213
328  #define WM8958_MBC_BAND_1_K_1                   0x2400
329  #define WM8958_MBC_BAND_1_K_2                   0x2401
330  #define WM8958_MBC_BAND_1_N1_1                  0x2402
331  #define WM8958_MBC_BAND_1_N1_2                  0x2403
332  #define WM8958_MBC_BAND_1_N2_1                  0x2404
333  #define WM8958_MBC_BAND_1_N2_2                  0x2405
334  #define WM8958_MBC_BAND_1_N3_1                  0x2406
335  #define WM8958_MBC_BAND_1_N3_2                  0x2407
336  #define WM8958_MBC_BAND_1_N4_1                  0x2408
337  #define WM8958_MBC_BAND_1_N4_2                  0x2409
338  #define WM8958_MBC_BAND_1_N5_1                  0x240A
339  #define WM8958_MBC_BAND_1_N5_2                  0x240B
340  #define WM8958_MBC_BAND_1_X1_1                  0x240C
341  #define WM8958_MBC_BAND_1_X1_2                  0x240D
342  #define WM8958_MBC_BAND_1_X2_1                  0x240E
343  #define WM8958_MBC_BAND_1_X2_2                  0x240F
344  #define WM8958_MBC_BAND_1_X3_1                  0x2410
345  #define WM8958_MBC_BAND_1_X3_2                  0x2411
346  #define WM8958_MBC_BAND_1_ATTACK_1              0x2412
347  #define WM8958_MBC_BAND_1_ATTACK_2              0x2413
348  #define WM8958_MBC_BAND_1_DECAY_1               0x2414
349  #define WM8958_MBC_BAND_1_DECAY_2               0x2415
350  #define WM8958_MBC_BAND_2_K_1                   0x2416
351  #define WM8958_MBC_BAND_2_K_2                   0x2417
352  #define WM8958_MBC_BAND_2_N1_1                  0x2418
353  #define WM8958_MBC_BAND_2_N1_2                  0x2419
354  #define WM8958_MBC_BAND_2_N2_1                  0x241A
355  #define WM8958_MBC_BAND_2_N2_2                  0x241B
356  #define WM8958_MBC_BAND_2_N3_1                  0x241C
357  #define WM8958_MBC_BAND_2_N3_2                  0x241D
358  #define WM8958_MBC_BAND_2_N4_1                  0x241E
359  #define WM8958_MBC_BAND_2_N4_2                  0x241F
360  #define WM8958_MBC_BAND_2_N5_1                  0x2420
361  #define WM8958_MBC_BAND_2_N5_2                  0x2421
362  #define WM8958_MBC_BAND_2_X1_1                  0x2422
363  #define WM8958_MBC_BAND_2_X1_2                  0x2423
364  #define WM8958_MBC_BAND_2_X2_1                  0x2424
365  #define WM8958_MBC_BAND_2_X2_2                  0x2425
366  #define WM8958_MBC_BAND_2_X3_1                  0x2426
367  #define WM8958_MBC_BAND_2_X3_2                  0x2427
368  #define WM8958_MBC_BAND_2_ATTACK_1              0x2428
369  #define WM8958_MBC_BAND_2_ATTACK_2              0x2429
370  #define WM8958_MBC_BAND_2_DECAY_1               0x242A
371  #define WM8958_MBC_BAND_2_DECAY_2               0x242B
372  #define WM8958_MBC_B2_PG2_1                     0x242C
373  #define WM8958_MBC_B2_PG2_2                     0x242D
374  #define WM8958_MBC_B1_PG2_1                     0x242E
375  #define WM8958_MBC_B1_PG2_2                     0x242F
376  #define WM8958_MBC_CROSSOVER_1                  0x2600
377  #define WM8958_MBC_CROSSOVER_2                  0x2601
378  #define WM8958_MBC_HPF_1                        0x2602
379  #define WM8958_MBC_HPF_2                        0x2603
380  #define WM8958_MBC_LPF_1                        0x2606
381  #define WM8958_MBC_LPF_2                        0x2607
382  #define WM8958_MBC_RMS_LIMIT_1                  0x260A
383  #define WM8958_MBC_RMS_LIMIT_2                  0x260B
384  #define WM8994_WRITE_SEQUENCER_0                0x3000
385  #define WM8994_WRITE_SEQUENCER_1                0x3001
386  #define WM8994_WRITE_SEQUENCER_2                0x3002
387  #define WM8994_WRITE_SEQUENCER_3                0x3003
388  #define WM8994_WRITE_SEQUENCER_4                0x3004
389  #define WM8994_WRITE_SEQUENCER_5                0x3005
390  #define WM8994_WRITE_SEQUENCER_6                0x3006
391  #define WM8994_WRITE_SEQUENCER_7                0x3007
392  #define WM8994_WRITE_SEQUENCER_8                0x3008
393  #define WM8994_WRITE_SEQUENCER_9                0x3009
394  #define WM8994_WRITE_SEQUENCER_10               0x300A
395  #define WM8994_WRITE_SEQUENCER_11               0x300B
396  #define WM8994_WRITE_SEQUENCER_12               0x300C
397  #define WM8994_WRITE_SEQUENCER_13               0x300D
398  #define WM8994_WRITE_SEQUENCER_14               0x300E
399  #define WM8994_WRITE_SEQUENCER_15               0x300F
400  #define WM8994_WRITE_SEQUENCER_16               0x3010
401  #define WM8994_WRITE_SEQUENCER_17               0x3011
402  #define WM8994_WRITE_SEQUENCER_18               0x3012
403  #define WM8994_WRITE_SEQUENCER_19               0x3013
404  #define WM8994_WRITE_SEQUENCER_20               0x3014
405  #define WM8994_WRITE_SEQUENCER_21               0x3015
406  #define WM8994_WRITE_SEQUENCER_22               0x3016
407  #define WM8994_WRITE_SEQUENCER_23               0x3017
408  #define WM8994_WRITE_SEQUENCER_24               0x3018
409  #define WM8994_WRITE_SEQUENCER_25               0x3019
410  #define WM8994_WRITE_SEQUENCER_26               0x301A
411  #define WM8994_WRITE_SEQUENCER_27               0x301B
412  #define WM8994_WRITE_SEQUENCER_28               0x301C
413  #define WM8994_WRITE_SEQUENCER_29               0x301D
414  #define WM8994_WRITE_SEQUENCER_30               0x301E
415  #define WM8994_WRITE_SEQUENCER_31               0x301F
416  #define WM8994_WRITE_SEQUENCER_32               0x3020
417  #define WM8994_WRITE_SEQUENCER_33               0x3021
418  #define WM8994_WRITE_SEQUENCER_34               0x3022
419  #define WM8994_WRITE_SEQUENCER_35               0x3023
420  #define WM8994_WRITE_SEQUENCER_36               0x3024
421  #define WM8994_WRITE_SEQUENCER_37               0x3025
422  #define WM8994_WRITE_SEQUENCER_38               0x3026
423  #define WM8994_WRITE_SEQUENCER_39               0x3027
424  #define WM8994_WRITE_SEQUENCER_40               0x3028
425  #define WM8994_WRITE_SEQUENCER_41               0x3029
426  #define WM8994_WRITE_SEQUENCER_42               0x302A
427  #define WM8994_WRITE_SEQUENCER_43               0x302B
428  #define WM8994_WRITE_SEQUENCER_44               0x302C
429  #define WM8994_WRITE_SEQUENCER_45               0x302D
430  #define WM8994_WRITE_SEQUENCER_46               0x302E
431  #define WM8994_WRITE_SEQUENCER_47               0x302F
432  #define WM8994_WRITE_SEQUENCER_48               0x3030
433  #define WM8994_WRITE_SEQUENCER_49               0x3031
434  #define WM8994_WRITE_SEQUENCER_50               0x3032
435  #define WM8994_WRITE_SEQUENCER_51               0x3033
436  #define WM8994_WRITE_SEQUENCER_52               0x3034
437  #define WM8994_WRITE_SEQUENCER_53               0x3035
438  #define WM8994_WRITE_SEQUENCER_54               0x3036
439  #define WM8994_WRITE_SEQUENCER_55               0x3037
440  #define WM8994_WRITE_SEQUENCER_56               0x3038
441  #define WM8994_WRITE_SEQUENCER_57               0x3039
442  #define WM8994_WRITE_SEQUENCER_58               0x303A
443  #define WM8994_WRITE_SEQUENCER_59               0x303B
444  #define WM8994_WRITE_SEQUENCER_60               0x303C
445  #define WM8994_WRITE_SEQUENCER_61               0x303D
446  #define WM8994_WRITE_SEQUENCER_62               0x303E
447  #define WM8994_WRITE_SEQUENCER_63               0x303F
448  #define WM8994_WRITE_SEQUENCER_64               0x3040
449  #define WM8994_WRITE_SEQUENCER_65               0x3041
450  #define WM8994_WRITE_SEQUENCER_66               0x3042
451  #define WM8994_WRITE_SEQUENCER_67               0x3043
452  #define WM8994_WRITE_SEQUENCER_68               0x3044
453  #define WM8994_WRITE_SEQUENCER_69               0x3045
454  #define WM8994_WRITE_SEQUENCER_70               0x3046
455  #define WM8994_WRITE_SEQUENCER_71               0x3047
456  #define WM8994_WRITE_SEQUENCER_72               0x3048
457  #define WM8994_WRITE_SEQUENCER_73               0x3049
458  #define WM8994_WRITE_SEQUENCER_74               0x304A
459  #define WM8994_WRITE_SEQUENCER_75               0x304B
460  #define WM8994_WRITE_SEQUENCER_76               0x304C
461  #define WM8994_WRITE_SEQUENCER_77               0x304D
462  #define WM8994_WRITE_SEQUENCER_78               0x304E
463  #define WM8994_WRITE_SEQUENCER_79               0x304F
464  #define WM8994_WRITE_SEQUENCER_80               0x3050
465  #define WM8994_WRITE_SEQUENCER_81               0x3051
466  #define WM8994_WRITE_SEQUENCER_82               0x3052
467  #define WM8994_WRITE_SEQUENCER_83               0x3053
468  #define WM8994_WRITE_SEQUENCER_84               0x3054
469  #define WM8994_WRITE_SEQUENCER_85               0x3055
470  #define WM8994_WRITE_SEQUENCER_86               0x3056
471  #define WM8994_WRITE_SEQUENCER_87               0x3057
472  #define WM8994_WRITE_SEQUENCER_88               0x3058
473  #define WM8994_WRITE_SEQUENCER_89               0x3059
474  #define WM8994_WRITE_SEQUENCER_90               0x305A
475  #define WM8994_WRITE_SEQUENCER_91               0x305B
476  #define WM8994_WRITE_SEQUENCER_92               0x305C
477  #define WM8994_WRITE_SEQUENCER_93               0x305D
478  #define WM8994_WRITE_SEQUENCER_94               0x305E
479  #define WM8994_WRITE_SEQUENCER_95               0x305F
480  #define WM8994_WRITE_SEQUENCER_96               0x3060
481  #define WM8994_WRITE_SEQUENCER_97               0x3061
482  #define WM8994_WRITE_SEQUENCER_98               0x3062
483  #define WM8994_WRITE_SEQUENCER_99               0x3063
484  #define WM8994_WRITE_SEQUENCER_100              0x3064
485  #define WM8994_WRITE_SEQUENCER_101              0x3065
486  #define WM8994_WRITE_SEQUENCER_102              0x3066
487  #define WM8994_WRITE_SEQUENCER_103              0x3067
488  #define WM8994_WRITE_SEQUENCER_104              0x3068
489  #define WM8994_WRITE_SEQUENCER_105              0x3069
490  #define WM8994_WRITE_SEQUENCER_106              0x306A
491  #define WM8994_WRITE_SEQUENCER_107              0x306B
492  #define WM8994_WRITE_SEQUENCER_108              0x306C
493  #define WM8994_WRITE_SEQUENCER_109              0x306D
494  #define WM8994_WRITE_SEQUENCER_110              0x306E
495  #define WM8994_WRITE_SEQUENCER_111              0x306F
496  #define WM8994_WRITE_SEQUENCER_112              0x3070
497  #define WM8994_WRITE_SEQUENCER_113              0x3071
498  #define WM8994_WRITE_SEQUENCER_114              0x3072
499  #define WM8994_WRITE_SEQUENCER_115              0x3073
500  #define WM8994_WRITE_SEQUENCER_116              0x3074
501  #define WM8994_WRITE_SEQUENCER_117              0x3075
502  #define WM8994_WRITE_SEQUENCER_118              0x3076
503  #define WM8994_WRITE_SEQUENCER_119              0x3077
504  #define WM8994_WRITE_SEQUENCER_120              0x3078
505  #define WM8994_WRITE_SEQUENCER_121              0x3079
506  #define WM8994_WRITE_SEQUENCER_122              0x307A
507  #define WM8994_WRITE_SEQUENCER_123              0x307B
508  #define WM8994_WRITE_SEQUENCER_124              0x307C
509  #define WM8994_WRITE_SEQUENCER_125              0x307D
510  #define WM8994_WRITE_SEQUENCER_126              0x307E
511  #define WM8994_WRITE_SEQUENCER_127              0x307F
512  #define WM8994_WRITE_SEQUENCER_128              0x3080
513  #define WM8994_WRITE_SEQUENCER_129              0x3081
514  #define WM8994_WRITE_SEQUENCER_130              0x3082
515  #define WM8994_WRITE_SEQUENCER_131              0x3083
516  #define WM8994_WRITE_SEQUENCER_132              0x3084
517  #define WM8994_WRITE_SEQUENCER_133              0x3085
518  #define WM8994_WRITE_SEQUENCER_134              0x3086
519  #define WM8994_WRITE_SEQUENCER_135              0x3087
520  #define WM8994_WRITE_SEQUENCER_136              0x3088
521  #define WM8994_WRITE_SEQUENCER_137              0x3089
522  #define WM8994_WRITE_SEQUENCER_138              0x308A
523  #define WM8994_WRITE_SEQUENCER_139              0x308B
524  #define WM8994_WRITE_SEQUENCER_140              0x308C
525  #define WM8994_WRITE_SEQUENCER_141              0x308D
526  #define WM8994_WRITE_SEQUENCER_142              0x308E
527  #define WM8994_WRITE_SEQUENCER_143              0x308F
528  #define WM8994_WRITE_SEQUENCER_144              0x3090
529  #define WM8994_WRITE_SEQUENCER_145              0x3091
530  #define WM8994_WRITE_SEQUENCER_146              0x3092
531  #define WM8994_WRITE_SEQUENCER_147              0x3093
532  #define WM8994_WRITE_SEQUENCER_148              0x3094
533  #define WM8994_WRITE_SEQUENCER_149              0x3095
534  #define WM8994_WRITE_SEQUENCER_150              0x3096
535  #define WM8994_WRITE_SEQUENCER_151              0x3097
536  #define WM8994_WRITE_SEQUENCER_152              0x3098
537  #define WM8994_WRITE_SEQUENCER_153              0x3099
538  #define WM8994_WRITE_SEQUENCER_154              0x309A
539  #define WM8994_WRITE_SEQUENCER_155              0x309B
540  #define WM8994_WRITE_SEQUENCER_156              0x309C
541  #define WM8994_WRITE_SEQUENCER_157              0x309D
542  #define WM8994_WRITE_SEQUENCER_158              0x309E
543  #define WM8994_WRITE_SEQUENCER_159              0x309F
544  #define WM8994_WRITE_SEQUENCER_160              0x30A0
545  #define WM8994_WRITE_SEQUENCER_161              0x30A1
546  #define WM8994_WRITE_SEQUENCER_162              0x30A2
547  #define WM8994_WRITE_SEQUENCER_163              0x30A3
548  #define WM8994_WRITE_SEQUENCER_164              0x30A4
549  #define WM8994_WRITE_SEQUENCER_165              0x30A5
550  #define WM8994_WRITE_SEQUENCER_166              0x30A6
551  #define WM8994_WRITE_SEQUENCER_167              0x30A7
552  #define WM8994_WRITE_SEQUENCER_168              0x30A8
553  #define WM8994_WRITE_SEQUENCER_169              0x30A9
554  #define WM8994_WRITE_SEQUENCER_170              0x30AA
555  #define WM8994_WRITE_SEQUENCER_171              0x30AB
556  #define WM8994_WRITE_SEQUENCER_172              0x30AC
557  #define WM8994_WRITE_SEQUENCER_173              0x30AD
558  #define WM8994_WRITE_SEQUENCER_174              0x30AE
559  #define WM8994_WRITE_SEQUENCER_175              0x30AF
560  #define WM8994_WRITE_SEQUENCER_176              0x30B0
561  #define WM8994_WRITE_SEQUENCER_177              0x30B1
562  #define WM8994_WRITE_SEQUENCER_178              0x30B2
563  #define WM8994_WRITE_SEQUENCER_179              0x30B3
564  #define WM8994_WRITE_SEQUENCER_180              0x30B4
565  #define WM8994_WRITE_SEQUENCER_181              0x30B5
566  #define WM8994_WRITE_SEQUENCER_182              0x30B6
567  #define WM8994_WRITE_SEQUENCER_183              0x30B7
568  #define WM8994_WRITE_SEQUENCER_184              0x30B8
569  #define WM8994_WRITE_SEQUENCER_185              0x30B9
570  #define WM8994_WRITE_SEQUENCER_186              0x30BA
571  #define WM8994_WRITE_SEQUENCER_187              0x30BB
572  #define WM8994_WRITE_SEQUENCER_188              0x30BC
573  #define WM8994_WRITE_SEQUENCER_189              0x30BD
574  #define WM8994_WRITE_SEQUENCER_190              0x30BE
575  #define WM8994_WRITE_SEQUENCER_191              0x30BF
576  #define WM8994_WRITE_SEQUENCER_192              0x30C0
577  #define WM8994_WRITE_SEQUENCER_193              0x30C1
578  #define WM8994_WRITE_SEQUENCER_194              0x30C2
579  #define WM8994_WRITE_SEQUENCER_195              0x30C3
580  #define WM8994_WRITE_SEQUENCER_196              0x30C4
581  #define WM8994_WRITE_SEQUENCER_197              0x30C5
582  #define WM8994_WRITE_SEQUENCER_198              0x30C6
583  #define WM8994_WRITE_SEQUENCER_199              0x30C7
584  #define WM8994_WRITE_SEQUENCER_200              0x30C8
585  #define WM8994_WRITE_SEQUENCER_201              0x30C9
586  #define WM8994_WRITE_SEQUENCER_202              0x30CA
587  #define WM8994_WRITE_SEQUENCER_203              0x30CB
588  #define WM8994_WRITE_SEQUENCER_204              0x30CC
589  #define WM8994_WRITE_SEQUENCER_205              0x30CD
590  #define WM8994_WRITE_SEQUENCER_206              0x30CE
591  #define WM8994_WRITE_SEQUENCER_207              0x30CF
592  #define WM8994_WRITE_SEQUENCER_208              0x30D0
593  #define WM8994_WRITE_SEQUENCER_209              0x30D1
594  #define WM8994_WRITE_SEQUENCER_210              0x30D2
595  #define WM8994_WRITE_SEQUENCER_211              0x30D3
596  #define WM8994_WRITE_SEQUENCER_212              0x30D4
597  #define WM8994_WRITE_SEQUENCER_213              0x30D5
598  #define WM8994_WRITE_SEQUENCER_214              0x30D6
599  #define WM8994_WRITE_SEQUENCER_215              0x30D7
600  #define WM8994_WRITE_SEQUENCER_216              0x30D8
601  #define WM8994_WRITE_SEQUENCER_217              0x30D9
602  #define WM8994_WRITE_SEQUENCER_218              0x30DA
603  #define WM8994_WRITE_SEQUENCER_219              0x30DB
604  #define WM8994_WRITE_SEQUENCER_220              0x30DC
605  #define WM8994_WRITE_SEQUENCER_221              0x30DD
606  #define WM8994_WRITE_SEQUENCER_222              0x30DE
607  #define WM8994_WRITE_SEQUENCER_223              0x30DF
608  #define WM8994_WRITE_SEQUENCER_224              0x30E0
609  #define WM8994_WRITE_SEQUENCER_225              0x30E1
610  #define WM8994_WRITE_SEQUENCER_226              0x30E2
611  #define WM8994_WRITE_SEQUENCER_227              0x30E3
612  #define WM8994_WRITE_SEQUENCER_228              0x30E4
613  #define WM8994_WRITE_SEQUENCER_229              0x30E5
614  #define WM8994_WRITE_SEQUENCER_230              0x30E6
615  #define WM8994_WRITE_SEQUENCER_231              0x30E7
616  #define WM8994_WRITE_SEQUENCER_232              0x30E8
617  #define WM8994_WRITE_SEQUENCER_233              0x30E9
618  #define WM8994_WRITE_SEQUENCER_234              0x30EA
619  #define WM8994_WRITE_SEQUENCER_235              0x30EB
620  #define WM8994_WRITE_SEQUENCER_236              0x30EC
621  #define WM8994_WRITE_SEQUENCER_237              0x30ED
622  #define WM8994_WRITE_SEQUENCER_238              0x30EE
623  #define WM8994_WRITE_SEQUENCER_239              0x30EF
624  #define WM8994_WRITE_SEQUENCER_240              0x30F0
625  #define WM8994_WRITE_SEQUENCER_241              0x30F1
626  #define WM8994_WRITE_SEQUENCER_242              0x30F2
627  #define WM8994_WRITE_SEQUENCER_243              0x30F3
628  #define WM8994_WRITE_SEQUENCER_244              0x30F4
629  #define WM8994_WRITE_SEQUENCER_245              0x30F5
630  #define WM8994_WRITE_SEQUENCER_246              0x30F6
631  #define WM8994_WRITE_SEQUENCER_247              0x30F7
632  #define WM8994_WRITE_SEQUENCER_248              0x30F8
633  #define WM8994_WRITE_SEQUENCER_249              0x30F9
634  #define WM8994_WRITE_SEQUENCER_250              0x30FA
635  #define WM8994_WRITE_SEQUENCER_251              0x30FB
636  #define WM8994_WRITE_SEQUENCER_252              0x30FC
637  #define WM8994_WRITE_SEQUENCER_253              0x30FD
638  #define WM8994_WRITE_SEQUENCER_254              0x30FE
639  #define WM8994_WRITE_SEQUENCER_255              0x30FF
640  #define WM8994_WRITE_SEQUENCER_256              0x3100
641  #define WM8994_WRITE_SEQUENCER_257              0x3101
642  #define WM8994_WRITE_SEQUENCER_258              0x3102
643  #define WM8994_WRITE_SEQUENCER_259              0x3103
644  #define WM8994_WRITE_SEQUENCER_260              0x3104
645  #define WM8994_WRITE_SEQUENCER_261              0x3105
646  #define WM8994_WRITE_SEQUENCER_262              0x3106
647  #define WM8994_WRITE_SEQUENCER_263              0x3107
648  #define WM8994_WRITE_SEQUENCER_264              0x3108
649  #define WM8994_WRITE_SEQUENCER_265              0x3109
650  #define WM8994_WRITE_SEQUENCER_266              0x310A
651  #define WM8994_WRITE_SEQUENCER_267              0x310B
652  #define WM8994_WRITE_SEQUENCER_268              0x310C
653  #define WM8994_WRITE_SEQUENCER_269              0x310D
654  #define WM8994_WRITE_SEQUENCER_270              0x310E
655  #define WM8994_WRITE_SEQUENCER_271              0x310F
656  #define WM8994_WRITE_SEQUENCER_272              0x3110
657  #define WM8994_WRITE_SEQUENCER_273              0x3111
658  #define WM8994_WRITE_SEQUENCER_274              0x3112
659  #define WM8994_WRITE_SEQUENCER_275              0x3113
660  #define WM8994_WRITE_SEQUENCER_276              0x3114
661  #define WM8994_WRITE_SEQUENCER_277              0x3115
662  #define WM8994_WRITE_SEQUENCER_278              0x3116
663  #define WM8994_WRITE_SEQUENCER_279              0x3117
664  #define WM8994_WRITE_SEQUENCER_280              0x3118
665  #define WM8994_WRITE_SEQUENCER_281              0x3119
666  #define WM8994_WRITE_SEQUENCER_282              0x311A
667  #define WM8994_WRITE_SEQUENCER_283              0x311B
668  #define WM8994_WRITE_SEQUENCER_284              0x311C
669  #define WM8994_WRITE_SEQUENCER_285              0x311D
670  #define WM8994_WRITE_SEQUENCER_286              0x311E
671  #define WM8994_WRITE_SEQUENCER_287              0x311F
672  #define WM8994_WRITE_SEQUENCER_288              0x3120
673  #define WM8994_WRITE_SEQUENCER_289              0x3121
674  #define WM8994_WRITE_SEQUENCER_290              0x3122
675  #define WM8994_WRITE_SEQUENCER_291              0x3123
676  #define WM8994_WRITE_SEQUENCER_292              0x3124
677  #define WM8994_WRITE_SEQUENCER_293              0x3125
678  #define WM8994_WRITE_SEQUENCER_294              0x3126
679  #define WM8994_WRITE_SEQUENCER_295              0x3127
680  #define WM8994_WRITE_SEQUENCER_296              0x3128
681  #define WM8994_WRITE_SEQUENCER_297              0x3129
682  #define WM8994_WRITE_SEQUENCER_298              0x312A
683  #define WM8994_WRITE_SEQUENCER_299              0x312B
684  #define WM8994_WRITE_SEQUENCER_300              0x312C
685  #define WM8994_WRITE_SEQUENCER_301              0x312D
686  #define WM8994_WRITE_SEQUENCER_302              0x312E
687  #define WM8994_WRITE_SEQUENCER_303              0x312F
688  #define WM8994_WRITE_SEQUENCER_304              0x3130
689  #define WM8994_WRITE_SEQUENCER_305              0x3131
690  #define WM8994_WRITE_SEQUENCER_306              0x3132
691  #define WM8994_WRITE_SEQUENCER_307              0x3133
692  #define WM8994_WRITE_SEQUENCER_308              0x3134
693  #define WM8994_WRITE_SEQUENCER_309              0x3135
694  #define WM8994_WRITE_SEQUENCER_310              0x3136
695  #define WM8994_WRITE_SEQUENCER_311              0x3137
696  #define WM8994_WRITE_SEQUENCER_312              0x3138
697  #define WM8994_WRITE_SEQUENCER_313              0x3139
698  #define WM8994_WRITE_SEQUENCER_314              0x313A
699  #define WM8994_WRITE_SEQUENCER_315              0x313B
700  #define WM8994_WRITE_SEQUENCER_316              0x313C
701  #define WM8994_WRITE_SEQUENCER_317              0x313D
702  #define WM8994_WRITE_SEQUENCER_318              0x313E
703  #define WM8994_WRITE_SEQUENCER_319              0x313F
704  #define WM8994_WRITE_SEQUENCER_320              0x3140
705  #define WM8994_WRITE_SEQUENCER_321              0x3141
706  #define WM8994_WRITE_SEQUENCER_322              0x3142
707  #define WM8994_WRITE_SEQUENCER_323              0x3143
708  #define WM8994_WRITE_SEQUENCER_324              0x3144
709  #define WM8994_WRITE_SEQUENCER_325              0x3145
710  #define WM8994_WRITE_SEQUENCER_326              0x3146
711  #define WM8994_WRITE_SEQUENCER_327              0x3147
712  #define WM8994_WRITE_SEQUENCER_328              0x3148
713  #define WM8994_WRITE_SEQUENCER_329              0x3149
714  #define WM8994_WRITE_SEQUENCER_330              0x314A
715  #define WM8994_WRITE_SEQUENCER_331              0x314B
716  #define WM8994_WRITE_SEQUENCER_332              0x314C
717  #define WM8994_WRITE_SEQUENCER_333              0x314D
718  #define WM8994_WRITE_SEQUENCER_334              0x314E
719  #define WM8994_WRITE_SEQUENCER_335              0x314F
720  #define WM8994_WRITE_SEQUENCER_336              0x3150
721  #define WM8994_WRITE_SEQUENCER_337              0x3151
722  #define WM8994_WRITE_SEQUENCER_338              0x3152
723  #define WM8994_WRITE_SEQUENCER_339              0x3153
724  #define WM8994_WRITE_SEQUENCER_340              0x3154
725  #define WM8994_WRITE_SEQUENCER_341              0x3155
726  #define WM8994_WRITE_SEQUENCER_342              0x3156
727  #define WM8994_WRITE_SEQUENCER_343              0x3157
728  #define WM8994_WRITE_SEQUENCER_344              0x3158
729  #define WM8994_WRITE_SEQUENCER_345              0x3159
730  #define WM8994_WRITE_SEQUENCER_346              0x315A
731  #define WM8994_WRITE_SEQUENCER_347              0x315B
732  #define WM8994_WRITE_SEQUENCER_348              0x315C
733  #define WM8994_WRITE_SEQUENCER_349              0x315D
734  #define WM8994_WRITE_SEQUENCER_350              0x315E
735  #define WM8994_WRITE_SEQUENCER_351              0x315F
736  #define WM8994_WRITE_SEQUENCER_352              0x3160
737  #define WM8994_WRITE_SEQUENCER_353              0x3161
738  #define WM8994_WRITE_SEQUENCER_354              0x3162
739  #define WM8994_WRITE_SEQUENCER_355              0x3163
740  #define WM8994_WRITE_SEQUENCER_356              0x3164
741  #define WM8994_WRITE_SEQUENCER_357              0x3165
742  #define WM8994_WRITE_SEQUENCER_358              0x3166
743  #define WM8994_WRITE_SEQUENCER_359              0x3167
744  #define WM8994_WRITE_SEQUENCER_360              0x3168
745  #define WM8994_WRITE_SEQUENCER_361              0x3169
746  #define WM8994_WRITE_SEQUENCER_362              0x316A
747  #define WM8994_WRITE_SEQUENCER_363              0x316B
748  #define WM8994_WRITE_SEQUENCER_364              0x316C
749  #define WM8994_WRITE_SEQUENCER_365              0x316D
750  #define WM8994_WRITE_SEQUENCER_366              0x316E
751  #define WM8994_WRITE_SEQUENCER_367              0x316F
752  #define WM8994_WRITE_SEQUENCER_368              0x3170
753  #define WM8994_WRITE_SEQUENCER_369              0x3171
754  #define WM8994_WRITE_SEQUENCER_370              0x3172
755  #define WM8994_WRITE_SEQUENCER_371              0x3173
756  #define WM8994_WRITE_SEQUENCER_372              0x3174
757  #define WM8994_WRITE_SEQUENCER_373              0x3175
758  #define WM8994_WRITE_SEQUENCER_374              0x3176
759  #define WM8994_WRITE_SEQUENCER_375              0x3177
760  #define WM8994_WRITE_SEQUENCER_376              0x3178
761  #define WM8994_WRITE_SEQUENCER_377              0x3179
762  #define WM8994_WRITE_SEQUENCER_378              0x317A
763  #define WM8994_WRITE_SEQUENCER_379              0x317B
764  #define WM8994_WRITE_SEQUENCER_380              0x317C
765  #define WM8994_WRITE_SEQUENCER_381              0x317D
766  #define WM8994_WRITE_SEQUENCER_382              0x317E
767  #define WM8994_WRITE_SEQUENCER_383              0x317F
768  #define WM8994_WRITE_SEQUENCER_384              0x3180
769  #define WM8994_WRITE_SEQUENCER_385              0x3181
770  #define WM8994_WRITE_SEQUENCER_386              0x3182
771  #define WM8994_WRITE_SEQUENCER_387              0x3183
772  #define WM8994_WRITE_SEQUENCER_388              0x3184
773  #define WM8994_WRITE_SEQUENCER_389              0x3185
774  #define WM8994_WRITE_SEQUENCER_390              0x3186
775  #define WM8994_WRITE_SEQUENCER_391              0x3187
776  #define WM8994_WRITE_SEQUENCER_392              0x3188
777  #define WM8994_WRITE_SEQUENCER_393              0x3189
778  #define WM8994_WRITE_SEQUENCER_394              0x318A
779  #define WM8994_WRITE_SEQUENCER_395              0x318B
780  #define WM8994_WRITE_SEQUENCER_396              0x318C
781  #define WM8994_WRITE_SEQUENCER_397              0x318D
782  #define WM8994_WRITE_SEQUENCER_398              0x318E
783  #define WM8994_WRITE_SEQUENCER_399              0x318F
784  #define WM8994_WRITE_SEQUENCER_400              0x3190
785  #define WM8994_WRITE_SEQUENCER_401              0x3191
786  #define WM8994_WRITE_SEQUENCER_402              0x3192
787  #define WM8994_WRITE_SEQUENCER_403              0x3193
788  #define WM8994_WRITE_SEQUENCER_404              0x3194
789  #define WM8994_WRITE_SEQUENCER_405              0x3195
790  #define WM8994_WRITE_SEQUENCER_406              0x3196
791  #define WM8994_WRITE_SEQUENCER_407              0x3197
792  #define WM8994_WRITE_SEQUENCER_408              0x3198
793  #define WM8994_WRITE_SEQUENCER_409              0x3199
794  #define WM8994_WRITE_SEQUENCER_410              0x319A
795  #define WM8994_WRITE_SEQUENCER_411              0x319B
796  #define WM8994_WRITE_SEQUENCER_412              0x319C
797  #define WM8994_WRITE_SEQUENCER_413              0x319D
798  #define WM8994_WRITE_SEQUENCER_414              0x319E
799  #define WM8994_WRITE_SEQUENCER_415              0x319F
800  #define WM8994_WRITE_SEQUENCER_416              0x31A0
801  #define WM8994_WRITE_SEQUENCER_417              0x31A1
802  #define WM8994_WRITE_SEQUENCER_418              0x31A2
803  #define WM8994_WRITE_SEQUENCER_419              0x31A3
804  #define WM8994_WRITE_SEQUENCER_420              0x31A4
805  #define WM8994_WRITE_SEQUENCER_421              0x31A5
806  #define WM8994_WRITE_SEQUENCER_422              0x31A6
807  #define WM8994_WRITE_SEQUENCER_423              0x31A7
808  #define WM8994_WRITE_SEQUENCER_424              0x31A8
809  #define WM8994_WRITE_SEQUENCER_425              0x31A9
810  #define WM8994_WRITE_SEQUENCER_426              0x31AA
811  #define WM8994_WRITE_SEQUENCER_427              0x31AB
812  #define WM8994_WRITE_SEQUENCER_428              0x31AC
813  #define WM8994_WRITE_SEQUENCER_429              0x31AD
814  #define WM8994_WRITE_SEQUENCER_430              0x31AE
815  #define WM8994_WRITE_SEQUENCER_431              0x31AF
816  #define WM8994_WRITE_SEQUENCER_432              0x31B0
817  #define WM8994_WRITE_SEQUENCER_433              0x31B1
818  #define WM8994_WRITE_SEQUENCER_434              0x31B2
819  #define WM8994_WRITE_SEQUENCER_435              0x31B3
820  #define WM8994_WRITE_SEQUENCER_436              0x31B4
821  #define WM8994_WRITE_SEQUENCER_437              0x31B5
822  #define WM8994_WRITE_SEQUENCER_438              0x31B6
823  #define WM8994_WRITE_SEQUENCER_439              0x31B7
824  #define WM8994_WRITE_SEQUENCER_440              0x31B8
825  #define WM8994_WRITE_SEQUENCER_441              0x31B9
826  #define WM8994_WRITE_SEQUENCER_442              0x31BA
827  #define WM8994_WRITE_SEQUENCER_443              0x31BB
828  #define WM8994_WRITE_SEQUENCER_444              0x31BC
829  #define WM8994_WRITE_SEQUENCER_445              0x31BD
830  #define WM8994_WRITE_SEQUENCER_446              0x31BE
831  #define WM8994_WRITE_SEQUENCER_447              0x31BF
832  #define WM8994_WRITE_SEQUENCER_448              0x31C0
833  #define WM8994_WRITE_SEQUENCER_449              0x31C1
834  #define WM8994_WRITE_SEQUENCER_450              0x31C2
835  #define WM8994_WRITE_SEQUENCER_451              0x31C3
836  #define WM8994_WRITE_SEQUENCER_452              0x31C4
837  #define WM8994_WRITE_SEQUENCER_453              0x31C5
838  #define WM8994_WRITE_SEQUENCER_454              0x31C6
839  #define WM8994_WRITE_SEQUENCER_455              0x31C7
840  #define WM8994_WRITE_SEQUENCER_456              0x31C8
841  #define WM8994_WRITE_SEQUENCER_457              0x31C9
842  #define WM8994_WRITE_SEQUENCER_458              0x31CA
843  #define WM8994_WRITE_SEQUENCER_459              0x31CB
844  #define WM8994_WRITE_SEQUENCER_460              0x31CC
845  #define WM8994_WRITE_SEQUENCER_461              0x31CD
846  #define WM8994_WRITE_SEQUENCER_462              0x31CE
847  #define WM8994_WRITE_SEQUENCER_463              0x31CF
848  #define WM8994_WRITE_SEQUENCER_464              0x31D0
849  #define WM8994_WRITE_SEQUENCER_465              0x31D1
850  #define WM8994_WRITE_SEQUENCER_466              0x31D2
851  #define WM8994_WRITE_SEQUENCER_467              0x31D3
852  #define WM8994_WRITE_SEQUENCER_468              0x31D4
853  #define WM8994_WRITE_SEQUENCER_469              0x31D5
854  #define WM8994_WRITE_SEQUENCER_470              0x31D6
855  #define WM8994_WRITE_SEQUENCER_471              0x31D7
856  #define WM8994_WRITE_SEQUENCER_472              0x31D8
857  #define WM8994_WRITE_SEQUENCER_473              0x31D9
858  #define WM8994_WRITE_SEQUENCER_474              0x31DA
859  #define WM8994_WRITE_SEQUENCER_475              0x31DB
860  #define WM8994_WRITE_SEQUENCER_476              0x31DC
861  #define WM8994_WRITE_SEQUENCER_477              0x31DD
862  #define WM8994_WRITE_SEQUENCER_478              0x31DE
863  #define WM8994_WRITE_SEQUENCER_479              0x31DF
864  #define WM8994_WRITE_SEQUENCER_480              0x31E0
865  #define WM8994_WRITE_SEQUENCER_481              0x31E1
866  #define WM8994_WRITE_SEQUENCER_482              0x31E2
867  #define WM8994_WRITE_SEQUENCER_483              0x31E3
868  #define WM8994_WRITE_SEQUENCER_484              0x31E4
869  #define WM8994_WRITE_SEQUENCER_485              0x31E5
870  #define WM8994_WRITE_SEQUENCER_486              0x31E6
871  #define WM8994_WRITE_SEQUENCER_487              0x31E7
872  #define WM8994_WRITE_SEQUENCER_488              0x31E8
873  #define WM8994_WRITE_SEQUENCER_489              0x31E9
874  #define WM8994_WRITE_SEQUENCER_490              0x31EA
875  #define WM8994_WRITE_SEQUENCER_491              0x31EB
876  #define WM8994_WRITE_SEQUENCER_492              0x31EC
877  #define WM8994_WRITE_SEQUENCER_493              0x31ED
878  #define WM8994_WRITE_SEQUENCER_494              0x31EE
879  #define WM8994_WRITE_SEQUENCER_495              0x31EF
880  #define WM8994_WRITE_SEQUENCER_496              0x31F0
881  #define WM8994_WRITE_SEQUENCER_497              0x31F1
882  #define WM8994_WRITE_SEQUENCER_498              0x31F2
883  #define WM8994_WRITE_SEQUENCER_499              0x31F3
884  #define WM8994_WRITE_SEQUENCER_500              0x31F4
885  #define WM8994_WRITE_SEQUENCER_501              0x31F5
886  #define WM8994_WRITE_SEQUENCER_502              0x31F6
887  #define WM8994_WRITE_SEQUENCER_503              0x31F7
888  #define WM8994_WRITE_SEQUENCER_504              0x31F8
889  #define WM8994_WRITE_SEQUENCER_505              0x31F9
890  #define WM8994_WRITE_SEQUENCER_506              0x31FA
891  #define WM8994_WRITE_SEQUENCER_507              0x31FB
892  #define WM8994_WRITE_SEQUENCER_508              0x31FC
893  #define WM8994_WRITE_SEQUENCER_509              0x31FD
894  #define WM8994_WRITE_SEQUENCER_510              0x31FE
895  #define WM8994_WRITE_SEQUENCER_511              0x31FF
896  
897  #define WM8994_REGISTER_COUNT                   736
898  #define WM8994_MAX_REGISTER                     0x31FF
899  #define WM8994_MAX_CACHED_REGISTER              0x749
900  
901  /*
902   * Field Definitions.
903   */
904  
905  /*
906   * R0 (0x00) - Software Reset
907   */
908  #define WM8994_SW_RESET_MASK                    0xFFFF  /* SW_RESET - [15:0] */
909  #define WM8994_SW_RESET_SHIFT                        0  /* SW_RESET - [15:0] */
910  #define WM8994_SW_RESET_WIDTH                       16  /* SW_RESET - [15:0] */
911  
912  /*
913   * R1 (0x01) - Power Management (1)
914   */
915  #define WM8994_SPKOUTR_ENA                      0x2000  /* SPKOUTR_ENA */
916  #define WM8994_SPKOUTR_ENA_MASK                 0x2000  /* SPKOUTR_ENA */
917  #define WM8994_SPKOUTR_ENA_SHIFT                    13  /* SPKOUTR_ENA */
918  #define WM8994_SPKOUTR_ENA_WIDTH                     1  /* SPKOUTR_ENA */
919  #define WM8994_SPKOUTL_ENA                      0x1000  /* SPKOUTL_ENA */
920  #define WM8994_SPKOUTL_ENA_MASK                 0x1000  /* SPKOUTL_ENA */
921  #define WM8994_SPKOUTL_ENA_SHIFT                    12  /* SPKOUTL_ENA */
922  #define WM8994_SPKOUTL_ENA_WIDTH                     1  /* SPKOUTL_ENA */
923  #define WM8994_HPOUT2_ENA                       0x0800  /* HPOUT2_ENA */
924  #define WM8994_HPOUT2_ENA_MASK                  0x0800  /* HPOUT2_ENA */
925  #define WM8994_HPOUT2_ENA_SHIFT                     11  /* HPOUT2_ENA */
926  #define WM8994_HPOUT2_ENA_WIDTH                      1  /* HPOUT2_ENA */
927  #define WM8994_HPOUT1L_ENA                      0x0200  /* HPOUT1L_ENA */
928  #define WM8994_HPOUT1L_ENA_MASK                 0x0200  /* HPOUT1L_ENA */
929  #define WM8994_HPOUT1L_ENA_SHIFT                     9  /* HPOUT1L_ENA */
930  #define WM8994_HPOUT1L_ENA_WIDTH                     1  /* HPOUT1L_ENA */
931  #define WM8994_HPOUT1R_ENA                      0x0100  /* HPOUT1R_ENA */
932  #define WM8994_HPOUT1R_ENA_MASK                 0x0100  /* HPOUT1R_ENA */
933  #define WM8994_HPOUT1R_ENA_SHIFT                     8  /* HPOUT1R_ENA */
934  #define WM8994_HPOUT1R_ENA_WIDTH                     1  /* HPOUT1R_ENA */
935  #define WM8994_MICB2_ENA                        0x0020  /* MICB2_ENA */
936  #define WM8994_MICB2_ENA_MASK                   0x0020  /* MICB2_ENA */
937  #define WM8994_MICB2_ENA_SHIFT                       5  /* MICB2_ENA */
938  #define WM8994_MICB2_ENA_WIDTH                       1  /* MICB2_ENA */
939  #define WM8994_MICB1_ENA                        0x0010  /* MICB1_ENA */
940  #define WM8994_MICB1_ENA_MASK                   0x0010  /* MICB1_ENA */
941  #define WM8994_MICB1_ENA_SHIFT                       4  /* MICB1_ENA */
942  #define WM8994_MICB1_ENA_WIDTH                       1  /* MICB1_ENA */
943  #define WM8994_VMID_SEL_MASK                    0x0006  /* VMID_SEL - [2:1] */
944  #define WM8994_VMID_SEL_SHIFT                        1  /* VMID_SEL - [2:1] */
945  #define WM8994_VMID_SEL_WIDTH                        2  /* VMID_SEL - [2:1] */
946  #define WM8994_BIAS_ENA                         0x0001  /* BIAS_ENA */
947  #define WM8994_BIAS_ENA_MASK                    0x0001  /* BIAS_ENA */
948  #define WM8994_BIAS_ENA_SHIFT                        0  /* BIAS_ENA */
949  #define WM8994_BIAS_ENA_WIDTH                        1  /* BIAS_ENA */
950  
951  /*
952   * R2 (0x02) - Power Management (2)
953   */
954  #define WM8994_TSHUT_ENA                        0x4000  /* TSHUT_ENA */
955  #define WM8994_TSHUT_ENA_MASK                   0x4000  /* TSHUT_ENA */
956  #define WM8994_TSHUT_ENA_SHIFT                      14  /* TSHUT_ENA */
957  #define WM8994_TSHUT_ENA_WIDTH                       1  /* TSHUT_ENA */
958  #define WM8994_TSHUT_OPDIS                      0x2000  /* TSHUT_OPDIS */
959  #define WM8994_TSHUT_OPDIS_MASK                 0x2000  /* TSHUT_OPDIS */
960  #define WM8994_TSHUT_OPDIS_SHIFT                    13  /* TSHUT_OPDIS */
961  #define WM8994_TSHUT_OPDIS_WIDTH                     1  /* TSHUT_OPDIS */
962  #define WM8994_OPCLK_ENA                        0x0800  /* OPCLK_ENA */
963  #define WM8994_OPCLK_ENA_MASK                   0x0800  /* OPCLK_ENA */
964  #define WM8994_OPCLK_ENA_SHIFT                      11  /* OPCLK_ENA */
965  #define WM8994_OPCLK_ENA_WIDTH                       1  /* OPCLK_ENA */
966  #define WM8994_MIXINL_ENA                       0x0200  /* MIXINL_ENA */
967  #define WM8994_MIXINL_ENA_MASK                  0x0200  /* MIXINL_ENA */
968  #define WM8994_MIXINL_ENA_SHIFT                      9  /* MIXINL_ENA */
969  #define WM8994_MIXINL_ENA_WIDTH                      1  /* MIXINL_ENA */
970  #define WM8994_MIXINR_ENA                       0x0100  /* MIXINR_ENA */
971  #define WM8994_MIXINR_ENA_MASK                  0x0100  /* MIXINR_ENA */
972  #define WM8994_MIXINR_ENA_SHIFT                      8  /* MIXINR_ENA */
973  #define WM8994_MIXINR_ENA_WIDTH                      1  /* MIXINR_ENA */
974  #define WM8994_IN2L_ENA                         0x0080  /* IN2L_ENA */
975  #define WM8994_IN2L_ENA_MASK                    0x0080  /* IN2L_ENA */
976  #define WM8994_IN2L_ENA_SHIFT                        7  /* IN2L_ENA */
977  #define WM8994_IN2L_ENA_WIDTH                        1  /* IN2L_ENA */
978  #define WM8994_IN1L_ENA                         0x0040  /* IN1L_ENA */
979  #define WM8994_IN1L_ENA_MASK                    0x0040  /* IN1L_ENA */
980  #define WM8994_IN1L_ENA_SHIFT                        6  /* IN1L_ENA */
981  #define WM8994_IN1L_ENA_WIDTH                        1  /* IN1L_ENA */
982  #define WM8994_IN2R_ENA                         0x0020  /* IN2R_ENA */
983  #define WM8994_IN2R_ENA_MASK                    0x0020  /* IN2R_ENA */
984  #define WM8994_IN2R_ENA_SHIFT                        5  /* IN2R_ENA */
985  #define WM8994_IN2R_ENA_WIDTH                        1  /* IN2R_ENA */
986  #define WM8994_IN1R_ENA                         0x0010  /* IN1R_ENA */
987  #define WM8994_IN1R_ENA_MASK                    0x0010  /* IN1R_ENA */
988  #define WM8994_IN1R_ENA_SHIFT                        4  /* IN1R_ENA */
989  #define WM8994_IN1R_ENA_WIDTH                        1  /* IN1R_ENA */
990  
991  /*
992   * R3 (0x03) - Power Management (3)
993   */
994  #define WM8994_LINEOUT1N_ENA                    0x2000  /* LINEOUT1N_ENA */
995  #define WM8994_LINEOUT1N_ENA_MASK               0x2000  /* LINEOUT1N_ENA */
996  #define WM8994_LINEOUT1N_ENA_SHIFT                  13  /* LINEOUT1N_ENA */
997  #define WM8994_LINEOUT1N_ENA_WIDTH                   1  /* LINEOUT1N_ENA */
998  #define WM8994_LINEOUT1P_ENA                    0x1000  /* LINEOUT1P_ENA */
999  #define WM8994_LINEOUT1P_ENA_MASK               0x1000  /* LINEOUT1P_ENA */
1000  #define WM8994_LINEOUT1P_ENA_SHIFT                  12  /* LINEOUT1P_ENA */
1001  #define WM8994_LINEOUT1P_ENA_WIDTH                   1  /* LINEOUT1P_ENA */
1002  #define WM8994_LINEOUT2N_ENA                    0x0800  /* LINEOUT2N_ENA */
1003  #define WM8994_LINEOUT2N_ENA_MASK               0x0800  /* LINEOUT2N_ENA */
1004  #define WM8994_LINEOUT2N_ENA_SHIFT                  11  /* LINEOUT2N_ENA */
1005  #define WM8994_LINEOUT2N_ENA_WIDTH                   1  /* LINEOUT2N_ENA */
1006  #define WM8994_LINEOUT2P_ENA                    0x0400  /* LINEOUT2P_ENA */
1007  #define WM8994_LINEOUT2P_ENA_MASK               0x0400  /* LINEOUT2P_ENA */
1008  #define WM8994_LINEOUT2P_ENA_SHIFT                  10  /* LINEOUT2P_ENA */
1009  #define WM8994_LINEOUT2P_ENA_WIDTH                   1  /* LINEOUT2P_ENA */
1010  #define WM8994_SPKRVOL_ENA                      0x0200  /* SPKRVOL_ENA */
1011  #define WM8994_SPKRVOL_ENA_MASK                 0x0200  /* SPKRVOL_ENA */
1012  #define WM8994_SPKRVOL_ENA_SHIFT                     9  /* SPKRVOL_ENA */
1013  #define WM8994_SPKRVOL_ENA_WIDTH                     1  /* SPKRVOL_ENA */
1014  #define WM8994_SPKLVOL_ENA                      0x0100  /* SPKLVOL_ENA */
1015  #define WM8994_SPKLVOL_ENA_MASK                 0x0100  /* SPKLVOL_ENA */
1016  #define WM8994_SPKLVOL_ENA_SHIFT                     8  /* SPKLVOL_ENA */
1017  #define WM8994_SPKLVOL_ENA_WIDTH                     1  /* SPKLVOL_ENA */
1018  #define WM8994_MIXOUTLVOL_ENA                   0x0080  /* MIXOUTLVOL_ENA */
1019  #define WM8994_MIXOUTLVOL_ENA_MASK              0x0080  /* MIXOUTLVOL_ENA */
1020  #define WM8994_MIXOUTLVOL_ENA_SHIFT                  7  /* MIXOUTLVOL_ENA */
1021  #define WM8994_MIXOUTLVOL_ENA_WIDTH                  1  /* MIXOUTLVOL_ENA */
1022  #define WM8994_MIXOUTRVOL_ENA                   0x0040  /* MIXOUTRVOL_ENA */
1023  #define WM8994_MIXOUTRVOL_ENA_MASK              0x0040  /* MIXOUTRVOL_ENA */
1024  #define WM8994_MIXOUTRVOL_ENA_SHIFT                  6  /* MIXOUTRVOL_ENA */
1025  #define WM8994_MIXOUTRVOL_ENA_WIDTH                  1  /* MIXOUTRVOL_ENA */
1026  #define WM8994_MIXOUTL_ENA                      0x0020  /* MIXOUTL_ENA */
1027  #define WM8994_MIXOUTL_ENA_MASK                 0x0020  /* MIXOUTL_ENA */
1028  #define WM8994_MIXOUTL_ENA_SHIFT                     5  /* MIXOUTL_ENA */
1029  #define WM8994_MIXOUTL_ENA_WIDTH                     1  /* MIXOUTL_ENA */
1030  #define WM8994_MIXOUTR_ENA                      0x0010  /* MIXOUTR_ENA */
1031  #define WM8994_MIXOUTR_ENA_MASK                 0x0010  /* MIXOUTR_ENA */
1032  #define WM8994_MIXOUTR_ENA_SHIFT                     4  /* MIXOUTR_ENA */
1033  #define WM8994_MIXOUTR_ENA_WIDTH                     1  /* MIXOUTR_ENA */
1034  
1035  /*
1036   * R4 (0x04) - Power Management (4)
1037   */
1038  #define WM8994_AIF2ADCL_ENA                     0x2000  /* AIF2ADCL_ENA */
1039  #define WM8994_AIF2ADCL_ENA_MASK                0x2000  /* AIF2ADCL_ENA */
1040  #define WM8994_AIF2ADCL_ENA_SHIFT                   13  /* AIF2ADCL_ENA */
1041  #define WM8994_AIF2ADCL_ENA_WIDTH                    1  /* AIF2ADCL_ENA */
1042  #define WM8994_AIF2ADCR_ENA                     0x1000  /* AIF2ADCR_ENA */
1043  #define WM8994_AIF2ADCR_ENA_MASK                0x1000  /* AIF2ADCR_ENA */
1044  #define WM8994_AIF2ADCR_ENA_SHIFT                   12  /* AIF2ADCR_ENA */
1045  #define WM8994_AIF2ADCR_ENA_WIDTH                    1  /* AIF2ADCR_ENA */
1046  #define WM8994_AIF1ADC2L_ENA                    0x0800  /* AIF1ADC2L_ENA */
1047  #define WM8994_AIF1ADC2L_ENA_MASK               0x0800  /* AIF1ADC2L_ENA */
1048  #define WM8994_AIF1ADC2L_ENA_SHIFT                  11  /* AIF1ADC2L_ENA */
1049  #define WM8994_AIF1ADC2L_ENA_WIDTH                   1  /* AIF1ADC2L_ENA */
1050  #define WM8994_AIF1ADC2R_ENA                    0x0400  /* AIF1ADC2R_ENA */
1051  #define WM8994_AIF1ADC2R_ENA_MASK               0x0400  /* AIF1ADC2R_ENA */
1052  #define WM8994_AIF1ADC2R_ENA_SHIFT                  10  /* AIF1ADC2R_ENA */
1053  #define WM8994_AIF1ADC2R_ENA_WIDTH                   1  /* AIF1ADC2R_ENA */
1054  #define WM8994_AIF1ADC1L_ENA                    0x0200  /* AIF1ADC1L_ENA */
1055  #define WM8994_AIF1ADC1L_ENA_MASK               0x0200  /* AIF1ADC1L_ENA */
1056  #define WM8994_AIF1ADC1L_ENA_SHIFT                   9  /* AIF1ADC1L_ENA */
1057  #define WM8994_AIF1ADC1L_ENA_WIDTH                   1  /* AIF1ADC1L_ENA */
1058  #define WM8994_AIF1ADC1R_ENA                    0x0100  /* AIF1ADC1R_ENA */
1059  #define WM8994_AIF1ADC1R_ENA_MASK               0x0100  /* AIF1ADC1R_ENA */
1060  #define WM8994_AIF1ADC1R_ENA_SHIFT                   8  /* AIF1ADC1R_ENA */
1061  #define WM8994_AIF1ADC1R_ENA_WIDTH                   1  /* AIF1ADC1R_ENA */
1062  #define WM8994_DMIC2L_ENA                       0x0020  /* DMIC2L_ENA */
1063  #define WM8994_DMIC2L_ENA_MASK                  0x0020  /* DMIC2L_ENA */
1064  #define WM8994_DMIC2L_ENA_SHIFT                      5  /* DMIC2L_ENA */
1065  #define WM8994_DMIC2L_ENA_WIDTH                      1  /* DMIC2L_ENA */
1066  #define WM8994_DMIC2R_ENA                       0x0010  /* DMIC2R_ENA */
1067  #define WM8994_DMIC2R_ENA_MASK                  0x0010  /* DMIC2R_ENA */
1068  #define WM8994_DMIC2R_ENA_SHIFT                      4  /* DMIC2R_ENA */
1069  #define WM8994_DMIC2R_ENA_WIDTH                      1  /* DMIC2R_ENA */
1070  #define WM8994_DMIC1L_ENA                       0x0008  /* DMIC1L_ENA */
1071  #define WM8994_DMIC1L_ENA_MASK                  0x0008  /* DMIC1L_ENA */
1072  #define WM8994_DMIC1L_ENA_SHIFT                      3  /* DMIC1L_ENA */
1073  #define WM8994_DMIC1L_ENA_WIDTH                      1  /* DMIC1L_ENA */
1074  #define WM8994_DMIC1R_ENA                       0x0004  /* DMIC1R_ENA */
1075  #define WM8994_DMIC1R_ENA_MASK                  0x0004  /* DMIC1R_ENA */
1076  #define WM8994_DMIC1R_ENA_SHIFT                      2  /* DMIC1R_ENA */
1077  #define WM8994_DMIC1R_ENA_WIDTH                      1  /* DMIC1R_ENA */
1078  #define WM8994_ADCL_ENA                         0x0002  /* ADCL_ENA */
1079  #define WM8994_ADCL_ENA_MASK                    0x0002  /* ADCL_ENA */
1080  #define WM8994_ADCL_ENA_SHIFT                        1  /* ADCL_ENA */
1081  #define WM8994_ADCL_ENA_WIDTH                        1  /* ADCL_ENA */
1082  #define WM8994_ADCR_ENA                         0x0001  /* ADCR_ENA */
1083  #define WM8994_ADCR_ENA_MASK                    0x0001  /* ADCR_ENA */
1084  #define WM8994_ADCR_ENA_SHIFT                        0  /* ADCR_ENA */
1085  #define WM8994_ADCR_ENA_WIDTH                        1  /* ADCR_ENA */
1086  
1087  /*
1088   * R5 (0x05) - Power Management (5)
1089   */
1090  #define WM8994_AIF2DACL_ENA                     0x2000  /* AIF2DACL_ENA */
1091  #define WM8994_AIF2DACL_ENA_MASK                0x2000  /* AIF2DACL_ENA */
1092  #define WM8994_AIF2DACL_ENA_SHIFT                   13  /* AIF2DACL_ENA */
1093  #define WM8994_AIF2DACL_ENA_WIDTH                    1  /* AIF2DACL_ENA */
1094  #define WM8994_AIF2DACR_ENA                     0x1000  /* AIF2DACR_ENA */
1095  #define WM8994_AIF2DACR_ENA_MASK                0x1000  /* AIF2DACR_ENA */
1096  #define WM8994_AIF2DACR_ENA_SHIFT                   12  /* AIF2DACR_ENA */
1097  #define WM8994_AIF2DACR_ENA_WIDTH                    1  /* AIF2DACR_ENA */
1098  #define WM8994_AIF1DAC2L_ENA                    0x0800  /* AIF1DAC2L_ENA */
1099  #define WM8994_AIF1DAC2L_ENA_MASK               0x0800  /* AIF1DAC2L_ENA */
1100  #define WM8994_AIF1DAC2L_ENA_SHIFT                  11  /* AIF1DAC2L_ENA */
1101  #define WM8994_AIF1DAC2L_ENA_WIDTH                   1  /* AIF1DAC2L_ENA */
1102  #define WM8994_AIF1DAC2R_ENA                    0x0400  /* AIF1DAC2R_ENA */
1103  #define WM8994_AIF1DAC2R_ENA_MASK               0x0400  /* AIF1DAC2R_ENA */
1104  #define WM8994_AIF1DAC2R_ENA_SHIFT                  10  /* AIF1DAC2R_ENA */
1105  #define WM8994_AIF1DAC2R_ENA_WIDTH                   1  /* AIF1DAC2R_ENA */
1106  #define WM8994_AIF1DAC1L_ENA                    0x0200  /* AIF1DAC1L_ENA */
1107  #define WM8994_AIF1DAC1L_ENA_MASK               0x0200  /* AIF1DAC1L_ENA */
1108  #define WM8994_AIF1DAC1L_ENA_SHIFT                   9  /* AIF1DAC1L_ENA */
1109  #define WM8994_AIF1DAC1L_ENA_WIDTH                   1  /* AIF1DAC1L_ENA */
1110  #define WM8994_AIF1DAC1R_ENA                    0x0100  /* AIF1DAC1R_ENA */
1111  #define WM8994_AIF1DAC1R_ENA_MASK               0x0100  /* AIF1DAC1R_ENA */
1112  #define WM8994_AIF1DAC1R_ENA_SHIFT                   8  /* AIF1DAC1R_ENA */
1113  #define WM8994_AIF1DAC1R_ENA_WIDTH                   1  /* AIF1DAC1R_ENA */
1114  #define WM8994_DAC2L_ENA                        0x0008  /* DAC2L_ENA */
1115  #define WM8994_DAC2L_ENA_MASK                   0x0008  /* DAC2L_ENA */
1116  #define WM8994_DAC2L_ENA_SHIFT                       3  /* DAC2L_ENA */
1117  #define WM8994_DAC2L_ENA_WIDTH                       1  /* DAC2L_ENA */
1118  #define WM8994_DAC2R_ENA                        0x0004  /* DAC2R_ENA */
1119  #define WM8994_DAC2R_ENA_MASK                   0x0004  /* DAC2R_ENA */
1120  #define WM8994_DAC2R_ENA_SHIFT                       2  /* DAC2R_ENA */
1121  #define WM8994_DAC2R_ENA_WIDTH                       1  /* DAC2R_ENA */
1122  #define WM8994_DAC1L_ENA                        0x0002  /* DAC1L_ENA */
1123  #define WM8994_DAC1L_ENA_MASK                   0x0002  /* DAC1L_ENA */
1124  #define WM8994_DAC1L_ENA_SHIFT                       1  /* DAC1L_ENA */
1125  #define WM8994_DAC1L_ENA_WIDTH                       1  /* DAC1L_ENA */
1126  #define WM8994_DAC1R_ENA                        0x0001  /* DAC1R_ENA */
1127  #define WM8994_DAC1R_ENA_MASK                   0x0001  /* DAC1R_ENA */
1128  #define WM8994_DAC1R_ENA_SHIFT                       0  /* DAC1R_ENA */
1129  #define WM8994_DAC1R_ENA_WIDTH                       1  /* DAC1R_ENA */
1130  
1131  /*
1132   * R6 (0x06) - Power Management (6)
1133   */
1134  #define WM8958_AIF3ADC_SRC_MASK                 0x0600  /* AIF3ADC_SRC - [10:9] */
1135  #define WM8958_AIF3ADC_SRC_SHIFT                     9  /* AIF3ADC_SRC - [10:9] */
1136  #define WM8958_AIF3ADC_SRC_WIDTH                     2  /* AIF3ADC_SRC - [10:9] */
1137  #define WM8958_AIF2DAC_SRC_MASK                 0x0180  /* AIF2DAC_SRC - [8:7] */
1138  #define WM8958_AIF2DAC_SRC_SHIFT                     7  /* AIF2DAC_SRC - [8:7] */
1139  #define WM8958_AIF2DAC_SRC_WIDTH                     2  /* AIF2DAC_SRC - [8:7] */
1140  #define WM8994_AIF3_TRI                         0x0020  /* AIF3_TRI */
1141  #define WM8994_AIF3_TRI_MASK                    0x0020  /* AIF3_TRI */
1142  #define WM8994_AIF3_TRI_SHIFT                        5  /* AIF3_TRI */
1143  #define WM8994_AIF3_TRI_WIDTH                        1  /* AIF3_TRI */
1144  #define WM8994_AIF3_ADCDAT_SRC_MASK             0x0018  /* AIF3_ADCDAT_SRC - [4:3] */
1145  #define WM8994_AIF3_ADCDAT_SRC_SHIFT                 3  /* AIF3_ADCDAT_SRC - [4:3] */
1146  #define WM8994_AIF3_ADCDAT_SRC_WIDTH                 2  /* AIF3_ADCDAT_SRC - [4:3] */
1147  #define WM8994_AIF2_ADCDAT_SRC                  0x0004  /* AIF2_ADCDAT_SRC */
1148  #define WM8994_AIF2_ADCDAT_SRC_MASK             0x0004  /* AIF2_ADCDAT_SRC */
1149  #define WM8994_AIF2_ADCDAT_SRC_SHIFT                 2  /* AIF2_ADCDAT_SRC */
1150  #define WM8994_AIF2_ADCDAT_SRC_WIDTH                 1  /* AIF2_ADCDAT_SRC */
1151  #define WM8994_AIF2_DACDAT_SRC                  0x0002  /* AIF2_DACDAT_SRC */
1152  #define WM8994_AIF2_DACDAT_SRC_MASK             0x0002  /* AIF2_DACDAT_SRC */
1153  #define WM8994_AIF2_DACDAT_SRC_SHIFT                 1  /* AIF2_DACDAT_SRC */
1154  #define WM8994_AIF2_DACDAT_SRC_WIDTH                 1  /* AIF2_DACDAT_SRC */
1155  #define WM8994_AIF1_DACDAT_SRC                  0x0001  /* AIF1_DACDAT_SRC */
1156  #define WM8994_AIF1_DACDAT_SRC_MASK             0x0001  /* AIF1_DACDAT_SRC */
1157  #define WM8994_AIF1_DACDAT_SRC_SHIFT                 0  /* AIF1_DACDAT_SRC */
1158  #define WM8994_AIF1_DACDAT_SRC_WIDTH                 1  /* AIF1_DACDAT_SRC */
1159  
1160  /*
1161   * R21 (0x15) - Input Mixer (1)
1162   */
1163  #define WM8994_IN1RP_MIXINR_BOOST               0x0100  /* IN1RP_MIXINR_BOOST */
1164  #define WM8994_IN1RP_MIXINR_BOOST_MASK          0x0100  /* IN1RP_MIXINR_BOOST */
1165  #define WM8994_IN1RP_MIXINR_BOOST_SHIFT              8  /* IN1RP_MIXINR_BOOST */
1166  #define WM8994_IN1RP_MIXINR_BOOST_WIDTH              1  /* IN1RP_MIXINR_BOOST */
1167  #define WM8994_IN1LP_MIXINL_BOOST               0x0080  /* IN1LP_MIXINL_BOOST */
1168  #define WM8994_IN1LP_MIXINL_BOOST_MASK          0x0080  /* IN1LP_MIXINL_BOOST */
1169  #define WM8994_IN1LP_MIXINL_BOOST_SHIFT              7  /* IN1LP_MIXINL_BOOST */
1170  #define WM8994_IN1LP_MIXINL_BOOST_WIDTH              1  /* IN1LP_MIXINL_BOOST */
1171  #define WM8994_INPUTS_CLAMP                     0x0040  /* INPUTS_CLAMP */
1172  #define WM8994_INPUTS_CLAMP_MASK                0x0040  /* INPUTS_CLAMP */
1173  #define WM8994_INPUTS_CLAMP_SHIFT                    6  /* INPUTS_CLAMP */
1174  #define WM8994_INPUTS_CLAMP_WIDTH                    1  /* INPUTS_CLAMP */
1175  
1176  /*
1177   * R24 (0x18) - Left Line Input 1&2 Volume
1178   */
1179  #define WM8994_IN1_VU                           0x0100  /* IN1_VU */
1180  #define WM8994_IN1_VU_MASK                      0x0100  /* IN1_VU */
1181  #define WM8994_IN1_VU_SHIFT                          8  /* IN1_VU */
1182  #define WM8994_IN1_VU_WIDTH                          1  /* IN1_VU */
1183  #define WM8994_IN1L_MUTE                        0x0080  /* IN1L_MUTE */
1184  #define WM8994_IN1L_MUTE_MASK                   0x0080  /* IN1L_MUTE */
1185  #define WM8994_IN1L_MUTE_SHIFT                       7  /* IN1L_MUTE */
1186  #define WM8994_IN1L_MUTE_WIDTH                       1  /* IN1L_MUTE */
1187  #define WM8994_IN1L_ZC                          0x0040  /* IN1L_ZC */
1188  #define WM8994_IN1L_ZC_MASK                     0x0040  /* IN1L_ZC */
1189  #define WM8994_IN1L_ZC_SHIFT                         6  /* IN1L_ZC */
1190  #define WM8994_IN1L_ZC_WIDTH                         1  /* IN1L_ZC */
1191  #define WM8994_IN1L_VOL_MASK                    0x001F  /* IN1L_VOL - [4:0] */
1192  #define WM8994_IN1L_VOL_SHIFT                        0  /* IN1L_VOL - [4:0] */
1193  #define WM8994_IN1L_VOL_WIDTH                        5  /* IN1L_VOL - [4:0] */
1194  
1195  /*
1196   * R25 (0x19) - Left Line Input 3&4 Volume
1197   */
1198  #define WM8994_IN2_VU                           0x0100  /* IN2_VU */
1199  #define WM8994_IN2_VU_MASK                      0x0100  /* IN2_VU */
1200  #define WM8994_IN2_VU_SHIFT                          8  /* IN2_VU */
1201  #define WM8994_IN2_VU_WIDTH                          1  /* IN2_VU */
1202  #define WM8994_IN2L_MUTE                        0x0080  /* IN2L_MUTE */
1203  #define WM8994_IN2L_MUTE_MASK                   0x0080  /* IN2L_MUTE */
1204  #define WM8994_IN2L_MUTE_SHIFT                       7  /* IN2L_MUTE */
1205  #define WM8994_IN2L_MUTE_WIDTH                       1  /* IN2L_MUTE */
1206  #define WM8994_IN2L_ZC                          0x0040  /* IN2L_ZC */
1207  #define WM8994_IN2L_ZC_MASK                     0x0040  /* IN2L_ZC */
1208  #define WM8994_IN2L_ZC_SHIFT                         6  /* IN2L_ZC */
1209  #define WM8994_IN2L_ZC_WIDTH                         1  /* IN2L_ZC */
1210  #define WM8994_IN2L_VOL_MASK                    0x001F  /* IN2L_VOL - [4:0] */
1211  #define WM8994_IN2L_VOL_SHIFT                        0  /* IN2L_VOL - [4:0] */
1212  #define WM8994_IN2L_VOL_WIDTH                        5  /* IN2L_VOL - [4:0] */
1213  
1214  /*
1215   * R26 (0x1A) - Right Line Input 1&2 Volume
1216   */
1217  #define WM8994_IN1_VU                           0x0100  /* IN1_VU */
1218  #define WM8994_IN1_VU_MASK                      0x0100  /* IN1_VU */
1219  #define WM8994_IN1_VU_SHIFT                          8  /* IN1_VU */
1220  #define WM8994_IN1_VU_WIDTH                          1  /* IN1_VU */
1221  #define WM8994_IN1R_MUTE                        0x0080  /* IN1R_MUTE */
1222  #define WM8994_IN1R_MUTE_MASK                   0x0080  /* IN1R_MUTE */
1223  #define WM8994_IN1R_MUTE_SHIFT                       7  /* IN1R_MUTE */
1224  #define WM8994_IN1R_MUTE_WIDTH                       1  /* IN1R_MUTE */
1225  #define WM8994_IN1R_ZC                          0x0040  /* IN1R_ZC */
1226  #define WM8994_IN1R_ZC_MASK                     0x0040  /* IN1R_ZC */
1227  #define WM8994_IN1R_ZC_SHIFT                         6  /* IN1R_ZC */
1228  #define WM8994_IN1R_ZC_WIDTH                         1  /* IN1R_ZC */
1229  #define WM8994_IN1R_VOL_MASK                    0x001F  /* IN1R_VOL - [4:0] */
1230  #define WM8994_IN1R_VOL_SHIFT                        0  /* IN1R_VOL - [4:0] */
1231  #define WM8994_IN1R_VOL_WIDTH                        5  /* IN1R_VOL - [4:0] */
1232  
1233  /*
1234   * R27 (0x1B) - Right Line Input 3&4 Volume
1235   */
1236  #define WM8994_IN2_VU                           0x0100  /* IN2_VU */
1237  #define WM8994_IN2_VU_MASK                      0x0100  /* IN2_VU */
1238  #define WM8994_IN2_VU_SHIFT                          8  /* IN2_VU */
1239  #define WM8994_IN2_VU_WIDTH                          1  /* IN2_VU */
1240  #define WM8994_IN2R_MUTE                        0x0080  /* IN2R_MUTE */
1241  #define WM8994_IN2R_MUTE_MASK                   0x0080  /* IN2R_MUTE */
1242  #define WM8994_IN2R_MUTE_SHIFT                       7  /* IN2R_MUTE */
1243  #define WM8994_IN2R_MUTE_WIDTH                       1  /* IN2R_MUTE */
1244  #define WM8994_IN2R_ZC                          0x0040  /* IN2R_ZC */
1245  #define WM8994_IN2R_ZC_MASK                     0x0040  /* IN2R_ZC */
1246  #define WM8994_IN2R_ZC_SHIFT                         6  /* IN2R_ZC */
1247  #define WM8994_IN2R_ZC_WIDTH                         1  /* IN2R_ZC */
1248  #define WM8994_IN2R_VOL_MASK                    0x001F  /* IN2R_VOL - [4:0] */
1249  #define WM8994_IN2R_VOL_SHIFT                        0  /* IN2R_VOL - [4:0] */
1250  #define WM8994_IN2R_VOL_WIDTH                        5  /* IN2R_VOL - [4:0] */
1251  
1252  /*
1253   * R28 (0x1C) - Left Output Volume
1254   */
1255  #define WM8994_HPOUT1_VU                        0x0100  /* HPOUT1_VU */
1256  #define WM8994_HPOUT1_VU_MASK                   0x0100  /* HPOUT1_VU */
1257  #define WM8994_HPOUT1_VU_SHIFT                       8  /* HPOUT1_VU */
1258  #define WM8994_HPOUT1_VU_WIDTH                       1  /* HPOUT1_VU */
1259  #define WM8994_HPOUT1L_ZC                       0x0080  /* HPOUT1L_ZC */
1260  #define WM8994_HPOUT1L_ZC_MASK                  0x0080  /* HPOUT1L_ZC */
1261  #define WM8994_HPOUT1L_ZC_SHIFT                      7  /* HPOUT1L_ZC */
1262  #define WM8994_HPOUT1L_ZC_WIDTH                      1  /* HPOUT1L_ZC */
1263  #define WM8994_HPOUT1L_MUTE_N                   0x0040  /* HPOUT1L_MUTE_N */
1264  #define WM8994_HPOUT1L_MUTE_N_MASK              0x0040  /* HPOUT1L_MUTE_N */
1265  #define WM8994_HPOUT1L_MUTE_N_SHIFT                  6  /* HPOUT1L_MUTE_N */
1266  #define WM8994_HPOUT1L_MUTE_N_WIDTH                  1  /* HPOUT1L_MUTE_N */
1267  #define WM8994_HPOUT1L_VOL_MASK                 0x003F  /* HPOUT1L_VOL - [5:0] */
1268  #define WM8994_HPOUT1L_VOL_SHIFT                     0  /* HPOUT1L_VOL - [5:0] */
1269  #define WM8994_HPOUT1L_VOL_WIDTH                     6  /* HPOUT1L_VOL - [5:0] */
1270  
1271  /*
1272   * R29 (0x1D) - Right Output Volume
1273   */
1274  #define WM8994_HPOUT1_VU                        0x0100  /* HPOUT1_VU */
1275  #define WM8994_HPOUT1_VU_MASK                   0x0100  /* HPOUT1_VU */
1276  #define WM8994_HPOUT1_VU_SHIFT                       8  /* HPOUT1_VU */
1277  #define WM8994_HPOUT1_VU_WIDTH                       1  /* HPOUT1_VU */
1278  #define WM8994_HPOUT1R_ZC                       0x0080  /* HPOUT1R_ZC */
1279  #define WM8994_HPOUT1R_ZC_MASK                  0x0080  /* HPOUT1R_ZC */
1280  #define WM8994_HPOUT1R_ZC_SHIFT                      7  /* HPOUT1R_ZC */
1281  #define WM8994_HPOUT1R_ZC_WIDTH                      1  /* HPOUT1R_ZC */
1282  #define WM8994_HPOUT1R_MUTE_N                   0x0040  /* HPOUT1R_MUTE_N */
1283  #define WM8994_HPOUT1R_MUTE_N_MASK              0x0040  /* HPOUT1R_MUTE_N */
1284  #define WM8994_HPOUT1R_MUTE_N_SHIFT                  6  /* HPOUT1R_MUTE_N */
1285  #define WM8994_HPOUT1R_MUTE_N_WIDTH                  1  /* HPOUT1R_MUTE_N */
1286  #define WM8994_HPOUT1R_VOL_MASK                 0x003F  /* HPOUT1R_VOL - [5:0] */
1287  #define WM8994_HPOUT1R_VOL_SHIFT                     0  /* HPOUT1R_VOL - [5:0] */
1288  #define WM8994_HPOUT1R_VOL_WIDTH                     6  /* HPOUT1R_VOL - [5:0] */
1289  
1290  /*
1291   * R30 (0x1E) - Line Outputs Volume
1292   */
1293  #define WM8994_LINEOUT1N_MUTE                   0x0040  /* LINEOUT1N_MUTE */
1294  #define WM8994_LINEOUT1N_MUTE_MASK              0x0040  /* LINEOUT1N_MUTE */
1295  #define WM8994_LINEOUT1N_MUTE_SHIFT                  6  /* LINEOUT1N_MUTE */
1296  #define WM8994_LINEOUT1N_MUTE_WIDTH                  1  /* LINEOUT1N_MUTE */
1297  #define WM8994_LINEOUT1P_MUTE                   0x0020  /* LINEOUT1P_MUTE */
1298  #define WM8994_LINEOUT1P_MUTE_MASK              0x0020  /* LINEOUT1P_MUTE */
1299  #define WM8994_LINEOUT1P_MUTE_SHIFT                  5  /* LINEOUT1P_MUTE */
1300  #define WM8994_LINEOUT1P_MUTE_WIDTH                  1  /* LINEOUT1P_MUTE */
1301  #define WM8994_LINEOUT1_VOL                     0x0010  /* LINEOUT1_VOL */
1302  #define WM8994_LINEOUT1_VOL_MASK                0x0010  /* LINEOUT1_VOL */
1303  #define WM8994_LINEOUT1_VOL_SHIFT                    4  /* LINEOUT1_VOL */
1304  #define WM8994_LINEOUT1_VOL_WIDTH                    1  /* LINEOUT1_VOL */
1305  #define WM8994_LINEOUT2N_MUTE                   0x0004  /* LINEOUT2N_MUTE */
1306  #define WM8994_LINEOUT2N_MUTE_MASK              0x0004  /* LINEOUT2N_MUTE */
1307  #define WM8994_LINEOUT2N_MUTE_SHIFT                  2  /* LINEOUT2N_MUTE */
1308  #define WM8994_LINEOUT2N_MUTE_WIDTH                  1  /* LINEOUT2N_MUTE */
1309  #define WM8994_LINEOUT2P_MUTE                   0x0002  /* LINEOUT2P_MUTE */
1310  #define WM8994_LINEOUT2P_MUTE_MASK              0x0002  /* LINEOUT2P_MUTE */
1311  #define WM8994_LINEOUT2P_MUTE_SHIFT                  1  /* LINEOUT2P_MUTE */
1312  #define WM8994_LINEOUT2P_MUTE_WIDTH                  1  /* LINEOUT2P_MUTE */
1313  #define WM8994_LINEOUT2_VOL                     0x0001  /* LINEOUT2_VOL */
1314  #define WM8994_LINEOUT2_VOL_MASK                0x0001  /* LINEOUT2_VOL */
1315  #define WM8994_LINEOUT2_VOL_SHIFT                    0  /* LINEOUT2_VOL */
1316  #define WM8994_LINEOUT2_VOL_WIDTH                    1  /* LINEOUT2_VOL */
1317  
1318  /*
1319   * R31 (0x1F) - HPOUT2 Volume
1320   */
1321  #define WM8994_HPOUT2_MUTE                      0x0020  /* HPOUT2_MUTE */
1322  #define WM8994_HPOUT2_MUTE_MASK                 0x0020  /* HPOUT2_MUTE */
1323  #define WM8994_HPOUT2_MUTE_SHIFT                     5  /* HPOUT2_MUTE */
1324  #define WM8994_HPOUT2_MUTE_WIDTH                     1  /* HPOUT2_MUTE */
1325  #define WM8994_HPOUT2_VOL                       0x0010  /* HPOUT2_VOL */
1326  #define WM8994_HPOUT2_VOL_MASK                  0x0010  /* HPOUT2_VOL */
1327  #define WM8994_HPOUT2_VOL_SHIFT                      4  /* HPOUT2_VOL */
1328  #define WM8994_HPOUT2_VOL_WIDTH                      1  /* HPOUT2_VOL */
1329  
1330  /*
1331   * R32 (0x20) - Left OPGA Volume
1332   */
1333  #define WM8994_MIXOUT_VU                        0x0100  /* MIXOUT_VU */
1334  #define WM8994_MIXOUT_VU_MASK                   0x0100  /* MIXOUT_VU */
1335  #define WM8994_MIXOUT_VU_SHIFT                       8  /* MIXOUT_VU */
1336  #define WM8994_MIXOUT_VU_WIDTH                       1  /* MIXOUT_VU */
1337  #define WM8994_MIXOUTL_ZC                       0x0080  /* MIXOUTL_ZC */
1338  #define WM8994_MIXOUTL_ZC_MASK                  0x0080  /* MIXOUTL_ZC */
1339  #define WM8994_MIXOUTL_ZC_SHIFT                      7  /* MIXOUTL_ZC */
1340  #define WM8994_MIXOUTL_ZC_WIDTH                      1  /* MIXOUTL_ZC */
1341  #define WM8994_MIXOUTL_MUTE_N                   0x0040  /* MIXOUTL_MUTE_N */
1342  #define WM8994_MIXOUTL_MUTE_N_MASK              0x0040  /* MIXOUTL_MUTE_N */
1343  #define WM8994_MIXOUTL_MUTE_N_SHIFT                  6  /* MIXOUTL_MUTE_N */
1344  #define WM8994_MIXOUTL_MUTE_N_WIDTH                  1  /* MIXOUTL_MUTE_N */
1345  #define WM8994_MIXOUTL_VOL_MASK                 0x003F  /* MIXOUTL_VOL - [5:0] */
1346  #define WM8994_MIXOUTL_VOL_SHIFT                     0  /* MIXOUTL_VOL - [5:0] */
1347  #define WM8994_MIXOUTL_VOL_WIDTH                     6  /* MIXOUTL_VOL - [5:0] */
1348  
1349  /*
1350   * R33 (0x21) - Right OPGA Volume
1351   */
1352  #define WM8994_MIXOUT_VU                        0x0100  /* MIXOUT_VU */
1353  #define WM8994_MIXOUT_VU_MASK                   0x0100  /* MIXOUT_VU */
1354  #define WM8994_MIXOUT_VU_SHIFT                       8  /* MIXOUT_VU */
1355  #define WM8994_MIXOUT_VU_WIDTH                       1  /* MIXOUT_VU */
1356  #define WM8994_MIXOUTR_ZC                       0x0080  /* MIXOUTR_ZC */
1357  #define WM8994_MIXOUTR_ZC_MASK                  0x0080  /* MIXOUTR_ZC */
1358  #define WM8994_MIXOUTR_ZC_SHIFT                      7  /* MIXOUTR_ZC */
1359  #define WM8994_MIXOUTR_ZC_WIDTH                      1  /* MIXOUTR_ZC */
1360  #define WM8994_MIXOUTR_MUTE_N                   0x0040  /* MIXOUTR_MUTE_N */
1361  #define WM8994_MIXOUTR_MUTE_N_MASK              0x0040  /* MIXOUTR_MUTE_N */
1362  #define WM8994_MIXOUTR_MUTE_N_SHIFT                  6  /* MIXOUTR_MUTE_N */
1363  #define WM8994_MIXOUTR_MUTE_N_WIDTH                  1  /* MIXOUTR_MUTE_N */
1364  #define WM8994_MIXOUTR_VOL_MASK                 0x003F  /* MIXOUTR_VOL - [5:0] */
1365  #define WM8994_MIXOUTR_VOL_SHIFT                     0  /* MIXOUTR_VOL - [5:0] */
1366  #define WM8994_MIXOUTR_VOL_WIDTH                     6  /* MIXOUTR_VOL - [5:0] */
1367  
1368  /*
1369   * R34 (0x22) - SPKMIXL Attenuation
1370   */
1371  #define WM8994_DAC2L_SPKMIXL_VOL                0x0040  /* DAC2L_SPKMIXL_VOL */
1372  #define WM8994_DAC2L_SPKMIXL_VOL_MASK           0x0040  /* DAC2L_SPKMIXL_VOL */
1373  #define WM8994_DAC2L_SPKMIXL_VOL_SHIFT               6  /* DAC2L_SPKMIXL_VOL */
1374  #define WM8994_DAC2L_SPKMIXL_VOL_WIDTH               1  /* DAC2L_SPKMIXL_VOL */
1375  #define WM8994_MIXINL_SPKMIXL_VOL               0x0020  /* MIXINL_SPKMIXL_VOL */
1376  #define WM8994_MIXINL_SPKMIXL_VOL_MASK          0x0020  /* MIXINL_SPKMIXL_VOL */
1377  #define WM8994_MIXINL_SPKMIXL_VOL_SHIFT              5  /* MIXINL_SPKMIXL_VOL */
1378  #define WM8994_MIXINL_SPKMIXL_VOL_WIDTH              1  /* MIXINL_SPKMIXL_VOL */
1379  #define WM8994_IN1LP_SPKMIXL_VOL                0x0010  /* IN1LP_SPKMIXL_VOL */
1380  #define WM8994_IN1LP_SPKMIXL_VOL_MASK           0x0010  /* IN1LP_SPKMIXL_VOL */
1381  #define WM8994_IN1LP_SPKMIXL_VOL_SHIFT               4  /* IN1LP_SPKMIXL_VOL */
1382  #define WM8994_IN1LP_SPKMIXL_VOL_WIDTH               1  /* IN1LP_SPKMIXL_VOL */
1383  #define WM8994_MIXOUTL_SPKMIXL_VOL              0x0008  /* MIXOUTL_SPKMIXL_VOL */
1384  #define WM8994_MIXOUTL_SPKMIXL_VOL_MASK         0x0008  /* MIXOUTL_SPKMIXL_VOL */
1385  #define WM8994_MIXOUTL_SPKMIXL_VOL_SHIFT             3  /* MIXOUTL_SPKMIXL_VOL */
1386  #define WM8994_MIXOUTL_SPKMIXL_VOL_WIDTH             1  /* MIXOUTL_SPKMIXL_VOL */
1387  #define WM8994_DAC1L_SPKMIXL_VOL                0x0004  /* DAC1L_SPKMIXL_VOL */
1388  #define WM8994_DAC1L_SPKMIXL_VOL_MASK           0x0004  /* DAC1L_SPKMIXL_VOL */
1389  #define WM8994_DAC1L_SPKMIXL_VOL_SHIFT               2  /* DAC1L_SPKMIXL_VOL */
1390  #define WM8994_DAC1L_SPKMIXL_VOL_WIDTH               1  /* DAC1L_SPKMIXL_VOL */
1391  #define WM8994_SPKMIXL_VOL_MASK                 0x0003  /* SPKMIXL_VOL - [1:0] */
1392  #define WM8994_SPKMIXL_VOL_SHIFT                     0  /* SPKMIXL_VOL - [1:0] */
1393  #define WM8994_SPKMIXL_VOL_WIDTH                     2  /* SPKMIXL_VOL - [1:0] */
1394  
1395  /*
1396   * R35 (0x23) - SPKMIXR Attenuation
1397   */
1398  #define WM8994_SPKOUT_CLASSAB                   0x0100  /* SPKOUT_CLASSAB */
1399  #define WM8994_SPKOUT_CLASSAB_MASK              0x0100  /* SPKOUT_CLASSAB */
1400  #define WM8994_SPKOUT_CLASSAB_SHIFT                  8  /* SPKOUT_CLASSAB */
1401  #define WM8994_SPKOUT_CLASSAB_WIDTH                  1  /* SPKOUT_CLASSAB */
1402  #define WM8994_DAC2R_SPKMIXR_VOL                0x0040  /* DAC2R_SPKMIXR_VOL */
1403  #define WM8994_DAC2R_SPKMIXR_VOL_MASK           0x0040  /* DAC2R_SPKMIXR_VOL */
1404  #define WM8994_DAC2R_SPKMIXR_VOL_SHIFT               6  /* DAC2R_SPKMIXR_VOL */
1405  #define WM8994_DAC2R_SPKMIXR_VOL_WIDTH               1  /* DAC2R_SPKMIXR_VOL */
1406  #define WM8994_MIXINR_SPKMIXR_VOL               0x0020  /* MIXINR_SPKMIXR_VOL */
1407  #define WM8994_MIXINR_SPKMIXR_VOL_MASK          0x0020  /* MIXINR_SPKMIXR_VOL */
1408  #define WM8994_MIXINR_SPKMIXR_VOL_SHIFT              5  /* MIXINR_SPKMIXR_VOL */
1409  #define WM8994_MIXINR_SPKMIXR_VOL_WIDTH              1  /* MIXINR_SPKMIXR_VOL */
1410  #define WM8994_IN1RP_SPKMIXR_VOL                0x0010  /* IN1RP_SPKMIXR_VOL */
1411  #define WM8994_IN1RP_SPKMIXR_VOL_MASK           0x0010  /* IN1RP_SPKMIXR_VOL */
1412  #define WM8994_IN1RP_SPKMIXR_VOL_SHIFT               4  /* IN1RP_SPKMIXR_VOL */
1413  #define WM8994_IN1RP_SPKMIXR_VOL_WIDTH               1  /* IN1RP_SPKMIXR_VOL */
1414  #define WM8994_MIXOUTR_SPKMIXR_VOL              0x0008  /* MIXOUTR_SPKMIXR_VOL */
1415  #define WM8994_MIXOUTR_SPKMIXR_VOL_MASK         0x0008  /* MIXOUTR_SPKMIXR_VOL */
1416  #define WM8994_MIXOUTR_SPKMIXR_VOL_SHIFT             3  /* MIXOUTR_SPKMIXR_VOL */
1417  #define WM8994_MIXOUTR_SPKMIXR_VOL_WIDTH             1  /* MIXOUTR_SPKMIXR_VOL */
1418  #define WM8994_DAC1R_SPKMIXR_VOL                0x0004  /* DAC1R_SPKMIXR_VOL */
1419  #define WM8994_DAC1R_SPKMIXR_VOL_MASK           0x0004  /* DAC1R_SPKMIXR_VOL */
1420  #define WM8994_DAC1R_SPKMIXR_VOL_SHIFT               2  /* DAC1R_SPKMIXR_VOL */
1421  #define WM8994_DAC1R_SPKMIXR_VOL_WIDTH               1  /* DAC1R_SPKMIXR_VOL */
1422  #define WM8994_SPKMIXR_VOL_MASK                 0x0003  /* SPKMIXR_VOL - [1:0] */
1423  #define WM8994_SPKMIXR_VOL_SHIFT                     0  /* SPKMIXR_VOL - [1:0] */
1424  #define WM8994_SPKMIXR_VOL_WIDTH                     2  /* SPKMIXR_VOL - [1:0] */
1425  
1426  /*
1427   * R36 (0x24) - SPKOUT Mixers
1428   */
1429  #define WM8994_IN2LRP_TO_SPKOUTL                0x0020  /* IN2LRP_TO_SPKOUTL */
1430  #define WM8994_IN2LRP_TO_SPKOUTL_MASK           0x0020  /* IN2LRP_TO_SPKOUTL */
1431  #define WM8994_IN2LRP_TO_SPKOUTL_SHIFT               5  /* IN2LRP_TO_SPKOUTL */
1432  #define WM8994_IN2LRP_TO_SPKOUTL_WIDTH               1  /* IN2LRP_TO_SPKOUTL */
1433  #define WM8994_SPKMIXL_TO_SPKOUTL               0x0010  /* SPKMIXL_TO_SPKOUTL */
1434  #define WM8994_SPKMIXL_TO_SPKOUTL_MASK          0x0010  /* SPKMIXL_TO_SPKOUTL */
1435  #define WM8994_SPKMIXL_TO_SPKOUTL_SHIFT              4  /* SPKMIXL_TO_SPKOUTL */
1436  #define WM8994_SPKMIXL_TO_SPKOUTL_WIDTH              1  /* SPKMIXL_TO_SPKOUTL */
1437  #define WM8994_SPKMIXR_TO_SPKOUTL               0x0008  /* SPKMIXR_TO_SPKOUTL */
1438  #define WM8994_SPKMIXR_TO_SPKOUTL_MASK          0x0008  /* SPKMIXR_TO_SPKOUTL */
1439  #define WM8994_SPKMIXR_TO_SPKOUTL_SHIFT              3  /* SPKMIXR_TO_SPKOUTL */
1440  #define WM8994_SPKMIXR_TO_SPKOUTL_WIDTH              1  /* SPKMIXR_TO_SPKOUTL */
1441  #define WM8994_IN2LRP_TO_SPKOUTR                0x0004  /* IN2LRP_TO_SPKOUTR */
1442  #define WM8994_IN2LRP_TO_SPKOUTR_MASK           0x0004  /* IN2LRP_TO_SPKOUTR */
1443  #define WM8994_IN2LRP_TO_SPKOUTR_SHIFT               2  /* IN2LRP_TO_SPKOUTR */
1444  #define WM8994_IN2LRP_TO_SPKOUTR_WIDTH               1  /* IN2LRP_TO_SPKOUTR */
1445  #define WM8994_SPKMIXL_TO_SPKOUTR               0x0002  /* SPKMIXL_TO_SPKOUTR */
1446  #define WM8994_SPKMIXL_TO_SPKOUTR_MASK          0x0002  /* SPKMIXL_TO_SPKOUTR */
1447  #define WM8994_SPKMIXL_TO_SPKOUTR_SHIFT              1  /* SPKMIXL_TO_SPKOUTR */
1448  #define WM8994_SPKMIXL_TO_SPKOUTR_WIDTH              1  /* SPKMIXL_TO_SPKOUTR */
1449  #define WM8994_SPKMIXR_TO_SPKOUTR               0x0001  /* SPKMIXR_TO_SPKOUTR */
1450  #define WM8994_SPKMIXR_TO_SPKOUTR_MASK          0x0001  /* SPKMIXR_TO_SPKOUTR */
1451  #define WM8994_SPKMIXR_TO_SPKOUTR_SHIFT              0  /* SPKMIXR_TO_SPKOUTR */
1452  #define WM8994_SPKMIXR_TO_SPKOUTR_WIDTH              1  /* SPKMIXR_TO_SPKOUTR */
1453  
1454  /*
1455   * R37 (0x25) - ClassD
1456   */
1457  #define WM8994_SPKOUTL_BOOST_MASK               0x0038  /* SPKOUTL_BOOST - [5:3] */
1458  #define WM8994_SPKOUTL_BOOST_SHIFT                   3  /* SPKOUTL_BOOST - [5:3] */
1459  #define WM8994_SPKOUTL_BOOST_WIDTH                   3  /* SPKOUTL_BOOST - [5:3] */
1460  #define WM8994_SPKOUTR_BOOST_MASK               0x0007  /* SPKOUTR_BOOST - [2:0] */
1461  #define WM8994_SPKOUTR_BOOST_SHIFT                   0  /* SPKOUTR_BOOST - [2:0] */
1462  #define WM8994_SPKOUTR_BOOST_WIDTH                   3  /* SPKOUTR_BOOST - [2:0] */
1463  
1464  /*
1465   * R38 (0x26) - Speaker Volume Left
1466   */
1467  #define WM8994_SPKOUT_VU                        0x0100  /* SPKOUT_VU */
1468  #define WM8994_SPKOUT_VU_MASK                   0x0100  /* SPKOUT_VU */
1469  #define WM8994_SPKOUT_VU_SHIFT                       8  /* SPKOUT_VU */
1470  #define WM8994_SPKOUT_VU_WIDTH                       1  /* SPKOUT_VU */
1471  #define WM8994_SPKOUTL_ZC                       0x0080  /* SPKOUTL_ZC */
1472  #define WM8994_SPKOUTL_ZC_MASK                  0x0080  /* SPKOUTL_ZC */
1473  #define WM8994_SPKOUTL_ZC_SHIFT                      7  /* SPKOUTL_ZC */
1474  #define WM8994_SPKOUTL_ZC_WIDTH                      1  /* SPKOUTL_ZC */
1475  #define WM8994_SPKOUTL_MUTE_N                   0x0040  /* SPKOUTL_MUTE_N */
1476  #define WM8994_SPKOUTL_MUTE_N_MASK              0x0040  /* SPKOUTL_MUTE_N */
1477  #define WM8994_SPKOUTL_MUTE_N_SHIFT                  6  /* SPKOUTL_MUTE_N */
1478  #define WM8994_SPKOUTL_MUTE_N_WIDTH                  1  /* SPKOUTL_MUTE_N */
1479  #define WM8994_SPKOUTL_VOL_MASK                 0x003F  /* SPKOUTL_VOL - [5:0] */
1480  #define WM8994_SPKOUTL_VOL_SHIFT                     0  /* SPKOUTL_VOL - [5:0] */
1481  #define WM8994_SPKOUTL_VOL_WIDTH                     6  /* SPKOUTL_VOL - [5:0] */
1482  
1483  /*
1484   * R39 (0x27) - Speaker Volume Right
1485   */
1486  #define WM8994_SPKOUT_VU                        0x0100  /* SPKOUT_VU */
1487  #define WM8994_SPKOUT_VU_MASK                   0x0100  /* SPKOUT_VU */
1488  #define WM8994_SPKOUT_VU_SHIFT                       8  /* SPKOUT_VU */
1489  #define WM8994_SPKOUT_VU_WIDTH                       1  /* SPKOUT_VU */
1490  #define WM8994_SPKOUTR_ZC                       0x0080  /* SPKOUTR_ZC */
1491  #define WM8994_SPKOUTR_ZC_MASK                  0x0080  /* SPKOUTR_ZC */
1492  #define WM8994_SPKOUTR_ZC_SHIFT                      7  /* SPKOUTR_ZC */
1493  #define WM8994_SPKOUTR_ZC_WIDTH                      1  /* SPKOUTR_ZC */
1494  #define WM8994_SPKOUTR_MUTE_N                   0x0040  /* SPKOUTR_MUTE_N */
1495  #define WM8994_SPKOUTR_MUTE_N_MASK              0x0040  /* SPKOUTR_MUTE_N */
1496  #define WM8994_SPKOUTR_MUTE_N_SHIFT                  6  /* SPKOUTR_MUTE_N */
1497  #define WM8994_SPKOUTR_MUTE_N_WIDTH                  1  /* SPKOUTR_MUTE_N */
1498  #define WM8994_SPKOUTR_VOL_MASK                 0x003F  /* SPKOUTR_VOL - [5:0] */
1499  #define WM8994_SPKOUTR_VOL_SHIFT                     0  /* SPKOUTR_VOL - [5:0] */
1500  #define WM8994_SPKOUTR_VOL_WIDTH                     6  /* SPKOUTR_VOL - [5:0] */
1501  
1502  /*
1503   * R40 (0x28) - Input Mixer (2)
1504   */
1505  #define WM8994_IN2LP_TO_IN2L                    0x0080  /* IN2LP_TO_IN2L */
1506  #define WM8994_IN2LP_TO_IN2L_MASK               0x0080  /* IN2LP_TO_IN2L */
1507  #define WM8994_IN2LP_TO_IN2L_SHIFT                   7  /* IN2LP_TO_IN2L */
1508  #define WM8994_IN2LP_TO_IN2L_WIDTH                   1  /* IN2LP_TO_IN2L */
1509  #define WM8994_IN2LN_TO_IN2L                    0x0040  /* IN2LN_TO_IN2L */
1510  #define WM8994_IN2LN_TO_IN2L_MASK               0x0040  /* IN2LN_TO_IN2L */
1511  #define WM8994_IN2LN_TO_IN2L_SHIFT                   6  /* IN2LN_TO_IN2L */
1512  #define WM8994_IN2LN_TO_IN2L_WIDTH                   1  /* IN2LN_TO_IN2L */
1513  #define WM8994_IN1LP_TO_IN1L                    0x0020  /* IN1LP_TO_IN1L */
1514  #define WM8994_IN1LP_TO_IN1L_MASK               0x0020  /* IN1LP_TO_IN1L */
1515  #define WM8994_IN1LP_TO_IN1L_SHIFT                   5  /* IN1LP_TO_IN1L */
1516  #define WM8994_IN1LP_TO_IN1L_WIDTH                   1  /* IN1LP_TO_IN1L */
1517  #define WM8994_IN1LN_TO_IN1L                    0x0010  /* IN1LN_TO_IN1L */
1518  #define WM8994_IN1LN_TO_IN1L_MASK               0x0010  /* IN1LN_TO_IN1L */
1519  #define WM8994_IN1LN_TO_IN1L_SHIFT                   4  /* IN1LN_TO_IN1L */
1520  #define WM8994_IN1LN_TO_IN1L_WIDTH                   1  /* IN1LN_TO_IN1L */
1521  #define WM8994_IN2RP_TO_IN2R                    0x0008  /* IN2RP_TO_IN2R */
1522  #define WM8994_IN2RP_TO_IN2R_MASK               0x0008  /* IN2RP_TO_IN2R */
1523  #define WM8994_IN2RP_TO_IN2R_SHIFT                   3  /* IN2RP_TO_IN2R */
1524  #define WM8994_IN2RP_TO_IN2R_WIDTH                   1  /* IN2RP_TO_IN2R */
1525  #define WM8994_IN2RN_TO_IN2R                    0x0004  /* IN2RN_TO_IN2R */
1526  #define WM8994_IN2RN_TO_IN2R_MASK               0x0004  /* IN2RN_TO_IN2R */
1527  #define WM8994_IN2RN_TO_IN2R_SHIFT                   2  /* IN2RN_TO_IN2R */
1528  #define WM8994_IN2RN_TO_IN2R_WIDTH                   1  /* IN2RN_TO_IN2R */
1529  #define WM8994_IN1RP_TO_IN1R                    0x0002  /* IN1RP_TO_IN1R */
1530  #define WM8994_IN1RP_TO_IN1R_MASK               0x0002  /* IN1RP_TO_IN1R */
1531  #define WM8994_IN1RP_TO_IN1R_SHIFT                   1  /* IN1RP_TO_IN1R */
1532  #define WM8994_IN1RP_TO_IN1R_WIDTH                   1  /* IN1RP_TO_IN1R */
1533  #define WM8994_IN1RN_TO_IN1R                    0x0001  /* IN1RN_TO_IN1R */
1534  #define WM8994_IN1RN_TO_IN1R_MASK               0x0001  /* IN1RN_TO_IN1R */
1535  #define WM8994_IN1RN_TO_IN1R_SHIFT                   0  /* IN1RN_TO_IN1R */
1536  #define WM8994_IN1RN_TO_IN1R_WIDTH                   1  /* IN1RN_TO_IN1R */
1537  
1538  /*
1539   * R41 (0x29) - Input Mixer (3)
1540   */
1541  #define WM8994_IN2L_TO_MIXINL                   0x0100  /* IN2L_TO_MIXINL */
1542  #define WM8994_IN2L_TO_MIXINL_MASK              0x0100  /* IN2L_TO_MIXINL */
1543  #define WM8994_IN2L_TO_MIXINL_SHIFT                  8  /* IN2L_TO_MIXINL */
1544  #define WM8994_IN2L_TO_MIXINL_WIDTH                  1  /* IN2L_TO_MIXINL */
1545  #define WM8994_IN2L_MIXINL_VOL                  0x0080  /* IN2L_MIXINL_VOL */
1546  #define WM8994_IN2L_MIXINL_VOL_MASK             0x0080  /* IN2L_MIXINL_VOL */
1547  #define WM8994_IN2L_MIXINL_VOL_SHIFT                 7  /* IN2L_MIXINL_VOL */
1548  #define WM8994_IN2L_MIXINL_VOL_WIDTH                 1  /* IN2L_MIXINL_VOL */
1549  #define WM8994_IN1L_TO_MIXINL                   0x0020  /* IN1L_TO_MIXINL */
1550  #define WM8994_IN1L_TO_MIXINL_MASK              0x0020  /* IN1L_TO_MIXINL */
1551  #define WM8994_IN1L_TO_MIXINL_SHIFT                  5  /* IN1L_TO_MIXINL */
1552  #define WM8994_IN1L_TO_MIXINL_WIDTH                  1  /* IN1L_TO_MIXINL */
1553  #define WM8994_IN1L_MIXINL_VOL                  0x0010  /* IN1L_MIXINL_VOL */
1554  #define WM8994_IN1L_MIXINL_VOL_MASK             0x0010  /* IN1L_MIXINL_VOL */
1555  #define WM8994_IN1L_MIXINL_VOL_SHIFT                 4  /* IN1L_MIXINL_VOL */
1556  #define WM8994_IN1L_MIXINL_VOL_WIDTH                 1  /* IN1L_MIXINL_VOL */
1557  #define WM8994_MIXOUTL_MIXINL_VOL_MASK          0x0007  /* MIXOUTL_MIXINL_VOL - [2:0] */
1558  #define WM8994_MIXOUTL_MIXINL_VOL_SHIFT              0  /* MIXOUTL_MIXINL_VOL - [2:0] */
1559  #define WM8994_MIXOUTL_MIXINL_VOL_WIDTH              3  /* MIXOUTL_MIXINL_VOL - [2:0] */
1560  
1561  /*
1562   * R42 (0x2A) - Input Mixer (4)
1563   */
1564  #define WM8994_IN2R_TO_MIXINR                   0x0100  /* IN2R_TO_MIXINR */
1565  #define WM8994_IN2R_TO_MIXINR_MASK              0x0100  /* IN2R_TO_MIXINR */
1566  #define WM8994_IN2R_TO_MIXINR_SHIFT                  8  /* IN2R_TO_MIXINR */
1567  #define WM8994_IN2R_TO_MIXINR_WIDTH                  1  /* IN2R_TO_MIXINR */
1568  #define WM8994_IN2R_MIXINR_VOL                  0x0080  /* IN2R_MIXINR_VOL */
1569  #define WM8994_IN2R_MIXINR_VOL_MASK             0x0080  /* IN2R_MIXINR_VOL */
1570  #define WM8994_IN2R_MIXINR_VOL_SHIFT                 7  /* IN2R_MIXINR_VOL */
1571  #define WM8994_IN2R_MIXINR_VOL_WIDTH                 1  /* IN2R_MIXINR_VOL */
1572  #define WM8994_IN1R_TO_MIXINR                   0x0020  /* IN1R_TO_MIXINR */
1573  #define WM8994_IN1R_TO_MIXINR_MASK              0x0020  /* IN1R_TO_MIXINR */
1574  #define WM8994_IN1R_TO_MIXINR_SHIFT                  5  /* IN1R_TO_MIXINR */
1575  #define WM8994_IN1R_TO_MIXINR_WIDTH                  1  /* IN1R_TO_MIXINR */
1576  #define WM8994_IN1R_MIXINR_VOL                  0x0010  /* IN1R_MIXINR_VOL */
1577  #define WM8994_IN1R_MIXINR_VOL_MASK             0x0010  /* IN1R_MIXINR_VOL */
1578  #define WM8994_IN1R_MIXINR_VOL_SHIFT                 4  /* IN1R_MIXINR_VOL */
1579  #define WM8994_IN1R_MIXINR_VOL_WIDTH                 1  /* IN1R_MIXINR_VOL */
1580  #define WM8994_MIXOUTR_MIXINR_VOL_MASK          0x0007  /* MIXOUTR_MIXINR_VOL - [2:0] */
1581  #define WM8994_MIXOUTR_MIXINR_VOL_SHIFT              0  /* MIXOUTR_MIXINR_VOL - [2:0] */
1582  #define WM8994_MIXOUTR_MIXINR_VOL_WIDTH              3  /* MIXOUTR_MIXINR_VOL - [2:0] */
1583  
1584  /*
1585   * R43 (0x2B) - Input Mixer (5)
1586   */
1587  #define WM8994_IN1LP_MIXINL_VOL_MASK            0x01C0  /* IN1LP_MIXINL_VOL - [8:6] */
1588  #define WM8994_IN1LP_MIXINL_VOL_SHIFT                6  /* IN1LP_MIXINL_VOL - [8:6] */
1589  #define WM8994_IN1LP_MIXINL_VOL_WIDTH                3  /* IN1LP_MIXINL_VOL - [8:6] */
1590  #define WM8994_IN2LRP_MIXINL_VOL_MASK           0x0007  /* IN2LRP_MIXINL_VOL - [2:0] */
1591  #define WM8994_IN2LRP_MIXINL_VOL_SHIFT               0  /* IN2LRP_MIXINL_VOL - [2:0] */
1592  #define WM8994_IN2LRP_MIXINL_VOL_WIDTH               3  /* IN2LRP_MIXINL_VOL - [2:0] */
1593  
1594  /*
1595   * R44 (0x2C) - Input Mixer (6)
1596   */
1597  #define WM8994_IN1RP_MIXINR_VOL_MASK            0x01C0  /* IN1RP_MIXINR_VOL - [8:6] */
1598  #define WM8994_IN1RP_MIXINR_VOL_SHIFT                6  /* IN1RP_MIXINR_VOL - [8:6] */
1599  #define WM8994_IN1RP_MIXINR_VOL_WIDTH                3  /* IN1RP_MIXINR_VOL - [8:6] */
1600  #define WM8994_IN2LRP_MIXINR_VOL_MASK           0x0007  /* IN2LRP_MIXINR_VOL - [2:0] */
1601  #define WM8994_IN2LRP_MIXINR_VOL_SHIFT               0  /* IN2LRP_MIXINR_VOL - [2:0] */
1602  #define WM8994_IN2LRP_MIXINR_VOL_WIDTH               3  /* IN2LRP_MIXINR_VOL - [2:0] */
1603  
1604  /*
1605   * R45 (0x2D) - Output Mixer (1)
1606   */
1607  #define WM8994_DAC1L_TO_HPOUT1L                 0x0100  /* DAC1L_TO_HPOUT1L */
1608  #define WM8994_DAC1L_TO_HPOUT1L_MASK            0x0100  /* DAC1L_TO_HPOUT1L */
1609  #define WM8994_DAC1L_TO_HPOUT1L_SHIFT                8  /* DAC1L_TO_HPOUT1L */
1610  #define WM8994_DAC1L_TO_HPOUT1L_WIDTH                1  /* DAC1L_TO_HPOUT1L */
1611  #define WM8994_MIXINR_TO_MIXOUTL                0x0080  /* MIXINR_TO_MIXOUTL */
1612  #define WM8994_MIXINR_TO_MIXOUTL_MASK           0x0080  /* MIXINR_TO_MIXOUTL */
1613  #define WM8994_MIXINR_TO_MIXOUTL_SHIFT               7  /* MIXINR_TO_MIXOUTL */
1614  #define WM8994_MIXINR_TO_MIXOUTL_WIDTH               1  /* MIXINR_TO_MIXOUTL */
1615  #define WM8994_MIXINL_TO_MIXOUTL                0x0040  /* MIXINL_TO_MIXOUTL */
1616  #define WM8994_MIXINL_TO_MIXOUTL_MASK           0x0040  /* MIXINL_TO_MIXOUTL */
1617  #define WM8994_MIXINL_TO_MIXOUTL_SHIFT               6  /* MIXINL_TO_MIXOUTL */
1618  #define WM8994_MIXINL_TO_MIXOUTL_WIDTH               1  /* MIXINL_TO_MIXOUTL */
1619  #define WM8994_IN2RN_TO_MIXOUTL                 0x0020  /* IN2RN_TO_MIXOUTL */
1620  #define WM8994_IN2RN_TO_MIXOUTL_MASK            0x0020  /* IN2RN_TO_MIXOUTL */
1621  #define WM8994_IN2RN_TO_MIXOUTL_SHIFT                5  /* IN2RN_TO_MIXOUTL */
1622  #define WM8994_IN2RN_TO_MIXOUTL_WIDTH                1  /* IN2RN_TO_MIXOUTL */
1623  #define WM8994_IN2LN_TO_MIXOUTL                 0x0010  /* IN2LN_TO_MIXOUTL */
1624  #define WM8994_IN2LN_TO_MIXOUTL_MASK            0x0010  /* IN2LN_TO_MIXOUTL */
1625  #define WM8994_IN2LN_TO_MIXOUTL_SHIFT                4  /* IN2LN_TO_MIXOUTL */
1626  #define WM8994_IN2LN_TO_MIXOUTL_WIDTH                1  /* IN2LN_TO_MIXOUTL */
1627  #define WM8994_IN1R_TO_MIXOUTL                  0x0008  /* IN1R_TO_MIXOUTL */
1628  #define WM8994_IN1R_TO_MIXOUTL_MASK             0x0008  /* IN1R_TO_MIXOUTL */
1629  #define WM8994_IN1R_TO_MIXOUTL_SHIFT                 3  /* IN1R_TO_MIXOUTL */
1630  #define WM8994_IN1R_TO_MIXOUTL_WIDTH                 1  /* IN1R_TO_MIXOUTL */
1631  #define WM8994_IN1L_TO_MIXOUTL                  0x0004  /* IN1L_TO_MIXOUTL */
1632  #define WM8994_IN1L_TO_MIXOUTL_MASK             0x0004  /* IN1L_TO_MIXOUTL */
1633  #define WM8994_IN1L_TO_MIXOUTL_SHIFT                 2  /* IN1L_TO_MIXOUTL */
1634  #define WM8994_IN1L_TO_MIXOUTL_WIDTH                 1  /* IN1L_TO_MIXOUTL */
1635  #define WM8994_IN2LP_TO_MIXOUTL                 0x0002  /* IN2LP_TO_MIXOUTL */
1636  #define WM8994_IN2LP_TO_MIXOUTL_MASK            0x0002  /* IN2LP_TO_MIXOUTL */
1637  #define WM8994_IN2LP_TO_MIXOUTL_SHIFT                1  /* IN2LP_TO_MIXOUTL */
1638  #define WM8994_IN2LP_TO_MIXOUTL_WIDTH                1  /* IN2LP_TO_MIXOUTL */
1639  #define WM8994_DAC1L_TO_MIXOUTL                 0x0001  /* DAC1L_TO_MIXOUTL */
1640  #define WM8994_DAC1L_TO_MIXOUTL_MASK            0x0001  /* DAC1L_TO_MIXOUTL */
1641  #define WM8994_DAC1L_TO_MIXOUTL_SHIFT                0  /* DAC1L_TO_MIXOUTL */
1642  #define WM8994_DAC1L_TO_MIXOUTL_WIDTH                1  /* DAC1L_TO_MIXOUTL */
1643  
1644  /*
1645   * R46 (0x2E) - Output Mixer (2)
1646   */
1647  #define WM8994_DAC1R_TO_HPOUT1R                 0x0100  /* DAC1R_TO_HPOUT1R */
1648  #define WM8994_DAC1R_TO_HPOUT1R_MASK            0x0100  /* DAC1R_TO_HPOUT1R */
1649  #define WM8994_DAC1R_TO_HPOUT1R_SHIFT                8  /* DAC1R_TO_HPOUT1R */
1650  #define WM8994_DAC1R_TO_HPOUT1R_WIDTH                1  /* DAC1R_TO_HPOUT1R */
1651  #define WM8994_MIXINL_TO_MIXOUTR                0x0080  /* MIXINL_TO_MIXOUTR */
1652  #define WM8994_MIXINL_TO_MIXOUTR_MASK           0x0080  /* MIXINL_TO_MIXOUTR */
1653  #define WM8994_MIXINL_TO_MIXOUTR_SHIFT               7  /* MIXINL_TO_MIXOUTR */
1654  #define WM8994_MIXINL_TO_MIXOUTR_WIDTH               1  /* MIXINL_TO_MIXOUTR */
1655  #define WM8994_MIXINR_TO_MIXOUTR                0x0040  /* MIXINR_TO_MIXOUTR */
1656  #define WM8994_MIXINR_TO_MIXOUTR_MASK           0x0040  /* MIXINR_TO_MIXOUTR */
1657  #define WM8994_MIXINR_TO_MIXOUTR_SHIFT               6  /* MIXINR_TO_MIXOUTR */
1658  #define WM8994_MIXINR_TO_MIXOUTR_WIDTH               1  /* MIXINR_TO_MIXOUTR */
1659  #define WM8994_IN2LN_TO_MIXOUTR                 0x0020  /* IN2LN_TO_MIXOUTR */
1660  #define WM8994_IN2LN_TO_MIXOUTR_MASK            0x0020  /* IN2LN_TO_MIXOUTR */
1661  #define WM8994_IN2LN_TO_MIXOUTR_SHIFT                5  /* IN2LN_TO_MIXOUTR */
1662  #define WM8994_IN2LN_TO_MIXOUTR_WIDTH                1  /* IN2LN_TO_MIXOUTR */
1663  #define WM8994_IN2RN_TO_MIXOUTR                 0x0010  /* IN2RN_TO_MIXOUTR */
1664  #define WM8994_IN2RN_TO_MIXOUTR_MASK            0x0010  /* IN2RN_TO_MIXOUTR */
1665  #define WM8994_IN2RN_TO_MIXOUTR_SHIFT                4  /* IN2RN_TO_MIXOUTR */
1666  #define WM8994_IN2RN_TO_MIXOUTR_WIDTH                1  /* IN2RN_TO_MIXOUTR */
1667  #define WM8994_IN1L_TO_MIXOUTR                  0x0008  /* IN1L_TO_MIXOUTR */
1668  #define WM8994_IN1L_TO_MIXOUTR_MASK             0x0008  /* IN1L_TO_MIXOUTR */
1669  #define WM8994_IN1L_TO_MIXOUTR_SHIFT                 3  /* IN1L_TO_MIXOUTR */
1670  #define WM8994_IN1L_TO_MIXOUTR_WIDTH                 1  /* IN1L_TO_MIXOUTR */
1671  #define WM8994_IN1R_TO_MIXOUTR                  0x0004  /* IN1R_TO_MIXOUTR */
1672  #define WM8994_IN1R_TO_MIXOUTR_MASK             0x0004  /* IN1R_TO_MIXOUTR */
1673  #define WM8994_IN1R_TO_MIXOUTR_SHIFT                 2  /* IN1R_TO_MIXOUTR */
1674  #define WM8994_IN1R_TO_MIXOUTR_WIDTH                 1  /* IN1R_TO_MIXOUTR */
1675  #define WM8994_IN2RP_TO_MIXOUTR                 0x0002  /* IN2RP_TO_MIXOUTR */
1676  #define WM8994_IN2RP_TO_MIXOUTR_MASK            0x0002  /* IN2RP_TO_MIXOUTR */
1677  #define WM8994_IN2RP_TO_MIXOUTR_SHIFT                1  /* IN2RP_TO_MIXOUTR */
1678  #define WM8994_IN2RP_TO_MIXOUTR_WIDTH                1  /* IN2RP_TO_MIXOUTR */
1679  #define WM8994_DAC1R_TO_MIXOUTR                 0x0001  /* DAC1R_TO_MIXOUTR */
1680  #define WM8994_DAC1R_TO_MIXOUTR_MASK            0x0001  /* DAC1R_TO_MIXOUTR */
1681  #define WM8994_DAC1R_TO_MIXOUTR_SHIFT                0  /* DAC1R_TO_MIXOUTR */
1682  #define WM8994_DAC1R_TO_MIXOUTR_WIDTH                1  /* DAC1R_TO_MIXOUTR */
1683  
1684  /*
1685   * R47 (0x2F) - Output Mixer (3)
1686   */
1687  #define WM8994_IN2LP_MIXOUTL_VOL_MASK           0x0E00  /* IN2LP_MIXOUTL_VOL - [11:9] */
1688  #define WM8994_IN2LP_MIXOUTL_VOL_SHIFT               9  /* IN2LP_MIXOUTL_VOL - [11:9] */
1689  #define WM8994_IN2LP_MIXOUTL_VOL_WIDTH               3  /* IN2LP_MIXOUTL_VOL - [11:9] */
1690  #define WM8994_IN2LN_MIXOUTL_VOL_MASK           0x01C0  /* IN2LN_MIXOUTL_VOL - [8:6] */
1691  #define WM8994_IN2LN_MIXOUTL_VOL_SHIFT               6  /* IN2LN_MIXOUTL_VOL - [8:6] */
1692  #define WM8994_IN2LN_MIXOUTL_VOL_WIDTH               3  /* IN2LN_MIXOUTL_VOL - [8:6] */
1693  #define WM8994_IN1R_MIXOUTL_VOL_MASK            0x0038  /* IN1R_MIXOUTL_VOL - [5:3] */
1694  #define WM8994_IN1R_MIXOUTL_VOL_SHIFT                3  /* IN1R_MIXOUTL_VOL - [5:3] */
1695  #define WM8994_IN1R_MIXOUTL_VOL_WIDTH                3  /* IN1R_MIXOUTL_VOL - [5:3] */
1696  #define WM8994_IN1L_MIXOUTL_VOL_MASK            0x0007  /* IN1L_MIXOUTL_VOL - [2:0] */
1697  #define WM8994_IN1L_MIXOUTL_VOL_SHIFT                0  /* IN1L_MIXOUTL_VOL - [2:0] */
1698  #define WM8994_IN1L_MIXOUTL_VOL_WIDTH                3  /* IN1L_MIXOUTL_VOL - [2:0] */
1699  
1700  /*
1701   * R48 (0x30) - Output Mixer (4)
1702   */
1703  #define WM8994_IN2RP_MIXOUTR_VOL_MASK           0x0E00  /* IN2RP_MIXOUTR_VOL - [11:9] */
1704  #define WM8994_IN2RP_MIXOUTR_VOL_SHIFT               9  /* IN2RP_MIXOUTR_VOL - [11:9] */
1705  #define WM8994_IN2RP_MIXOUTR_VOL_WIDTH               3  /* IN2RP_MIXOUTR_VOL - [11:9] */
1706  #define WM8994_IN2RN_MIXOUTR_VOL_MASK           0x01C0  /* IN2RN_MIXOUTR_VOL - [8:6] */
1707  #define WM8994_IN2RN_MIXOUTR_VOL_SHIFT               6  /* IN2RN_MIXOUTR_VOL - [8:6] */
1708  #define WM8994_IN2RN_MIXOUTR_VOL_WIDTH               3  /* IN2RN_MIXOUTR_VOL - [8:6] */
1709  #define WM8994_IN1L_MIXOUTR_VOL_MASK            0x0038  /* IN1L_MIXOUTR_VOL - [5:3] */
1710  #define WM8994_IN1L_MIXOUTR_VOL_SHIFT                3  /* IN1L_MIXOUTR_VOL - [5:3] */
1711  #define WM8994_IN1L_MIXOUTR_VOL_WIDTH                3  /* IN1L_MIXOUTR_VOL - [5:3] */
1712  #define WM8994_IN1R_MIXOUTR_VOL_MASK            0x0007  /* IN1R_MIXOUTR_VOL - [2:0] */
1713  #define WM8994_IN1R_MIXOUTR_VOL_SHIFT                0  /* IN1R_MIXOUTR_VOL - [2:0] */
1714  #define WM8994_IN1R_MIXOUTR_VOL_WIDTH                3  /* IN1R_MIXOUTR_VOL - [2:0] */
1715  
1716  /*
1717   * R49 (0x31) - Output Mixer (5)
1718   */
1719  #define WM8994_DAC1L_MIXOUTL_VOL_MASK           0x0E00  /* DAC1L_MIXOUTL_VOL - [11:9] */
1720  #define WM8994_DAC1L_MIXOUTL_VOL_SHIFT               9  /* DAC1L_MIXOUTL_VOL - [11:9] */
1721  #define WM8994_DAC1L_MIXOUTL_VOL_WIDTH               3  /* DAC1L_MIXOUTL_VOL - [11:9] */
1722  #define WM8994_IN2RN_MIXOUTL_VOL_MASK           0x01C0  /* IN2RN_MIXOUTL_VOL - [8:6] */
1723  #define WM8994_IN2RN_MIXOUTL_VOL_SHIFT               6  /* IN2RN_MIXOUTL_VOL - [8:6] */
1724  #define WM8994_IN2RN_MIXOUTL_VOL_WIDTH               3  /* IN2RN_MIXOUTL_VOL - [8:6] */
1725  #define WM8994_MIXINR_MIXOUTL_VOL_MASK          0x0038  /* MIXINR_MIXOUTL_VOL - [5:3] */
1726  #define WM8994_MIXINR_MIXOUTL_VOL_SHIFT              3  /* MIXINR_MIXOUTL_VOL - [5:3] */
1727  #define WM8994_MIXINR_MIXOUTL_VOL_WIDTH              3  /* MIXINR_MIXOUTL_VOL - [5:3] */
1728  #define WM8994_MIXINL_MIXOUTL_VOL_MASK          0x0007  /* MIXINL_MIXOUTL_VOL - [2:0] */
1729  #define WM8994_MIXINL_MIXOUTL_VOL_SHIFT              0  /* MIXINL_MIXOUTL_VOL - [2:0] */
1730  #define WM8994_MIXINL_MIXOUTL_VOL_WIDTH              3  /* MIXINL_MIXOUTL_VOL - [2:0] */
1731  
1732  /*
1733   * R50 (0x32) - Output Mixer (6)
1734   */
1735  #define WM8994_DAC1R_MIXOUTR_VOL_MASK           0x0E00  /* DAC1R_MIXOUTR_VOL - [11:9] */
1736  #define WM8994_DAC1R_MIXOUTR_VOL_SHIFT               9  /* DAC1R_MIXOUTR_VOL - [11:9] */
1737  #define WM8994_DAC1R_MIXOUTR_VOL_WIDTH               3  /* DAC1R_MIXOUTR_VOL - [11:9] */
1738  #define WM8994_IN2LN_MIXOUTR_VOL_MASK           0x01C0  /* IN2LN_MIXOUTR_VOL - [8:6] */
1739  #define WM8994_IN2LN_MIXOUTR_VOL_SHIFT               6  /* IN2LN_MIXOUTR_VOL - [8:6] */
1740  #define WM8994_IN2LN_MIXOUTR_VOL_WIDTH               3  /* IN2LN_MIXOUTR_VOL - [8:6] */
1741  #define WM8994_MIXINL_MIXOUTR_VOL_MASK          0x0038  /* MIXINL_MIXOUTR_VOL - [5:3] */
1742  #define WM8994_MIXINL_MIXOUTR_VOL_SHIFT              3  /* MIXINL_MIXOUTR_VOL - [5:3] */
1743  #define WM8994_MIXINL_MIXOUTR_VOL_WIDTH              3  /* MIXINL_MIXOUTR_VOL - [5:3] */
1744  #define WM8994_MIXINR_MIXOUTR_VOL_MASK          0x0007  /* MIXINR_MIXOUTR_VOL - [2:0] */
1745  #define WM8994_MIXINR_MIXOUTR_VOL_SHIFT              0  /* MIXINR_MIXOUTR_VOL - [2:0] */
1746  #define WM8994_MIXINR_MIXOUTR_VOL_WIDTH              3  /* MIXINR_MIXOUTR_VOL - [2:0] */
1747  
1748  /*
1749   * R51 (0x33) - HPOUT2 Mixer
1750   */
1751  #define WM8994_IN2LRP_TO_HPOUT2                 0x0020  /* IN2LRP_TO_HPOUT2 */
1752  #define WM8994_IN2LRP_TO_HPOUT2_MASK            0x0020  /* IN2LRP_TO_HPOUT2 */
1753  #define WM8994_IN2LRP_TO_HPOUT2_SHIFT                5  /* IN2LRP_TO_HPOUT2 */
1754  #define WM8994_IN2LRP_TO_HPOUT2_WIDTH                1  /* IN2LRP_TO_HPOUT2 */
1755  #define WM8994_MIXOUTLVOL_TO_HPOUT2             0x0010  /* MIXOUTLVOL_TO_HPOUT2 */
1756  #define WM8994_MIXOUTLVOL_TO_HPOUT2_MASK        0x0010  /* MIXOUTLVOL_TO_HPOUT2 */
1757  #define WM8994_MIXOUTLVOL_TO_HPOUT2_SHIFT            4  /* MIXOUTLVOL_TO_HPOUT2 */
1758  #define WM8994_MIXOUTLVOL_TO_HPOUT2_WIDTH            1  /* MIXOUTLVOL_TO_HPOUT2 */
1759  #define WM8994_MIXOUTRVOL_TO_HPOUT2             0x0008  /* MIXOUTRVOL_TO_HPOUT2 */
1760  #define WM8994_MIXOUTRVOL_TO_HPOUT2_MASK        0x0008  /* MIXOUTRVOL_TO_HPOUT2 */
1761  #define WM8994_MIXOUTRVOL_TO_HPOUT2_SHIFT            3  /* MIXOUTRVOL_TO_HPOUT2 */
1762  #define WM8994_MIXOUTRVOL_TO_HPOUT2_WIDTH            1  /* MIXOUTRVOL_TO_HPOUT2 */
1763  
1764  /*
1765   * R52 (0x34) - Line Mixer (1)
1766   */
1767  #define WM8994_MIXOUTL_TO_LINEOUT1N             0x0040  /* MIXOUTL_TO_LINEOUT1N */
1768  #define WM8994_MIXOUTL_TO_LINEOUT1N_MASK        0x0040  /* MIXOUTL_TO_LINEOUT1N */
1769  #define WM8994_MIXOUTL_TO_LINEOUT1N_SHIFT            6  /* MIXOUTL_TO_LINEOUT1N */
1770  #define WM8994_MIXOUTL_TO_LINEOUT1N_WIDTH            1  /* MIXOUTL_TO_LINEOUT1N */
1771  #define WM8994_MIXOUTR_TO_LINEOUT1N             0x0020  /* MIXOUTR_TO_LINEOUT1N */
1772  #define WM8994_MIXOUTR_TO_LINEOUT1N_MASK        0x0020  /* MIXOUTR_TO_LINEOUT1N */
1773  #define WM8994_MIXOUTR_TO_LINEOUT1N_SHIFT            5  /* MIXOUTR_TO_LINEOUT1N */
1774  #define WM8994_MIXOUTR_TO_LINEOUT1N_WIDTH            1  /* MIXOUTR_TO_LINEOUT1N */
1775  #define WM8994_LINEOUT1_MODE                    0x0010  /* LINEOUT1_MODE */
1776  #define WM8994_LINEOUT1_MODE_MASK               0x0010  /* LINEOUT1_MODE */
1777  #define WM8994_LINEOUT1_MODE_SHIFT                   4  /* LINEOUT1_MODE */
1778  #define WM8994_LINEOUT1_MODE_WIDTH                   1  /* LINEOUT1_MODE */
1779  #define WM8994_IN1R_TO_LINEOUT1P                0x0004  /* IN1R_TO_LINEOUT1P */
1780  #define WM8994_IN1R_TO_LINEOUT1P_MASK           0x0004  /* IN1R_TO_LINEOUT1P */
1781  #define WM8994_IN1R_TO_LINEOUT1P_SHIFT               2  /* IN1R_TO_LINEOUT1P */
1782  #define WM8994_IN1R_TO_LINEOUT1P_WIDTH               1  /* IN1R_TO_LINEOUT1P */
1783  #define WM8994_IN1L_TO_LINEOUT1P                0x0002  /* IN1L_TO_LINEOUT1P */
1784  #define WM8994_IN1L_TO_LINEOUT1P_MASK           0x0002  /* IN1L_TO_LINEOUT1P */
1785  #define WM8994_IN1L_TO_LINEOUT1P_SHIFT               1  /* IN1L_TO_LINEOUT1P */
1786  #define WM8994_IN1L_TO_LINEOUT1P_WIDTH               1  /* IN1L_TO_LINEOUT1P */
1787  #define WM8994_MIXOUTL_TO_LINEOUT1P             0x0001  /* MIXOUTL_TO_LINEOUT1P */
1788  #define WM8994_MIXOUTL_TO_LINEOUT1P_MASK        0x0001  /* MIXOUTL_TO_LINEOUT1P */
1789  #define WM8994_MIXOUTL_TO_LINEOUT1P_SHIFT            0  /* MIXOUTL_TO_LINEOUT1P */
1790  #define WM8994_MIXOUTL_TO_LINEOUT1P_WIDTH            1  /* MIXOUTL_TO_LINEOUT1P */
1791  
1792  /*
1793   * R53 (0x35) - Line Mixer (2)
1794   */
1795  #define WM8994_MIXOUTR_TO_LINEOUT2N             0x0040  /* MIXOUTR_TO_LINEOUT2N */
1796  #define WM8994_MIXOUTR_TO_LINEOUT2N_MASK        0x0040  /* MIXOUTR_TO_LINEOUT2N */
1797  #define WM8994_MIXOUTR_TO_LINEOUT2N_SHIFT            6  /* MIXOUTR_TO_LINEOUT2N */
1798  #define WM8994_MIXOUTR_TO_LINEOUT2N_WIDTH            1  /* MIXOUTR_TO_LINEOUT2N */
1799  #define WM8994_MIXOUTL_TO_LINEOUT2N             0x0020  /* MIXOUTL_TO_LINEOUT2N */
1800  #define WM8994_MIXOUTL_TO_LINEOUT2N_MASK        0x0020  /* MIXOUTL_TO_LINEOUT2N */
1801  #define WM8994_MIXOUTL_TO_LINEOUT2N_SHIFT            5  /* MIXOUTL_TO_LINEOUT2N */
1802  #define WM8994_MIXOUTL_TO_LINEOUT2N_WIDTH            1  /* MIXOUTL_TO_LINEOUT2N */
1803  #define WM8994_LINEOUT2_MODE                    0x0010  /* LINEOUT2_MODE */
1804  #define WM8994_LINEOUT2_MODE_MASK               0x0010  /* LINEOUT2_MODE */
1805  #define WM8994_LINEOUT2_MODE_SHIFT                   4  /* LINEOUT2_MODE */
1806  #define WM8994_LINEOUT2_MODE_WIDTH                   1  /* LINEOUT2_MODE */
1807  #define WM8994_IN1L_TO_LINEOUT2P                0x0004  /* IN1L_TO_LINEOUT2P */
1808  #define WM8994_IN1L_TO_LINEOUT2P_MASK           0x0004  /* IN1L_TO_LINEOUT2P */
1809  #define WM8994_IN1L_TO_LINEOUT2P_SHIFT               2  /* IN1L_TO_LINEOUT2P */
1810  #define WM8994_IN1L_TO_LINEOUT2P_WIDTH               1  /* IN1L_TO_LINEOUT2P */
1811  #define WM8994_IN1R_TO_LINEOUT2P                0x0002  /* IN1R_TO_LINEOUT2P */
1812  #define WM8994_IN1R_TO_LINEOUT2P_MASK           0x0002  /* IN1R_TO_LINEOUT2P */
1813  #define WM8994_IN1R_TO_LINEOUT2P_SHIFT               1  /* IN1R_TO_LINEOUT2P */
1814  #define WM8994_IN1R_TO_LINEOUT2P_WIDTH               1  /* IN1R_TO_LINEOUT2P */
1815  #define WM8994_MIXOUTR_TO_LINEOUT2P             0x0001  /* MIXOUTR_TO_LINEOUT2P */
1816  #define WM8994_MIXOUTR_TO_LINEOUT2P_MASK        0x0001  /* MIXOUTR_TO_LINEOUT2P */
1817  #define WM8994_MIXOUTR_TO_LINEOUT2P_SHIFT            0  /* MIXOUTR_TO_LINEOUT2P */
1818  #define WM8994_MIXOUTR_TO_LINEOUT2P_WIDTH            1  /* MIXOUTR_TO_LINEOUT2P */
1819  
1820  /*
1821   * R54 (0x36) - Speaker Mixer
1822   */
1823  #define WM8994_DAC2L_TO_SPKMIXL                 0x0200  /* DAC2L_TO_SPKMIXL */
1824  #define WM8994_DAC2L_TO_SPKMIXL_MASK            0x0200  /* DAC2L_TO_SPKMIXL */
1825  #define WM8994_DAC2L_TO_SPKMIXL_SHIFT                9  /* DAC2L_TO_SPKMIXL */
1826  #define WM8994_DAC2L_TO_SPKMIXL_WIDTH                1  /* DAC2L_TO_SPKMIXL */
1827  #define WM8994_DAC2R_TO_SPKMIXR                 0x0100  /* DAC2R_TO_SPKMIXR */
1828  #define WM8994_DAC2R_TO_SPKMIXR_MASK            0x0100  /* DAC2R_TO_SPKMIXR */
1829  #define WM8994_DAC2R_TO_SPKMIXR_SHIFT                8  /* DAC2R_TO_SPKMIXR */
1830  #define WM8994_DAC2R_TO_SPKMIXR_WIDTH                1  /* DAC2R_TO_SPKMIXR */
1831  #define WM8994_MIXINL_TO_SPKMIXL                0x0080  /* MIXINL_TO_SPKMIXL */
1832  #define WM8994_MIXINL_TO_SPKMIXL_MASK           0x0080  /* MIXINL_TO_SPKMIXL */
1833  #define WM8994_MIXINL_TO_SPKMIXL_SHIFT               7  /* MIXINL_TO_SPKMIXL */
1834  #define WM8994_MIXINL_TO_SPKMIXL_WIDTH               1  /* MIXINL_TO_SPKMIXL */
1835  #define WM8994_MIXINR_TO_SPKMIXR                0x0040  /* MIXINR_TO_SPKMIXR */
1836  #define WM8994_MIXINR_TO_SPKMIXR_MASK           0x0040  /* MIXINR_TO_SPKMIXR */
1837  #define WM8994_MIXINR_TO_SPKMIXR_SHIFT               6  /* MIXINR_TO_SPKMIXR */
1838  #define WM8994_MIXINR_TO_SPKMIXR_WIDTH               1  /* MIXINR_TO_SPKMIXR */
1839  #define WM8994_IN1LP_TO_SPKMIXL                 0x0020  /* IN1LP_TO_SPKMIXL */
1840  #define WM8994_IN1LP_TO_SPKMIXL_MASK            0x0020  /* IN1LP_TO_SPKMIXL */
1841  #define WM8994_IN1LP_TO_SPKMIXL_SHIFT                5  /* IN1LP_TO_SPKMIXL */
1842  #define WM8994_IN1LP_TO_SPKMIXL_WIDTH                1  /* IN1LP_TO_SPKMIXL */
1843  #define WM8994_IN1RP_TO_SPKMIXR                 0x0010  /* IN1RP_TO_SPKMIXR */
1844  #define WM8994_IN1RP_TO_SPKMIXR_MASK            0x0010  /* IN1RP_TO_SPKMIXR */
1845  #define WM8994_IN1RP_TO_SPKMIXR_SHIFT                4  /* IN1RP_TO_SPKMIXR */
1846  #define WM8994_IN1RP_TO_SPKMIXR_WIDTH                1  /* IN1RP_TO_SPKMIXR */
1847  #define WM8994_MIXOUTL_TO_SPKMIXL               0x0008  /* MIXOUTL_TO_SPKMIXL */
1848  #define WM8994_MIXOUTL_TO_SPKMIXL_MASK          0x0008  /* MIXOUTL_TO_SPKMIXL */
1849  #define WM8994_MIXOUTL_TO_SPKMIXL_SHIFT              3  /* MIXOUTL_TO_SPKMIXL */
1850  #define WM8994_MIXOUTL_TO_SPKMIXL_WIDTH              1  /* MIXOUTL_TO_SPKMIXL */
1851  #define WM8994_MIXOUTR_TO_SPKMIXR               0x0004  /* MIXOUTR_TO_SPKMIXR */
1852  #define WM8994_MIXOUTR_TO_SPKMIXR_MASK          0x0004  /* MIXOUTR_TO_SPKMIXR */
1853  #define WM8994_MIXOUTR_TO_SPKMIXR_SHIFT              2  /* MIXOUTR_TO_SPKMIXR */
1854  #define WM8994_MIXOUTR_TO_SPKMIXR_WIDTH              1  /* MIXOUTR_TO_SPKMIXR */
1855  #define WM8994_DAC1L_TO_SPKMIXL                 0x0002  /* DAC1L_TO_SPKMIXL */
1856  #define WM8994_DAC1L_TO_SPKMIXL_MASK            0x0002  /* DAC1L_TO_SPKMIXL */
1857  #define WM8994_DAC1L_TO_SPKMIXL_SHIFT                1  /* DAC1L_TO_SPKMIXL */
1858  #define WM8994_DAC1L_TO_SPKMIXL_WIDTH                1  /* DAC1L_TO_SPKMIXL */
1859  #define WM8994_DAC1R_TO_SPKMIXR                 0x0001  /* DAC1R_TO_SPKMIXR */
1860  #define WM8994_DAC1R_TO_SPKMIXR_MASK            0x0001  /* DAC1R_TO_SPKMIXR */
1861  #define WM8994_DAC1R_TO_SPKMIXR_SHIFT                0  /* DAC1R_TO_SPKMIXR */
1862  #define WM8994_DAC1R_TO_SPKMIXR_WIDTH                1  /* DAC1R_TO_SPKMIXR */
1863  
1864  /*
1865   * R55 (0x37) - Additional Control
1866   */
1867  #define WM8994_LINEOUT1_FB                      0x0080  /* LINEOUT1_FB */
1868  #define WM8994_LINEOUT1_FB_MASK                 0x0080  /* LINEOUT1_FB */
1869  #define WM8994_LINEOUT1_FB_SHIFT                     7  /* LINEOUT1_FB */
1870  #define WM8994_LINEOUT1_FB_WIDTH                     1  /* LINEOUT1_FB */
1871  #define WM8994_LINEOUT2_FB                      0x0040  /* LINEOUT2_FB */
1872  #define WM8994_LINEOUT2_FB_MASK                 0x0040  /* LINEOUT2_FB */
1873  #define WM8994_LINEOUT2_FB_SHIFT                     6  /* LINEOUT2_FB */
1874  #define WM8994_LINEOUT2_FB_WIDTH                     1  /* LINEOUT2_FB */
1875  #define WM8994_VROI                             0x0001  /* VROI */
1876  #define WM8994_VROI_MASK                        0x0001  /* VROI */
1877  #define WM8994_VROI_SHIFT                            0  /* VROI */
1878  #define WM8994_VROI_WIDTH                            1  /* VROI */
1879  
1880  /*
1881   * R56 (0x38) - AntiPOP (1)
1882   */
1883  #define WM8994_LINEOUT_VMID_BUF_ENA             0x0080  /* LINEOUT_VMID_BUF_ENA */
1884  #define WM8994_LINEOUT_VMID_BUF_ENA_MASK        0x0080  /* LINEOUT_VMID_BUF_ENA */
1885  #define WM8994_LINEOUT_VMID_BUF_ENA_SHIFT            7  /* LINEOUT_VMID_BUF_ENA */
1886  #define WM8994_LINEOUT_VMID_BUF_ENA_WIDTH            1  /* LINEOUT_VMID_BUF_ENA */
1887  #define WM8994_HPOUT2_IN_ENA                    0x0040  /* HPOUT2_IN_ENA */
1888  #define WM8994_HPOUT2_IN_ENA_MASK               0x0040  /* HPOUT2_IN_ENA */
1889  #define WM8994_HPOUT2_IN_ENA_SHIFT                   6  /* HPOUT2_IN_ENA */
1890  #define WM8994_HPOUT2_IN_ENA_WIDTH                   1  /* HPOUT2_IN_ENA */
1891  #define WM8994_LINEOUT1_DISCH                   0x0020  /* LINEOUT1_DISCH */
1892  #define WM8994_LINEOUT1_DISCH_MASK              0x0020  /* LINEOUT1_DISCH */
1893  #define WM8994_LINEOUT1_DISCH_SHIFT                  5  /* LINEOUT1_DISCH */
1894  #define WM8994_LINEOUT1_DISCH_WIDTH                  1  /* LINEOUT1_DISCH */
1895  #define WM8994_LINEOUT2_DISCH                   0x0010  /* LINEOUT2_DISCH */
1896  #define WM8994_LINEOUT2_DISCH_MASK              0x0010  /* LINEOUT2_DISCH */
1897  #define WM8994_LINEOUT2_DISCH_SHIFT                  4  /* LINEOUT2_DISCH */
1898  #define WM8994_LINEOUT2_DISCH_WIDTH                  1  /* LINEOUT2_DISCH */
1899  
1900  /*
1901   * R57 (0x39) - AntiPOP (2)
1902   */
1903  #define WM1811_JACKDET_MODE_MASK                0x0180  /* JACKDET_MODE - [8:7] */
1904  #define WM1811_JACKDET_MODE_SHIFT                    7  /* JACKDET_MODE - [8:7] */
1905  #define WM1811_JACKDET_MODE_WIDTH                    2  /* JACKDET_MODE - [8:7] */
1906  #define WM8994_MICB2_DISCH                      0x0100  /* MICB2_DISCH */
1907  #define WM8994_MICB2_DISCH_MASK                 0x0100  /* MICB2_DISCH */
1908  #define WM8994_MICB2_DISCH_SHIFT                     8  /* MICB2_DISCH */
1909  #define WM8994_MICB2_DISCH_WIDTH                     1  /* MICB2_DISCH */
1910  #define WM8994_MICB1_DISCH                      0x0080  /* MICB1_DISCH */
1911  #define WM8994_MICB1_DISCH_MASK                 0x0080  /* MICB1_DISCH */
1912  #define WM8994_MICB1_DISCH_SHIFT                     7  /* MICB1_DISCH */
1913  #define WM8994_MICB1_DISCH_WIDTH                     1  /* MICB1_DISCH */
1914  #define WM8994_VMID_RAMP_MASK                   0x0060  /* VMID_RAMP - [6:5] */
1915  #define WM8994_VMID_RAMP_SHIFT                       5  /* VMID_RAMP - [6:5] */
1916  #define WM8994_VMID_RAMP_WIDTH                       2  /* VMID_RAMP - [6:5] */
1917  #define WM8994_VMID_BUF_ENA                     0x0008  /* VMID_BUF_ENA */
1918  #define WM8994_VMID_BUF_ENA_MASK                0x0008  /* VMID_BUF_ENA */
1919  #define WM8994_VMID_BUF_ENA_SHIFT                    3  /* VMID_BUF_ENA */
1920  #define WM8994_VMID_BUF_ENA_WIDTH                    1  /* VMID_BUF_ENA */
1921  #define WM8994_STARTUP_BIAS_ENA                 0x0004  /* STARTUP_BIAS_ENA */
1922  #define WM8994_STARTUP_BIAS_ENA_MASK            0x0004  /* STARTUP_BIAS_ENA */
1923  #define WM8994_STARTUP_BIAS_ENA_SHIFT                2  /* STARTUP_BIAS_ENA */
1924  #define WM8994_STARTUP_BIAS_ENA_WIDTH                1  /* STARTUP_BIAS_ENA */
1925  #define WM8994_BIAS_SRC                         0x0002  /* BIAS_SRC */
1926  #define WM8994_BIAS_SRC_MASK                    0x0002  /* BIAS_SRC */
1927  #define WM8994_BIAS_SRC_SHIFT                        1  /* BIAS_SRC */
1928  #define WM8994_BIAS_SRC_WIDTH                        1  /* BIAS_SRC */
1929  #define WM8994_VMID_DISCH                       0x0001  /* VMID_DISCH */
1930  #define WM8994_VMID_DISCH_MASK                  0x0001  /* VMID_DISCH */
1931  #define WM8994_VMID_DISCH_SHIFT                      0  /* VMID_DISCH */
1932  #define WM8994_VMID_DISCH_WIDTH                      1  /* VMID_DISCH */
1933  
1934  /*
1935   * R58 (0x3A) - MICBIAS
1936   */
1937  #define WM8994_MICD_SCTHR_MASK                  0x00C0  /* MICD_SCTHR - [7:6] */
1938  #define WM8994_MICD_SCTHR_SHIFT                      6  /* MICD_SCTHR - [7:6] */
1939  #define WM8994_MICD_SCTHR_WIDTH                      2  /* MICD_SCTHR - [7:6] */
1940  #define WM8994_MICD_THR_MASK                    0x0038  /* MICD_THR - [5:3] */
1941  #define WM8994_MICD_THR_SHIFT                        3  /* MICD_THR - [5:3] */
1942  #define WM8994_MICD_THR_WIDTH                        3  /* MICD_THR - [5:3] */
1943  #define WM8994_MICD_ENA                         0x0004  /* MICD_ENA */
1944  #define WM8994_MICD_ENA_MASK                    0x0004  /* MICD_ENA */
1945  #define WM8994_MICD_ENA_SHIFT                        2  /* MICD_ENA */
1946  #define WM8994_MICD_ENA_WIDTH                        1  /* MICD_ENA */
1947  #define WM8994_MICB2_LVL                        0x0002  /* MICB2_LVL */
1948  #define WM8994_MICB2_LVL_MASK                   0x0002  /* MICB2_LVL */
1949  #define WM8994_MICB2_LVL_SHIFT                       1  /* MICB2_LVL */
1950  #define WM8994_MICB2_LVL_WIDTH                       1  /* MICB2_LVL */
1951  #define WM8994_MICB1_LVL                        0x0001  /* MICB1_LVL */
1952  #define WM8994_MICB1_LVL_MASK                   0x0001  /* MICB1_LVL */
1953  #define WM8994_MICB1_LVL_SHIFT                       0  /* MICB1_LVL */
1954  #define WM8994_MICB1_LVL_WIDTH                       1  /* MICB1_LVL */
1955  
1956  /*
1957   * R59 (0x3B) - LDO 1
1958   */
1959  #define WM8994_LDO1_VSEL_MASK                   0x000E  /* LDO1_VSEL - [3:1] */
1960  #define WM8994_LDO1_VSEL_SHIFT                       1  /* LDO1_VSEL - [3:1] */
1961  #define WM8994_LDO1_VSEL_WIDTH                       3  /* LDO1_VSEL - [3:1] */
1962  #define WM8994_LDO1_DISCH                       0x0001  /* LDO1_DISCH */
1963  #define WM8994_LDO1_DISCH_MASK                  0x0001  /* LDO1_DISCH */
1964  #define WM8994_LDO1_DISCH_SHIFT                      0  /* LDO1_DISCH */
1965  #define WM8994_LDO1_DISCH_WIDTH                      1  /* LDO1_DISCH */
1966  
1967  /*
1968   * R60 (0x3C) - LDO 2
1969   */
1970  #define WM8994_LDO2_VSEL_MASK                   0x0006  /* LDO2_VSEL - [2:1] */
1971  #define WM8994_LDO2_VSEL_SHIFT                       1  /* LDO2_VSEL - [2:1] */
1972  #define WM8994_LDO2_VSEL_WIDTH                       2  /* LDO2_VSEL - [2:1] */
1973  #define WM8994_LDO2_DISCH                       0x0001  /* LDO2_DISCH */
1974  #define WM8994_LDO2_DISCH_MASK                  0x0001  /* LDO2_DISCH */
1975  #define WM8994_LDO2_DISCH_SHIFT                      0  /* LDO2_DISCH */
1976  #define WM8994_LDO2_DISCH_WIDTH                      1  /* LDO2_DISCH */
1977  
1978  /*
1979   * R61 (0x3D) - MICBIAS1
1980   */
1981  #define WM8958_MICB1_RATE                       0x0020  /* MICB1_RATE */
1982  #define WM8958_MICB1_RATE_MASK                  0x0020  /* MICB1_RATE */
1983  #define WM8958_MICB1_RATE_SHIFT                      5  /* MICB1_RATE */
1984  #define WM8958_MICB1_RATE_WIDTH                      1  /* MICB1_RATE */
1985  #define WM8958_MICB1_MODE                       0x0010  /* MICB1_MODE */
1986  #define WM8958_MICB1_MODE_MASK                  0x0010  /* MICB1_MODE */
1987  #define WM8958_MICB1_MODE_SHIFT                      4  /* MICB1_MODE */
1988  #define WM8958_MICB1_MODE_WIDTH                      1  /* MICB1_MODE */
1989  #define WM8958_MICB1_LVL_MASK                   0x000E  /* MICB1_LVL - [3:1] */
1990  #define WM8958_MICB1_LVL_SHIFT                       1  /* MICB1_LVL - [3:1] */
1991  #define WM8958_MICB1_LVL_WIDTH                       3  /* MICB1_LVL - [3:1] */
1992  #define WM8958_MICB1_DISCH                      0x0001  /* MICB1_DISCH */
1993  #define WM8958_MICB1_DISCH_MASK                 0x0001  /* MICB1_DISCH */
1994  #define WM8958_MICB1_DISCH_SHIFT                     0  /* MICB1_DISCH */
1995  #define WM8958_MICB1_DISCH_WIDTH                     1  /* MICB1_DISCH */
1996  
1997  /*
1998   * R62 (0x3E) - MICBIAS2
1999   */
2000  #define WM8958_MICB2_RATE                       0x0020  /* MICB2_RATE */
2001  #define WM8958_MICB2_RATE_MASK                  0x0020  /* MICB2_RATE */
2002  #define WM8958_MICB2_RATE_SHIFT                      5  /* MICB2_RATE */
2003  #define WM8958_MICB2_RATE_WIDTH                      1  /* MICB2_RATE */
2004  #define WM8958_MICB2_MODE                       0x0010  /* MICB2_MODE */
2005  #define WM8958_MICB2_MODE_MASK                  0x0010  /* MICB2_MODE */
2006  #define WM8958_MICB2_MODE_SHIFT                      4  /* MICB2_MODE */
2007  #define WM8958_MICB2_MODE_WIDTH                      1  /* MICB2_MODE */
2008  #define WM8958_MICB2_LVL_MASK                   0x000E  /* MICB2_LVL - [3:1] */
2009  #define WM8958_MICB2_LVL_SHIFT                       1  /* MICB2_LVL - [3:1] */
2010  #define WM8958_MICB2_LVL_WIDTH                       3  /* MICB2_LVL - [3:1] */
2011  #define WM8958_MICB2_DISCH                      0x0001  /* MICB2_DISCH */
2012  #define WM8958_MICB2_DISCH_MASK                 0x0001  /* MICB2_DISCH */
2013  #define WM8958_MICB2_DISCH_SHIFT                     0  /* MICB2_DISCH */
2014  #define WM8958_MICB2_DISCH_WIDTH                     1  /* MICB2_DISCH */
2015  
2016  /*
2017   * R210 (0xD2) - Mic Detect 3
2018   */
2019  #define WM8958_MICD_LVL_MASK                    0x07FC  /* MICD_LVL - [10:2] */
2020  #define WM8958_MICD_LVL_SHIFT                        2  /* MICD_LVL - [10:2] */
2021  #define WM8958_MICD_LVL_WIDTH                        9  /* MICD_LVL - [10:2] */
2022  #define WM8958_MICD_VALID                       0x0002  /* MICD_VALID */
2023  #define WM8958_MICD_VALID_MASK                  0x0002  /* MICD_VALID */
2024  #define WM8958_MICD_VALID_SHIFT                      1  /* MICD_VALID */
2025  #define WM8958_MICD_VALID_WIDTH                      1  /* MICD_VALID */
2026  #define WM8958_MICD_STS                         0x0001  /* MICD_STS */
2027  #define WM8958_MICD_STS_MASK                    0x0001  /* MICD_STS */
2028  #define WM8958_MICD_STS_SHIFT                        0  /* MICD_STS */
2029  #define WM8958_MICD_STS_WIDTH                        1  /* MICD_STS */
2030  
2031  /*
2032   * R76 (0x4C) - Charge Pump (1)
2033   */
2034  #define WM8994_CP_ENA                           0x8000  /* CP_ENA */
2035  #define WM8994_CP_ENA_MASK                      0x8000  /* CP_ENA */
2036  #define WM8994_CP_ENA_SHIFT                         15  /* CP_ENA */
2037  #define WM8994_CP_ENA_WIDTH                          1  /* CP_ENA */
2038  
2039  /*
2040   * R77 (0x4D) - Charge Pump (2)
2041   */
2042  #define WM8958_CP_DISCH                         0x8000  /* CP_DISCH */
2043  #define WM8958_CP_DISCH_MASK                    0x8000  /* CP_DISCH */
2044  #define WM8958_CP_DISCH_SHIFT                       15  /* CP_DISCH */
2045  #define WM8958_CP_DISCH_WIDTH                        1  /* CP_DISCH */
2046  
2047  /*
2048   * R81 (0x51) - Class W (1)
2049   */
2050  #define WM8994_CP_DYN_SRC_SEL_MASK              0x0300  /* CP_DYN_SRC_SEL - [9:8] */
2051  #define WM8994_CP_DYN_SRC_SEL_SHIFT                  8  /* CP_DYN_SRC_SEL - [9:8] */
2052  #define WM8994_CP_DYN_SRC_SEL_WIDTH                  2  /* CP_DYN_SRC_SEL - [9:8] */
2053  #define WM8994_CP_DYN_PWR                       0x0001  /* CP_DYN_PWR */
2054  #define WM8994_CP_DYN_PWR_MASK                  0x0001  /* CP_DYN_PWR */
2055  #define WM8994_CP_DYN_PWR_SHIFT                      0  /* CP_DYN_PWR */
2056  #define WM8994_CP_DYN_PWR_WIDTH                      1  /* CP_DYN_PWR */
2057  
2058  /*
2059   * R84 (0x54) - DC Servo (1)
2060   */
2061  #define WM8994_DCS_TRIG_SINGLE_1                0x2000  /* DCS_TRIG_SINGLE_1 */
2062  #define WM8994_DCS_TRIG_SINGLE_1_MASK           0x2000  /* DCS_TRIG_SINGLE_1 */
2063  #define WM8994_DCS_TRIG_SINGLE_1_SHIFT              13  /* DCS_TRIG_SINGLE_1 */
2064  #define WM8994_DCS_TRIG_SINGLE_1_WIDTH               1  /* DCS_TRIG_SINGLE_1 */
2065  #define WM8994_DCS_TRIG_SINGLE_0                0x1000  /* DCS_TRIG_SINGLE_0 */
2066  #define WM8994_DCS_TRIG_SINGLE_0_MASK           0x1000  /* DCS_TRIG_SINGLE_0 */
2067  #define WM8994_DCS_TRIG_SINGLE_0_SHIFT              12  /* DCS_TRIG_SINGLE_0 */
2068  #define WM8994_DCS_TRIG_SINGLE_0_WIDTH               1  /* DCS_TRIG_SINGLE_0 */
2069  #define WM8994_DCS_TRIG_SERIES_1                0x0200  /* DCS_TRIG_SERIES_1 */
2070  #define WM8994_DCS_TRIG_SERIES_1_MASK           0x0200  /* DCS_TRIG_SERIES_1 */
2071  #define WM8994_DCS_TRIG_SERIES_1_SHIFT               9  /* DCS_TRIG_SERIES_1 */
2072  #define WM8994_DCS_TRIG_SERIES_1_WIDTH               1  /* DCS_TRIG_SERIES_1 */
2073  #define WM8994_DCS_TRIG_SERIES_0                0x0100  /* DCS_TRIG_SERIES_0 */
2074  #define WM8994_DCS_TRIG_SERIES_0_MASK           0x0100  /* DCS_TRIG_SERIES_0 */
2075  #define WM8994_DCS_TRIG_SERIES_0_SHIFT               8  /* DCS_TRIG_SERIES_0 */
2076  #define WM8994_DCS_TRIG_SERIES_0_WIDTH               1  /* DCS_TRIG_SERIES_0 */
2077  #define WM8994_DCS_TRIG_STARTUP_1               0x0020  /* DCS_TRIG_STARTUP_1 */
2078  #define WM8994_DCS_TRIG_STARTUP_1_MASK          0x0020  /* DCS_TRIG_STARTUP_1 */
2079  #define WM8994_DCS_TRIG_STARTUP_1_SHIFT              5  /* DCS_TRIG_STARTUP_1 */
2080  #define WM8994_DCS_TRIG_STARTUP_1_WIDTH              1  /* DCS_TRIG_STARTUP_1 */
2081  #define WM8994_DCS_TRIG_STARTUP_0               0x0010  /* DCS_TRIG_STARTUP_0 */
2082  #define WM8994_DCS_TRIG_STARTUP_0_MASK          0x0010  /* DCS_TRIG_STARTUP_0 */
2083  #define WM8994_DCS_TRIG_STARTUP_0_SHIFT              4  /* DCS_TRIG_STARTUP_0 */
2084  #define WM8994_DCS_TRIG_STARTUP_0_WIDTH              1  /* DCS_TRIG_STARTUP_0 */
2085  #define WM8994_DCS_TRIG_DAC_WR_1                0x0008  /* DCS_TRIG_DAC_WR_1 */
2086  #define WM8994_DCS_TRIG_DAC_WR_1_MASK           0x0008  /* DCS_TRIG_DAC_WR_1 */
2087  #define WM8994_DCS_TRIG_DAC_WR_1_SHIFT               3  /* DCS_TRIG_DAC_WR_1 */
2088  #define WM8994_DCS_TRIG_DAC_WR_1_WIDTH               1  /* DCS_TRIG_DAC_WR_1 */
2089  #define WM8994_DCS_TRIG_DAC_WR_0                0x0004  /* DCS_TRIG_DAC_WR_0 */
2090  #define WM8994_DCS_TRIG_DAC_WR_0_MASK           0x0004  /* DCS_TRIG_DAC_WR_0 */
2091  #define WM8994_DCS_TRIG_DAC_WR_0_SHIFT               2  /* DCS_TRIG_DAC_WR_0 */
2092  #define WM8994_DCS_TRIG_DAC_WR_0_WIDTH               1  /* DCS_TRIG_DAC_WR_0 */
2093  #define WM8994_DCS_ENA_CHAN_1                   0x0002  /* DCS_ENA_CHAN_1 */
2094  #define WM8994_DCS_ENA_CHAN_1_MASK              0x0002  /* DCS_ENA_CHAN_1 */
2095  #define WM8994_DCS_ENA_CHAN_1_SHIFT                  1  /* DCS_ENA_CHAN_1 */
2096  #define WM8994_DCS_ENA_CHAN_1_WIDTH                  1  /* DCS_ENA_CHAN_1 */
2097  #define WM8994_DCS_ENA_CHAN_0                   0x0001  /* DCS_ENA_CHAN_0 */
2098  #define WM8994_DCS_ENA_CHAN_0_MASK              0x0001  /* DCS_ENA_CHAN_0 */
2099  #define WM8994_DCS_ENA_CHAN_0_SHIFT                  0  /* DCS_ENA_CHAN_0 */
2100  #define WM8994_DCS_ENA_CHAN_0_WIDTH                  1  /* DCS_ENA_CHAN_0 */
2101  
2102  /*
2103   * R85 (0x55) - DC Servo (2)
2104   */
2105  #define WM8994_DCS_SERIES_NO_01_MASK            0x0FE0  /* DCS_SERIES_NO_01 - [11:5] */
2106  #define WM8994_DCS_SERIES_NO_01_SHIFT                5  /* DCS_SERIES_NO_01 - [11:5] */
2107  #define WM8994_DCS_SERIES_NO_01_WIDTH                7  /* DCS_SERIES_NO_01 - [11:5] */
2108  #define WM8994_DCS_TIMER_PERIOD_01_MASK         0x000F  /* DCS_TIMER_PERIOD_01 - [3:0] */
2109  #define WM8994_DCS_TIMER_PERIOD_01_SHIFT             0  /* DCS_TIMER_PERIOD_01 - [3:0] */
2110  #define WM8994_DCS_TIMER_PERIOD_01_WIDTH             4  /* DCS_TIMER_PERIOD_01 - [3:0] */
2111  
2112  /*
2113   * R87 (0x57) - DC Servo (4)
2114   */
2115  #define WM8994_DCS_DAC_WR_VAL_1_MASK            0xFF00  /* DCS_DAC_WR_VAL_1 - [15:8] */
2116  #define WM8994_DCS_DAC_WR_VAL_1_SHIFT                8  /* DCS_DAC_WR_VAL_1 - [15:8] */
2117  #define WM8994_DCS_DAC_WR_VAL_1_WIDTH                8  /* DCS_DAC_WR_VAL_1 - [15:8] */
2118  #define WM8994_DCS_DAC_WR_VAL_0_MASK            0x00FF  /* DCS_DAC_WR_VAL_0 - [7:0] */
2119  #define WM8994_DCS_DAC_WR_VAL_0_SHIFT                0  /* DCS_DAC_WR_VAL_0 - [7:0] */
2120  #define WM8994_DCS_DAC_WR_VAL_0_WIDTH                8  /* DCS_DAC_WR_VAL_0 - [7:0] */
2121  
2122  /*
2123   * R88 (0x58) - DC Servo Readback
2124   */
2125  #define WM8994_DCS_CAL_COMPLETE_MASK            0x0300  /* DCS_CAL_COMPLETE - [9:8] */
2126  #define WM8994_DCS_CAL_COMPLETE_SHIFT                8  /* DCS_CAL_COMPLETE - [9:8] */
2127  #define WM8994_DCS_CAL_COMPLETE_WIDTH                2  /* DCS_CAL_COMPLETE - [9:8] */
2128  #define WM8994_DCS_DAC_WR_COMPLETE_MASK         0x0030  /* DCS_DAC_WR_COMPLETE - [5:4] */
2129  #define WM8994_DCS_DAC_WR_COMPLETE_SHIFT             4  /* DCS_DAC_WR_COMPLETE - [5:4] */
2130  #define WM8994_DCS_DAC_WR_COMPLETE_WIDTH             2  /* DCS_DAC_WR_COMPLETE - [5:4] */
2131  #define WM8994_DCS_STARTUP_COMPLETE_MASK        0x0003  /* DCS_STARTUP_COMPLETE - [1:0] */
2132  #define WM8994_DCS_STARTUP_COMPLETE_SHIFT            0  /* DCS_STARTUP_COMPLETE - [1:0] */
2133  #define WM8994_DCS_STARTUP_COMPLETE_WIDTH            2  /* DCS_STARTUP_COMPLETE - [1:0] */
2134  
2135  /*
2136   * R96 (0x60) - Analogue HP (1)
2137   */
2138  #define WM1811_HPOUT1_ATTN                      0x0100  /* HPOUT1_ATTN */
2139  #define WM1811_HPOUT1_ATTN_MASK                 0x0100  /* HPOUT1_ATTN */
2140  #define WM1811_HPOUT1_ATTN_SHIFT                     8  /* HPOUT1_ATTN */
2141  #define WM1811_HPOUT1_ATTN_WIDTH                     1  /* HPOUT1_ATTN */
2142  #define WM8994_HPOUT1L_RMV_SHORT                0x0080  /* HPOUT1L_RMV_SHORT */
2143  #define WM8994_HPOUT1L_RMV_SHORT_MASK           0x0080  /* HPOUT1L_RMV_SHORT */
2144  #define WM8994_HPOUT1L_RMV_SHORT_SHIFT               7  /* HPOUT1L_RMV_SHORT */
2145  #define WM8994_HPOUT1L_RMV_SHORT_WIDTH               1  /* HPOUT1L_RMV_SHORT */
2146  #define WM8994_HPOUT1L_OUTP                     0x0040  /* HPOUT1L_OUTP */
2147  #define WM8994_HPOUT1L_OUTP_MASK                0x0040  /* HPOUT1L_OUTP */
2148  #define WM8994_HPOUT1L_OUTP_SHIFT                    6  /* HPOUT1L_OUTP */
2149  #define WM8994_HPOUT1L_OUTP_WIDTH                    1  /* HPOUT1L_OUTP */
2150  #define WM8994_HPOUT1L_DLY                      0x0020  /* HPOUT1L_DLY */
2151  #define WM8994_HPOUT1L_DLY_MASK                 0x0020  /* HPOUT1L_DLY */
2152  #define WM8994_HPOUT1L_DLY_SHIFT                     5  /* HPOUT1L_DLY */
2153  #define WM8994_HPOUT1L_DLY_WIDTH                     1  /* HPOUT1L_DLY */
2154  #define WM8994_HPOUT1R_RMV_SHORT                0x0008  /* HPOUT1R_RMV_SHORT */
2155  #define WM8994_HPOUT1R_RMV_SHORT_MASK           0x0008  /* HPOUT1R_RMV_SHORT */
2156  #define WM8994_HPOUT1R_RMV_SHORT_SHIFT               3  /* HPOUT1R_RMV_SHORT */
2157  #define WM8994_HPOUT1R_RMV_SHORT_WIDTH               1  /* HPOUT1R_RMV_SHORT */
2158  #define WM8994_HPOUT1R_OUTP                     0x0004  /* HPOUT1R_OUTP */
2159  #define WM8994_HPOUT1R_OUTP_MASK                0x0004  /* HPOUT1R_OUTP */
2160  #define WM8994_HPOUT1R_OUTP_SHIFT                    2  /* HPOUT1R_OUTP */
2161  #define WM8994_HPOUT1R_OUTP_WIDTH                    1  /* HPOUT1R_OUTP */
2162  #define WM8994_HPOUT1R_DLY                      0x0002  /* HPOUT1R_DLY */
2163  #define WM8994_HPOUT1R_DLY_MASK                 0x0002  /* HPOUT1R_DLY */
2164  #define WM8994_HPOUT1R_DLY_SHIFT                     1  /* HPOUT1R_DLY */
2165  #define WM8994_HPOUT1R_DLY_WIDTH                     1  /* HPOUT1R_DLY */
2166  
2167  /*
2168   * R208 (0xD0) - Mic Detect 1
2169   */
2170  #define WM8958_MICD_BIAS_STARTTIME_MASK         0xF000  /* MICD_BIAS_STARTTIME - [15:12] */
2171  #define WM8958_MICD_BIAS_STARTTIME_SHIFT            12  /* MICD_BIAS_STARTTIME - [15:12] */
2172  #define WM8958_MICD_BIAS_STARTTIME_WIDTH             4  /* MICD_BIAS_STARTTIME - [15:12] */
2173  #define WM8958_MICD_RATE_MASK                   0x0F00  /* MICD_RATE - [11:8] */
2174  #define WM8958_MICD_RATE_SHIFT                       8  /* MICD_RATE - [11:8] */
2175  #define WM8958_MICD_RATE_WIDTH                       4  /* MICD_RATE - [11:8] */
2176  #define WM8958_MICD_DBTIME                      0x0002  /* MICD_DBTIME */
2177  #define WM8958_MICD_DBTIME_MASK                 0x0002  /* MICD_DBTIME */
2178  #define WM8958_MICD_DBTIME_SHIFT                     1  /* MICD_DBTIME */
2179  #define WM8958_MICD_DBTIME_WIDTH                     1  /* MICD_DBTIME */
2180  #define WM8958_MICD_ENA                         0x0001  /* MICD_ENA */
2181  #define WM8958_MICD_ENA_MASK                    0x0001  /* MICD_ENA */
2182  #define WM8958_MICD_ENA_SHIFT                        0  /* MICD_ENA */
2183  #define WM8958_MICD_ENA_WIDTH                        1  /* MICD_ENA */
2184  
2185  /*
2186   * R209 (0xD1) - Mic Detect 2
2187   */
2188  #define WM8958_MICD_LVL_SEL_MASK                0x00FF  /* MICD_LVL_SEL - [7:0] */
2189  #define WM8958_MICD_LVL_SEL_SHIFT                    0  /* MICD_LVL_SEL - [7:0] */
2190  #define WM8958_MICD_LVL_SEL_WIDTH                    8  /* MICD_LVL_SEL - [7:0] */
2191  
2192  /*
2193   * R210 (0xD2) - Mic Detect 3
2194   */
2195  #define WM8958_MICD_LVL_MASK                    0x07FC  /* MICD_LVL - [10:2] */
2196  #define WM8958_MICD_LVL_SHIFT                        2  /* MICD_LVL - [10:2] */
2197  #define WM8958_MICD_LVL_WIDTH                        9  /* MICD_LVL - [10:2] */
2198  #define WM8958_MICD_VALID                       0x0002  /* MICD_VALID */
2199  #define WM8958_MICD_VALID_MASK                  0x0002  /* MICD_VALID */
2200  #define WM8958_MICD_VALID_SHIFT                      1  /* MICD_VALID */
2201  #define WM8958_MICD_VALID_WIDTH                      1  /* MICD_VALID */
2202  #define WM8958_MICD_STS                         0x0001  /* MICD_STS */
2203  #define WM8958_MICD_STS_MASK                    0x0001  /* MICD_STS */
2204  #define WM8958_MICD_STS_SHIFT                        0  /* MICD_STS */
2205  #define WM8958_MICD_STS_WIDTH                        1  /* MICD_STS */
2206  
2207  /*
2208   * R256 (0x100) - Chip Revision
2209   */
2210  #define WM8994_CUST_ID_MASK                     0xFF00  /* CUST_ID - [15:8] */
2211  #define WM8994_CUST_ID_SHIFT                         8  /* CUST_ID - [15:8] */
2212  #define WM8994_CUST_ID_WIDTH                         8  /* CUST_ID - [15:8] */
2213  #define WM8994_CHIP_REV_MASK                    0x000F  /* CHIP_REV - [3:0] */
2214  #define WM8994_CHIP_REV_SHIFT                        0  /* CHIP_REV - [3:0] */
2215  #define WM8994_CHIP_REV_WIDTH                        4  /* CHIP_REV - [3:0] */
2216  
2217  /*
2218   * R257 (0x101) - Control Interface
2219   */
2220  #define WM8994_SPI_CONTRD                       0x0040  /* SPI_CONTRD */
2221  #define WM8994_SPI_CONTRD_MASK                  0x0040  /* SPI_CONTRD */
2222  #define WM8994_SPI_CONTRD_SHIFT                      6  /* SPI_CONTRD */
2223  #define WM8994_SPI_CONTRD_WIDTH                      1  /* SPI_CONTRD */
2224  #define WM8994_SPI_4WIRE                        0x0020  /* SPI_4WIRE */
2225  #define WM8994_SPI_4WIRE_MASK                   0x0020  /* SPI_4WIRE */
2226  #define WM8994_SPI_4WIRE_SHIFT                       5  /* SPI_4WIRE */
2227  #define WM8994_SPI_4WIRE_WIDTH                       1  /* SPI_4WIRE */
2228  #define WM8994_SPI_CFG                          0x0010  /* SPI_CFG */
2229  #define WM8994_SPI_CFG_MASK                     0x0010  /* SPI_CFG */
2230  #define WM8994_SPI_CFG_SHIFT                         4  /* SPI_CFG */
2231  #define WM8994_SPI_CFG_WIDTH                         1  /* SPI_CFG */
2232  #define WM8994_AUTO_INC                         0x0004  /* AUTO_INC */
2233  #define WM8994_AUTO_INC_MASK                    0x0004  /* AUTO_INC */
2234  #define WM8994_AUTO_INC_SHIFT                        2  /* AUTO_INC */
2235  #define WM8994_AUTO_INC_WIDTH                        1  /* AUTO_INC */
2236  
2237  /*
2238   * R272 (0x110) - Write Sequencer Ctrl (1)
2239   */
2240  #define WM8994_WSEQ_ENA                         0x8000  /* WSEQ_ENA */
2241  #define WM8994_WSEQ_ENA_MASK                    0x8000  /* WSEQ_ENA */
2242  #define WM8994_WSEQ_ENA_SHIFT                       15  /* WSEQ_ENA */
2243  #define WM8994_WSEQ_ENA_WIDTH                        1  /* WSEQ_ENA */
2244  #define WM8994_WSEQ_ABORT                       0x0200  /* WSEQ_ABORT */
2245  #define WM8994_WSEQ_ABORT_MASK                  0x0200  /* WSEQ_ABORT */
2246  #define WM8994_WSEQ_ABORT_SHIFT                      9  /* WSEQ_ABORT */
2247  #define WM8994_WSEQ_ABORT_WIDTH                      1  /* WSEQ_ABORT */
2248  #define WM8994_WSEQ_START                       0x0100  /* WSEQ_START */
2249  #define WM8994_WSEQ_START_MASK                  0x0100  /* WSEQ_START */
2250  #define WM8994_WSEQ_START_SHIFT                      8  /* WSEQ_START */
2251  #define WM8994_WSEQ_START_WIDTH                      1  /* WSEQ_START */
2252  #define WM8994_WSEQ_START_INDEX_MASK            0x007F  /* WSEQ_START_INDEX - [6:0] */
2253  #define WM8994_WSEQ_START_INDEX_SHIFT                0  /* WSEQ_START_INDEX - [6:0] */
2254  #define WM8994_WSEQ_START_INDEX_WIDTH                7  /* WSEQ_START_INDEX - [6:0] */
2255  
2256  /*
2257   * R273 (0x111) - Write Sequencer Ctrl (2)
2258   */
2259  #define WM8994_WSEQ_BUSY                        0x0100  /* WSEQ_BUSY */
2260  #define WM8994_WSEQ_BUSY_MASK                   0x0100  /* WSEQ_BUSY */
2261  #define WM8994_WSEQ_BUSY_SHIFT                       8  /* WSEQ_BUSY */
2262  #define WM8994_WSEQ_BUSY_WIDTH                       1  /* WSEQ_BUSY */
2263  #define WM8994_WSEQ_CURRENT_INDEX_MASK          0x007F  /* WSEQ_CURRENT_INDEX - [6:0] */
2264  #define WM8994_WSEQ_CURRENT_INDEX_SHIFT              0  /* WSEQ_CURRENT_INDEX - [6:0] */
2265  #define WM8994_WSEQ_CURRENT_INDEX_WIDTH              7  /* WSEQ_CURRENT_INDEX - [6:0] */
2266  
2267  /*
2268   * R512 (0x200) - AIF1 Clocking (1)
2269   */
2270  #define WM8994_AIF1CLK_SRC_MASK                 0x0018  /* AIF1CLK_SRC - [4:3] */
2271  #define WM8994_AIF1CLK_SRC_SHIFT                     3  /* AIF1CLK_SRC - [4:3] */
2272  #define WM8994_AIF1CLK_SRC_WIDTH                     2  /* AIF1CLK_SRC - [4:3] */
2273  #define WM8994_AIF1CLK_INV                      0x0004  /* AIF1CLK_INV */
2274  #define WM8994_AIF1CLK_INV_MASK                 0x0004  /* AIF1CLK_INV */
2275  #define WM8994_AIF1CLK_INV_SHIFT                     2  /* AIF1CLK_INV */
2276  #define WM8994_AIF1CLK_INV_WIDTH                     1  /* AIF1CLK_INV */
2277  #define WM8994_AIF1CLK_DIV                      0x0002  /* AIF1CLK_DIV */
2278  #define WM8994_AIF1CLK_DIV_MASK                 0x0002  /* AIF1CLK_DIV */
2279  #define WM8994_AIF1CLK_DIV_SHIFT                     1  /* AIF1CLK_DIV */
2280  #define WM8994_AIF1CLK_DIV_WIDTH                     1  /* AIF1CLK_DIV */
2281  #define WM8994_AIF1CLK_ENA                      0x0001  /* AIF1CLK_ENA */
2282  #define WM8994_AIF1CLK_ENA_MASK                 0x0001  /* AIF1CLK_ENA */
2283  #define WM8994_AIF1CLK_ENA_SHIFT                     0  /* AIF1CLK_ENA */
2284  #define WM8994_AIF1CLK_ENA_WIDTH                     1  /* AIF1CLK_ENA */
2285  
2286  /*
2287   * R513 (0x201) - AIF1 Clocking (2)
2288   */
2289  #define WM8994_AIF1DAC_DIV_MASK                 0x0038  /* AIF1DAC_DIV - [5:3] */
2290  #define WM8994_AIF1DAC_DIV_SHIFT                     3  /* AIF1DAC_DIV - [5:3] */
2291  #define WM8994_AIF1DAC_DIV_WIDTH                     3  /* AIF1DAC_DIV - [5:3] */
2292  #define WM8994_AIF1ADC_DIV_MASK                 0x0007  /* AIF1ADC_DIV - [2:0] */
2293  #define WM8994_AIF1ADC_DIV_SHIFT                     0  /* AIF1ADC_DIV - [2:0] */
2294  #define WM8994_AIF1ADC_DIV_WIDTH                     3  /* AIF1ADC_DIV - [2:0] */
2295  
2296  /*
2297   * R516 (0x204) - AIF2 Clocking (1)
2298   */
2299  #define WM8994_AIF2CLK_SRC_MASK                 0x0018  /* AIF2CLK_SRC - [4:3] */
2300  #define WM8994_AIF2CLK_SRC_SHIFT                     3  /* AIF2CLK_SRC - [4:3] */
2301  #define WM8994_AIF2CLK_SRC_WIDTH                     2  /* AIF2CLK_SRC - [4:3] */
2302  #define WM8994_AIF2CLK_INV                      0x0004  /* AIF2CLK_INV */
2303  #define WM8994_AIF2CLK_INV_MASK                 0x0004  /* AIF2CLK_INV */
2304  #define WM8994_AIF2CLK_INV_SHIFT                     2  /* AIF2CLK_INV */
2305  #define WM8994_AIF2CLK_INV_WIDTH                     1  /* AIF2CLK_INV */
2306  #define WM8994_AIF2CLK_DIV                      0x0002  /* AIF2CLK_DIV */
2307  #define WM8994_AIF2CLK_DIV_MASK                 0x0002  /* AIF2CLK_DIV */
2308  #define WM8994_AIF2CLK_DIV_SHIFT                     1  /* AIF2CLK_DIV */
2309  #define WM8994_AIF2CLK_DIV_WIDTH                     1  /* AIF2CLK_DIV */
2310  #define WM8994_AIF2CLK_ENA                      0x0001  /* AIF2CLK_ENA */
2311  #define WM8994_AIF2CLK_ENA_MASK                 0x0001  /* AIF2CLK_ENA */
2312  #define WM8994_AIF2CLK_ENA_SHIFT                     0  /* AIF2CLK_ENA */
2313  #define WM8994_AIF2CLK_ENA_WIDTH                     1  /* AIF2CLK_ENA */
2314  
2315  /*
2316   * R517 (0x205) - AIF2 Clocking (2)
2317   */
2318  #define WM8994_AIF2DAC_DIV_MASK                 0x0038  /* AIF2DAC_DIV - [5:3] */
2319  #define WM8994_AIF2DAC_DIV_SHIFT                     3  /* AIF2DAC_DIV - [5:3] */
2320  #define WM8994_AIF2DAC_DIV_WIDTH                     3  /* AIF2DAC_DIV - [5:3] */
2321  #define WM8994_AIF2ADC_DIV_MASK                 0x0007  /* AIF2ADC_DIV - [2:0] */
2322  #define WM8994_AIF2ADC_DIV_SHIFT                     0  /* AIF2ADC_DIV - [2:0] */
2323  #define WM8994_AIF2ADC_DIV_WIDTH                     3  /* AIF2ADC_DIV - [2:0] */
2324  
2325  /*
2326   * R520 (0x208) - Clocking (1)
2327   */
2328  #define WM8958_DSP2CLK_ENA                      0x4000  /* DSP2CLK_ENA */
2329  #define WM8958_DSP2CLK_ENA_MASK                 0x4000  /* DSP2CLK_ENA */
2330  #define WM8958_DSP2CLK_ENA_SHIFT                    14  /* DSP2CLK_ENA */
2331  #define WM8958_DSP2CLK_ENA_WIDTH                     1  /* DSP2CLK_ENA */
2332  #define WM8958_DSP2CLK_SRC                      0x1000  /* DSP2CLK_SRC */
2333  #define WM8958_DSP2CLK_SRC_MASK                 0x1000  /* DSP2CLK_SRC */
2334  #define WM8958_DSP2CLK_SRC_SHIFT                    12  /* DSP2CLK_SRC */
2335  #define WM8958_DSP2CLK_SRC_WIDTH                     1  /* DSP2CLK_SRC */
2336  #define WM8994_TOCLK_ENA                        0x0010  /* TOCLK_ENA */
2337  #define WM8994_TOCLK_ENA_MASK                   0x0010  /* TOCLK_ENA */
2338  #define WM8994_TOCLK_ENA_SHIFT                       4  /* TOCLK_ENA */
2339  #define WM8994_TOCLK_ENA_WIDTH                       1  /* TOCLK_ENA */
2340  #define WM8994_AIF1DSPCLK_ENA                   0x0008  /* AIF1DSPCLK_ENA */
2341  #define WM8994_AIF1DSPCLK_ENA_MASK              0x0008  /* AIF1DSPCLK_ENA */
2342  #define WM8994_AIF1DSPCLK_ENA_SHIFT                  3  /* AIF1DSPCLK_ENA */
2343  #define WM8994_AIF1DSPCLK_ENA_WIDTH                  1  /* AIF1DSPCLK_ENA */
2344  #define WM8994_AIF2DSPCLK_ENA                   0x0004  /* AIF2DSPCLK_ENA */
2345  #define WM8994_AIF2DSPCLK_ENA_MASK              0x0004  /* AIF2DSPCLK_ENA */
2346  #define WM8994_AIF2DSPCLK_ENA_SHIFT                  2  /* AIF2DSPCLK_ENA */
2347  #define WM8994_AIF2DSPCLK_ENA_WIDTH                  1  /* AIF2DSPCLK_ENA */
2348  #define WM8994_SYSDSPCLK_ENA                    0x0002  /* SYSDSPCLK_ENA */
2349  #define WM8994_SYSDSPCLK_ENA_MASK               0x0002  /* SYSDSPCLK_ENA */
2350  #define WM8994_SYSDSPCLK_ENA_SHIFT                   1  /* SYSDSPCLK_ENA */
2351  #define WM8994_SYSDSPCLK_ENA_WIDTH                   1  /* SYSDSPCLK_ENA */
2352  #define WM8994_SYSCLK_SRC                       0x0001  /* SYSCLK_SRC */
2353  #define WM8994_SYSCLK_SRC_MASK                  0x0001  /* SYSCLK_SRC */
2354  #define WM8994_SYSCLK_SRC_SHIFT                      0  /* SYSCLK_SRC */
2355  #define WM8994_SYSCLK_SRC_WIDTH                      1  /* SYSCLK_SRC */
2356  
2357  /*
2358   * R521 (0x209) - Clocking (2)
2359   */
2360  #define WM8994_TOCLK_DIV_MASK                   0x0700  /* TOCLK_DIV - [10:8] */
2361  #define WM8994_TOCLK_DIV_SHIFT                       8  /* TOCLK_DIV - [10:8] */
2362  #define WM8994_TOCLK_DIV_WIDTH                       3  /* TOCLK_DIV - [10:8] */
2363  #define WM8994_DBCLK_DIV_MASK                   0x0070  /* DBCLK_DIV - [6:4] */
2364  #define WM8994_DBCLK_DIV_SHIFT                       4  /* DBCLK_DIV - [6:4] */
2365  #define WM8994_DBCLK_DIV_WIDTH                       3  /* DBCLK_DIV - [6:4] */
2366  #define WM8994_OPCLK_DIV_MASK                   0x0007  /* OPCLK_DIV - [2:0] */
2367  #define WM8994_OPCLK_DIV_SHIFT                       0  /* OPCLK_DIV - [2:0] */
2368  #define WM8994_OPCLK_DIV_WIDTH                       3  /* OPCLK_DIV - [2:0] */
2369  
2370  /*
2371   * R528 (0x210) - AIF1 Rate
2372   */
2373  #define WM8994_AIF1_SR_MASK                     0x00F0  /* AIF1_SR - [7:4] */
2374  #define WM8994_AIF1_SR_SHIFT                         4  /* AIF1_SR - [7:4] */
2375  #define WM8994_AIF1_SR_WIDTH                         4  /* AIF1_SR - [7:4] */
2376  #define WM8994_AIF1CLK_RATE_MASK                0x000F  /* AIF1CLK_RATE - [3:0] */
2377  #define WM8994_AIF1CLK_RATE_SHIFT                    0  /* AIF1CLK_RATE - [3:0] */
2378  #define WM8994_AIF1CLK_RATE_WIDTH                    4  /* AIF1CLK_RATE - [3:0] */
2379  
2380  /*
2381   * R529 (0x211) - AIF2 Rate
2382   */
2383  #define WM8994_AIF2_SR_MASK                     0x00F0  /* AIF2_SR - [7:4] */
2384  #define WM8994_AIF2_SR_SHIFT                         4  /* AIF2_SR - [7:4] */
2385  #define WM8994_AIF2_SR_WIDTH                         4  /* AIF2_SR - [7:4] */
2386  #define WM8994_AIF2CLK_RATE_MASK                0x000F  /* AIF2CLK_RATE - [3:0] */
2387  #define WM8994_AIF2CLK_RATE_SHIFT                    0  /* AIF2CLK_RATE - [3:0] */
2388  #define WM8994_AIF2CLK_RATE_WIDTH                    4  /* AIF2CLK_RATE - [3:0] */
2389  
2390  /*
2391   * R530 (0x212) - Rate Status
2392   */
2393  #define WM8994_SR_ERROR_MASK                    0x000F  /* SR_ERROR - [3:0] */
2394  #define WM8994_SR_ERROR_SHIFT                        0  /* SR_ERROR - [3:0] */
2395  #define WM8994_SR_ERROR_WIDTH                        4  /* SR_ERROR - [3:0] */
2396  
2397  /*
2398   * R544 (0x220) - FLL1 Control (1)
2399   */
2400  #define WM8994_FLL1_FRAC                        0x0004  /* FLL1_FRAC */
2401  #define WM8994_FLL1_FRAC_MASK                   0x0004  /* FLL1_FRAC */
2402  #define WM8994_FLL1_FRAC_SHIFT                       2  /* FLL1_FRAC */
2403  #define WM8994_FLL1_FRAC_WIDTH                       1  /* FLL1_FRAC */
2404  #define WM8994_FLL1_OSC_ENA                     0x0002  /* FLL1_OSC_ENA */
2405  #define WM8994_FLL1_OSC_ENA_MASK                0x0002  /* FLL1_OSC_ENA */
2406  #define WM8994_FLL1_OSC_ENA_SHIFT                    1  /* FLL1_OSC_ENA */
2407  #define WM8994_FLL1_OSC_ENA_WIDTH                    1  /* FLL1_OSC_ENA */
2408  #define WM8994_FLL1_ENA                         0x0001  /* FLL1_ENA */
2409  #define WM8994_FLL1_ENA_MASK                    0x0001  /* FLL1_ENA */
2410  #define WM8994_FLL1_ENA_SHIFT                        0  /* FLL1_ENA */
2411  #define WM8994_FLL1_ENA_WIDTH                        1  /* FLL1_ENA */
2412  
2413  /*
2414   * R545 (0x221) - FLL1 Control (2)
2415   */
2416  #define WM8994_FLL1_OUTDIV_MASK                 0x3F00  /* FLL1_OUTDIV - [13:8] */
2417  #define WM8994_FLL1_OUTDIV_SHIFT                     8  /* FLL1_OUTDIV - [13:8] */
2418  #define WM8994_FLL1_OUTDIV_WIDTH                     6  /* FLL1_OUTDIV - [13:8] */
2419  #define WM8994_FLL1_CTRL_RATE_MASK              0x0070  /* FLL1_CTRL_RATE - [6:4] */
2420  #define WM8994_FLL1_CTRL_RATE_SHIFT                  4  /* FLL1_CTRL_RATE - [6:4] */
2421  #define WM8994_FLL1_CTRL_RATE_WIDTH                  3  /* FLL1_CTRL_RATE - [6:4] */
2422  #define WM8994_FLL1_FRATIO_MASK                 0x0007  /* FLL1_FRATIO - [2:0] */
2423  #define WM8994_FLL1_FRATIO_SHIFT                     0  /* FLL1_FRATIO - [2:0] */
2424  #define WM8994_FLL1_FRATIO_WIDTH                     3  /* FLL1_FRATIO - [2:0] */
2425  
2426  /*
2427   * R546 (0x222) - FLL1 Control (3)
2428   */
2429  #define WM8994_FLL1_K_MASK                      0xFFFF  /* FLL1_K - [15:0] */
2430  #define WM8994_FLL1_K_SHIFT                          0  /* FLL1_K - [15:0] */
2431  #define WM8994_FLL1_K_WIDTH                         16  /* FLL1_K - [15:0] */
2432  
2433  /*
2434   * R547 (0x223) - FLL1 Control (4)
2435   */
2436  #define WM8994_FLL1_N_MASK                      0x7FE0  /* FLL1_N - [14:5] */
2437  #define WM8994_FLL1_N_SHIFT                          5  /* FLL1_N - [14:5] */
2438  #define WM8994_FLL1_N_WIDTH                         10  /* FLL1_N - [14:5] */
2439  #define WM8994_FLL1_LOOP_GAIN_MASK              0x000F  /* FLL1_LOOP_GAIN - [3:0] */
2440  #define WM8994_FLL1_LOOP_GAIN_SHIFT                  0  /* FLL1_LOOP_GAIN - [3:0] */
2441  #define WM8994_FLL1_LOOP_GAIN_WIDTH                  4  /* FLL1_LOOP_GAIN - [3:0] */
2442  
2443  /*
2444   * R548 (0x224) - FLL1 Control (5)
2445   */
2446  #define WM8958_FLL1_BYP                         0x8000  /* FLL1_BYP */
2447  #define WM8958_FLL1_BYP_MASK                    0x8000  /* FLL1_BYP */
2448  #define WM8958_FLL1_BYP_SHIFT                       15  /* FLL1_BYP */
2449  #define WM8958_FLL1_BYP_WIDTH                        1  /* FLL1_BYP */
2450  #define WM8994_FLL1_FRC_NCO_VAL_MASK            0x1F80  /* FLL1_FRC_NCO_VAL - [12:7] */
2451  #define WM8994_FLL1_FRC_NCO_VAL_SHIFT                7  /* FLL1_FRC_NCO_VAL - [12:7] */
2452  #define WM8994_FLL1_FRC_NCO_VAL_WIDTH                6  /* FLL1_FRC_NCO_VAL - [12:7] */
2453  #define WM8994_FLL1_FRC_NCO                     0x0040  /* FLL1_FRC_NCO */
2454  #define WM8994_FLL1_FRC_NCO_MASK                0x0040  /* FLL1_FRC_NCO */
2455  #define WM8994_FLL1_FRC_NCO_SHIFT                    6  /* FLL1_FRC_NCO */
2456  #define WM8994_FLL1_FRC_NCO_WIDTH                    1  /* FLL1_FRC_NCO */
2457  #define WM8994_FLL1_REFCLK_DIV_MASK             0x0018  /* FLL1_REFCLK_DIV - [4:3] */
2458  #define WM8994_FLL1_REFCLK_DIV_SHIFT                 3  /* FLL1_REFCLK_DIV - [4:3] */
2459  #define WM8994_FLL1_REFCLK_DIV_WIDTH                 2  /* FLL1_REFCLK_DIV - [4:3] */
2460  #define WM8994_FLL1_REFCLK_SRC_MASK             0x0003  /* FLL1_REFCLK_SRC - [1:0] */
2461  #define WM8994_FLL1_REFCLK_SRC_SHIFT                 0  /* FLL1_REFCLK_SRC - [1:0] */
2462  #define WM8994_FLL1_REFCLK_SRC_WIDTH                 2  /* FLL1_REFCLK_SRC - [1:0] */
2463  
2464  /*
2465   * R550 (0x226) - FLL1 EFS 1
2466   */
2467  #define WM8958_FLL1_LAMBDA_MASK                 0xFFFF  /* FLL1_LAMBDA - [15:0] */
2468  #define WM8958_FLL1_LAMBDA_SHIFT                     0  /* FLL1_LAMBDA - [15:0] */
2469  #define WM8958_FLL1_LAMBDA_WIDTH                    16  /* FLL1_LAMBDA - [15:0] */
2470  
2471  /*
2472   * R551 (0x227) - FLL1 EFS 2
2473   */
2474  #define WM8958_FLL1_LFSR_SEL_MASK               0x0006  /* FLL1_LFSR_SEL - [2:1] */
2475  #define WM8958_FLL1_LFSR_SEL_SHIFT                   1  /* FLL1_LFSR_SEL - [2:1] */
2476  #define WM8958_FLL1_LFSR_SEL_WIDTH                   2  /* FLL1_LFSR_SEL - [2:1] */
2477  #define WM8958_FLL1_EFS_ENA                     0x0001  /* FLL1_EFS_ENA */
2478  #define WM8958_FLL1_EFS_ENA_MASK                0x0001  /* FLL1_EFS_ENA */
2479  #define WM8958_FLL1_EFS_ENA_SHIFT                    0  /* FLL1_EFS_ENA */
2480  #define WM8958_FLL1_EFS_ENA_WIDTH                    1  /* FLL1_EFS_ENA */
2481  
2482  /*
2483   * R576 (0x240) - FLL2 Control (1)
2484   */
2485  #define WM8994_FLL2_FRAC                        0x0004  /* FLL2_FRAC */
2486  #define WM8994_FLL2_FRAC_MASK                   0x0004  /* FLL2_FRAC */
2487  #define WM8994_FLL2_FRAC_SHIFT                       2  /* FLL2_FRAC */
2488  #define WM8994_FLL2_FRAC_WIDTH                       1  /* FLL2_FRAC */
2489  #define WM8994_FLL2_OSC_ENA                     0x0002  /* FLL2_OSC_ENA */
2490  #define WM8994_FLL2_OSC_ENA_MASK                0x0002  /* FLL2_OSC_ENA */
2491  #define WM8994_FLL2_OSC_ENA_SHIFT                    1  /* FLL2_OSC_ENA */
2492  #define WM8994_FLL2_OSC_ENA_WIDTH                    1  /* FLL2_OSC_ENA */
2493  #define WM8994_FLL2_ENA                         0x0001  /* FLL2_ENA */
2494  #define WM8994_FLL2_ENA_MASK                    0x0001  /* FLL2_ENA */
2495  #define WM8994_FLL2_ENA_SHIFT                        0  /* FLL2_ENA */
2496  #define WM8994_FLL2_ENA_WIDTH                        1  /* FLL2_ENA */
2497  
2498  /*
2499   * R577 (0x241) - FLL2 Control (2)
2500   */
2501  #define WM8994_FLL2_OUTDIV_MASK                 0x3F00  /* FLL2_OUTDIV - [13:8] */
2502  #define WM8994_FLL2_OUTDIV_SHIFT                     8  /* FLL2_OUTDIV - [13:8] */
2503  #define WM8994_FLL2_OUTDIV_WIDTH                     6  /* FLL2_OUTDIV - [13:8] */
2504  #define WM8994_FLL2_CTRL_RATE_MASK              0x0070  /* FLL2_CTRL_RATE - [6:4] */
2505  #define WM8994_FLL2_CTRL_RATE_SHIFT                  4  /* FLL2_CTRL_RATE - [6:4] */
2506  #define WM8994_FLL2_CTRL_RATE_WIDTH                  3  /* FLL2_CTRL_RATE - [6:4] */
2507  #define WM8994_FLL2_FRATIO_MASK                 0x0007  /* FLL2_FRATIO - [2:0] */
2508  #define WM8994_FLL2_FRATIO_SHIFT                     0  /* FLL2_FRATIO - [2:0] */
2509  #define WM8994_FLL2_FRATIO_WIDTH                     3  /* FLL2_FRATIO - [2:0] */
2510  
2511  /*
2512   * R578 (0x242) - FLL2 Control (3)
2513   */
2514  #define WM8994_FLL2_K_MASK                      0xFFFF  /* FLL2_K - [15:0] */
2515  #define WM8994_FLL2_K_SHIFT                          0  /* FLL2_K - [15:0] */
2516  #define WM8994_FLL2_K_WIDTH                         16  /* FLL2_K - [15:0] */
2517  
2518  /*
2519   * R579 (0x243) - FLL2 Control (4)
2520   */
2521  #define WM8994_FLL2_N_MASK                      0x7FE0  /* FLL2_N - [14:5] */
2522  #define WM8994_FLL2_N_SHIFT                          5  /* FLL2_N - [14:5] */
2523  #define WM8994_FLL2_N_WIDTH                         10  /* FLL2_N - [14:5] */
2524  #define WM8994_FLL2_LOOP_GAIN_MASK              0x000F  /* FLL2_LOOP_GAIN - [3:0] */
2525  #define WM8994_FLL2_LOOP_GAIN_SHIFT                  0  /* FLL2_LOOP_GAIN - [3:0] */
2526  #define WM8994_FLL2_LOOP_GAIN_WIDTH                  4  /* FLL2_LOOP_GAIN - [3:0] */
2527  
2528  /*
2529   * R580 (0x244) - FLL2 Control (5)
2530   */
2531  #define WM8958_FLL2_BYP                         0x8000  /* FLL2_BYP */
2532  #define WM8958_FLL2_BYP_MASK                    0x8000  /* FLL2_BYP */
2533  #define WM8958_FLL2_BYP_SHIFT                       15  /* FLL2_BYP */
2534  #define WM8958_FLL2_BYP_WIDTH                        1  /* FLL2_BYP */
2535  #define WM8994_FLL2_FRC_NCO_VAL_MASK            0x1F80  /* FLL2_FRC_NCO_VAL - [12:7] */
2536  #define WM8994_FLL2_FRC_NCO_VAL_SHIFT                7  /* FLL2_FRC_NCO_VAL - [12:7] */
2537  #define WM8994_FLL2_FRC_NCO_VAL_WIDTH                6  /* FLL2_FRC_NCO_VAL - [12:7] */
2538  #define WM8994_FLL2_FRC_NCO                     0x0040  /* FLL2_FRC_NCO */
2539  #define WM8994_FLL2_FRC_NCO_MASK                0x0040  /* FLL2_FRC_NCO */
2540  #define WM8994_FLL2_FRC_NCO_SHIFT                    6  /* FLL2_FRC_NCO */
2541  #define WM8994_FLL2_FRC_NCO_WIDTH                    1  /* FLL2_FRC_NCO */
2542  #define WM8994_FLL2_REFCLK_DIV_MASK             0x0018  /* FLL2_REFCLK_DIV - [4:3] */
2543  #define WM8994_FLL2_REFCLK_DIV_SHIFT                 3  /* FLL2_REFCLK_DIV - [4:3] */
2544  #define WM8994_FLL2_REFCLK_DIV_WIDTH                 2  /* FLL2_REFCLK_DIV - [4:3] */
2545  #define WM8994_FLL2_REFCLK_SRC_MASK             0x0003  /* FLL2_REFCLK_SRC - [1:0] */
2546  #define WM8994_FLL2_REFCLK_SRC_SHIFT                 0  /* FLL2_REFCLK_SRC - [1:0] */
2547  #define WM8994_FLL2_REFCLK_SRC_WIDTH                 2  /* FLL2_REFCLK_SRC - [1:0] */
2548  
2549  /*
2550   * R582 (0x246) - FLL2 EFS 1
2551   */
2552  #define WM8958_FLL2_LAMBDA_MASK                 0xFFFF  /* FLL2_LAMBDA - [15:0] */
2553  #define WM8958_FLL2_LAMBDA_SHIFT                     0  /* FLL2_LAMBDA - [15:0] */
2554  #define WM8958_FLL2_LAMBDA_WIDTH                    16  /* FLL2_LAMBDA - [15:0] */
2555  
2556  /*
2557   * R583 (0x247) - FLL2 EFS 2
2558   */
2559  #define WM8958_FLL2_LFSR_SEL_MASK               0x0006  /* FLL2_LFSR_SEL - [2:1] */
2560  #define WM8958_FLL2_LFSR_SEL_SHIFT                   1  /* FLL2_LFSR_SEL - [2:1] */
2561  #define WM8958_FLL2_LFSR_SEL_WIDTH                   2  /* FLL2_LFSR_SEL - [2:1] */
2562  #define WM8958_FLL2_EFS_ENA                     0x0001  /* FLL2_EFS_ENA */
2563  #define WM8958_FLL2_EFS_ENA_MASK                0x0001  /* FLL2_EFS_ENA */
2564  #define WM8958_FLL2_EFS_ENA_SHIFT                    0  /* FLL2_EFS_ENA */
2565  #define WM8958_FLL2_EFS_ENA_WIDTH                    1  /* FLL2_EFS_ENA */
2566  
2567  /*
2568   * R768 (0x300) - AIF1 Control (1)
2569   */
2570  #define WM8994_AIF1ADCL_SRC                     0x8000  /* AIF1ADCL_SRC */
2571  #define WM8994_AIF1ADCL_SRC_MASK                0x8000  /* AIF1ADCL_SRC */
2572  #define WM8994_AIF1ADCL_SRC_SHIFT                   15  /* AIF1ADCL_SRC */
2573  #define WM8994_AIF1ADCL_SRC_WIDTH                    1  /* AIF1ADCL_SRC */
2574  #define WM8994_AIF1ADCR_SRC                     0x4000  /* AIF1ADCR_SRC */
2575  #define WM8994_AIF1ADCR_SRC_MASK                0x4000  /* AIF1ADCR_SRC */
2576  #define WM8994_AIF1ADCR_SRC_SHIFT                   14  /* AIF1ADCR_SRC */
2577  #define WM8994_AIF1ADCR_SRC_WIDTH                    1  /* AIF1ADCR_SRC */
2578  #define WM8994_AIF1ADC_TDM                      0x2000  /* AIF1ADC_TDM */
2579  #define WM8994_AIF1ADC_TDM_MASK                 0x2000  /* AIF1ADC_TDM */
2580  #define WM8994_AIF1ADC_TDM_SHIFT                    13  /* AIF1ADC_TDM */
2581  #define WM8994_AIF1ADC_TDM_WIDTH                     1  /* AIF1ADC_TDM */
2582  #define WM8994_AIF1_BCLK_INV                    0x0100  /* AIF1_BCLK_INV */
2583  #define WM8994_AIF1_BCLK_INV_MASK               0x0100  /* AIF1_BCLK_INV */
2584  #define WM8994_AIF1_BCLK_INV_SHIFT                   8  /* AIF1_BCLK_INV */
2585  #define WM8994_AIF1_BCLK_INV_WIDTH                   1  /* AIF1_BCLK_INV */
2586  #define WM8994_AIF1_LRCLK_INV                   0x0080  /* AIF1_LRCLK_INV */
2587  #define WM8994_AIF1_LRCLK_INV_MASK              0x0080  /* AIF1_LRCLK_INV */
2588  #define WM8994_AIF1_LRCLK_INV_SHIFT                  7  /* AIF1_LRCLK_INV */
2589  #define WM8994_AIF1_LRCLK_INV_WIDTH                  1  /* AIF1_LRCLK_INV */
2590  #define WM8994_AIF1_WL_MASK                     0x0060  /* AIF1_WL - [6:5] */
2591  #define WM8994_AIF1_WL_SHIFT                         5  /* AIF1_WL - [6:5] */
2592  #define WM8994_AIF1_WL_WIDTH                         2  /* AIF1_WL - [6:5] */
2593  #define WM8994_AIF1_FMT_MASK                    0x0018  /* AIF1_FMT - [4:3] */
2594  #define WM8994_AIF1_FMT_SHIFT                        3  /* AIF1_FMT - [4:3] */
2595  #define WM8994_AIF1_FMT_WIDTH                        2  /* AIF1_FMT - [4:3] */
2596  
2597  /*
2598   * R769 (0x301) - AIF1 Control (2)
2599   */
2600  #define WM8994_AIF1DACL_SRC                     0x8000  /* AIF1DACL_SRC */
2601  #define WM8994_AIF1DACL_SRC_MASK                0x8000  /* AIF1DACL_SRC */
2602  #define WM8994_AIF1DACL_SRC_SHIFT                   15  /* AIF1DACL_SRC */
2603  #define WM8994_AIF1DACL_SRC_WIDTH                    1  /* AIF1DACL_SRC */
2604  #define WM8994_AIF1DACR_SRC                     0x4000  /* AIF1DACR_SRC */
2605  #define WM8994_AIF1DACR_SRC_MASK                0x4000  /* AIF1DACR_SRC */
2606  #define WM8994_AIF1DACR_SRC_SHIFT                   14  /* AIF1DACR_SRC */
2607  #define WM8994_AIF1DACR_SRC_WIDTH                    1  /* AIF1DACR_SRC */
2608  #define WM8994_AIF1DAC_BOOST_MASK               0x0C00  /* AIF1DAC_BOOST - [11:10] */
2609  #define WM8994_AIF1DAC_BOOST_SHIFT                  10  /* AIF1DAC_BOOST - [11:10] */
2610  #define WM8994_AIF1DAC_BOOST_WIDTH                   2  /* AIF1DAC_BOOST - [11:10] */
2611  #define WM8994_AIF1_MONO                        0x0100  /* AIF1_MONO */
2612  #define WM8994_AIF1_MONO_MASK                   0x0100  /* AIF1_MONO */
2613  #define WM8994_AIF1_MONO_SHIFT                       8  /* AIF1_MONO */
2614  #define WM8994_AIF1_MONO_WIDTH                       1  /* AIF1_MONO */
2615  #define WM8994_AIF1DAC_COMP                     0x0010  /* AIF1DAC_COMP */
2616  #define WM8994_AIF1DAC_COMP_MASK                0x0010  /* AIF1DAC_COMP */
2617  #define WM8994_AIF1DAC_COMP_SHIFT                    4  /* AIF1DAC_COMP */
2618  #define WM8994_AIF1DAC_COMP_WIDTH                    1  /* AIF1DAC_COMP */
2619  #define WM8994_AIF1DAC_COMPMODE                 0x0008  /* AIF1DAC_COMPMODE */
2620  #define WM8994_AIF1DAC_COMPMODE_MASK            0x0008  /* AIF1DAC_COMPMODE */
2621  #define WM8994_AIF1DAC_COMPMODE_SHIFT                3  /* AIF1DAC_COMPMODE */
2622  #define WM8994_AIF1DAC_COMPMODE_WIDTH                1  /* AIF1DAC_COMPMODE */
2623  #define WM8994_AIF1ADC_COMP                     0x0004  /* AIF1ADC_COMP */
2624  #define WM8994_AIF1ADC_COMP_MASK                0x0004  /* AIF1ADC_COMP */
2625  #define WM8994_AIF1ADC_COMP_SHIFT                    2  /* AIF1ADC_COMP */
2626  #define WM8994_AIF1ADC_COMP_WIDTH                    1  /* AIF1ADC_COMP */
2627  #define WM8994_AIF1ADC_COMPMODE                 0x0002  /* AIF1ADC_COMPMODE */
2628  #define WM8994_AIF1ADC_COMPMODE_MASK            0x0002  /* AIF1ADC_COMPMODE */
2629  #define WM8994_AIF1ADC_COMPMODE_SHIFT                1  /* AIF1ADC_COMPMODE */
2630  #define WM8994_AIF1ADC_COMPMODE_WIDTH                1  /* AIF1ADC_COMPMODE */
2631  #define WM8994_AIF1_LOOPBACK                    0x0001  /* AIF1_LOOPBACK */
2632  #define WM8994_AIF1_LOOPBACK_MASK               0x0001  /* AIF1_LOOPBACK */
2633  #define WM8994_AIF1_LOOPBACK_SHIFT                   0  /* AIF1_LOOPBACK */
2634  #define WM8994_AIF1_LOOPBACK_WIDTH                   1  /* AIF1_LOOPBACK */
2635  
2636  /*
2637   * R770 (0x302) - AIF1 Master/Slave
2638   */
2639  #define WM8994_AIF1_TRI                         0x8000  /* AIF1_TRI */
2640  #define WM8994_AIF1_TRI_MASK                    0x8000  /* AIF1_TRI */
2641  #define WM8994_AIF1_TRI_SHIFT                       15  /* AIF1_TRI */
2642  #define WM8994_AIF1_TRI_WIDTH                        1  /* AIF1_TRI */
2643  #define WM8994_AIF1_MSTR                        0x4000  /* AIF1_MSTR */
2644  #define WM8994_AIF1_MSTR_MASK                   0x4000  /* AIF1_MSTR */
2645  #define WM8994_AIF1_MSTR_SHIFT                      14  /* AIF1_MSTR */
2646  #define WM8994_AIF1_MSTR_WIDTH                       1  /* AIF1_MSTR */
2647  #define WM8994_AIF1_CLK_FRC                     0x2000  /* AIF1_CLK_FRC */
2648  #define WM8994_AIF1_CLK_FRC_MASK                0x2000  /* AIF1_CLK_FRC */
2649  #define WM8994_AIF1_CLK_FRC_SHIFT                   13  /* AIF1_CLK_FRC */
2650  #define WM8994_AIF1_CLK_FRC_WIDTH                    1  /* AIF1_CLK_FRC */
2651  #define WM8994_AIF1_LRCLK_FRC                   0x1000  /* AIF1_LRCLK_FRC */
2652  #define WM8994_AIF1_LRCLK_FRC_MASK              0x1000  /* AIF1_LRCLK_FRC */
2653  #define WM8994_AIF1_LRCLK_FRC_SHIFT                 12  /* AIF1_LRCLK_FRC */
2654  #define WM8994_AIF1_LRCLK_FRC_WIDTH                  1  /* AIF1_LRCLK_FRC */
2655  
2656  /*
2657   * R771 (0x303) - AIF1 BCLK
2658   */
2659  #define WM8994_AIF1_BCLK_DIV_MASK               0x01F0  /* AIF1_BCLK_DIV - [8:4] */
2660  #define WM8994_AIF1_BCLK_DIV_SHIFT                   4  /* AIF1_BCLK_DIV - [8:4] */
2661  #define WM8994_AIF1_BCLK_DIV_WIDTH                   5  /* AIF1_BCLK_DIV - [8:4] */
2662  
2663  /*
2664   * R772 (0x304) - AIF1ADC LRCLK
2665   */
2666  #define WM8958_AIF1_LRCLK_INV                   0x1000  /* AIF1_LRCLK_INV */
2667  #define WM8958_AIF1_LRCLK_INV_MASK              0x1000  /* AIF1_LRCLK_INV */
2668  #define WM8958_AIF1_LRCLK_INV_SHIFT                 12  /* AIF1_LRCLK_INV */
2669  #define WM8958_AIF1_LRCLK_INV_WIDTH                  1  /* AIF1_LRCLK_INV */
2670  #define WM8994_AIF1ADC_LRCLK_DIR                0x0800  /* AIF1ADC_LRCLK_DIR */
2671  #define WM8994_AIF1ADC_LRCLK_DIR_MASK           0x0800  /* AIF1ADC_LRCLK_DIR */
2672  #define WM8994_AIF1ADC_LRCLK_DIR_SHIFT              11  /* AIF1ADC_LRCLK_DIR */
2673  #define WM8994_AIF1ADC_LRCLK_DIR_WIDTH               1  /* AIF1ADC_LRCLK_DIR */
2674  #define WM8994_AIF1ADC_RATE_MASK                0x07FF  /* AIF1ADC_RATE - [10:0] */
2675  #define WM8994_AIF1ADC_RATE_SHIFT                    0  /* AIF1ADC_RATE - [10:0] */
2676  #define WM8994_AIF1ADC_RATE_WIDTH                   11  /* AIF1ADC_RATE - [10:0] */
2677  
2678  /*
2679   * R773 (0x305) - AIF1DAC LRCLK
2680   */
2681  #define WM8958_AIF1_LRCLK_INV                   0x1000  /* AIF1_LRCLK_INV */
2682  #define WM8958_AIF1_LRCLK_INV_MASK              0x1000  /* AIF1_LRCLK_INV */
2683  #define WM8958_AIF1_LRCLK_INV_SHIFT                 12  /* AIF1_LRCLK_INV */
2684  #define WM8958_AIF1_LRCLK_INV_WIDTH                  1  /* AIF1_LRCLK_INV */
2685  #define WM8994_AIF1DAC_LRCLK_DIR                0x0800  /* AIF1DAC_LRCLK_DIR */
2686  #define WM8994_AIF1DAC_LRCLK_DIR_MASK           0x0800  /* AIF1DAC_LRCLK_DIR */
2687  #define WM8994_AIF1DAC_LRCLK_DIR_SHIFT              11  /* AIF1DAC_LRCLK_DIR */
2688  #define WM8994_AIF1DAC_LRCLK_DIR_WIDTH               1  /* AIF1DAC_LRCLK_DIR */
2689  #define WM8994_AIF1DAC_RATE_MASK                0x07FF  /* AIF1DAC_RATE - [10:0] */
2690  #define WM8994_AIF1DAC_RATE_SHIFT                    0  /* AIF1DAC_RATE - [10:0] */
2691  #define WM8994_AIF1DAC_RATE_WIDTH                   11  /* AIF1DAC_RATE - [10:0] */
2692  
2693  /*
2694   * R774 (0x306) - AIF1DAC Data
2695   */
2696  #define WM8994_AIF1DACL_DAT_INV                 0x0002  /* AIF1DACL_DAT_INV */
2697  #define WM8994_AIF1DACL_DAT_INV_MASK            0x0002  /* AIF1DACL_DAT_INV */
2698  #define WM8994_AIF1DACL_DAT_INV_SHIFT                1  /* AIF1DACL_DAT_INV */
2699  #define WM8994_AIF1DACL_DAT_INV_WIDTH                1  /* AIF1DACL_DAT_INV */
2700  #define WM8994_AIF1DACR_DAT_INV                 0x0001  /* AIF1DACR_DAT_INV */
2701  #define WM8994_AIF1DACR_DAT_INV_MASK            0x0001  /* AIF1DACR_DAT_INV */
2702  #define WM8994_AIF1DACR_DAT_INV_SHIFT                0  /* AIF1DACR_DAT_INV */
2703  #define WM8994_AIF1DACR_DAT_INV_WIDTH                1  /* AIF1DACR_DAT_INV */
2704  
2705  /*
2706   * R775 (0x307) - AIF1ADC Data
2707   */
2708  #define WM8994_AIF1ADCL_DAT_INV                 0x0002  /* AIF1ADCL_DAT_INV */
2709  #define WM8994_AIF1ADCL_DAT_INV_MASK            0x0002  /* AIF1ADCL_DAT_INV */
2710  #define WM8994_AIF1ADCL_DAT_INV_SHIFT                1  /* AIF1ADCL_DAT_INV */
2711  #define WM8994_AIF1ADCL_DAT_INV_WIDTH                1  /* AIF1ADCL_DAT_INV */
2712  #define WM8994_AIF1ADCR_DAT_INV                 0x0001  /* AIF1ADCR_DAT_INV */
2713  #define WM8994_AIF1ADCR_DAT_INV_MASK            0x0001  /* AIF1ADCR_DAT_INV */
2714  #define WM8994_AIF1ADCR_DAT_INV_SHIFT                0  /* AIF1ADCR_DAT_INV */
2715  #define WM8994_AIF1ADCR_DAT_INV_WIDTH                1  /* AIF1ADCR_DAT_INV */
2716  
2717  /*
2718   * R784 (0x310) - AIF2 Control (1)
2719   */
2720  #define WM8994_AIF2ADCL_SRC                     0x8000  /* AIF2ADCL_SRC */
2721  #define WM8994_AIF2ADCL_SRC_MASK                0x8000  /* AIF2ADCL_SRC */
2722  #define WM8994_AIF2ADCL_SRC_SHIFT                   15  /* AIF2ADCL_SRC */
2723  #define WM8994_AIF2ADCL_SRC_WIDTH                    1  /* AIF2ADCL_SRC */
2724  #define WM8994_AIF2ADCR_SRC                     0x4000  /* AIF2ADCR_SRC */
2725  #define WM8994_AIF2ADCR_SRC_MASK                0x4000  /* AIF2ADCR_SRC */
2726  #define WM8994_AIF2ADCR_SRC_SHIFT                   14  /* AIF2ADCR_SRC */
2727  #define WM8994_AIF2ADCR_SRC_WIDTH                    1  /* AIF2ADCR_SRC */
2728  #define WM8994_AIF2ADC_TDM                      0x2000  /* AIF2ADC_TDM */
2729  #define WM8994_AIF2ADC_TDM_MASK                 0x2000  /* AIF2ADC_TDM */
2730  #define WM8994_AIF2ADC_TDM_SHIFT                    13  /* AIF2ADC_TDM */
2731  #define WM8994_AIF2ADC_TDM_WIDTH                     1  /* AIF2ADC_TDM */
2732  #define WM8994_AIF2ADC_TDM_CHAN                 0x1000  /* AIF2ADC_TDM_CHAN */
2733  #define WM8994_AIF2ADC_TDM_CHAN_MASK            0x1000  /* AIF2ADC_TDM_CHAN */
2734  #define WM8994_AIF2ADC_TDM_CHAN_SHIFT               12  /* AIF2ADC_TDM_CHAN */
2735  #define WM8994_AIF2ADC_TDM_CHAN_WIDTH                1  /* AIF2ADC_TDM_CHAN */
2736  #define WM8994_AIF2_BCLK_INV                    0x0100  /* AIF2_BCLK_INV */
2737  #define WM8994_AIF2_BCLK_INV_MASK               0x0100  /* AIF2_BCLK_INV */
2738  #define WM8994_AIF2_BCLK_INV_SHIFT                   8  /* AIF2_BCLK_INV */
2739  #define WM8994_AIF2_BCLK_INV_WIDTH                   1  /* AIF2_BCLK_INV */
2740  #define WM8994_AIF2_LRCLK_INV                   0x0080  /* AIF2_LRCLK_INV */
2741  #define WM8994_AIF2_LRCLK_INV_MASK              0x0080  /* AIF2_LRCLK_INV */
2742  #define WM8994_AIF2_LRCLK_INV_SHIFT                  7  /* AIF2_LRCLK_INV */
2743  #define WM8994_AIF2_LRCLK_INV_WIDTH                  1  /* AIF2_LRCLK_INV */
2744  #define WM8994_AIF2_WL_MASK                     0x0060  /* AIF2_WL - [6:5] */
2745  #define WM8994_AIF2_WL_SHIFT                         5  /* AIF2_WL - [6:5] */
2746  #define WM8994_AIF2_WL_WIDTH                         2  /* AIF2_WL - [6:5] */
2747  #define WM8994_AIF2_FMT_MASK                    0x0018  /* AIF2_FMT - [4:3] */
2748  #define WM8994_AIF2_FMT_SHIFT                        3  /* AIF2_FMT - [4:3] */
2749  #define WM8994_AIF2_FMT_WIDTH                        2  /* AIF2_FMT - [4:3] */
2750  
2751  /*
2752   * R785 (0x311) - AIF2 Control (2)
2753   */
2754  #define WM8994_AIF2DACL_SRC                     0x8000  /* AIF2DACL_SRC */
2755  #define WM8994_AIF2DACL_SRC_MASK                0x8000  /* AIF2DACL_SRC */
2756  #define WM8994_AIF2DACL_SRC_SHIFT                   15  /* AIF2DACL_SRC */
2757  #define WM8994_AIF2DACL_SRC_WIDTH                    1  /* AIF2DACL_SRC */
2758  #define WM8994_AIF2DACR_SRC                     0x4000  /* AIF2DACR_SRC */
2759  #define WM8994_AIF2DACR_SRC_MASK                0x4000  /* AIF2DACR_SRC */
2760  #define WM8994_AIF2DACR_SRC_SHIFT                   14  /* AIF2DACR_SRC */
2761  #define WM8994_AIF2DACR_SRC_WIDTH                    1  /* AIF2DACR_SRC */
2762  #define WM8994_AIF2DAC_TDM                      0x2000  /* AIF2DAC_TDM */
2763  #define WM8994_AIF2DAC_TDM_MASK                 0x2000  /* AIF2DAC_TDM */
2764  #define WM8994_AIF2DAC_TDM_SHIFT                    13  /* AIF2DAC_TDM */
2765  #define WM8994_AIF2DAC_TDM_WIDTH                     1  /* AIF2DAC_TDM */
2766  #define WM8994_AIF2DAC_TDM_CHAN                 0x1000  /* AIF2DAC_TDM_CHAN */
2767  #define WM8994_AIF2DAC_TDM_CHAN_MASK            0x1000  /* AIF2DAC_TDM_CHAN */
2768  #define WM8994_AIF2DAC_TDM_CHAN_SHIFT               12  /* AIF2DAC_TDM_CHAN */
2769  #define WM8994_AIF2DAC_TDM_CHAN_WIDTH                1  /* AIF2DAC_TDM_CHAN */
2770  #define WM8994_AIF2DAC_BOOST_MASK               0x0C00  /* AIF2DAC_BOOST - [11:10] */
2771  #define WM8994_AIF2DAC_BOOST_SHIFT                  10  /* AIF2DAC_BOOST - [11:10] */
2772  #define WM8994_AIF2DAC_BOOST_WIDTH                   2  /* AIF2DAC_BOOST - [11:10] */
2773  #define WM8994_AIF2_MONO                        0x0100  /* AIF2_MONO */
2774  #define WM8994_AIF2_MONO_MASK                   0x0100  /* AIF2_MONO */
2775  #define WM8994_AIF2_MONO_SHIFT                       8  /* AIF2_MONO */
2776  #define WM8994_AIF2_MONO_WIDTH                       1  /* AIF2_MONO */
2777  #define WM8994_AIF2DAC_COMP                     0x0010  /* AIF2DAC_COMP */
2778  #define WM8994_AIF2DAC_COMP_MASK                0x0010  /* AIF2DAC_COMP */
2779  #define WM8994_AIF2DAC_COMP_SHIFT                    4  /* AIF2DAC_COMP */
2780  #define WM8994_AIF2DAC_COMP_WIDTH                    1  /* AIF2DAC_COMP */
2781  #define WM8994_AIF2DAC_COMPMODE                 0x0008  /* AIF2DAC_COMPMODE */
2782  #define WM8994_AIF2DAC_COMPMODE_MASK            0x0008  /* AIF2DAC_COMPMODE */
2783  #define WM8994_AIF2DAC_COMPMODE_SHIFT                3  /* AIF2DAC_COMPMODE */
2784  #define WM8994_AIF2DAC_COMPMODE_WIDTH                1  /* AIF2DAC_COMPMODE */
2785  #define WM8994_AIF2ADC_COMP                     0x0004  /* AIF2ADC_COMP */
2786  #define WM8994_AIF2ADC_COMP_MASK                0x0004  /* AIF2ADC_COMP */
2787  #define WM8994_AIF2ADC_COMP_SHIFT                    2  /* AIF2ADC_COMP */
2788  #define WM8994_AIF2ADC_COMP_WIDTH                    1  /* AIF2ADC_COMP */
2789  #define WM8994_AIF2ADC_COMPMODE                 0x0002  /* AIF2ADC_COMPMODE */
2790  #define WM8994_AIF2ADC_COMPMODE_MASK            0x0002  /* AIF2ADC_COMPMODE */
2791  #define WM8994_AIF2ADC_COMPMODE_SHIFT                1  /* AIF2ADC_COMPMODE */
2792  #define WM8994_AIF2ADC_COMPMODE_WIDTH                1  /* AIF2ADC_COMPMODE */
2793  #define WM8994_AIF2_LOOPBACK                    0x0001  /* AIF2_LOOPBACK */
2794  #define WM8994_AIF2_LOOPBACK_MASK               0x0001  /* AIF2_LOOPBACK */
2795  #define WM8994_AIF2_LOOPBACK_SHIFT                   0  /* AIF2_LOOPBACK */
2796  #define WM8994_AIF2_LOOPBACK_WIDTH                   1  /* AIF2_LOOPBACK */
2797  
2798  /*
2799   * R786 (0x312) - AIF2 Master/Slave
2800   */
2801  #define WM8994_AIF2_TRI                         0x8000  /* AIF2_TRI */
2802  #define WM8994_AIF2_TRI_MASK                    0x8000  /* AIF2_TRI */
2803  #define WM8994_AIF2_TRI_SHIFT                       15  /* AIF2_TRI */
2804  #define WM8994_AIF2_TRI_WIDTH                        1  /* AIF2_TRI */
2805  #define WM8994_AIF2_MSTR                        0x4000  /* AIF2_MSTR */
2806  #define WM8994_AIF2_MSTR_MASK                   0x4000  /* AIF2_MSTR */
2807  #define WM8994_AIF2_MSTR_SHIFT                      14  /* AIF2_MSTR */
2808  #define WM8994_AIF2_MSTR_WIDTH                       1  /* AIF2_MSTR */
2809  #define WM8994_AIF2_CLK_FRC                     0x2000  /* AIF2_CLK_FRC */
2810  #define WM8994_AIF2_CLK_FRC_MASK                0x2000  /* AIF2_CLK_FRC */
2811  #define WM8994_AIF2_CLK_FRC_SHIFT                   13  /* AIF2_CLK_FRC */
2812  #define WM8994_AIF2_CLK_FRC_WIDTH                    1  /* AIF2_CLK_FRC */
2813  #define WM8994_AIF2_LRCLK_FRC                   0x1000  /* AIF2_LRCLK_FRC */
2814  #define WM8994_AIF2_LRCLK_FRC_MASK              0x1000  /* AIF2_LRCLK_FRC */
2815  #define WM8994_AIF2_LRCLK_FRC_SHIFT                 12  /* AIF2_LRCLK_FRC */
2816  #define WM8994_AIF2_LRCLK_FRC_WIDTH                  1  /* AIF2_LRCLK_FRC */
2817  
2818  /*
2819   * R787 (0x313) - AIF2 BCLK
2820   */
2821  #define WM8994_AIF2_BCLK_DIV_MASK               0x01F0  /* AIF2_BCLK_DIV - [8:4] */
2822  #define WM8994_AIF2_BCLK_DIV_SHIFT                   4  /* AIF2_BCLK_DIV - [8:4] */
2823  #define WM8994_AIF2_BCLK_DIV_WIDTH                   5  /* AIF2_BCLK_DIV - [8:4] */
2824  
2825  /*
2826   * R788 (0x314) - AIF2ADC LRCLK
2827   */
2828  #define WM8994_AIF2ADC_LRCLK_DIR                0x0800  /* AIF2ADC_LRCLK_DIR */
2829  #define WM8994_AIF2ADC_LRCLK_DIR_MASK           0x0800  /* AIF2ADC_LRCLK_DIR */
2830  #define WM8994_AIF2ADC_LRCLK_DIR_SHIFT              11  /* AIF2ADC_LRCLK_DIR */
2831  #define WM8994_AIF2ADC_LRCLK_DIR_WIDTH               1  /* AIF2ADC_LRCLK_DIR */
2832  #define WM8994_AIF2ADC_RATE_MASK                0x07FF  /* AIF2ADC_RATE - [10:0] */
2833  #define WM8994_AIF2ADC_RATE_SHIFT                    0  /* AIF2ADC_RATE - [10:0] */
2834  #define WM8994_AIF2ADC_RATE_WIDTH                   11  /* AIF2ADC_RATE - [10:0] */
2835  
2836  /*
2837   * R789 (0x315) - AIF2DAC LRCLK
2838   */
2839  #define WM8994_AIF2DAC_LRCLK_DIR                0x0800  /* AIF2DAC_LRCLK_DIR */
2840  #define WM8994_AIF2DAC_LRCLK_DIR_MASK           0x0800  /* AIF2DAC_LRCLK_DIR */
2841  #define WM8994_AIF2DAC_LRCLK_DIR_SHIFT              11  /* AIF2DAC_LRCLK_DIR */
2842  #define WM8994_AIF2DAC_LRCLK_DIR_WIDTH               1  /* AIF2DAC_LRCLK_DIR */
2843  #define WM8994_AIF2DAC_RATE_MASK                0x07FF  /* AIF2DAC_RATE - [10:0] */
2844  #define WM8994_AIF2DAC_RATE_SHIFT                    0  /* AIF2DAC_RATE - [10:0] */
2845  #define WM8994_AIF2DAC_RATE_WIDTH                   11  /* AIF2DAC_RATE - [10:0] */
2846  
2847  /*
2848   * R790 (0x316) - AIF2DAC Data
2849   */
2850  #define WM8994_AIF2DACL_DAT_INV                 0x0002  /* AIF2DACL_DAT_INV */
2851  #define WM8994_AIF2DACL_DAT_INV_MASK            0x0002  /* AIF2DACL_DAT_INV */
2852  #define WM8994_AIF2DACL_DAT_INV_SHIFT                1  /* AIF2DACL_DAT_INV */
2853  #define WM8994_AIF2DACL_DAT_INV_WIDTH                1  /* AIF2DACL_DAT_INV */
2854  #define WM8994_AIF2DACR_DAT_INV                 0x0001  /* AIF2DACR_DAT_INV */
2855  #define WM8994_AIF2DACR_DAT_INV_MASK            0x0001  /* AIF2DACR_DAT_INV */
2856  #define WM8994_AIF2DACR_DAT_INV_SHIFT                0  /* AIF2DACR_DAT_INV */
2857  #define WM8994_AIF2DACR_DAT_INV_WIDTH                1  /* AIF2DACR_DAT_INV */
2858  
2859  /*
2860   * R791 (0x317) - AIF2ADC Data
2861   */
2862  #define WM8994_AIF2ADCL_DAT_INV                 0x0002  /* AIF2ADCL_DAT_INV */
2863  #define WM8994_AIF2ADCL_DAT_INV_MASK            0x0002  /* AIF2ADCL_DAT_INV */
2864  #define WM8994_AIF2ADCL_DAT_INV_SHIFT                1  /* AIF2ADCL_DAT_INV */
2865  #define WM8994_AIF2ADCL_DAT_INV_WIDTH                1  /* AIF2ADCL_DAT_INV */
2866  #define WM8994_AIF2ADCR_DAT_INV                 0x0001  /* AIF2ADCR_DAT_INV */
2867  #define WM8994_AIF2ADCR_DAT_INV_MASK            0x0001  /* AIF2ADCR_DAT_INV */
2868  #define WM8994_AIF2ADCR_DAT_INV_SHIFT                0  /* AIF2ADCR_DAT_INV */
2869  #define WM8994_AIF2ADCR_DAT_INV_WIDTH                1  /* AIF2ADCR_DAT_INV */
2870  
2871  /*
2872   * R800 (0x320) - AIF3 Control (1)
2873   */
2874  #define WM8958_AIF3_LRCLK_INV                   0x0080  /* AIF3_LRCLK_INV */
2875  #define WM8958_AIF3_LRCLK_INV_MASK              0x0080  /* AIF3_LRCLK_INV */
2876  #define WM8958_AIF3_LRCLK_INV_SHIFT                  7  /* AIF3_LRCLK_INV */
2877  #define WM8958_AIF3_LRCLK_INV_WIDTH                  1  /* AIF3_LRCLK_INV */
2878  #define WM8958_AIF3_WL_MASK                     0x0060  /* AIF3_WL - [6:5] */
2879  #define WM8958_AIF3_WL_SHIFT                         5  /* AIF3_WL - [6:5] */
2880  #define WM8958_AIF3_WL_WIDTH                         2  /* AIF3_WL - [6:5] */
2881  #define WM8958_AIF3_FMT_MASK                    0x0018  /* AIF3_FMT - [4:3] */
2882  #define WM8958_AIF3_FMT_SHIFT                        3  /* AIF3_FMT - [4:3] */
2883  #define WM8958_AIF3_FMT_WIDTH                        2  /* AIF3_FMT - [4:3] */
2884  
2885  /*
2886   * R801 (0x321) - AIF3 Control (2)
2887   */
2888  #define WM8958_AIF3DAC_BOOST_MASK               0x0C00  /* AIF3DAC_BOOST - [11:10] */
2889  #define WM8958_AIF3DAC_BOOST_SHIFT                  10  /* AIF3DAC_BOOST - [11:10] */
2890  #define WM8958_AIF3DAC_BOOST_WIDTH                   2  /* AIF3DAC_BOOST - [11:10] */
2891  #define WM8958_AIF3DAC_COMP                     0x0010  /* AIF3DAC_COMP */
2892  #define WM8958_AIF3DAC_COMP_MASK                0x0010  /* AIF3DAC_COMP */
2893  #define WM8958_AIF3DAC_COMP_SHIFT                    4  /* AIF3DAC_COMP */
2894  #define WM8958_AIF3DAC_COMP_WIDTH                    1  /* AIF3DAC_COMP */
2895  #define WM8958_AIF3DAC_COMPMODE                 0x0008  /* AIF3DAC_COMPMODE */
2896  #define WM8958_AIF3DAC_COMPMODE_MASK            0x0008  /* AIF3DAC_COMPMODE */
2897  #define WM8958_AIF3DAC_COMPMODE_SHIFT                3  /* AIF3DAC_COMPMODE */
2898  #define WM8958_AIF3DAC_COMPMODE_WIDTH                1  /* AIF3DAC_COMPMODE */
2899  #define WM8958_AIF3ADC_COMP                     0x0004  /* AIF3ADC_COMP */
2900  #define WM8958_AIF3ADC_COMP_MASK                0x0004  /* AIF3ADC_COMP */
2901  #define WM8958_AIF3ADC_COMP_SHIFT                    2  /* AIF3ADC_COMP */
2902  #define WM8958_AIF3ADC_COMP_WIDTH                    1  /* AIF3ADC_COMP */
2903  #define WM8958_AIF3ADC_COMPMODE                 0x0002  /* AIF3ADC_COMPMODE */
2904  #define WM8958_AIF3ADC_COMPMODE_MASK            0x0002  /* AIF3ADC_COMPMODE */
2905  #define WM8958_AIF3ADC_COMPMODE_SHIFT                1  /* AIF3ADC_COMPMODE */
2906  #define WM8958_AIF3ADC_COMPMODE_WIDTH                1  /* AIF3ADC_COMPMODE */
2907  #define WM8958_AIF3_LOOPBACK                    0x0001  /* AIF3_LOOPBACK */
2908  #define WM8958_AIF3_LOOPBACK_MASK               0x0001  /* AIF3_LOOPBACK */
2909  #define WM8958_AIF3_LOOPBACK_SHIFT                   0  /* AIF3_LOOPBACK */
2910  #define WM8958_AIF3_LOOPBACK_WIDTH                   1  /* AIF3_LOOPBACK */
2911  
2912  /*
2913   * R802 (0x322) - AIF3DAC Data
2914   */
2915  #define WM8958_AIF3DAC_DAT_INV                  0x0001  /* AIF3DAC_DAT_INV */
2916  #define WM8958_AIF3DAC_DAT_INV_MASK             0x0001  /* AIF3DAC_DAT_INV */
2917  #define WM8958_AIF3DAC_DAT_INV_SHIFT                 0  /* AIF3DAC_DAT_INV */
2918  #define WM8958_AIF3DAC_DAT_INV_WIDTH                 1  /* AIF3DAC_DAT_INV */
2919  
2920  /*
2921   * R803 (0x323) - AIF3ADC Data
2922   */
2923  #define WM8958_AIF3ADC_DAT_INV                  0x0001  /* AIF3ADC_DAT_INV */
2924  #define WM8958_AIF3ADC_DAT_INV_MASK             0x0001  /* AIF3ADC_DAT_INV */
2925  #define WM8958_AIF3ADC_DAT_INV_SHIFT                 0  /* AIF3ADC_DAT_INV */
2926  #define WM8958_AIF3ADC_DAT_INV_WIDTH                 1  /* AIF3ADC_DAT_INV */
2927  
2928  /*
2929   * R1024 (0x400) - AIF1 ADC1 Left Volume
2930   */
2931  #define WM8994_AIF1ADC1_VU                      0x0100  /* AIF1ADC1_VU */
2932  #define WM8994_AIF1ADC1_VU_MASK                 0x0100  /* AIF1ADC1_VU */
2933  #define WM8994_AIF1ADC1_VU_SHIFT                     8  /* AIF1ADC1_VU */
2934  #define WM8994_AIF1ADC1_VU_WIDTH                     1  /* AIF1ADC1_VU */
2935  #define WM8994_AIF1ADC1L_VOL_MASK               0x00FF  /* AIF1ADC1L_VOL - [7:0] */
2936  #define WM8994_AIF1ADC1L_VOL_SHIFT                   0  /* AIF1ADC1L_VOL - [7:0] */
2937  #define WM8994_AIF1ADC1L_VOL_WIDTH                   8  /* AIF1ADC1L_VOL - [7:0] */
2938  
2939  /*
2940   * R1025 (0x401) - AIF1 ADC1 Right Volume
2941   */
2942  #define WM8994_AIF1ADC1_VU                      0x0100  /* AIF1ADC1_VU */
2943  #define WM8994_AIF1ADC1_VU_MASK                 0x0100  /* AIF1ADC1_VU */
2944  #define WM8994_AIF1ADC1_VU_SHIFT                     8  /* AIF1ADC1_VU */
2945  #define WM8994_AIF1ADC1_VU_WIDTH                     1  /* AIF1ADC1_VU */
2946  #define WM8994_AIF1ADC1R_VOL_MASK               0x00FF  /* AIF1ADC1R_VOL - [7:0] */
2947  #define WM8994_AIF1ADC1R_VOL_SHIFT                   0  /* AIF1ADC1R_VOL - [7:0] */
2948  #define WM8994_AIF1ADC1R_VOL_WIDTH                   8  /* AIF1ADC1R_VOL - [7:0] */
2949  
2950  /*
2951   * R1026 (0x402) - AIF1 DAC1 Left Volume
2952   */
2953  #define WM8994_AIF1DAC1_VU                      0x0100  /* AIF1DAC1_VU */
2954  #define WM8994_AIF1DAC1_VU_MASK                 0x0100  /* AIF1DAC1_VU */
2955  #define WM8994_AIF1DAC1_VU_SHIFT                     8  /* AIF1DAC1_VU */
2956  #define WM8994_AIF1DAC1_VU_WIDTH                     1  /* AIF1DAC1_VU */
2957  #define WM8994_AIF1DAC1L_VOL_MASK               0x00FF  /* AIF1DAC1L_VOL - [7:0] */
2958  #define WM8994_AIF1DAC1L_VOL_SHIFT                   0  /* AIF1DAC1L_VOL - [7:0] */
2959  #define WM8994_AIF1DAC1L_VOL_WIDTH                   8  /* AIF1DAC1L_VOL - [7:0] */
2960  
2961  /*
2962   * R1027 (0x403) - AIF1 DAC1 Right Volume
2963   */
2964  #define WM8994_AIF1DAC1_VU                      0x0100  /* AIF1DAC1_VU */
2965  #define WM8994_AIF1DAC1_VU_MASK                 0x0100  /* AIF1DAC1_VU */
2966  #define WM8994_AIF1DAC1_VU_SHIFT                     8  /* AIF1DAC1_VU */
2967  #define WM8994_AIF1DAC1_VU_WIDTH                     1  /* AIF1DAC1_VU */
2968  #define WM8994_AIF1DAC1R_VOL_MASK               0x00FF  /* AIF1DAC1R_VOL - [7:0] */
2969  #define WM8994_AIF1DAC1R_VOL_SHIFT                   0  /* AIF1DAC1R_VOL - [7:0] */
2970  #define WM8994_AIF1DAC1R_VOL_WIDTH                   8  /* AIF1DAC1R_VOL - [7:0] */
2971  
2972  /*
2973   * R1028 (0x404) - AIF1 ADC2 Left Volume
2974   */
2975  #define WM8994_AIF1ADC2_VU                      0x0100  /* AIF1ADC2_VU */
2976  #define WM8994_AIF1ADC2_VU_MASK                 0x0100  /* AIF1ADC2_VU */
2977  #define WM8994_AIF1ADC2_VU_SHIFT                     8  /* AIF1ADC2_VU */
2978  #define WM8994_AIF1ADC2_VU_WIDTH                     1  /* AIF1ADC2_VU */
2979  #define WM8994_AIF1ADC2L_VOL_MASK               0x00FF  /* AIF1ADC2L_VOL - [7:0] */
2980  #define WM8994_AIF1ADC2L_VOL_SHIFT                   0  /* AIF1ADC2L_VOL - [7:0] */
2981  #define WM8994_AIF1ADC2L_VOL_WIDTH                   8  /* AIF1ADC2L_VOL - [7:0] */
2982  
2983  /*
2984   * R1029 (0x405) - AIF1 ADC2 Right Volume
2985   */
2986  #define WM8994_AIF1ADC2_VU                      0x0100  /* AIF1ADC2_VU */
2987  #define WM8994_AIF1ADC2_VU_MASK                 0x0100  /* AIF1ADC2_VU */
2988  #define WM8994_AIF1ADC2_VU_SHIFT                     8  /* AIF1ADC2_VU */
2989  #define WM8994_AIF1ADC2_VU_WIDTH                     1  /* AIF1ADC2_VU */
2990  #define WM8994_AIF1ADC2R_VOL_MASK               0x00FF  /* AIF1ADC2R_VOL - [7:0] */
2991  #define WM8994_AIF1ADC2R_VOL_SHIFT                   0  /* AIF1ADC2R_VOL - [7:0] */
2992  #define WM8994_AIF1ADC2R_VOL_WIDTH                   8  /* AIF1ADC2R_VOL - [7:0] */
2993  
2994  /*
2995   * R1030 (0x406) - AIF1 DAC2 Left Volume
2996   */
2997  #define WM8994_AIF1DAC2_VU                      0x0100  /* AIF1DAC2_VU */
2998  #define WM8994_AIF1DAC2_VU_MASK                 0x0100  /* AIF1DAC2_VU */
2999  #define WM8994_AIF1DAC2_VU_SHIFT                     8  /* AIF1DAC2_VU */
3000  #define WM8994_AIF1DAC2_VU_WIDTH                     1  /* AIF1DAC2_VU */
3001  #define WM8994_AIF1DAC2L_VOL_MASK               0x00FF  /* AIF1DAC2L_VOL - [7:0] */
3002  #define WM8994_AIF1DAC2L_VOL_SHIFT                   0  /* AIF1DAC2L_VOL - [7:0] */
3003  #define WM8994_AIF1DAC2L_VOL_WIDTH                   8  /* AIF1DAC2L_VOL - [7:0] */
3004  
3005  /*
3006   * R1031 (0x407) - AIF1 DAC2 Right Volume
3007   */
3008  #define WM8994_AIF1DAC2_VU                      0x0100  /* AIF1DAC2_VU */
3009  #define WM8994_AIF1DAC2_VU_MASK                 0x0100  /* AIF1DAC2_VU */
3010  #define WM8994_AIF1DAC2_VU_SHIFT                     8  /* AIF1DAC2_VU */
3011  #define WM8994_AIF1DAC2_VU_WIDTH                     1  /* AIF1DAC2_VU */
3012  #define WM8994_AIF1DAC2R_VOL_MASK               0x00FF  /* AIF1DAC2R_VOL - [7:0] */
3013  #define WM8994_AIF1DAC2R_VOL_SHIFT                   0  /* AIF1DAC2R_VOL - [7:0] */
3014  #define WM8994_AIF1DAC2R_VOL_WIDTH                   8  /* AIF1DAC2R_VOL - [7:0] */
3015  
3016  /*
3017   * R1040 (0x410) - AIF1 ADC1 Filters
3018   */
3019  #define WM8994_AIF1ADC_4FS                      0x8000  /* AIF1ADC_4FS */
3020  #define WM8994_AIF1ADC_4FS_MASK                 0x8000  /* AIF1ADC_4FS */
3021  #define WM8994_AIF1ADC_4FS_SHIFT                    15  /* AIF1ADC_4FS */
3022  #define WM8994_AIF1ADC_4FS_WIDTH                     1  /* AIF1ADC_4FS */
3023  #define WM8994_AIF1ADC1_HPF_CUT_MASK            0x6000  /* AIF1ADC1_HPF_CUT - [14:13] */
3024  #define WM8994_AIF1ADC1_HPF_CUT_SHIFT               13  /* AIF1ADC1_HPF_CUT - [14:13] */
3025  #define WM8994_AIF1ADC1_HPF_CUT_WIDTH                2  /* AIF1ADC1_HPF_CUT - [14:13] */
3026  #define WM8994_AIF1ADC1L_HPF                    0x1000  /* AIF1ADC1L_HPF */
3027  #define WM8994_AIF1ADC1L_HPF_MASK               0x1000  /* AIF1ADC1L_HPF */
3028  #define WM8994_AIF1ADC1L_HPF_SHIFT                  12  /* AIF1ADC1L_HPF */
3029  #define WM8994_AIF1ADC1L_HPF_WIDTH                   1  /* AIF1ADC1L_HPF */
3030  #define WM8994_AIF1ADC1R_HPF                    0x0800  /* AIF1ADC1R_HPF */
3031  #define WM8994_AIF1ADC1R_HPF_MASK               0x0800  /* AIF1ADC1R_HPF */
3032  #define WM8994_AIF1ADC1R_HPF_SHIFT                  11  /* AIF1ADC1R_HPF */
3033  #define WM8994_AIF1ADC1R_HPF_WIDTH                   1  /* AIF1ADC1R_HPF */
3034  
3035  /*
3036   * R1041 (0x411) - AIF1 ADC2 Filters
3037   */
3038  #define WM8994_AIF1ADC2_HPF_CUT_MASK            0x6000  /* AIF1ADC2_HPF_CUT - [14:13] */
3039  #define WM8994_AIF1ADC2_HPF_CUT_SHIFT               13  /* AIF1ADC2_HPF_CUT - [14:13] */
3040  #define WM8994_AIF1ADC2_HPF_CUT_WIDTH                2  /* AIF1ADC2_HPF_CUT - [14:13] */
3041  #define WM8994_AIF1ADC2L_HPF                    0x1000  /* AIF1ADC2L_HPF */
3042  #define WM8994_AIF1ADC2L_HPF_MASK               0x1000  /* AIF1ADC2L_HPF */
3043  #define WM8994_AIF1ADC2L_HPF_SHIFT                  12  /* AIF1ADC2L_HPF */
3044  #define WM8994_AIF1ADC2L_HPF_WIDTH                   1  /* AIF1ADC2L_HPF */
3045  #define WM8994_AIF1ADC2R_HPF                    0x0800  /* AIF1ADC2R_HPF */
3046  #define WM8994_AIF1ADC2R_HPF_MASK               0x0800  /* AIF1ADC2R_HPF */
3047  #define WM8994_AIF1ADC2R_HPF_SHIFT                  11  /* AIF1ADC2R_HPF */
3048  #define WM8994_AIF1ADC2R_HPF_WIDTH                   1  /* AIF1ADC2R_HPF */
3049  
3050  /*
3051   * R1056 (0x420) - AIF1 DAC1 Filters (1)
3052   */
3053  #define WM8994_AIF1DAC1_MUTE                    0x0200  /* AIF1DAC1_MUTE */
3054  #define WM8994_AIF1DAC1_MUTE_MASK               0x0200  /* AIF1DAC1_MUTE */
3055  #define WM8994_AIF1DAC1_MUTE_SHIFT                   9  /* AIF1DAC1_MUTE */
3056  #define WM8994_AIF1DAC1_MUTE_WIDTH                   1  /* AIF1DAC1_MUTE */
3057  #define WM8994_AIF1DAC1_MONO                    0x0080  /* AIF1DAC1_MONO */
3058  #define WM8994_AIF1DAC1_MONO_MASK               0x0080  /* AIF1DAC1_MONO */
3059  #define WM8994_AIF1DAC1_MONO_SHIFT                   7  /* AIF1DAC1_MONO */
3060  #define WM8994_AIF1DAC1_MONO_WIDTH                   1  /* AIF1DAC1_MONO */
3061  #define WM8994_AIF1DAC1_MUTERATE                0x0020  /* AIF1DAC1_MUTERATE */
3062  #define WM8994_AIF1DAC1_MUTERATE_MASK           0x0020  /* AIF1DAC1_MUTERATE */
3063  #define WM8994_AIF1DAC1_MUTERATE_SHIFT               5  /* AIF1DAC1_MUTERATE */
3064  #define WM8994_AIF1DAC1_MUTERATE_WIDTH               1  /* AIF1DAC1_MUTERATE */
3065  #define WM8994_AIF1DAC1_UNMUTE_RAMP             0x0010  /* AIF1DAC1_UNMUTE_RAMP */
3066  #define WM8994_AIF1DAC1_UNMUTE_RAMP_MASK        0x0010  /* AIF1DAC1_UNMUTE_RAMP */
3067  #define WM8994_AIF1DAC1_UNMUTE_RAMP_SHIFT            4  /* AIF1DAC1_UNMUTE_RAMP */
3068  #define WM8994_AIF1DAC1_UNMUTE_RAMP_WIDTH            1  /* AIF1DAC1_UNMUTE_RAMP */
3069  #define WM8994_AIF1DAC1_DEEMP_MASK              0x0006  /* AIF1DAC1_DEEMP - [2:1] */
3070  #define WM8994_AIF1DAC1_DEEMP_SHIFT                  1  /* AIF1DAC1_DEEMP - [2:1] */
3071  #define WM8994_AIF1DAC1_DEEMP_WIDTH                  2  /* AIF1DAC1_DEEMP - [2:1] */
3072  
3073  /*
3074   * R1057 (0x421) - AIF1 DAC1 Filters (2)
3075   */
3076  #define WM8994_AIF1DAC1_3D_GAIN_MASK            0x3E00  /* AIF1DAC1_3D_GAIN - [13:9] */
3077  #define WM8994_AIF1DAC1_3D_GAIN_SHIFT                9  /* AIF1DAC1_3D_GAIN - [13:9] */
3078  #define WM8994_AIF1DAC1_3D_GAIN_WIDTH                5  /* AIF1DAC1_3D_GAIN - [13:9] */
3079  #define WM8994_AIF1DAC1_3D_ENA                  0x0100  /* AIF1DAC1_3D_ENA */
3080  #define WM8994_AIF1DAC1_3D_ENA_MASK             0x0100  /* AIF1DAC1_3D_ENA */
3081  #define WM8994_AIF1DAC1_3D_ENA_SHIFT                 8  /* AIF1DAC1_3D_ENA */
3082  #define WM8994_AIF1DAC1_3D_ENA_WIDTH                 1  /* AIF1DAC1_3D_ENA */
3083  
3084  /*
3085   * R1058 (0x422) - AIF1 DAC2 Filters (1)
3086   */
3087  #define WM8994_AIF1DAC2_MUTE                    0x0200  /* AIF1DAC2_MUTE */
3088  #define WM8994_AIF1DAC2_MUTE_MASK               0x0200  /* AIF1DAC2_MUTE */
3089  #define WM8994_AIF1DAC2_MUTE_SHIFT                   9  /* AIF1DAC2_MUTE */
3090  #define WM8994_AIF1DAC2_MUTE_WIDTH                   1  /* AIF1DAC2_MUTE */
3091  #define WM8994_AIF1DAC2_MONO                    0x0080  /* AIF1DAC2_MONO */
3092  #define WM8994_AIF1DAC2_MONO_MASK               0x0080  /* AIF1DAC2_MONO */
3093  #define WM8994_AIF1DAC2_MONO_SHIFT                   7  /* AIF1DAC2_MONO */
3094  #define WM8994_AIF1DAC2_MONO_WIDTH                   1  /* AIF1DAC2_MONO */
3095  #define WM8994_AIF1DAC2_MUTERATE                0x0020  /* AIF1DAC2_MUTERATE */
3096  #define WM8994_AIF1DAC2_MUTERATE_MASK           0x0020  /* AIF1DAC2_MUTERATE */
3097  #define WM8994_AIF1DAC2_MUTERATE_SHIFT               5  /* AIF1DAC2_MUTERATE */
3098  #define WM8994_AIF1DAC2_MUTERATE_WIDTH               1  /* AIF1DAC2_MUTERATE */
3099  #define WM8994_AIF1DAC2_UNMUTE_RAMP             0x0010  /* AIF1DAC2_UNMUTE_RAMP */
3100  #define WM8994_AIF1DAC2_UNMUTE_RAMP_MASK        0x0010  /* AIF1DAC2_UNMUTE_RAMP */
3101  #define WM8994_AIF1DAC2_UNMUTE_RAMP_SHIFT            4  /* AIF1DAC2_UNMUTE_RAMP */
3102  #define WM8994_AIF1DAC2_UNMUTE_RAMP_WIDTH            1  /* AIF1DAC2_UNMUTE_RAMP */
3103  #define WM8994_AIF1DAC2_DEEMP_MASK              0x0006  /* AIF1DAC2_DEEMP - [2:1] */
3104  #define WM8994_AIF1DAC2_DEEMP_SHIFT                  1  /* AIF1DAC2_DEEMP - [2:1] */
3105  #define WM8994_AIF1DAC2_DEEMP_WIDTH                  2  /* AIF1DAC2_DEEMP - [2:1] */
3106  
3107  /*
3108   * R1059 (0x423) - AIF1 DAC2 Filters (2)
3109   */
3110  #define WM8994_AIF1DAC2_3D_GAIN_MASK            0x3E00  /* AIF1DAC2_3D_GAIN - [13:9] */
3111  #define WM8994_AIF1DAC2_3D_GAIN_SHIFT                9  /* AIF1DAC2_3D_GAIN - [13:9] */
3112  #define WM8994_AIF1DAC2_3D_GAIN_WIDTH                5  /* AIF1DAC2_3D_GAIN - [13:9] */
3113  #define WM8994_AIF1DAC2_3D_ENA                  0x0100  /* AIF1DAC2_3D_ENA */
3114  #define WM8994_AIF1DAC2_3D_ENA_MASK             0x0100  /* AIF1DAC2_3D_ENA */
3115  #define WM8994_AIF1DAC2_3D_ENA_SHIFT                 8  /* AIF1DAC2_3D_ENA */
3116  #define WM8994_AIF1DAC2_3D_ENA_WIDTH                 1  /* AIF1DAC2_3D_ENA */
3117  
3118  /*
3119   * R1072 (0x430) - AIF1 DAC1 Noise Gate
3120   */
3121  #define WM8958_AIF1DAC1_NG_HLD_MASK             0x0060  /* AIF1DAC1_NG_HLD - [6:5] */
3122  #define WM8958_AIF1DAC1_NG_HLD_SHIFT                 5  /* AIF1DAC1_NG_HLD - [6:5] */
3123  #define WM8958_AIF1DAC1_NG_HLD_WIDTH                 2  /* AIF1DAC1_NG_HLD - [6:5] */
3124  #define WM8958_AIF1DAC1_NG_THR_MASK             0x000E  /* AIF1DAC1_NG_THR - [3:1] */
3125  #define WM8958_AIF1DAC1_NG_THR_SHIFT                 1  /* AIF1DAC1_NG_THR - [3:1] */
3126  #define WM8958_AIF1DAC1_NG_THR_WIDTH                 3  /* AIF1DAC1_NG_THR - [3:1] */
3127  #define WM8958_AIF1DAC1_NG_ENA                  0x0001  /* AIF1DAC1_NG_ENA */
3128  #define WM8958_AIF1DAC1_NG_ENA_MASK             0x0001  /* AIF1DAC1_NG_ENA */
3129  #define WM8958_AIF1DAC1_NG_ENA_SHIFT                 0  /* AIF1DAC1_NG_ENA */
3130  #define WM8958_AIF1DAC1_NG_ENA_WIDTH                 1  /* AIF1DAC1_NG_ENA */
3131  
3132  /*
3133   * R1073 (0x431) - AIF1 DAC2 Noise Gate
3134   */
3135  #define WM8958_AIF1DAC2_NG_HLD_MASK             0x0060  /* AIF1DAC2_NG_HLD - [6:5] */
3136  #define WM8958_AIF1DAC2_NG_HLD_SHIFT                 5  /* AIF1DAC2_NG_HLD - [6:5] */
3137  #define WM8958_AIF1DAC2_NG_HLD_WIDTH                 2  /* AIF1DAC2_NG_HLD - [6:5] */
3138  #define WM8958_AIF1DAC2_NG_THR_MASK             0x000E  /* AIF1DAC2_NG_THR - [3:1] */
3139  #define WM8958_AIF1DAC2_NG_THR_SHIFT                 1  /* AIF1DAC2_NG_THR - [3:1] */
3140  #define WM8958_AIF1DAC2_NG_THR_WIDTH                 3  /* AIF1DAC2_NG_THR - [3:1] */
3141  #define WM8958_AIF1DAC2_NG_ENA                  0x0001  /* AIF1DAC2_NG_ENA */
3142  #define WM8958_AIF1DAC2_NG_ENA_MASK             0x0001  /* AIF1DAC2_NG_ENA */
3143  #define WM8958_AIF1DAC2_NG_ENA_SHIFT                 0  /* AIF1DAC2_NG_ENA */
3144  #define WM8958_AIF1DAC2_NG_ENA_WIDTH                 1  /* AIF1DAC2_NG_ENA */
3145  
3146  /*
3147   * R1088 (0x440) - AIF1 DRC1 (1)
3148   */
3149  #define WM8994_AIF1DRC1_SIG_DET_RMS_MASK        0xF800  /* AIF1DRC1_SIG_DET_RMS - [15:11] */
3150  #define WM8994_AIF1DRC1_SIG_DET_RMS_SHIFT           11  /* AIF1DRC1_SIG_DET_RMS - [15:11] */
3151  #define WM8994_AIF1DRC1_SIG_DET_RMS_WIDTH            5  /* AIF1DRC1_SIG_DET_RMS - [15:11] */
3152  #define WM8994_AIF1DRC1_SIG_DET_PK_MASK         0x0600  /* AIF1DRC1_SIG_DET_PK - [10:9] */
3153  #define WM8994_AIF1DRC1_SIG_DET_PK_SHIFT             9  /* AIF1DRC1_SIG_DET_PK - [10:9] */
3154  #define WM8994_AIF1DRC1_SIG_DET_PK_WIDTH             2  /* AIF1DRC1_SIG_DET_PK - [10:9] */
3155  #define WM8994_AIF1DRC1_NG_ENA                  0x0100  /* AIF1DRC1_NG_ENA */
3156  #define WM8994_AIF1DRC1_NG_ENA_MASK             0x0100  /* AIF1DRC1_NG_ENA */
3157  #define WM8994_AIF1DRC1_NG_ENA_SHIFT                 8  /* AIF1DRC1_NG_ENA */
3158  #define WM8994_AIF1DRC1_NG_ENA_WIDTH                 1  /* AIF1DRC1_NG_ENA */
3159  #define WM8994_AIF1DRC1_SIG_DET_MODE            0x0080  /* AIF1DRC1_SIG_DET_MODE */
3160  #define WM8994_AIF1DRC1_SIG_DET_MODE_MASK       0x0080  /* AIF1DRC1_SIG_DET_MODE */
3161  #define WM8994_AIF1DRC1_SIG_DET_MODE_SHIFT           7  /* AIF1DRC1_SIG_DET_MODE */
3162  #define WM8994_AIF1DRC1_SIG_DET_MODE_WIDTH           1  /* AIF1DRC1_SIG_DET_MODE */
3163  #define WM8994_AIF1DRC1_SIG_DET                 0x0040  /* AIF1DRC1_SIG_DET */
3164  #define WM8994_AIF1DRC1_SIG_DET_MASK            0x0040  /* AIF1DRC1_SIG_DET */
3165  #define WM8994_AIF1DRC1_SIG_DET_SHIFT                6  /* AIF1DRC1_SIG_DET */
3166  #define WM8994_AIF1DRC1_SIG_DET_WIDTH                1  /* AIF1DRC1_SIG_DET */
3167  #define WM8994_AIF1DRC1_KNEE2_OP_ENA            0x0020  /* AIF1DRC1_KNEE2_OP_ENA */
3168  #define WM8994_AIF1DRC1_KNEE2_OP_ENA_MASK       0x0020  /* AIF1DRC1_KNEE2_OP_ENA */
3169  #define WM8994_AIF1DRC1_KNEE2_OP_ENA_SHIFT           5  /* AIF1DRC1_KNEE2_OP_ENA */
3170  #define WM8994_AIF1DRC1_KNEE2_OP_ENA_WIDTH           1  /* AIF1DRC1_KNEE2_OP_ENA */
3171  #define WM8994_AIF1DRC1_QR                      0x0010  /* AIF1DRC1_QR */
3172  #define WM8994_AIF1DRC1_QR_MASK                 0x0010  /* AIF1DRC1_QR */
3173  #define WM8994_AIF1DRC1_QR_SHIFT                     4  /* AIF1DRC1_QR */
3174  #define WM8994_AIF1DRC1_QR_WIDTH                     1  /* AIF1DRC1_QR */
3175  #define WM8994_AIF1DRC1_ANTICLIP                0x0008  /* AIF1DRC1_ANTICLIP */
3176  #define WM8994_AIF1DRC1_ANTICLIP_MASK           0x0008  /* AIF1DRC1_ANTICLIP */
3177  #define WM8994_AIF1DRC1_ANTICLIP_SHIFT               3  /* AIF1DRC1_ANTICLIP */
3178  #define WM8994_AIF1DRC1_ANTICLIP_WIDTH               1  /* AIF1DRC1_ANTICLIP */
3179  #define WM8994_AIF1DAC1_DRC_ENA                 0x0004  /* AIF1DAC1_DRC_ENA */
3180  #define WM8994_AIF1DAC1_DRC_ENA_MASK            0x0004  /* AIF1DAC1_DRC_ENA */
3181  #define WM8994_AIF1DAC1_DRC_ENA_SHIFT                2  /* AIF1DAC1_DRC_ENA */
3182  #define WM8994_AIF1DAC1_DRC_ENA_WIDTH                1  /* AIF1DAC1_DRC_ENA */
3183  #define WM8994_AIF1ADC1L_DRC_ENA                0x0002  /* AIF1ADC1L_DRC_ENA */
3184  #define WM8994_AIF1ADC1L_DRC_ENA_MASK           0x0002  /* AIF1ADC1L_DRC_ENA */
3185  #define WM8994_AIF1ADC1L_DRC_ENA_SHIFT               1  /* AIF1ADC1L_DRC_ENA */
3186  #define WM8994_AIF1ADC1L_DRC_ENA_WIDTH               1  /* AIF1ADC1L_DRC_ENA */
3187  #define WM8994_AIF1ADC1R_DRC_ENA                0x0001  /* AIF1ADC1R_DRC_ENA */
3188  #define WM8994_AIF1ADC1R_DRC_ENA_MASK           0x0001  /* AIF1ADC1R_DRC_ENA */
3189  #define WM8994_AIF1ADC1R_DRC_ENA_SHIFT               0  /* AIF1ADC1R_DRC_ENA */
3190  #define WM8994_AIF1ADC1R_DRC_ENA_WIDTH               1  /* AIF1ADC1R_DRC_ENA */
3191  
3192  /*
3193   * R1089 (0x441) - AIF1 DRC1 (2)
3194   */
3195  #define WM8994_AIF1DRC1_ATK_MASK                0x1E00  /* AIF1DRC1_ATK - [12:9] */
3196  #define WM8994_AIF1DRC1_ATK_SHIFT                    9  /* AIF1DRC1_ATK - [12:9] */
3197  #define WM8994_AIF1DRC1_ATK_WIDTH                    4  /* AIF1DRC1_ATK - [12:9] */
3198  #define WM8994_AIF1DRC1_DCY_MASK                0x01E0  /* AIF1DRC1_DCY - [8:5] */
3199  #define WM8994_AIF1DRC1_DCY_SHIFT                    5  /* AIF1DRC1_DCY - [8:5] */
3200  #define WM8994_AIF1DRC1_DCY_WIDTH                    4  /* AIF1DRC1_DCY - [8:5] */
3201  #define WM8994_AIF1DRC1_MINGAIN_MASK            0x001C  /* AIF1DRC1_MINGAIN - [4:2] */
3202  #define WM8994_AIF1DRC1_MINGAIN_SHIFT                2  /* AIF1DRC1_MINGAIN - [4:2] */
3203  #define WM8994_AIF1DRC1_MINGAIN_WIDTH                3  /* AIF1DRC1_MINGAIN - [4:2] */
3204  #define WM8994_AIF1DRC1_MAXGAIN_MASK            0x0003  /* AIF1DRC1_MAXGAIN - [1:0] */
3205  #define WM8994_AIF1DRC1_MAXGAIN_SHIFT                0  /* AIF1DRC1_MAXGAIN - [1:0] */
3206  #define WM8994_AIF1DRC1_MAXGAIN_WIDTH                2  /* AIF1DRC1_MAXGAIN - [1:0] */
3207  
3208  /*
3209   * R1090 (0x442) - AIF1 DRC1 (3)
3210   */
3211  #define WM8994_AIF1DRC1_NG_MINGAIN_MASK         0xF000  /* AIF1DRC1_NG_MINGAIN - [15:12] */
3212  #define WM8994_AIF1DRC1_NG_MINGAIN_SHIFT            12  /* AIF1DRC1_NG_MINGAIN - [15:12] */
3213  #define WM8994_AIF1DRC1_NG_MINGAIN_WIDTH             4  /* AIF1DRC1_NG_MINGAIN - [15:12] */
3214  #define WM8994_AIF1DRC1_NG_EXP_MASK             0x0C00  /* AIF1DRC1_NG_EXP - [11:10] */
3215  #define WM8994_AIF1DRC1_NG_EXP_SHIFT                10  /* AIF1DRC1_NG_EXP - [11:10] */
3216  #define WM8994_AIF1DRC1_NG_EXP_WIDTH                 2  /* AIF1DRC1_NG_EXP - [11:10] */
3217  #define WM8994_AIF1DRC1_QR_THR_MASK             0x0300  /* AIF1DRC1_QR_THR - [9:8] */
3218  #define WM8994_AIF1DRC1_QR_THR_SHIFT                 8  /* AIF1DRC1_QR_THR - [9:8] */
3219  #define WM8994_AIF1DRC1_QR_THR_WIDTH                 2  /* AIF1DRC1_QR_THR - [9:8] */
3220  #define WM8994_AIF1DRC1_QR_DCY_MASK             0x00C0  /* AIF1DRC1_QR_DCY - [7:6] */
3221  #define WM8994_AIF1DRC1_QR_DCY_SHIFT                 6  /* AIF1DRC1_QR_DCY - [7:6] */
3222  #define WM8994_AIF1DRC1_QR_DCY_WIDTH                 2  /* AIF1DRC1_QR_DCY - [7:6] */
3223  #define WM8994_AIF1DRC1_HI_COMP_MASK            0x0038  /* AIF1DRC1_HI_COMP - [5:3] */
3224  #define WM8994_AIF1DRC1_HI_COMP_SHIFT                3  /* AIF1DRC1_HI_COMP - [5:3] */
3225  #define WM8994_AIF1DRC1_HI_COMP_WIDTH                3  /* AIF1DRC1_HI_COMP - [5:3] */
3226  #define WM8994_AIF1DRC1_LO_COMP_MASK            0x0007  /* AIF1DRC1_LO_COMP - [2:0] */
3227  #define WM8994_AIF1DRC1_LO_COMP_SHIFT                0  /* AIF1DRC1_LO_COMP - [2:0] */
3228  #define WM8994_AIF1DRC1_LO_COMP_WIDTH                3  /* AIF1DRC1_LO_COMP - [2:0] */
3229  
3230  /*
3231   * R1091 (0x443) - AIF1 DRC1 (4)
3232   */
3233  #define WM8994_AIF1DRC1_KNEE_IP_MASK            0x07E0  /* AIF1DRC1_KNEE_IP - [10:5] */
3234  #define WM8994_AIF1DRC1_KNEE_IP_SHIFT                5  /* AIF1DRC1_KNEE_IP - [10:5] */
3235  #define WM8994_AIF1DRC1_KNEE_IP_WIDTH                6  /* AIF1DRC1_KNEE_IP - [10:5] */
3236  #define WM8994_AIF1DRC1_KNEE_OP_MASK            0x001F  /* AIF1DRC1_KNEE_OP - [4:0] */
3237  #define WM8994_AIF1DRC1_KNEE_OP_SHIFT                0  /* AIF1DRC1_KNEE_OP - [4:0] */
3238  #define WM8994_AIF1DRC1_KNEE_OP_WIDTH                5  /* AIF1DRC1_KNEE_OP - [4:0] */
3239  
3240  /*
3241   * R1092 (0x444) - AIF1 DRC1 (5)
3242   */
3243  #define WM8994_AIF1DRC1_KNEE2_IP_MASK           0x03E0  /* AIF1DRC1_KNEE2_IP - [9:5] */
3244  #define WM8994_AIF1DRC1_KNEE2_IP_SHIFT               5  /* AIF1DRC1_KNEE2_IP - [9:5] */
3245  #define WM8994_AIF1DRC1_KNEE2_IP_WIDTH               5  /* AIF1DRC1_KNEE2_IP - [9:5] */
3246  #define WM8994_AIF1DRC1_KNEE2_OP_MASK           0x001F  /* AIF1DRC1_KNEE2_OP - [4:0] */
3247  #define WM8994_AIF1DRC1_KNEE2_OP_SHIFT               0  /* AIF1DRC1_KNEE2_OP - [4:0] */
3248  #define WM8994_AIF1DRC1_KNEE2_OP_WIDTH               5  /* AIF1DRC1_KNEE2_OP - [4:0] */
3249  
3250  /*
3251   * R1104 (0x450) - AIF1 DRC2 (1)
3252   */
3253  #define WM8994_AIF1DRC2_SIG_DET_RMS_MASK        0xF800  /* AIF1DRC2_SIG_DET_RMS - [15:11] */
3254  #define WM8994_AIF1DRC2_SIG_DET_RMS_SHIFT           11  /* AIF1DRC2_SIG_DET_RMS - [15:11] */
3255  #define WM8994_AIF1DRC2_SIG_DET_RMS_WIDTH            5  /* AIF1DRC2_SIG_DET_RMS - [15:11] */
3256  #define WM8994_AIF1DRC2_SIG_DET_PK_MASK         0x0600  /* AIF1DRC2_SIG_DET_PK - [10:9] */
3257  #define WM8994_AIF1DRC2_SIG_DET_PK_SHIFT             9  /* AIF1DRC2_SIG_DET_PK - [10:9] */
3258  #define WM8994_AIF1DRC2_SIG_DET_PK_WIDTH             2  /* AIF1DRC2_SIG_DET_PK - [10:9] */
3259  #define WM8994_AIF1DRC2_NG_ENA                  0x0100  /* AIF1DRC2_NG_ENA */
3260  #define WM8994_AIF1DRC2_NG_ENA_MASK             0x0100  /* AIF1DRC2_NG_ENA */
3261  #define WM8994_AIF1DRC2_NG_ENA_SHIFT                 8  /* AIF1DRC2_NG_ENA */
3262  #define WM8994_AIF1DRC2_NG_ENA_WIDTH                 1  /* AIF1DRC2_NG_ENA */
3263  #define WM8994_AIF1DRC2_SIG_DET_MODE            0x0080  /* AIF1DRC2_SIG_DET_MODE */
3264  #define WM8994_AIF1DRC2_SIG_DET_MODE_MASK       0x0080  /* AIF1DRC2_SIG_DET_MODE */
3265  #define WM8994_AIF1DRC2_SIG_DET_MODE_SHIFT           7  /* AIF1DRC2_SIG_DET_MODE */
3266  #define WM8994_AIF1DRC2_SIG_DET_MODE_WIDTH           1  /* AIF1DRC2_SIG_DET_MODE */
3267  #define WM8994_AIF1DRC2_SIG_DET                 0x0040  /* AIF1DRC2_SIG_DET */
3268  #define WM8994_AIF1DRC2_SIG_DET_MASK            0x0040  /* AIF1DRC2_SIG_DET */
3269  #define WM8994_AIF1DRC2_SIG_DET_SHIFT                6  /* AIF1DRC2_SIG_DET */
3270  #define WM8994_AIF1DRC2_SIG_DET_WIDTH                1  /* AIF1DRC2_SIG_DET */
3271  #define WM8994_AIF1DRC2_KNEE2_OP_ENA            0x0020  /* AIF1DRC2_KNEE2_OP_ENA */
3272  #define WM8994_AIF1DRC2_KNEE2_OP_ENA_MASK       0x0020  /* AIF1DRC2_KNEE2_OP_ENA */
3273  #define WM8994_AIF1DRC2_KNEE2_OP_ENA_SHIFT           5  /* AIF1DRC2_KNEE2_OP_ENA */
3274  #define WM8994_AIF1DRC2_KNEE2_OP_ENA_WIDTH           1  /* AIF1DRC2_KNEE2_OP_ENA */
3275  #define WM8994_AIF1DRC2_QR                      0x0010  /* AIF1DRC2_QR */
3276  #define WM8994_AIF1DRC2_QR_MASK                 0x0010  /* AIF1DRC2_QR */
3277  #define WM8994_AIF1DRC2_QR_SHIFT                     4  /* AIF1DRC2_QR */
3278  #define WM8994_AIF1DRC2_QR_WIDTH                     1  /* AIF1DRC2_QR */
3279  #define WM8994_AIF1DRC2_ANTICLIP                0x0008  /* AIF1DRC2_ANTICLIP */
3280  #define WM8994_AIF1DRC2_ANTICLIP_MASK           0x0008  /* AIF1DRC2_ANTICLIP */
3281  #define WM8994_AIF1DRC2_ANTICLIP_SHIFT               3  /* AIF1DRC2_ANTICLIP */
3282  #define WM8994_AIF1DRC2_ANTICLIP_WIDTH               1  /* AIF1DRC2_ANTICLIP */
3283  #define WM8994_AIF1DAC2_DRC_ENA                 0x0004  /* AIF1DAC2_DRC_ENA */
3284  #define WM8994_AIF1DAC2_DRC_ENA_MASK            0x0004  /* AIF1DAC2_DRC_ENA */
3285  #define WM8994_AIF1DAC2_DRC_ENA_SHIFT                2  /* AIF1DAC2_DRC_ENA */
3286  #define WM8994_AIF1DAC2_DRC_ENA_WIDTH                1  /* AIF1DAC2_DRC_ENA */
3287  #define WM8994_AIF1ADC2L_DRC_ENA                0x0002  /* AIF1ADC2L_DRC_ENA */
3288  #define WM8994_AIF1ADC2L_DRC_ENA_MASK           0x0002  /* AIF1ADC2L_DRC_ENA */
3289  #define WM8994_AIF1ADC2L_DRC_ENA_SHIFT               1  /* AIF1ADC2L_DRC_ENA */
3290  #define WM8994_AIF1ADC2L_DRC_ENA_WIDTH               1  /* AIF1ADC2L_DRC_ENA */
3291  #define WM8994_AIF1ADC2R_DRC_ENA                0x0001  /* AIF1ADC2R_DRC_ENA */
3292  #define WM8994_AIF1ADC2R_DRC_ENA_MASK           0x0001  /* AIF1ADC2R_DRC_ENA */
3293  #define WM8994_AIF1ADC2R_DRC_ENA_SHIFT               0  /* AIF1ADC2R_DRC_ENA */
3294  #define WM8994_AIF1ADC2R_DRC_ENA_WIDTH               1  /* AIF1ADC2R_DRC_ENA */
3295  
3296  /*
3297   * R1105 (0x451) - AIF1 DRC2 (2)
3298   */
3299  #define WM8994_AIF1DRC2_ATK_MASK                0x1E00  /* AIF1DRC2_ATK - [12:9] */
3300  #define WM8994_AIF1DRC2_ATK_SHIFT                    9  /* AIF1DRC2_ATK - [12:9] */
3301  #define WM8994_AIF1DRC2_ATK_WIDTH                    4  /* AIF1DRC2_ATK - [12:9] */
3302  #define WM8994_AIF1DRC2_DCY_MASK                0x01E0  /* AIF1DRC2_DCY - [8:5] */
3303  #define WM8994_AIF1DRC2_DCY_SHIFT                    5  /* AIF1DRC2_DCY - [8:5] */
3304  #define WM8994_AIF1DRC2_DCY_WIDTH                    4  /* AIF1DRC2_DCY - [8:5] */
3305  #define WM8994_AIF1DRC2_MINGAIN_MASK            0x001C  /* AIF1DRC2_MINGAIN - [4:2] */
3306  #define WM8994_AIF1DRC2_MINGAIN_SHIFT                2  /* AIF1DRC2_MINGAIN - [4:2] */
3307  #define WM8994_AIF1DRC2_MINGAIN_WIDTH                3  /* AIF1DRC2_MINGAIN - [4:2] */
3308  #define WM8994_AIF1DRC2_MAXGAIN_MASK            0x0003  /* AIF1DRC2_MAXGAIN - [1:0] */
3309  #define WM8994_AIF1DRC2_MAXGAIN_SHIFT                0  /* AIF1DRC2_MAXGAIN - [1:0] */
3310  #define WM8994_AIF1DRC2_MAXGAIN_WIDTH                2  /* AIF1DRC2_MAXGAIN - [1:0] */
3311  
3312  /*
3313   * R1106 (0x452) - AIF1 DRC2 (3)
3314   */
3315  #define WM8994_AIF1DRC2_NG_MINGAIN_MASK         0xF000  /* AIF1DRC2_NG_MINGAIN - [15:12] */
3316  #define WM8994_AIF1DRC2_NG_MINGAIN_SHIFT            12  /* AIF1DRC2_NG_MINGAIN - [15:12] */
3317  #define WM8994_AIF1DRC2_NG_MINGAIN_WIDTH             4  /* AIF1DRC2_NG_MINGAIN - [15:12] */
3318  #define WM8994_AIF1DRC2_NG_EXP_MASK             0x0C00  /* AIF1DRC2_NG_EXP - [11:10] */
3319  #define WM8994_AIF1DRC2_NG_EXP_SHIFT                10  /* AIF1DRC2_NG_EXP - [11:10] */
3320  #define WM8994_AIF1DRC2_NG_EXP_WIDTH                 2  /* AIF1DRC2_NG_EXP - [11:10] */
3321  #define WM8994_AIF1DRC2_QR_THR_MASK             0x0300  /* AIF1DRC2_QR_THR - [9:8] */
3322  #define WM8994_AIF1DRC2_QR_THR_SHIFT                 8  /* AIF1DRC2_QR_THR - [9:8] */
3323  #define WM8994_AIF1DRC2_QR_THR_WIDTH                 2  /* AIF1DRC2_QR_THR - [9:8] */
3324  #define WM8994_AIF1DRC2_QR_DCY_MASK             0x00C0  /* AIF1DRC2_QR_DCY - [7:6] */
3325  #define WM8994_AIF1DRC2_QR_DCY_SHIFT                 6  /* AIF1DRC2_QR_DCY - [7:6] */
3326  #define WM8994_AIF1DRC2_QR_DCY_WIDTH                 2  /* AIF1DRC2_QR_DCY - [7:6] */
3327  #define WM8994_AIF1DRC2_HI_COMP_MASK            0x0038  /* AIF1DRC2_HI_COMP - [5:3] */
3328  #define WM8994_AIF1DRC2_HI_COMP_SHIFT                3  /* AIF1DRC2_HI_COMP - [5:3] */
3329  #define WM8994_AIF1DRC2_HI_COMP_WIDTH                3  /* AIF1DRC2_HI_COMP - [5:3] */
3330  #define WM8994_AIF1DRC2_LO_COMP_MASK            0x0007  /* AIF1DRC2_LO_COMP - [2:0] */
3331  #define WM8994_AIF1DRC2_LO_COMP_SHIFT                0  /* AIF1DRC2_LO_COMP - [2:0] */
3332  #define WM8994_AIF1DRC2_LO_COMP_WIDTH                3  /* AIF1DRC2_LO_COMP - [2:0] */
3333  
3334  /*
3335   * R1107 (0x453) - AIF1 DRC2 (4)
3336   */
3337  #define WM8994_AIF1DRC2_KNEE_IP_MASK            0x07E0  /* AIF1DRC2_KNEE_IP - [10:5] */
3338  #define WM8994_AIF1DRC2_KNEE_IP_SHIFT                5  /* AIF1DRC2_KNEE_IP - [10:5] */
3339  #define WM8994_AIF1DRC2_KNEE_IP_WIDTH                6  /* AIF1DRC2_KNEE_IP - [10:5] */
3340  #define WM8994_AIF1DRC2_KNEE_OP_MASK            0x001F  /* AIF1DRC2_KNEE_OP - [4:0] */
3341  #define WM8994_AIF1DRC2_KNEE_OP_SHIFT                0  /* AIF1DRC2_KNEE_OP - [4:0] */
3342  #define WM8994_AIF1DRC2_KNEE_OP_WIDTH                5  /* AIF1DRC2_KNEE_OP - [4:0] */
3343  
3344  /*
3345   * R1108 (0x454) - AIF1 DRC2 (5)
3346   */
3347  #define WM8994_AIF1DRC2_KNEE2_IP_MASK           0x03E0  /* AIF1DRC2_KNEE2_IP - [9:5] */
3348  #define WM8994_AIF1DRC2_KNEE2_IP_SHIFT               5  /* AIF1DRC2_KNEE2_IP - [9:5] */
3349  #define WM8994_AIF1DRC2_KNEE2_IP_WIDTH               5  /* AIF1DRC2_KNEE2_IP - [9:5] */
3350  #define WM8994_AIF1DRC2_KNEE2_OP_MASK           0x001F  /* AIF1DRC2_KNEE2_OP - [4:0] */
3351  #define WM8994_AIF1DRC2_KNEE2_OP_SHIFT               0  /* AIF1DRC2_KNEE2_OP - [4:0] */
3352  #define WM8994_AIF1DRC2_KNEE2_OP_WIDTH               5  /* AIF1DRC2_KNEE2_OP - [4:0] */
3353  
3354  /*
3355   * R1152 (0x480) - AIF1 DAC1 EQ Gains (1)
3356   */
3357  #define WM8994_AIF1DAC1_EQ_B1_GAIN_MASK         0xF800  /* AIF1DAC1_EQ_B1_GAIN - [15:11] */
3358  #define WM8994_AIF1DAC1_EQ_B1_GAIN_SHIFT            11  /* AIF1DAC1_EQ_B1_GAIN - [15:11] */
3359  #define WM8994_AIF1DAC1_EQ_B1_GAIN_WIDTH             5  /* AIF1DAC1_EQ_B1_GAIN - [15:11] */
3360  #define WM8994_AIF1DAC1_EQ_B2_GAIN_MASK         0x07C0  /* AIF1DAC1_EQ_B2_GAIN - [10:6] */
3361  #define WM8994_AIF1DAC1_EQ_B2_GAIN_SHIFT             6  /* AIF1DAC1_EQ_B2_GAIN - [10:6] */
3362  #define WM8994_AIF1DAC1_EQ_B2_GAIN_WIDTH             5  /* AIF1DAC1_EQ_B2_GAIN - [10:6] */
3363  #define WM8994_AIF1DAC1_EQ_B3_GAIN_MASK         0x003E  /* AIF1DAC1_EQ_B3_GAIN - [5:1] */
3364  #define WM8994_AIF1DAC1_EQ_B3_GAIN_SHIFT             1  /* AIF1DAC1_EQ_B3_GAIN - [5:1] */
3365  #define WM8994_AIF1DAC1_EQ_B3_GAIN_WIDTH             5  /* AIF1DAC1_EQ_B3_GAIN - [5:1] */
3366  #define WM8994_AIF1DAC1_EQ_ENA                  0x0001  /* AIF1DAC1_EQ_ENA */
3367  #define WM8994_AIF1DAC1_EQ_ENA_MASK             0x0001  /* AIF1DAC1_EQ_ENA */
3368  #define WM8994_AIF1DAC1_EQ_ENA_SHIFT                 0  /* AIF1DAC1_EQ_ENA */
3369  #define WM8994_AIF1DAC1_EQ_ENA_WIDTH                 1  /* AIF1DAC1_EQ_ENA */
3370  
3371  /*
3372   * R1153 (0x481) - AIF1 DAC1 EQ Gains (2)
3373   */
3374  #define WM8994_AIF1DAC1_EQ_B4_GAIN_MASK         0xF800  /* AIF1DAC1_EQ_B4_GAIN - [15:11] */
3375  #define WM8994_AIF1DAC1_EQ_B4_GAIN_SHIFT            11  /* AIF1DAC1_EQ_B4_GAIN - [15:11] */
3376  #define WM8994_AIF1DAC1_EQ_B4_GAIN_WIDTH             5  /* AIF1DAC1_EQ_B4_GAIN - [15:11] */
3377  #define WM8994_AIF1DAC1_EQ_B5_GAIN_MASK         0x07C0  /* AIF1DAC1_EQ_B5_GAIN - [10:6] */
3378  #define WM8994_AIF1DAC1_EQ_B5_GAIN_SHIFT             6  /* AIF1DAC1_EQ_B5_GAIN - [10:6] */
3379  #define WM8994_AIF1DAC1_EQ_B5_GAIN_WIDTH             5  /* AIF1DAC1_EQ_B5_GAIN - [10:6] */
3380  
3381  /*
3382   * R1154 (0x482) - AIF1 DAC1 EQ Band 1 A
3383   */
3384  #define WM8994_AIF1DAC1_EQ_B1_A_MASK            0xFFFF  /* AIF1DAC1_EQ_B1_A - [15:0] */
3385  #define WM8994_AIF1DAC1_EQ_B1_A_SHIFT                0  /* AIF1DAC1_EQ_B1_A - [15:0] */
3386  #define WM8994_AIF1DAC1_EQ_B1_A_WIDTH               16  /* AIF1DAC1_EQ_B1_A - [15:0] */
3387  
3388  /*
3389   * R1155 (0x483) - AIF1 DAC1 EQ Band 1 B
3390   */
3391  #define WM8994_AIF1DAC1_EQ_B1_B_MASK            0xFFFF  /* AIF1DAC1_EQ_B1_B - [15:0] */
3392  #define WM8994_AIF1DAC1_EQ_B1_B_SHIFT                0  /* AIF1DAC1_EQ_B1_B - [15:0] */
3393  #define WM8994_AIF1DAC1_EQ_B1_B_WIDTH               16  /* AIF1DAC1_EQ_B1_B - [15:0] */
3394  
3395  /*
3396   * R1156 (0x484) - AIF1 DAC1 EQ Band 1 PG
3397   */
3398  #define WM8994_AIF1DAC1_EQ_B1_PG_MASK           0xFFFF  /* AIF1DAC1_EQ_B1_PG - [15:0] */
3399  #define WM8994_AIF1DAC1_EQ_B1_PG_SHIFT               0  /* AIF1DAC1_EQ_B1_PG - [15:0] */
3400  #define WM8994_AIF1DAC1_EQ_B1_PG_WIDTH              16  /* AIF1DAC1_EQ_B1_PG - [15:0] */
3401  
3402  /*
3403   * R1157 (0x485) - AIF1 DAC1 EQ Band 2 A
3404   */
3405  #define WM8994_AIF1DAC1_EQ_B2_A_MASK            0xFFFF  /* AIF1DAC1_EQ_B2_A - [15:0] */
3406  #define WM8994_AIF1DAC1_EQ_B2_A_SHIFT                0  /* AIF1DAC1_EQ_B2_A - [15:0] */
3407  #define WM8994_AIF1DAC1_EQ_B2_A_WIDTH               16  /* AIF1DAC1_EQ_B2_A - [15:0] */
3408  
3409  /*
3410   * R1158 (0x486) - AIF1 DAC1 EQ Band 2 B
3411   */
3412  #define WM8994_AIF1DAC1_EQ_B2_B_MASK            0xFFFF  /* AIF1DAC1_EQ_B2_B - [15:0] */
3413  #define WM8994_AIF1DAC1_EQ_B2_B_SHIFT                0  /* AIF1DAC1_EQ_B2_B - [15:0] */
3414  #define WM8994_AIF1DAC1_EQ_B2_B_WIDTH               16  /* AIF1DAC1_EQ_B2_B - [15:0] */
3415  
3416  /*
3417   * R1159 (0x487) - AIF1 DAC1 EQ Band 2 C
3418   */
3419  #define WM8994_AIF1DAC1_EQ_B2_C_MASK            0xFFFF  /* AIF1DAC1_EQ_B2_C - [15:0] */
3420  #define WM8994_AIF1DAC1_EQ_B2_C_SHIFT                0  /* AIF1DAC1_EQ_B2_C - [15:0] */
3421  #define WM8994_AIF1DAC1_EQ_B2_C_WIDTH               16  /* AIF1DAC1_EQ_B2_C - [15:0] */
3422  
3423  /*
3424   * R1160 (0x488) - AIF1 DAC1 EQ Band 2 PG
3425   */
3426  #define WM8994_AIF1DAC1_EQ_B2_PG_MASK           0xFFFF  /* AIF1DAC1_EQ_B2_PG - [15:0] */
3427  #define WM8994_AIF1DAC1_EQ_B2_PG_SHIFT               0  /* AIF1DAC1_EQ_B2_PG - [15:0] */
3428  #define WM8994_AIF1DAC1_EQ_B2_PG_WIDTH              16  /* AIF1DAC1_EQ_B2_PG - [15:0] */
3429  
3430  /*
3431   * R1161 (0x489) - AIF1 DAC1 EQ Band 3 A
3432   */
3433  #define WM8994_AIF1DAC1_EQ_B3_A_MASK            0xFFFF  /* AIF1DAC1_EQ_B3_A - [15:0] */
3434  #define WM8994_AIF1DAC1_EQ_B3_A_SHIFT                0  /* AIF1DAC1_EQ_B3_A - [15:0] */
3435  #define WM8994_AIF1DAC1_EQ_B3_A_WIDTH               16  /* AIF1DAC1_EQ_B3_A - [15:0] */
3436  
3437  /*
3438   * R1162 (0x48A) - AIF1 DAC1 EQ Band 3 B
3439   */
3440  #define WM8994_AIF1DAC1_EQ_B3_B_MASK            0xFFFF  /* AIF1DAC1_EQ_B3_B - [15:0] */
3441  #define WM8994_AIF1DAC1_EQ_B3_B_SHIFT                0  /* AIF1DAC1_EQ_B3_B - [15:0] */
3442  #define WM8994_AIF1DAC1_EQ_B3_B_WIDTH               16  /* AIF1DAC1_EQ_B3_B - [15:0] */
3443  
3444  /*
3445   * R1163 (0x48B) - AIF1 DAC1 EQ Band 3 C
3446   */
3447  #define WM8994_AIF1DAC1_EQ_B3_C_MASK            0xFFFF  /* AIF1DAC1_EQ_B3_C - [15:0] */
3448  #define WM8994_AIF1DAC1_EQ_B3_C_SHIFT                0  /* AIF1DAC1_EQ_B3_C - [15:0] */
3449  #define WM8994_AIF1DAC1_EQ_B3_C_WIDTH               16  /* AIF1DAC1_EQ_B3_C - [15:0] */
3450  
3451  /*
3452   * R1164 (0x48C) - AIF1 DAC1 EQ Band 3 PG
3453   */
3454  #define WM8994_AIF1DAC1_EQ_B3_PG_MASK           0xFFFF  /* AIF1DAC1_EQ_B3_PG - [15:0] */
3455  #define WM8994_AIF1DAC1_EQ_B3_PG_SHIFT               0  /* AIF1DAC1_EQ_B3_PG - [15:0] */
3456  #define WM8994_AIF1DAC1_EQ_B3_PG_WIDTH              16  /* AIF1DAC1_EQ_B3_PG - [15:0] */
3457  
3458  /*
3459   * R1165 (0x48D) - AIF1 DAC1 EQ Band 4 A
3460   */
3461  #define WM8994_AIF1DAC1_EQ_B4_A_MASK            0xFFFF  /* AIF1DAC1_EQ_B4_A - [15:0] */
3462  #define WM8994_AIF1DAC1_EQ_B4_A_SHIFT                0  /* AIF1DAC1_EQ_B4_A - [15:0] */
3463  #define WM8994_AIF1DAC1_EQ_B4_A_WIDTH               16  /* AIF1DAC1_EQ_B4_A - [15:0] */
3464  
3465  /*
3466   * R1166 (0x48E) - AIF1 DAC1 EQ Band 4 B
3467   */
3468  #define WM8994_AIF1DAC1_EQ_B4_B_MASK            0xFFFF  /* AIF1DAC1_EQ_B4_B - [15:0] */
3469  #define WM8994_AIF1DAC1_EQ_B4_B_SHIFT                0  /* AIF1DAC1_EQ_B4_B - [15:0] */
3470  #define WM8994_AIF1DAC1_EQ_B4_B_WIDTH               16  /* AIF1DAC1_EQ_B4_B - [15:0] */
3471  
3472  /*
3473   * R1167 (0x48F) - AIF1 DAC1 EQ Band 4 C
3474   */
3475  #define WM8994_AIF1DAC1_EQ_B4_C_MASK            0xFFFF  /* AIF1DAC1_EQ_B4_C - [15:0] */
3476  #define WM8994_AIF1DAC1_EQ_B4_C_SHIFT                0  /* AIF1DAC1_EQ_B4_C - [15:0] */
3477  #define WM8994_AIF1DAC1_EQ_B4_C_WIDTH               16  /* AIF1DAC1_EQ_B4_C - [15:0] */
3478  
3479  /*
3480   * R1168 (0x490) - AIF1 DAC1 EQ Band 4 PG
3481   */
3482  #define WM8994_AIF1DAC1_EQ_B4_PG_MASK           0xFFFF  /* AIF1DAC1_EQ_B4_PG - [15:0] */
3483  #define WM8994_AIF1DAC1_EQ_B4_PG_SHIFT               0  /* AIF1DAC1_EQ_B4_PG - [15:0] */
3484  #define WM8994_AIF1DAC1_EQ_B4_PG_WIDTH              16  /* AIF1DAC1_EQ_B4_PG - [15:0] */
3485  
3486  /*
3487   * R1169 (0x491) - AIF1 DAC1 EQ Band 5 A
3488   */
3489  #define WM8994_AIF1DAC1_EQ_B5_A_MASK            0xFFFF  /* AIF1DAC1_EQ_B5_A - [15:0] */
3490  #define WM8994_AIF1DAC1_EQ_B5_A_SHIFT                0  /* AIF1DAC1_EQ_B5_A - [15:0] */
3491  #define WM8994_AIF1DAC1_EQ_B5_A_WIDTH               16  /* AIF1DAC1_EQ_B5_A - [15:0] */
3492  
3493  /*
3494   * R1170 (0x492) - AIF1 DAC1 EQ Band 5 B
3495   */
3496  #define WM8994_AIF1DAC1_EQ_B5_B_MASK            0xFFFF  /* AIF1DAC1_EQ_B5_B - [15:0] */
3497  #define WM8994_AIF1DAC1_EQ_B5_B_SHIFT                0  /* AIF1DAC1_EQ_B5_B - [15:0] */
3498  #define WM8994_AIF1DAC1_EQ_B5_B_WIDTH               16  /* AIF1DAC1_EQ_B5_B - [15:0] */
3499  
3500  /*
3501   * R1171 (0x493) - AIF1 DAC1 EQ Band 5 PG
3502   */
3503  #define WM8994_AIF1DAC1_EQ_B5_PG_MASK           0xFFFF  /* AIF1DAC1_EQ_B5_PG - [15:0] */
3504  #define WM8994_AIF1DAC1_EQ_B5_PG_SHIFT               0  /* AIF1DAC1_EQ_B5_PG - [15:0] */
3505  #define WM8994_AIF1DAC1_EQ_B5_PG_WIDTH              16  /* AIF1DAC1_EQ_B5_PG - [15:0] */
3506  
3507  /*
3508   * R1184 (0x4A0) - AIF1 DAC2 EQ Gains (1)
3509   */
3510  #define WM8994_AIF1DAC2_EQ_B1_GAIN_MASK         0xF800  /* AIF1DAC2_EQ_B1_GAIN - [15:11] */
3511  #define WM8994_AIF1DAC2_EQ_B1_GAIN_SHIFT            11  /* AIF1DAC2_EQ_B1_GAIN - [15:11] */
3512  #define WM8994_AIF1DAC2_EQ_B1_GAIN_WIDTH             5  /* AIF1DAC2_EQ_B1_GAIN - [15:11] */
3513  #define WM8994_AIF1DAC2_EQ_B2_GAIN_MASK         0x07C0  /* AIF1DAC2_EQ_B2_GAIN - [10:6] */
3514  #define WM8994_AIF1DAC2_EQ_B2_GAIN_SHIFT             6  /* AIF1DAC2_EQ_B2_GAIN - [10:6] */
3515  #define WM8994_AIF1DAC2_EQ_B2_GAIN_WIDTH             5  /* AIF1DAC2_EQ_B2_GAIN - [10:6] */
3516  #define WM8994_AIF1DAC2_EQ_B3_GAIN_MASK         0x003E  /* AIF1DAC2_EQ_B3_GAIN - [5:1] */
3517  #define WM8994_AIF1DAC2_EQ_B3_GAIN_SHIFT             1  /* AIF1DAC2_EQ_B3_GAIN - [5:1] */
3518  #define WM8994_AIF1DAC2_EQ_B3_GAIN_WIDTH             5  /* AIF1DAC2_EQ_B3_GAIN - [5:1] */
3519  #define WM8994_AIF1DAC2_EQ_ENA                  0x0001  /* AIF1DAC2_EQ_ENA */
3520  #define WM8994_AIF1DAC2_EQ_ENA_MASK             0x0001  /* AIF1DAC2_EQ_ENA */
3521  #define WM8994_AIF1DAC2_EQ_ENA_SHIFT                 0  /* AIF1DAC2_EQ_ENA */
3522  #define WM8994_AIF1DAC2_EQ_ENA_WIDTH                 1  /* AIF1DAC2_EQ_ENA */
3523  
3524  /*
3525   * R1185 (0x4A1) - AIF1 DAC2 EQ Gains (2)
3526   */
3527  #define WM8994_AIF1DAC2_EQ_B4_GAIN_MASK         0xF800  /* AIF1DAC2_EQ_B4_GAIN - [15:11] */
3528  #define WM8994_AIF1DAC2_EQ_B4_GAIN_SHIFT            11  /* AIF1DAC2_EQ_B4_GAIN - [15:11] */
3529  #define WM8994_AIF1DAC2_EQ_B4_GAIN_WIDTH             5  /* AIF1DAC2_EQ_B4_GAIN - [15:11] */
3530  #define WM8994_AIF1DAC2_EQ_B5_GAIN_MASK         0x07C0  /* AIF1DAC2_EQ_B5_GAIN - [10:6] */
3531  #define WM8994_AIF1DAC2_EQ_B5_GAIN_SHIFT             6  /* AIF1DAC2_EQ_B5_GAIN - [10:6] */
3532  #define WM8994_AIF1DAC2_EQ_B5_GAIN_WIDTH             5  /* AIF1DAC2_EQ_B5_GAIN - [10:6] */
3533  
3534  /*
3535   * R1186 (0x4A2) - AIF1 DAC2 EQ Band 1 A
3536   */
3537  #define WM8994_AIF1DAC2_EQ_B1_A_MASK            0xFFFF  /* AIF1DAC2_EQ_B1_A - [15:0] */
3538  #define WM8994_AIF1DAC2_EQ_B1_A_SHIFT                0  /* AIF1DAC2_EQ_B1_A - [15:0] */
3539  #define WM8994_AIF1DAC2_EQ_B1_A_WIDTH               16  /* AIF1DAC2_EQ_B1_A - [15:0] */
3540  
3541  /*
3542   * R1187 (0x4A3) - AIF1 DAC2 EQ Band 1 B
3543   */
3544  #define WM8994_AIF1DAC2_EQ_B1_B_MASK            0xFFFF  /* AIF1DAC2_EQ_B1_B - [15:0] */
3545  #define WM8994_AIF1DAC2_EQ_B1_B_SHIFT                0  /* AIF1DAC2_EQ_B1_B - [15:0] */
3546  #define WM8994_AIF1DAC2_EQ_B1_B_WIDTH               16  /* AIF1DAC2_EQ_B1_B - [15:0] */
3547  
3548  /*
3549   * R1188 (0x4A4) - AIF1 DAC2 EQ Band 1 PG
3550   */
3551  #define WM8994_AIF1DAC2_EQ_B1_PG_MASK           0xFFFF  /* AIF1DAC2_EQ_B1_PG - [15:0] */
3552  #define WM8994_AIF1DAC2_EQ_B1_PG_SHIFT               0  /* AIF1DAC2_EQ_B1_PG - [15:0] */
3553  #define WM8994_AIF1DAC2_EQ_B1_PG_WIDTH              16  /* AIF1DAC2_EQ_B1_PG - [15:0] */
3554  
3555  /*
3556   * R1189 (0x4A5) - AIF1 DAC2 EQ Band 2 A
3557   */
3558  #define WM8994_AIF1DAC2_EQ_B2_A_MASK            0xFFFF  /* AIF1DAC2_EQ_B2_A - [15:0] */
3559  #define WM8994_AIF1DAC2_EQ_B2_A_SHIFT                0  /* AIF1DAC2_EQ_B2_A - [15:0] */
3560  #define WM8994_AIF1DAC2_EQ_B2_A_WIDTH               16  /* AIF1DAC2_EQ_B2_A - [15:0] */
3561  
3562  /*
3563   * R1190 (0x4A6) - AIF1 DAC2 EQ Band 2 B
3564   */
3565  #define WM8994_AIF1DAC2_EQ_B2_B_MASK            0xFFFF  /* AIF1DAC2_EQ_B2_B - [15:0] */
3566  #define WM8994_AIF1DAC2_EQ_B2_B_SHIFT                0  /* AIF1DAC2_EQ_B2_B - [15:0] */
3567  #define WM8994_AIF1DAC2_EQ_B2_B_WIDTH               16  /* AIF1DAC2_EQ_B2_B - [15:0] */
3568  
3569  /*
3570   * R1191 (0x4A7) - AIF1 DAC2 EQ Band 2 C
3571   */
3572  #define WM8994_AIF1DAC2_EQ_B2_C_MASK            0xFFFF  /* AIF1DAC2_EQ_B2_C - [15:0] */
3573  #define WM8994_AIF1DAC2_EQ_B2_C_SHIFT                0  /* AIF1DAC2_EQ_B2_C - [15:0] */
3574  #define WM8994_AIF1DAC2_EQ_B2_C_WIDTH               16  /* AIF1DAC2_EQ_B2_C - [15:0] */
3575  
3576  /*
3577   * R1192 (0x4A8) - AIF1 DAC2 EQ Band 2 PG
3578   */
3579  #define WM8994_AIF1DAC2_EQ_B2_PG_MASK           0xFFFF  /* AIF1DAC2_EQ_B2_PG - [15:0] */
3580  #define WM8994_AIF1DAC2_EQ_B2_PG_SHIFT               0  /* AIF1DAC2_EQ_B2_PG - [15:0] */
3581  #define WM8994_AIF1DAC2_EQ_B2_PG_WIDTH              16  /* AIF1DAC2_EQ_B2_PG - [15:0] */
3582  
3583  /*
3584   * R1193 (0x4A9) - AIF1 DAC2 EQ Band 3 A
3585   */
3586  #define WM8994_AIF1DAC2_EQ_B3_A_MASK            0xFFFF  /* AIF1DAC2_EQ_B3_A - [15:0] */
3587  #define WM8994_AIF1DAC2_EQ_B3_A_SHIFT                0  /* AIF1DAC2_EQ_B3_A - [15:0] */
3588  #define WM8994_AIF1DAC2_EQ_B3_A_WIDTH               16  /* AIF1DAC2_EQ_B3_A - [15:0] */
3589  
3590  /*
3591   * R1194 (0x4AA) - AIF1 DAC2 EQ Band 3 B
3592   */
3593  #define WM8994_AIF1DAC2_EQ_B3_B_MASK            0xFFFF  /* AIF1DAC2_EQ_B3_B - [15:0] */
3594  #define WM8994_AIF1DAC2_EQ_B3_B_SHIFT                0  /* AIF1DAC2_EQ_B3_B - [15:0] */
3595  #define WM8994_AIF1DAC2_EQ_B3_B_WIDTH               16  /* AIF1DAC2_EQ_B3_B - [15:0] */
3596  
3597  /*
3598   * R1195 (0x4AB) - AIF1 DAC2 EQ Band 3 C
3599   */
3600  #define WM8994_AIF1DAC2_EQ_B3_C_MASK            0xFFFF  /* AIF1DAC2_EQ_B3_C - [15:0] */
3601  #define WM8994_AIF1DAC2_EQ_B3_C_SHIFT                0  /* AIF1DAC2_EQ_B3_C - [15:0] */
3602  #define WM8994_AIF1DAC2_EQ_B3_C_WIDTH               16  /* AIF1DAC2_EQ_B3_C - [15:0] */
3603  
3604  /*
3605   * R1196 (0x4AC) - AIF1 DAC2 EQ Band 3 PG
3606   */
3607  #define WM8994_AIF1DAC2_EQ_B3_PG_MASK           0xFFFF  /* AIF1DAC2_EQ_B3_PG - [15:0] */
3608  #define WM8994_AIF1DAC2_EQ_B3_PG_SHIFT               0  /* AIF1DAC2_EQ_B3_PG - [15:0] */
3609  #define WM8994_AIF1DAC2_EQ_B3_PG_WIDTH              16  /* AIF1DAC2_EQ_B3_PG - [15:0] */
3610  
3611  /*
3612   * R1197 (0x4AD) - AIF1 DAC2 EQ Band 4 A
3613   */
3614  #define WM8994_AIF1DAC2_EQ_B4_A_MASK            0xFFFF  /* AIF1DAC2_EQ_B4_A - [15:0] */
3615  #define WM8994_AIF1DAC2_EQ_B4_A_SHIFT                0  /* AIF1DAC2_EQ_B4_A - [15:0] */
3616  #define WM8994_AIF1DAC2_EQ_B4_A_WIDTH               16  /* AIF1DAC2_EQ_B4_A - [15:0] */
3617  
3618  /*
3619   * R1198 (0x4AE) - AIF1 DAC2 EQ Band 4 B
3620   */
3621  #define WM8994_AIF1DAC2_EQ_B4_B_MASK            0xFFFF  /* AIF1DAC2_EQ_B4_B - [15:0] */
3622  #define WM8994_AIF1DAC2_EQ_B4_B_SHIFT                0  /* AIF1DAC2_EQ_B4_B - [15:0] */
3623  #define WM8994_AIF1DAC2_EQ_B4_B_WIDTH               16  /* AIF1DAC2_EQ_B4_B - [15:0] */
3624  
3625  /*
3626   * R1199 (0x4AF) - AIF1 DAC2 EQ Band 4 C
3627   */
3628  #define WM8994_AIF1DAC2_EQ_B4_C_MASK            0xFFFF  /* AIF1DAC2_EQ_B4_C - [15:0] */
3629  #define WM8994_AIF1DAC2_EQ_B4_C_SHIFT                0  /* AIF1DAC2_EQ_B4_C - [15:0] */
3630  #define WM8994_AIF1DAC2_EQ_B4_C_WIDTH               16  /* AIF1DAC2_EQ_B4_C - [15:0] */
3631  
3632  /*
3633   * R1200 (0x4B0) - AIF1 DAC2 EQ Band 4 PG
3634   */
3635  #define WM8994_AIF1DAC2_EQ_B4_PG_MASK           0xFFFF  /* AIF1DAC2_EQ_B4_PG - [15:0] */
3636  #define WM8994_AIF1DAC2_EQ_B4_PG_SHIFT               0  /* AIF1DAC2_EQ_B4_PG - [15:0] */
3637  #define WM8994_AIF1DAC2_EQ_B4_PG_WIDTH              16  /* AIF1DAC2_EQ_B4_PG - [15:0] */
3638  
3639  /*
3640   * R1201 (0x4B1) - AIF1 DAC2 EQ Band 5 A
3641   */
3642  #define WM8994_AIF1DAC2_EQ_B5_A_MASK            0xFFFF  /* AIF1DAC2_EQ_B5_A - [15:0] */
3643  #define WM8994_AIF1DAC2_EQ_B5_A_SHIFT                0  /* AIF1DAC2_EQ_B5_A - [15:0] */
3644  #define WM8994_AIF1DAC2_EQ_B5_A_WIDTH               16  /* AIF1DAC2_EQ_B5_A - [15:0] */
3645  
3646  /*
3647   * R1202 (0x4B2) - AIF1 DAC2 EQ Band 5 B
3648   */
3649  #define WM8994_AIF1DAC2_EQ_B5_B_MASK            0xFFFF  /* AIF1DAC2_EQ_B5_B - [15:0] */
3650  #define WM8994_AIF1DAC2_EQ_B5_B_SHIFT                0  /* AIF1DAC2_EQ_B5_B - [15:0] */
3651  #define WM8994_AIF1DAC2_EQ_B5_B_WIDTH               16  /* AIF1DAC2_EQ_B5_B - [15:0] */
3652  
3653  /*
3654   * R1203 (0x4B3) - AIF1 DAC2 EQ Band 5 PG
3655   */
3656  #define WM8994_AIF1DAC2_EQ_B5_PG_MASK           0xFFFF  /* AIF1DAC2_EQ_B5_PG - [15:0] */
3657  #define WM8994_AIF1DAC2_EQ_B5_PG_SHIFT               0  /* AIF1DAC2_EQ_B5_PG - [15:0] */
3658  #define WM8994_AIF1DAC2_EQ_B5_PG_WIDTH              16  /* AIF1DAC2_EQ_B5_PG - [15:0] */
3659  
3660  /*
3661   * R1280 (0x500) - AIF2 ADC Left Volume
3662   */
3663  #define WM8994_AIF2ADC_VU                       0x0100  /* AIF2ADC_VU */
3664  #define WM8994_AIF2ADC_VU_MASK                  0x0100  /* AIF2ADC_VU */
3665  #define WM8994_AIF2ADC_VU_SHIFT                      8  /* AIF2ADC_VU */
3666  #define WM8994_AIF2ADC_VU_WIDTH                      1  /* AIF2ADC_VU */
3667  #define WM8994_AIF2ADCL_VOL_MASK                0x00FF  /* AIF2ADCL_VOL - [7:0] */
3668  #define WM8994_AIF2ADCL_VOL_SHIFT                    0  /* AIF2ADCL_VOL - [7:0] */
3669  #define WM8994_AIF2ADCL_VOL_WIDTH                    8  /* AIF2ADCL_VOL - [7:0] */
3670  
3671  /*
3672   * R1281 (0x501) - AIF2 ADC Right Volume
3673   */
3674  #define WM8994_AIF2ADC_VU                       0x0100  /* AIF2ADC_VU */
3675  #define WM8994_AIF2ADC_VU_MASK                  0x0100  /* AIF2ADC_VU */
3676  #define WM8994_AIF2ADC_VU_SHIFT                      8  /* AIF2ADC_VU */
3677  #define WM8994_AIF2ADC_VU_WIDTH                      1  /* AIF2ADC_VU */
3678  #define WM8994_AIF2ADCR_VOL_MASK                0x00FF  /* AIF2ADCR_VOL - [7:0] */
3679  #define WM8994_AIF2ADCR_VOL_SHIFT                    0  /* AIF2ADCR_VOL - [7:0] */
3680  #define WM8994_AIF2ADCR_VOL_WIDTH                    8  /* AIF2ADCR_VOL - [7:0] */
3681  
3682  /*
3683   * R1282 (0x502) - AIF2 DAC Left Volume
3684   */
3685  #define WM8994_AIF2DAC_VU                       0x0100  /* AIF2DAC_VU */
3686  #define WM8994_AIF2DAC_VU_MASK                  0x0100  /* AIF2DAC_VU */
3687  #define WM8994_AIF2DAC_VU_SHIFT                      8  /* AIF2DAC_VU */
3688  #define WM8994_AIF2DAC_VU_WIDTH                      1  /* AIF2DAC_VU */
3689  #define WM8994_AIF2DACL_VOL_MASK                0x00FF  /* AIF2DACL_VOL - [7:0] */
3690  #define WM8994_AIF2DACL_VOL_SHIFT                    0  /* AIF2DACL_VOL - [7:0] */
3691  #define WM8994_AIF2DACL_VOL_WIDTH                    8  /* AIF2DACL_VOL - [7:0] */
3692  
3693  /*
3694   * R1283 (0x503) - AIF2 DAC Right Volume
3695   */
3696  #define WM8994_AIF2DAC_VU                       0x0100  /* AIF2DAC_VU */
3697  #define WM8994_AIF2DAC_VU_MASK                  0x0100  /* AIF2DAC_VU */
3698  #define WM8994_AIF2DAC_VU_SHIFT                      8  /* AIF2DAC_VU */
3699  #define WM8994_AIF2DAC_VU_WIDTH                      1  /* AIF2DAC_VU */
3700  #define WM8994_AIF2DACR_VOL_MASK                0x00FF  /* AIF2DACR_VOL - [7:0] */
3701  #define WM8994_AIF2DACR_VOL_SHIFT                    0  /* AIF2DACR_VOL - [7:0] */
3702  #define WM8994_AIF2DACR_VOL_WIDTH                    8  /* AIF2DACR_VOL - [7:0] */
3703  
3704  /*
3705   * R1296 (0x510) - AIF2 ADC Filters
3706   */
3707  #define WM8994_AIF2ADC_4FS                      0x8000  /* AIF2ADC_4FS */
3708  #define WM8994_AIF2ADC_4FS_MASK                 0x8000  /* AIF2ADC_4FS */
3709  #define WM8994_AIF2ADC_4FS_SHIFT                    15  /* AIF2ADC_4FS */
3710  #define WM8994_AIF2ADC_4FS_WIDTH                     1  /* AIF2ADC_4FS */
3711  #define WM8994_AIF2ADC_HPF_CUT_MASK             0x6000  /* AIF2ADC_HPF_CUT - [14:13] */
3712  #define WM8994_AIF2ADC_HPF_CUT_SHIFT                13  /* AIF2ADC_HPF_CUT - [14:13] */
3713  #define WM8994_AIF2ADC_HPF_CUT_WIDTH                 2  /* AIF2ADC_HPF_CUT - [14:13] */
3714  #define WM8994_AIF2ADCL_HPF                     0x1000  /* AIF2ADCL_HPF */
3715  #define WM8994_AIF2ADCL_HPF_MASK                0x1000  /* AIF2ADCL_HPF */
3716  #define WM8994_AIF2ADCL_HPF_SHIFT                   12  /* AIF2ADCL_HPF */
3717  #define WM8994_AIF2ADCL_HPF_WIDTH                    1  /* AIF2ADCL_HPF */
3718  #define WM8994_AIF2ADCR_HPF                     0x0800  /* AIF2ADCR_HPF */
3719  #define WM8994_AIF2ADCR_HPF_MASK                0x0800  /* AIF2ADCR_HPF */
3720  #define WM8994_AIF2ADCR_HPF_SHIFT                   11  /* AIF2ADCR_HPF */
3721  #define WM8994_AIF2ADCR_HPF_WIDTH                    1  /* AIF2ADCR_HPF */
3722  
3723  /*
3724   * R1312 (0x520) - AIF2 DAC Filters (1)
3725   */
3726  #define WM8994_AIF2DAC_MUTE                     0x0200  /* AIF2DAC_MUTE */
3727  #define WM8994_AIF2DAC_MUTE_MASK                0x0200  /* AIF2DAC_MUTE */
3728  #define WM8994_AIF2DAC_MUTE_SHIFT                    9  /* AIF2DAC_MUTE */
3729  #define WM8994_AIF2DAC_MUTE_WIDTH                    1  /* AIF2DAC_MUTE */
3730  #define WM8994_AIF2DAC_MONO                     0x0080  /* AIF2DAC_MONO */
3731  #define WM8994_AIF2DAC_MONO_MASK                0x0080  /* AIF2DAC_MONO */
3732  #define WM8994_AIF2DAC_MONO_SHIFT                    7  /* AIF2DAC_MONO */
3733  #define WM8994_AIF2DAC_MONO_WIDTH                    1  /* AIF2DAC_MONO */
3734  #define WM8994_AIF2DAC_MUTERATE                 0x0020  /* AIF2DAC_MUTERATE */
3735  #define WM8994_AIF2DAC_MUTERATE_MASK            0x0020  /* AIF2DAC_MUTERATE */
3736  #define WM8994_AIF2DAC_MUTERATE_SHIFT                5  /* AIF2DAC_MUTERATE */
3737  #define WM8994_AIF2DAC_MUTERATE_WIDTH                1  /* AIF2DAC_MUTERATE */
3738  #define WM8994_AIF2DAC_UNMUTE_RAMP              0x0010  /* AIF2DAC_UNMUTE_RAMP */
3739  #define WM8994_AIF2DAC_UNMUTE_RAMP_MASK         0x0010  /* AIF2DAC_UNMUTE_RAMP */
3740  #define WM8994_AIF2DAC_UNMUTE_RAMP_SHIFT             4  /* AIF2DAC_UNMUTE_RAMP */
3741  #define WM8994_AIF2DAC_UNMUTE_RAMP_WIDTH             1  /* AIF2DAC_UNMUTE_RAMP */
3742  #define WM8994_AIF2DAC_DEEMP_MASK               0x0006  /* AIF2DAC_DEEMP - [2:1] */
3743  #define WM8994_AIF2DAC_DEEMP_SHIFT                   1  /* AIF2DAC_DEEMP - [2:1] */
3744  #define WM8994_AIF2DAC_DEEMP_WIDTH                   2  /* AIF2DAC_DEEMP - [2:1] */
3745  
3746  /*
3747   * R1313 (0x521) - AIF2 DAC Filters (2)
3748   */
3749  #define WM8994_AIF2DAC_3D_GAIN_MASK             0x3E00  /* AIF2DAC_3D_GAIN - [13:9] */
3750  #define WM8994_AIF2DAC_3D_GAIN_SHIFT                 9  /* AIF2DAC_3D_GAIN - [13:9] */
3751  #define WM8994_AIF2DAC_3D_GAIN_WIDTH                 5  /* AIF2DAC_3D_GAIN - [13:9] */
3752  #define WM8994_AIF2DAC_3D_ENA                   0x0100  /* AIF2DAC_3D_ENA */
3753  #define WM8994_AIF2DAC_3D_ENA_MASK              0x0100  /* AIF2DAC_3D_ENA */
3754  #define WM8994_AIF2DAC_3D_ENA_SHIFT                  8  /* AIF2DAC_3D_ENA */
3755  #define WM8994_AIF2DAC_3D_ENA_WIDTH                  1  /* AIF2DAC_3D_ENA */
3756  
3757  /*
3758   * R1328 (0x530) - AIF2 DAC Noise Gate
3759   */
3760  #define WM8958_AIF2DAC_NG_HLD_MASK              0x0060  /* AIF2DAC_NG_HLD - [6:5] */
3761  #define WM8958_AIF2DAC_NG_HLD_SHIFT                  5  /* AIF2DAC_NG_HLD - [6:5] */
3762  #define WM8958_AIF2DAC_NG_HLD_WIDTH                  2  /* AIF2DAC_NG_HLD - [6:5] */
3763  #define WM8958_AIF2DAC_NG_THR_MASK              0x000E  /* AIF2DAC_NG_THR - [3:1] */
3764  #define WM8958_AIF2DAC_NG_THR_SHIFT                  1  /* AIF2DAC_NG_THR - [3:1] */
3765  #define WM8958_AIF2DAC_NG_THR_WIDTH                  3  /* AIF2DAC_NG_THR - [3:1] */
3766  #define WM8958_AIF2DAC_NG_ENA                   0x0001  /* AIF2DAC_NG_ENA */
3767  #define WM8958_AIF2DAC_NG_ENA_MASK              0x0001  /* AIF2DAC_NG_ENA */
3768  #define WM8958_AIF2DAC_NG_ENA_SHIFT                  0  /* AIF2DAC_NG_ENA */
3769  #define WM8958_AIF2DAC_NG_ENA_WIDTH                  1  /* AIF2DAC_NG_ENA */
3770  
3771  /*
3772   * R1344 (0x540) - AIF2 DRC (1)
3773   */
3774  #define WM8994_AIF2DRC_SIG_DET_RMS_MASK         0xF800  /* AIF2DRC_SIG_DET_RMS - [15:11] */
3775  #define WM8994_AIF2DRC_SIG_DET_RMS_SHIFT            11  /* AIF2DRC_SIG_DET_RMS - [15:11] */
3776  #define WM8994_AIF2DRC_SIG_DET_RMS_WIDTH             5  /* AIF2DRC_SIG_DET_RMS - [15:11] */
3777  #define WM8994_AIF2DRC_SIG_DET_PK_MASK          0x0600  /* AIF2DRC_SIG_DET_PK - [10:9] */
3778  #define WM8994_AIF2DRC_SIG_DET_PK_SHIFT              9  /* AIF2DRC_SIG_DET_PK - [10:9] */
3779  #define WM8994_AIF2DRC_SIG_DET_PK_WIDTH              2  /* AIF2DRC_SIG_DET_PK - [10:9] */
3780  #define WM8994_AIF2DRC_NG_ENA                   0x0100  /* AIF2DRC_NG_ENA */
3781  #define WM8994_AIF2DRC_NG_ENA_MASK              0x0100  /* AIF2DRC_NG_ENA */
3782  #define WM8994_AIF2DRC_NG_ENA_SHIFT                  8  /* AIF2DRC_NG_ENA */
3783  #define WM8994_AIF2DRC_NG_ENA_WIDTH                  1  /* AIF2DRC_NG_ENA */
3784  #define WM8994_AIF2DRC_SIG_DET_MODE             0x0080  /* AIF2DRC_SIG_DET_MODE */
3785  #define WM8994_AIF2DRC_SIG_DET_MODE_MASK        0x0080  /* AIF2DRC_SIG_DET_MODE */
3786  #define WM8994_AIF2DRC_SIG_DET_MODE_SHIFT            7  /* AIF2DRC_SIG_DET_MODE */
3787  #define WM8994_AIF2DRC_SIG_DET_MODE_WIDTH            1  /* AIF2DRC_SIG_DET_MODE */
3788  #define WM8994_AIF2DRC_SIG_DET                  0x0040  /* AIF2DRC_SIG_DET */
3789  #define WM8994_AIF2DRC_SIG_DET_MASK             0x0040  /* AIF2DRC_SIG_DET */
3790  #define WM8994_AIF2DRC_SIG_DET_SHIFT                 6  /* AIF2DRC_SIG_DET */
3791  #define WM8994_AIF2DRC_SIG_DET_WIDTH                 1  /* AIF2DRC_SIG_DET */
3792  #define WM8994_AIF2DRC_KNEE2_OP_ENA             0x0020  /* AIF2DRC_KNEE2_OP_ENA */
3793  #define WM8994_AIF2DRC_KNEE2_OP_ENA_MASK        0x0020  /* AIF2DRC_KNEE2_OP_ENA */
3794  #define WM8994_AIF2DRC_KNEE2_OP_ENA_SHIFT            5  /* AIF2DRC_KNEE2_OP_ENA */
3795  #define WM8994_AIF2DRC_KNEE2_OP_ENA_WIDTH            1  /* AIF2DRC_KNEE2_OP_ENA */
3796  #define WM8994_AIF2DRC_QR                       0x0010  /* AIF2DRC_QR */
3797  #define WM8994_AIF2DRC_QR_MASK                  0x0010  /* AIF2DRC_QR */
3798  #define WM8994_AIF2DRC_QR_SHIFT                      4  /* AIF2DRC_QR */
3799  #define WM8994_AIF2DRC_QR_WIDTH                      1  /* AIF2DRC_QR */
3800  #define WM8994_AIF2DRC_ANTICLIP                 0x0008  /* AIF2DRC_ANTICLIP */
3801  #define WM8994_AIF2DRC_ANTICLIP_MASK            0x0008  /* AIF2DRC_ANTICLIP */
3802  #define WM8994_AIF2DRC_ANTICLIP_SHIFT                3  /* AIF2DRC_ANTICLIP */
3803  #define WM8994_AIF2DRC_ANTICLIP_WIDTH                1  /* AIF2DRC_ANTICLIP */
3804  #define WM8994_AIF2DAC_DRC_ENA                  0x0004  /* AIF2DAC_DRC_ENA */
3805  #define WM8994_AIF2DAC_DRC_ENA_MASK             0x0004  /* AIF2DAC_DRC_ENA */
3806  #define WM8994_AIF2DAC_DRC_ENA_SHIFT                 2  /* AIF2DAC_DRC_ENA */
3807  #define WM8994_AIF2DAC_DRC_ENA_WIDTH                 1  /* AIF2DAC_DRC_ENA */
3808  #define WM8994_AIF2ADCL_DRC_ENA                 0x0002  /* AIF2ADCL_DRC_ENA */
3809  #define WM8994_AIF2ADCL_DRC_ENA_MASK            0x0002  /* AIF2ADCL_DRC_ENA */
3810  #define WM8994_AIF2ADCL_DRC_ENA_SHIFT                1  /* AIF2ADCL_DRC_ENA */
3811  #define WM8994_AIF2ADCL_DRC_ENA_WIDTH                1  /* AIF2ADCL_DRC_ENA */
3812  #define WM8994_AIF2ADCR_DRC_ENA                 0x0001  /* AIF2ADCR_DRC_ENA */
3813  #define WM8994_AIF2ADCR_DRC_ENA_MASK            0x0001  /* AIF2ADCR_DRC_ENA */
3814  #define WM8994_AIF2ADCR_DRC_ENA_SHIFT                0  /* AIF2ADCR_DRC_ENA */
3815  #define WM8994_AIF2ADCR_DRC_ENA_WIDTH                1  /* AIF2ADCR_DRC_ENA */
3816  
3817  /*
3818   * R1345 (0x541) - AIF2 DRC (2)
3819   */
3820  #define WM8994_AIF2DRC_ATK_MASK                 0x1E00  /* AIF2DRC_ATK - [12:9] */
3821  #define WM8994_AIF2DRC_ATK_SHIFT                     9  /* AIF2DRC_ATK - [12:9] */
3822  #define WM8994_AIF2DRC_ATK_WIDTH                     4  /* AIF2DRC_ATK - [12:9] */
3823  #define WM8994_AIF2DRC_DCY_MASK                 0x01E0  /* AIF2DRC_DCY - [8:5] */
3824  #define WM8994_AIF2DRC_DCY_SHIFT                     5  /* AIF2DRC_DCY - [8:5] */
3825  #define WM8994_AIF2DRC_DCY_WIDTH                     4  /* AIF2DRC_DCY - [8:5] */
3826  #define WM8994_AIF2DRC_MINGAIN_MASK             0x001C  /* AIF2DRC_MINGAIN - [4:2] */
3827  #define WM8994_AIF2DRC_MINGAIN_SHIFT                 2  /* AIF2DRC_MINGAIN - [4:2] */
3828  #define WM8994_AIF2DRC_MINGAIN_WIDTH                 3  /* AIF2DRC_MINGAIN - [4:2] */
3829  #define WM8994_AIF2DRC_MAXGAIN_MASK             0x0003  /* AIF2DRC_MAXGAIN - [1:0] */
3830  #define WM8994_AIF2DRC_MAXGAIN_SHIFT                 0  /* AIF2DRC_MAXGAIN - [1:0] */
3831  #define WM8994_AIF2DRC_MAXGAIN_WIDTH                 2  /* AIF2DRC_MAXGAIN - [1:0] */
3832  
3833  /*
3834   * R1346 (0x542) - AIF2 DRC (3)
3835   */
3836  #define WM8994_AIF2DRC_NG_MINGAIN_MASK          0xF000  /* AIF2DRC_NG_MINGAIN - [15:12] */
3837  #define WM8994_AIF2DRC_NG_MINGAIN_SHIFT             12  /* AIF2DRC_NG_MINGAIN - [15:12] */
3838  #define WM8994_AIF2DRC_NG_MINGAIN_WIDTH              4  /* AIF2DRC_NG_MINGAIN - [15:12] */
3839  #define WM8994_AIF2DRC_NG_EXP_MASK              0x0C00  /* AIF2DRC_NG_EXP - [11:10] */
3840  #define WM8994_AIF2DRC_NG_EXP_SHIFT                 10  /* AIF2DRC_NG_EXP - [11:10] */
3841  #define WM8994_AIF2DRC_NG_EXP_WIDTH                  2  /* AIF2DRC_NG_EXP - [11:10] */
3842  #define WM8994_AIF2DRC_QR_THR_MASK              0x0300  /* AIF2DRC_QR_THR - [9:8] */
3843  #define WM8994_AIF2DRC_QR_THR_SHIFT                  8  /* AIF2DRC_QR_THR - [9:8] */
3844  #define WM8994_AIF2DRC_QR_THR_WIDTH                  2  /* AIF2DRC_QR_THR - [9:8] */
3845  #define WM8994_AIF2DRC_QR_DCY_MASK              0x00C0  /* AIF2DRC_QR_DCY - [7:6] */
3846  #define WM8994_AIF2DRC_QR_DCY_SHIFT                  6  /* AIF2DRC_QR_DCY - [7:6] */
3847  #define WM8994_AIF2DRC_QR_DCY_WIDTH                  2  /* AIF2DRC_QR_DCY - [7:6] */
3848  #define WM8994_AIF2DRC_HI_COMP_MASK             0x0038  /* AIF2DRC_HI_COMP - [5:3] */
3849  #define WM8994_AIF2DRC_HI_COMP_SHIFT                 3  /* AIF2DRC_HI_COMP - [5:3] */
3850  #define WM8994_AIF2DRC_HI_COMP_WIDTH                 3  /* AIF2DRC_HI_COMP - [5:3] */
3851  #define WM8994_AIF2DRC_LO_COMP_MASK             0x0007  /* AIF2DRC_LO_COMP - [2:0] */
3852  #define WM8994_AIF2DRC_LO_COMP_SHIFT                 0  /* AIF2DRC_LO_COMP - [2:0] */
3853  #define WM8994_AIF2DRC_LO_COMP_WIDTH                 3  /* AIF2DRC_LO_COMP - [2:0] */
3854  
3855  /*
3856   * R1347 (0x543) - AIF2 DRC (4)
3857   */
3858  #define WM8994_AIF2DRC_KNEE_IP_MASK             0x07E0  /* AIF2DRC_KNEE_IP - [10:5] */
3859  #define WM8994_AIF2DRC_KNEE_IP_SHIFT                 5  /* AIF2DRC_KNEE_IP - [10:5] */
3860  #define WM8994_AIF2DRC_KNEE_IP_WIDTH                 6  /* AIF2DRC_KNEE_IP - [10:5] */
3861  #define WM8994_AIF2DRC_KNEE_OP_MASK             0x001F  /* AIF2DRC_KNEE_OP - [4:0] */
3862  #define WM8994_AIF2DRC_KNEE_OP_SHIFT                 0  /* AIF2DRC_KNEE_OP - [4:0] */
3863  #define WM8994_AIF2DRC_KNEE_OP_WIDTH                 5  /* AIF2DRC_KNEE_OP - [4:0] */
3864  
3865  /*
3866   * R1348 (0x544) - AIF2 DRC (5)
3867   */
3868  #define WM8994_AIF2DRC_KNEE2_IP_MASK            0x03E0  /* AIF2DRC_KNEE2_IP - [9:5] */
3869  #define WM8994_AIF2DRC_KNEE2_IP_SHIFT                5  /* AIF2DRC_KNEE2_IP - [9:5] */
3870  #define WM8994_AIF2DRC_KNEE2_IP_WIDTH                5  /* AIF2DRC_KNEE2_IP - [9:5] */
3871  #define WM8994_AIF2DRC_KNEE2_OP_MASK            0x001F  /* AIF2DRC_KNEE2_OP - [4:0] */
3872  #define WM8994_AIF2DRC_KNEE2_OP_SHIFT                0  /* AIF2DRC_KNEE2_OP - [4:0] */
3873  #define WM8994_AIF2DRC_KNEE2_OP_WIDTH                5  /* AIF2DRC_KNEE2_OP - [4:0] */
3874  
3875  /*
3876   * R1408 (0x580) - AIF2 EQ Gains (1)
3877   */
3878  #define WM8994_AIF2DAC_EQ_B1_GAIN_MASK          0xF800  /* AIF2DAC_EQ_B1_GAIN - [15:11] */
3879  #define WM8994_AIF2DAC_EQ_B1_GAIN_SHIFT             11  /* AIF2DAC_EQ_B1_GAIN - [15:11] */
3880  #define WM8994_AIF2DAC_EQ_B1_GAIN_WIDTH              5  /* AIF2DAC_EQ_B1_GAIN - [15:11] */
3881  #define WM8994_AIF2DAC_EQ_B2_GAIN_MASK          0x07C0  /* AIF2DAC_EQ_B2_GAIN - [10:6] */
3882  #define WM8994_AIF2DAC_EQ_B2_GAIN_SHIFT              6  /* AIF2DAC_EQ_B2_GAIN - [10:6] */
3883  #define WM8994_AIF2DAC_EQ_B2_GAIN_WIDTH              5  /* AIF2DAC_EQ_B2_GAIN - [10:6] */
3884  #define WM8994_AIF2DAC_EQ_B3_GAIN_MASK          0x003E  /* AIF2DAC_EQ_B3_GAIN - [5:1] */
3885  #define WM8994_AIF2DAC_EQ_B3_GAIN_SHIFT              1  /* AIF2DAC_EQ_B3_GAIN - [5:1] */
3886  #define WM8994_AIF2DAC_EQ_B3_GAIN_WIDTH              5  /* AIF2DAC_EQ_B3_GAIN - [5:1] */
3887  #define WM8994_AIF2DAC_EQ_ENA                   0x0001  /* AIF2DAC_EQ_ENA */
3888  #define WM8994_AIF2DAC_EQ_ENA_MASK              0x0001  /* AIF2DAC_EQ_ENA */
3889  #define WM8994_AIF2DAC_EQ_ENA_SHIFT                  0  /* AIF2DAC_EQ_ENA */
3890  #define WM8994_AIF2DAC_EQ_ENA_WIDTH                  1  /* AIF2DAC_EQ_ENA */
3891  
3892  /*
3893   * R1409 (0x581) - AIF2 EQ Gains (2)
3894   */
3895  #define WM8994_AIF2DAC_EQ_B4_GAIN_MASK          0xF800  /* AIF2DAC_EQ_B4_GAIN - [15:11] */
3896  #define WM8994_AIF2DAC_EQ_B4_GAIN_SHIFT             11  /* AIF2DAC_EQ_B4_GAIN - [15:11] */
3897  #define WM8994_AIF2DAC_EQ_B4_GAIN_WIDTH              5  /* AIF2DAC_EQ_B4_GAIN - [15:11] */
3898  #define WM8994_AIF2DAC_EQ_B5_GAIN_MASK          0x07C0  /* AIF2DAC_EQ_B5_GAIN - [10:6] */
3899  #define WM8994_AIF2DAC_EQ_B5_GAIN_SHIFT              6  /* AIF2DAC_EQ_B5_GAIN - [10:6] */
3900  #define WM8994_AIF2DAC_EQ_B5_GAIN_WIDTH              5  /* AIF2DAC_EQ_B5_GAIN - [10:6] */
3901  
3902  /*
3903   * R1410 (0x582) - AIF2 EQ Band 1 A
3904   */
3905  #define WM8994_AIF2DAC_EQ_B1_A_MASK             0xFFFF  /* AIF2DAC_EQ_B1_A - [15:0] */
3906  #define WM8994_AIF2DAC_EQ_B1_A_SHIFT                 0  /* AIF2DAC_EQ_B1_A - [15:0] */
3907  #define WM8994_AIF2DAC_EQ_B1_A_WIDTH                16  /* AIF2DAC_EQ_B1_A - [15:0] */
3908  
3909  /*
3910   * R1411 (0x583) - AIF2 EQ Band 1 B
3911   */
3912  #define WM8994_AIF2DAC_EQ_B1_B_MASK             0xFFFF  /* AIF2DAC_EQ_B1_B - [15:0] */
3913  #define WM8994_AIF2DAC_EQ_B1_B_SHIFT                 0  /* AIF2DAC_EQ_B1_B - [15:0] */
3914  #define WM8994_AIF2DAC_EQ_B1_B_WIDTH                16  /* AIF2DAC_EQ_B1_B - [15:0] */
3915  
3916  /*
3917   * R1412 (0x584) - AIF2 EQ Band 1 PG
3918   */
3919  #define WM8994_AIF2DAC_EQ_B1_PG_MASK            0xFFFF  /* AIF2DAC_EQ_B1_PG - [15:0] */
3920  #define WM8994_AIF2DAC_EQ_B1_PG_SHIFT                0  /* AIF2DAC_EQ_B1_PG - [15:0] */
3921  #define WM8994_AIF2DAC_EQ_B1_PG_WIDTH               16  /* AIF2DAC_EQ_B1_PG - [15:0] */
3922  
3923  /*
3924   * R1413 (0x585) - AIF2 EQ Band 2 A
3925   */
3926  #define WM8994_AIF2DAC_EQ_B2_A_MASK             0xFFFF  /* AIF2DAC_EQ_B2_A - [15:0] */
3927  #define WM8994_AIF2DAC_EQ_B2_A_SHIFT                 0  /* AIF2DAC_EQ_B2_A - [15:0] */
3928  #define WM8994_AIF2DAC_EQ_B2_A_WIDTH                16  /* AIF2DAC_EQ_B2_A - [15:0] */
3929  
3930  /*
3931   * R1414 (0x586) - AIF2 EQ Band 2 B
3932   */
3933  #define WM8994_AIF2DAC_EQ_B2_B_MASK             0xFFFF  /* AIF2DAC_EQ_B2_B - [15:0] */
3934  #define WM8994_AIF2DAC_EQ_B2_B_SHIFT                 0  /* AIF2DAC_EQ_B2_B - [15:0] */
3935  #define WM8994_AIF2DAC_EQ_B2_B_WIDTH                16  /* AIF2DAC_EQ_B2_B - [15:0] */
3936  
3937  /*
3938   * R1415 (0x587) - AIF2 EQ Band 2 C
3939   */
3940  #define WM8994_AIF2DAC_EQ_B2_C_MASK             0xFFFF  /* AIF2DAC_EQ_B2_C - [15:0] */
3941  #define WM8994_AIF2DAC_EQ_B2_C_SHIFT                 0  /* AIF2DAC_EQ_B2_C - [15:0] */
3942  #define WM8994_AIF2DAC_EQ_B2_C_WIDTH                16  /* AIF2DAC_EQ_B2_C - [15:0] */
3943  
3944  /*
3945   * R1416 (0x588) - AIF2 EQ Band 2 PG
3946   */
3947  #define WM8994_AIF2DAC_EQ_B2_PG_MASK            0xFFFF  /* AIF2DAC_EQ_B2_PG - [15:0] */
3948  #define WM8994_AIF2DAC_EQ_B2_PG_SHIFT                0  /* AIF2DAC_EQ_B2_PG - [15:0] */
3949  #define WM8994_AIF2DAC_EQ_B2_PG_WIDTH               16  /* AIF2DAC_EQ_B2_PG - [15:0] */
3950  
3951  /*
3952   * R1417 (0x589) - AIF2 EQ Band 3 A
3953   */
3954  #define WM8994_AIF2DAC_EQ_B3_A_MASK             0xFFFF  /* AIF2DAC_EQ_B3_A - [15:0] */
3955  #define WM8994_AIF2DAC_EQ_B3_A_SHIFT                 0  /* AIF2DAC_EQ_B3_A - [15:0] */
3956  #define WM8994_AIF2DAC_EQ_B3_A_WIDTH                16  /* AIF2DAC_EQ_B3_A - [15:0] */
3957  
3958  /*
3959   * R1418 (0x58A) - AIF2 EQ Band 3 B
3960   */
3961  #define WM8994_AIF2DAC_EQ_B3_B_MASK             0xFFFF  /* AIF2DAC_EQ_B3_B - [15:0] */
3962  #define WM8994_AIF2DAC_EQ_B3_B_SHIFT                 0  /* AIF2DAC_EQ_B3_B - [15:0] */
3963  #define WM8994_AIF2DAC_EQ_B3_B_WIDTH                16  /* AIF2DAC_EQ_B3_B - [15:0] */
3964  
3965  /*
3966   * R1419 (0x58B) - AIF2 EQ Band 3 C
3967   */
3968  #define WM8994_AIF2DAC_EQ_B3_C_MASK             0xFFFF  /* AIF2DAC_EQ_B3_C - [15:0] */
3969  #define WM8994_AIF2DAC_EQ_B3_C_SHIFT                 0  /* AIF2DAC_EQ_B3_C - [15:0] */
3970  #define WM8994_AIF2DAC_EQ_B3_C_WIDTH                16  /* AIF2DAC_EQ_B3_C - [15:0] */
3971  
3972  /*
3973   * R1420 (0x58C) - AIF2 EQ Band 3 PG
3974   */
3975  #define WM8994_AIF2DAC_EQ_B3_PG_MASK            0xFFFF  /* AIF2DAC_EQ_B3_PG - [15:0] */
3976  #define WM8994_AIF2DAC_EQ_B3_PG_SHIFT                0  /* AIF2DAC_EQ_B3_PG - [15:0] */
3977  #define WM8994_AIF2DAC_EQ_B3_PG_WIDTH               16  /* AIF2DAC_EQ_B3_PG - [15:0] */
3978  
3979  /*
3980   * R1421 (0x58D) - AIF2 EQ Band 4 A
3981   */
3982  #define WM8994_AIF2DAC_EQ_B4_A_MASK             0xFFFF  /* AIF2DAC_EQ_B4_A - [15:0] */
3983  #define WM8994_AIF2DAC_EQ_B4_A_SHIFT                 0  /* AIF2DAC_EQ_B4_A - [15:0] */
3984  #define WM8994_AIF2DAC_EQ_B4_A_WIDTH                16  /* AIF2DAC_EQ_B4_A - [15:0] */
3985  
3986  /*
3987   * R1422 (0x58E) - AIF2 EQ Band 4 B
3988   */
3989  #define WM8994_AIF2DAC_EQ_B4_B_MASK             0xFFFF  /* AIF2DAC_EQ_B4_B - [15:0] */
3990  #define WM8994_AIF2DAC_EQ_B4_B_SHIFT                 0  /* AIF2DAC_EQ_B4_B - [15:0] */
3991  #define WM8994_AIF2DAC_EQ_B4_B_WIDTH                16  /* AIF2DAC_EQ_B4_B - [15:0] */
3992  
3993  /*
3994   * R1423 (0x58F) - AIF2 EQ Band 4 C
3995   */
3996  #define WM8994_AIF2DAC_EQ_B4_C_MASK             0xFFFF  /* AIF2DAC_EQ_B4_C - [15:0] */
3997  #define WM8994_AIF2DAC_EQ_B4_C_SHIFT                 0  /* AIF2DAC_EQ_B4_C - [15:0] */
3998  #define WM8994_AIF2DAC_EQ_B4_C_WIDTH                16  /* AIF2DAC_EQ_B4_C - [15:0] */
3999  
4000  /*
4001   * R1424 (0x590) - AIF2 EQ Band 4 PG
4002   */
4003  #define WM8994_AIF2DAC_EQ_B4_PG_MASK            0xFFFF  /* AIF2DAC_EQ_B4_PG - [15:0] */
4004  #define WM8994_AIF2DAC_EQ_B4_PG_SHIFT                0  /* AIF2DAC_EQ_B4_PG - [15:0] */
4005  #define WM8994_AIF2DAC_EQ_B4_PG_WIDTH               16  /* AIF2DAC_EQ_B4_PG - [15:0] */
4006  
4007  /*
4008   * R1425 (0x591) - AIF2 EQ Band 5 A
4009   */
4010  #define WM8994_AIF2DAC_EQ_B5_A_MASK             0xFFFF  /* AIF2DAC_EQ_B5_A - [15:0] */
4011  #define WM8994_AIF2DAC_EQ_B5_A_SHIFT                 0  /* AIF2DAC_EQ_B5_A - [15:0] */
4012  #define WM8994_AIF2DAC_EQ_B5_A_WIDTH                16  /* AIF2DAC_EQ_B5_A - [15:0] */
4013  
4014  /*
4015   * R1426 (0x592) - AIF2 EQ Band 5 B
4016   */
4017  #define WM8994_AIF2DAC_EQ_B5_B_MASK             0xFFFF  /* AIF2DAC_EQ_B5_B - [15:0] */
4018  #define WM8994_AIF2DAC_EQ_B5_B_SHIFT                 0  /* AIF2DAC_EQ_B5_B - [15:0] */
4019  #define WM8994_AIF2DAC_EQ_B5_B_WIDTH                16  /* AIF2DAC_EQ_B5_B - [15:0] */
4020  
4021  /*
4022   * R1427 (0x593) - AIF2 EQ Band 5 PG
4023   */
4024  #define WM8994_AIF2DAC_EQ_B5_PG_MASK            0xFFFF  /* AIF2DAC_EQ_B5_PG - [15:0] */
4025  #define WM8994_AIF2DAC_EQ_B5_PG_SHIFT                0  /* AIF2DAC_EQ_B5_PG - [15:0] */
4026  #define WM8994_AIF2DAC_EQ_B5_PG_WIDTH               16  /* AIF2DAC_EQ_B5_PG - [15:0] */
4027  
4028  /*
4029   * R1536 (0x600) - DAC1 Mixer Volumes
4030   */
4031  #define WM8994_ADCR_DAC1_VOL_MASK               0x01E0  /* ADCR_DAC1_VOL - [8:5] */
4032  #define WM8994_ADCR_DAC1_VOL_SHIFT                   5  /* ADCR_DAC1_VOL - [8:5] */
4033  #define WM8994_ADCR_DAC1_VOL_WIDTH                   4  /* ADCR_DAC1_VOL - [8:5] */
4034  #define WM8994_ADCL_DAC1_VOL_MASK               0x000F  /* ADCL_DAC1_VOL - [3:0] */
4035  #define WM8994_ADCL_DAC1_VOL_SHIFT                   0  /* ADCL_DAC1_VOL - [3:0] */
4036  #define WM8994_ADCL_DAC1_VOL_WIDTH                   4  /* ADCL_DAC1_VOL - [3:0] */
4037  
4038  /*
4039   * R1537 (0x601) - DAC1 Left Mixer Routing
4040   */
4041  #define WM8994_ADCR_TO_DAC1L                    0x0020  /* ADCR_TO_DAC1L */
4042  #define WM8994_ADCR_TO_DAC1L_MASK               0x0020  /* ADCR_TO_DAC1L */
4043  #define WM8994_ADCR_TO_DAC1L_SHIFT                   5  /* ADCR_TO_DAC1L */
4044  #define WM8994_ADCR_TO_DAC1L_WIDTH                   1  /* ADCR_TO_DAC1L */
4045  #define WM8994_ADCL_TO_DAC1L                    0x0010  /* ADCL_TO_DAC1L */
4046  #define WM8994_ADCL_TO_DAC1L_MASK               0x0010  /* ADCL_TO_DAC1L */
4047  #define WM8994_ADCL_TO_DAC1L_SHIFT                   4  /* ADCL_TO_DAC1L */
4048  #define WM8994_ADCL_TO_DAC1L_WIDTH                   1  /* ADCL_TO_DAC1L */
4049  #define WM8994_AIF2DACL_TO_DAC1L                0x0004  /* AIF2DACL_TO_DAC1L */
4050  #define WM8994_AIF2DACL_TO_DAC1L_MASK           0x0004  /* AIF2DACL_TO_DAC1L */
4051  #define WM8994_AIF2DACL_TO_DAC1L_SHIFT               2  /* AIF2DACL_TO_DAC1L */
4052  #define WM8994_AIF2DACL_TO_DAC1L_WIDTH               1  /* AIF2DACL_TO_DAC1L */
4053  #define WM8994_AIF1DAC2L_TO_DAC1L               0x0002  /* AIF1DAC2L_TO_DAC1L */
4054  #define WM8994_AIF1DAC2L_TO_DAC1L_MASK          0x0002  /* AIF1DAC2L_TO_DAC1L */
4055  #define WM8994_AIF1DAC2L_TO_DAC1L_SHIFT              1  /* AIF1DAC2L_TO_DAC1L */
4056  #define WM8994_AIF1DAC2L_TO_DAC1L_WIDTH              1  /* AIF1DAC2L_TO_DAC1L */
4057  #define WM8994_AIF1DAC1L_TO_DAC1L               0x0001  /* AIF1DAC1L_TO_DAC1L */
4058  #define WM8994_AIF1DAC1L_TO_DAC1L_MASK          0x0001  /* AIF1DAC1L_TO_DAC1L */
4059  #define WM8994_AIF1DAC1L_TO_DAC1L_SHIFT              0  /* AIF1DAC1L_TO_DAC1L */
4060  #define WM8994_AIF1DAC1L_TO_DAC1L_WIDTH              1  /* AIF1DAC1L_TO_DAC1L */
4061  
4062  /*
4063   * R1538 (0x602) - DAC1 Right Mixer Routing
4064   */
4065  #define WM8994_ADCR_TO_DAC1R                    0x0020  /* ADCR_TO_DAC1R */
4066  #define WM8994_ADCR_TO_DAC1R_MASK               0x0020  /* ADCR_TO_DAC1R */
4067  #define WM8994_ADCR_TO_DAC1R_SHIFT                   5  /* ADCR_TO_DAC1R */
4068  #define WM8994_ADCR_TO_DAC1R_WIDTH                   1  /* ADCR_TO_DAC1R */
4069  #define WM8994_ADCL_TO_DAC1R                    0x0010  /* ADCL_TO_DAC1R */
4070  #define WM8994_ADCL_TO_DAC1R_MASK               0x0010  /* ADCL_TO_DAC1R */
4071  #define WM8994_ADCL_TO_DAC1R_SHIFT                   4  /* ADCL_TO_DAC1R */
4072  #define WM8994_ADCL_TO_DAC1R_WIDTH                   1  /* ADCL_TO_DAC1R */
4073  #define WM8994_AIF2DACR_TO_DAC1R                0x0004  /* AIF2DACR_TO_DAC1R */
4074  #define WM8994_AIF2DACR_TO_DAC1R_MASK           0x0004  /* AIF2DACR_TO_DAC1R */
4075  #define WM8994_AIF2DACR_TO_DAC1R_SHIFT               2  /* AIF2DACR_TO_DAC1R */
4076  #define WM8994_AIF2DACR_TO_DAC1R_WIDTH               1  /* AIF2DACR_TO_DAC1R */
4077  #define WM8994_AIF1DAC2R_TO_DAC1R               0x0002  /* AIF1DAC2R_TO_DAC1R */
4078  #define WM8994_AIF1DAC2R_TO_DAC1R_MASK          0x0002  /* AIF1DAC2R_TO_DAC1R */
4079  #define WM8994_AIF1DAC2R_TO_DAC1R_SHIFT              1  /* AIF1DAC2R_TO_DAC1R */
4080  #define WM8994_AIF1DAC2R_TO_DAC1R_WIDTH              1  /* AIF1DAC2R_TO_DAC1R */
4081  #define WM8994_AIF1DAC1R_TO_DAC1R               0x0001  /* AIF1DAC1R_TO_DAC1R */
4082  #define WM8994_AIF1DAC1R_TO_DAC1R_MASK          0x0001  /* AIF1DAC1R_TO_DAC1R */
4083  #define WM8994_AIF1DAC1R_TO_DAC1R_SHIFT              0  /* AIF1DAC1R_TO_DAC1R */
4084  #define WM8994_AIF1DAC1R_TO_DAC1R_WIDTH              1  /* AIF1DAC1R_TO_DAC1R */
4085  
4086  /*
4087   * R1539 (0x603) - DAC2 Mixer Volumes
4088   */
4089  #define WM8994_ADCR_DAC2_VOL_MASK               0x01E0  /* ADCR_DAC2_VOL - [8:5] */
4090  #define WM8994_ADCR_DAC2_VOL_SHIFT                   5  /* ADCR_DAC2_VOL - [8:5] */
4091  #define WM8994_ADCR_DAC2_VOL_WIDTH                   4  /* ADCR_DAC2_VOL - [8:5] */
4092  #define WM8994_ADCL_DAC2_VOL_MASK               0x000F  /* ADCL_DAC2_VOL - [3:0] */
4093  #define WM8994_ADCL_DAC2_VOL_SHIFT                   0  /* ADCL_DAC2_VOL - [3:0] */
4094  #define WM8994_ADCL_DAC2_VOL_WIDTH                   4  /* ADCL_DAC2_VOL - [3:0] */
4095  
4096  /*
4097   * R1540 (0x604) - DAC2 Left Mixer Routing
4098   */
4099  #define WM8994_ADCR_TO_DAC2L                    0x0020  /* ADCR_TO_DAC2L */
4100  #define WM8994_ADCR_TO_DAC2L_MASK               0x0020  /* ADCR_TO_DAC2L */
4101  #define WM8994_ADCR_TO_DAC2L_SHIFT                   5  /* ADCR_TO_DAC2L */
4102  #define WM8994_ADCR_TO_DAC2L_WIDTH                   1  /* ADCR_TO_DAC2L */
4103  #define WM8994_ADCL_TO_DAC2L                    0x0010  /* ADCL_TO_DAC2L */
4104  #define WM8994_ADCL_TO_DAC2L_MASK               0x0010  /* ADCL_TO_DAC2L */
4105  #define WM8994_ADCL_TO_DAC2L_SHIFT                   4  /* ADCL_TO_DAC2L */
4106  #define WM8994_ADCL_TO_DAC2L_WIDTH                   1  /* ADCL_TO_DAC2L */
4107  #define WM8994_AIF2DACL_TO_DAC2L                0x0004  /* AIF2DACL_TO_DAC2L */
4108  #define WM8994_AIF2DACL_TO_DAC2L_MASK           0x0004  /* AIF2DACL_TO_DAC2L */
4109  #define WM8994_AIF2DACL_TO_DAC2L_SHIFT               2  /* AIF2DACL_TO_DAC2L */
4110  #define WM8994_AIF2DACL_TO_DAC2L_WIDTH               1  /* AIF2DACL_TO_DAC2L */
4111  #define WM8994_AIF1DAC2L_TO_DAC2L               0x0002  /* AIF1DAC2L_TO_DAC2L */
4112  #define WM8994_AIF1DAC2L_TO_DAC2L_MASK          0x0002  /* AIF1DAC2L_TO_DAC2L */
4113  #define WM8994_AIF1DAC2L_TO_DAC2L_SHIFT              1  /* AIF1DAC2L_TO_DAC2L */
4114  #define WM8994_AIF1DAC2L_TO_DAC2L_WIDTH              1  /* AIF1DAC2L_TO_DAC2L */
4115  #define WM8994_AIF1DAC1L_TO_DAC2L               0x0001  /* AIF1DAC1L_TO_DAC2L */
4116  #define WM8994_AIF1DAC1L_TO_DAC2L_MASK          0x0001  /* AIF1DAC1L_TO_DAC2L */
4117  #define WM8994_AIF1DAC1L_TO_DAC2L_SHIFT              0  /* AIF1DAC1L_TO_DAC2L */
4118  #define WM8994_AIF1DAC1L_TO_DAC2L_WIDTH              1  /* AIF1DAC1L_TO_DAC2L */
4119  
4120  /*
4121   * R1541 (0x605) - DAC2 Right Mixer Routing
4122   */
4123  #define WM8994_ADCR_TO_DAC2R                    0x0020  /* ADCR_TO_DAC2R */
4124  #define WM8994_ADCR_TO_DAC2R_MASK               0x0020  /* ADCR_TO_DAC2R */
4125  #define WM8994_ADCR_TO_DAC2R_SHIFT                   5  /* ADCR_TO_DAC2R */
4126  #define WM8994_ADCR_TO_DAC2R_WIDTH                   1  /* ADCR_TO_DAC2R */
4127  #define WM8994_ADCL_TO_DAC2R                    0x0010  /* ADCL_TO_DAC2R */
4128  #define WM8994_ADCL_TO_DAC2R_MASK               0x0010  /* ADCL_TO_DAC2R */
4129  #define WM8994_ADCL_TO_DAC2R_SHIFT                   4  /* ADCL_TO_DAC2R */
4130  #define WM8994_ADCL_TO_DAC2R_WIDTH                   1  /* ADCL_TO_DAC2R */
4131  #define WM8994_AIF2DACR_TO_DAC2R                0x0004  /* AIF2DACR_TO_DAC2R */
4132  #define WM8994_AIF2DACR_TO_DAC2R_MASK           0x0004  /* AIF2DACR_TO_DAC2R */
4133  #define WM8994_AIF2DACR_TO_DAC2R_SHIFT               2  /* AIF2DACR_TO_DAC2R */
4134  #define WM8994_AIF2DACR_TO_DAC2R_WIDTH               1  /* AIF2DACR_TO_DAC2R */
4135  #define WM8994_AIF1DAC2R_TO_DAC2R               0x0002  /* AIF1DAC2R_TO_DAC2R */
4136  #define WM8994_AIF1DAC2R_TO_DAC2R_MASK          0x0002  /* AIF1DAC2R_TO_DAC2R */
4137  #define WM8994_AIF1DAC2R_TO_DAC2R_SHIFT              1  /* AIF1DAC2R_TO_DAC2R */
4138  #define WM8994_AIF1DAC2R_TO_DAC2R_WIDTH              1  /* AIF1DAC2R_TO_DAC2R */
4139  #define WM8994_AIF1DAC1R_TO_DAC2R               0x0001  /* AIF1DAC1R_TO_DAC2R */
4140  #define WM8994_AIF1DAC1R_TO_DAC2R_MASK          0x0001  /* AIF1DAC1R_TO_DAC2R */
4141  #define WM8994_AIF1DAC1R_TO_DAC2R_SHIFT              0  /* AIF1DAC1R_TO_DAC2R */
4142  #define WM8994_AIF1DAC1R_TO_DAC2R_WIDTH              1  /* AIF1DAC1R_TO_DAC2R */
4143  
4144  /*
4145   * R1542 (0x606) - AIF1 ADC1 Left Mixer Routing
4146   */
4147  #define WM8994_ADC1L_TO_AIF1ADC1L               0x0002  /* ADC1L_TO_AIF1ADC1L */
4148  #define WM8994_ADC1L_TO_AIF1ADC1L_MASK          0x0002  /* ADC1L_TO_AIF1ADC1L */
4149  #define WM8994_ADC1L_TO_AIF1ADC1L_SHIFT              1  /* ADC1L_TO_AIF1ADC1L */
4150  #define WM8994_ADC1L_TO_AIF1ADC1L_WIDTH              1  /* ADC1L_TO_AIF1ADC1L */
4151  #define WM8994_AIF2DACL_TO_AIF1ADC1L            0x0001  /* AIF2DACL_TO_AIF1ADC1L */
4152  #define WM8994_AIF2DACL_TO_AIF1ADC1L_MASK       0x0001  /* AIF2DACL_TO_AIF1ADC1L */
4153  #define WM8994_AIF2DACL_TO_AIF1ADC1L_SHIFT           0  /* AIF2DACL_TO_AIF1ADC1L */
4154  #define WM8994_AIF2DACL_TO_AIF1ADC1L_WIDTH           1  /* AIF2DACL_TO_AIF1ADC1L */
4155  
4156  /*
4157   * R1543 (0x607) - AIF1 ADC1 Right Mixer Routing
4158   */
4159  #define WM8994_ADC1R_TO_AIF1ADC1R               0x0002  /* ADC1R_TO_AIF1ADC1R */
4160  #define WM8994_ADC1R_TO_AIF1ADC1R_MASK          0x0002  /* ADC1R_TO_AIF1ADC1R */
4161  #define WM8994_ADC1R_TO_AIF1ADC1R_SHIFT              1  /* ADC1R_TO_AIF1ADC1R */
4162  #define WM8994_ADC1R_TO_AIF1ADC1R_WIDTH              1  /* ADC1R_TO_AIF1ADC1R */
4163  #define WM8994_AIF2DACR_TO_AIF1ADC1R            0x0001  /* AIF2DACR_TO_AIF1ADC1R */
4164  #define WM8994_AIF2DACR_TO_AIF1ADC1R_MASK       0x0001  /* AIF2DACR_TO_AIF1ADC1R */
4165  #define WM8994_AIF2DACR_TO_AIF1ADC1R_SHIFT           0  /* AIF2DACR_TO_AIF1ADC1R */
4166  #define WM8994_AIF2DACR_TO_AIF1ADC1R_WIDTH           1  /* AIF2DACR_TO_AIF1ADC1R */
4167  
4168  /*
4169   * R1544 (0x608) - AIF1 ADC2 Left Mixer Routing
4170   */
4171  #define WM8994_ADC2L_TO_AIF1ADC2L               0x0002  /* ADC2L_TO_AIF1ADC2L */
4172  #define WM8994_ADC2L_TO_AIF1ADC2L_MASK          0x0002  /* ADC2L_TO_AIF1ADC2L */
4173  #define WM8994_ADC2L_TO_AIF1ADC2L_SHIFT              1  /* ADC2L_TO_AIF1ADC2L */
4174  #define WM8994_ADC2L_TO_AIF1ADC2L_WIDTH              1  /* ADC2L_TO_AIF1ADC2L */
4175  #define WM8994_AIF2DACL_TO_AIF1ADC2L            0x0001  /* AIF2DACL_TO_AIF1ADC2L */
4176  #define WM8994_AIF2DACL_TO_AIF1ADC2L_MASK       0x0001  /* AIF2DACL_TO_AIF1ADC2L */
4177  #define WM8994_AIF2DACL_TO_AIF1ADC2L_SHIFT           0  /* AIF2DACL_TO_AIF1ADC2L */
4178  #define WM8994_AIF2DACL_TO_AIF1ADC2L_WIDTH           1  /* AIF2DACL_TO_AIF1ADC2L */
4179  
4180  /*
4181   * R1545 (0x609) - AIF1 ADC2 Right mixer Routing
4182   */
4183  #define WM8994_ADC2R_TO_AIF1ADC2R               0x0002  /* ADC2R_TO_AIF1ADC2R */
4184  #define WM8994_ADC2R_TO_AIF1ADC2R_MASK          0x0002  /* ADC2R_TO_AIF1ADC2R */
4185  #define WM8994_ADC2R_TO_AIF1ADC2R_SHIFT              1  /* ADC2R_TO_AIF1ADC2R */
4186  #define WM8994_ADC2R_TO_AIF1ADC2R_WIDTH              1  /* ADC2R_TO_AIF1ADC2R */
4187  #define WM8994_AIF2DACR_TO_AIF1ADC2R            0x0001  /* AIF2DACR_TO_AIF1ADC2R */
4188  #define WM8994_AIF2DACR_TO_AIF1ADC2R_MASK       0x0001  /* AIF2DACR_TO_AIF1ADC2R */
4189  #define WM8994_AIF2DACR_TO_AIF1ADC2R_SHIFT           0  /* AIF2DACR_TO_AIF1ADC2R */
4190  #define WM8994_AIF2DACR_TO_AIF1ADC2R_WIDTH           1  /* AIF2DACR_TO_AIF1ADC2R */
4191  
4192  /*
4193   * R1552 (0x610) - DAC1 Left Volume
4194   */
4195  #define WM8994_DAC1L_MUTE                       0x0200  /* DAC1L_MUTE */
4196  #define WM8994_DAC1L_MUTE_MASK                  0x0200  /* DAC1L_MUTE */
4197  #define WM8994_DAC1L_MUTE_SHIFT                      9  /* DAC1L_MUTE */
4198  #define WM8994_DAC1L_MUTE_WIDTH                      1  /* DAC1L_MUTE */
4199  #define WM8994_DAC1_VU                          0x0100  /* DAC1_VU */
4200  #define WM8994_DAC1_VU_MASK                     0x0100  /* DAC1_VU */
4201  #define WM8994_DAC1_VU_SHIFT                         8  /* DAC1_VU */
4202  #define WM8994_DAC1_VU_WIDTH                         1  /* DAC1_VU */
4203  #define WM8994_DAC1L_VOL_MASK                   0x00FF  /* DAC1L_VOL - [7:0] */
4204  #define WM8994_DAC1L_VOL_SHIFT                       0  /* DAC1L_VOL - [7:0] */
4205  #define WM8994_DAC1L_VOL_WIDTH                       8  /* DAC1L_VOL - [7:0] */
4206  
4207  /*
4208   * R1553 (0x611) - DAC1 Right Volume
4209   */
4210  #define WM8994_DAC1R_MUTE                       0x0200  /* DAC1R_MUTE */
4211  #define WM8994_DAC1R_MUTE_MASK                  0x0200  /* DAC1R_MUTE */
4212  #define WM8994_DAC1R_MUTE_SHIFT                      9  /* DAC1R_MUTE */
4213  #define WM8994_DAC1R_MUTE_WIDTH                      1  /* DAC1R_MUTE */
4214  #define WM8994_DAC1_VU                          0x0100  /* DAC1_VU */
4215  #define WM8994_DAC1_VU_MASK                     0x0100  /* DAC1_VU */
4216  #define WM8994_DAC1_VU_SHIFT                         8  /* DAC1_VU */
4217  #define WM8994_DAC1_VU_WIDTH                         1  /* DAC1_VU */
4218  #define WM8994_DAC1R_VOL_MASK                   0x00FF  /* DAC1R_VOL - [7:0] */
4219  #define WM8994_DAC1R_VOL_SHIFT                       0  /* DAC1R_VOL - [7:0] */
4220  #define WM8994_DAC1R_VOL_WIDTH                       8  /* DAC1R_VOL - [7:0] */
4221  
4222  /*
4223   * R1554 (0x612) - DAC2 Left Volume
4224   */
4225  #define WM8994_DAC2L_MUTE                       0x0200  /* DAC2L_MUTE */
4226  #define WM8994_DAC2L_MUTE_MASK                  0x0200  /* DAC2L_MUTE */
4227  #define WM8994_DAC2L_MUTE_SHIFT                      9  /* DAC2L_MUTE */
4228  #define WM8994_DAC2L_MUTE_WIDTH                      1  /* DAC2L_MUTE */
4229  #define WM8994_DAC2_VU                          0x0100  /* DAC2_VU */
4230  #define WM8994_DAC2_VU_MASK                     0x0100  /* DAC2_VU */
4231  #define WM8994_DAC2_VU_SHIFT                         8  /* DAC2_VU */
4232  #define WM8994_DAC2_VU_WIDTH                         1  /* DAC2_VU */
4233  #define WM8994_DAC2L_VOL_MASK                   0x00FF  /* DAC2L_VOL - [7:0] */
4234  #define WM8994_DAC2L_VOL_SHIFT                       0  /* DAC2L_VOL - [7:0] */
4235  #define WM8994_DAC2L_VOL_WIDTH                       8  /* DAC2L_VOL - [7:0] */
4236  
4237  /*
4238   * R1555 (0x613) - DAC2 Right Volume
4239   */
4240  #define WM8994_DAC2R_MUTE                       0x0200  /* DAC2R_MUTE */
4241  #define WM8994_DAC2R_MUTE_MASK                  0x0200  /* DAC2R_MUTE */
4242  #define WM8994_DAC2R_MUTE_SHIFT                      9  /* DAC2R_MUTE */
4243  #define WM8994_DAC2R_MUTE_WIDTH                      1  /* DAC2R_MUTE */
4244  #define WM8994_DAC2_VU                          0x0100  /* DAC2_VU */
4245  #define WM8994_DAC2_VU_MASK                     0x0100  /* DAC2_VU */
4246  #define WM8994_DAC2_VU_SHIFT                         8  /* DAC2_VU */
4247  #define WM8994_DAC2_VU_WIDTH                         1  /* DAC2_VU */
4248  #define WM8994_DAC2R_VOL_MASK                   0x00FF  /* DAC2R_VOL - [7:0] */
4249  #define WM8994_DAC2R_VOL_SHIFT                       0  /* DAC2R_VOL - [7:0] */
4250  #define WM8994_DAC2R_VOL_WIDTH                       8  /* DAC2R_VOL - [7:0] */
4251  
4252  /*
4253   * R1556 (0x614) - DAC Softmute
4254   */
4255  #define WM8994_DAC_SOFTMUTEMODE                 0x0002  /* DAC_SOFTMUTEMODE */
4256  #define WM8994_DAC_SOFTMUTEMODE_MASK            0x0002  /* DAC_SOFTMUTEMODE */
4257  #define WM8994_DAC_SOFTMUTEMODE_SHIFT                1  /* DAC_SOFTMUTEMODE */
4258  #define WM8994_DAC_SOFTMUTEMODE_WIDTH                1  /* DAC_SOFTMUTEMODE */
4259  #define WM8994_DAC_MUTERATE                     0x0001  /* DAC_MUTERATE */
4260  #define WM8994_DAC_MUTERATE_MASK                0x0001  /* DAC_MUTERATE */
4261  #define WM8994_DAC_MUTERATE_SHIFT                    0  /* DAC_MUTERATE */
4262  #define WM8994_DAC_MUTERATE_WIDTH                    1  /* DAC_MUTERATE */
4263  
4264  /*
4265   * R1568 (0x620) - Oversampling
4266   */
4267  #define WM8994_ADC_OSR128                       0x0002  /* ADC_OSR128 */
4268  #define WM8994_ADC_OSR128_MASK                  0x0002  /* ADC_OSR128 */
4269  #define WM8994_ADC_OSR128_SHIFT                      1  /* ADC_OSR128 */
4270  #define WM8994_ADC_OSR128_WIDTH                      1  /* ADC_OSR128 */
4271  #define WM8994_DAC_OSR128                       0x0001  /* DAC_OSR128 */
4272  #define WM8994_DAC_OSR128_MASK                  0x0001  /* DAC_OSR128 */
4273  #define WM8994_DAC_OSR128_SHIFT                      0  /* DAC_OSR128 */
4274  #define WM8994_DAC_OSR128_WIDTH                      1  /* DAC_OSR128 */
4275  
4276  /*
4277   * R1569 (0x621) - Sidetone
4278   */
4279  #define WM8994_ST_HPF_CUT_MASK                  0x0380  /* ST_HPF_CUT - [9:7] */
4280  #define WM8994_ST_HPF_CUT_SHIFT                      7  /* ST_HPF_CUT - [9:7] */
4281  #define WM8994_ST_HPF_CUT_WIDTH                      3  /* ST_HPF_CUT - [9:7] */
4282  #define WM8994_ST_HPF                           0x0040  /* ST_HPF */
4283  #define WM8994_ST_HPF_MASK                      0x0040  /* ST_HPF */
4284  #define WM8994_ST_HPF_SHIFT                          6  /* ST_HPF */
4285  #define WM8994_ST_HPF_WIDTH                          1  /* ST_HPF */
4286  #define WM8994_STR_SEL                          0x0002  /* STR_SEL */
4287  #define WM8994_STR_SEL_MASK                     0x0002  /* STR_SEL */
4288  #define WM8994_STR_SEL_SHIFT                         1  /* STR_SEL */
4289  #define WM8994_STR_SEL_WIDTH                         1  /* STR_SEL */
4290  #define WM8994_STL_SEL                          0x0001  /* STL_SEL */
4291  #define WM8994_STL_SEL_MASK                     0x0001  /* STL_SEL */
4292  #define WM8994_STL_SEL_SHIFT                         0  /* STL_SEL */
4293  #define WM8994_STL_SEL_WIDTH                         1  /* STL_SEL */
4294  
4295  /*
4296   * R1797 (0x705) - JACKDET Ctrl
4297   */
4298  #define WM1811_JACKDET_DB                       0x0100  /* JACKDET_DB */
4299  #define WM1811_JACKDET_DB_MASK                  0x0100  /* JACKDET_DB */
4300  #define WM1811_JACKDET_DB_SHIFT                      8  /* JACKDET_DB */
4301  #define WM1811_JACKDET_DB_WIDTH                      1  /* JACKDET_DB */
4302  #define WM1811_JACKDET_LVL                      0x0040  /* JACKDET_LVL */
4303  #define WM1811_JACKDET_LVL_MASK                 0x0040  /* JACKDET_LVL */
4304  #define WM1811_JACKDET_LVL_SHIFT                     6  /* JACKDET_LVL */
4305  #define WM1811_JACKDET_LVL_WIDTH                     1  /* JACKDET_LVL */
4306  
4307  /*
4308   * R1824 (0x720) - Pull Control (1)
4309   */
4310  #define WM8994_DMICDAT2_PU                      0x0800  /* DMICDAT2_PU */
4311  #define WM8994_DMICDAT2_PU_MASK                 0x0800  /* DMICDAT2_PU */
4312  #define WM8994_DMICDAT2_PU_SHIFT                    11  /* DMICDAT2_PU */
4313  #define WM8994_DMICDAT2_PU_WIDTH                     1  /* DMICDAT2_PU */
4314  #define WM8994_DMICDAT2_PD                      0x0400  /* DMICDAT2_PD */
4315  #define WM8994_DMICDAT2_PD_MASK                 0x0400  /* DMICDAT2_PD */
4316  #define WM8994_DMICDAT2_PD_SHIFT                    10  /* DMICDAT2_PD */
4317  #define WM8994_DMICDAT2_PD_WIDTH                     1  /* DMICDAT2_PD */
4318  #define WM8994_DMICDAT1_PU                      0x0200  /* DMICDAT1_PU */
4319  #define WM8994_DMICDAT1_PU_MASK                 0x0200  /* DMICDAT1_PU */
4320  #define WM8994_DMICDAT1_PU_SHIFT                     9  /* DMICDAT1_PU */
4321  #define WM8994_DMICDAT1_PU_WIDTH                     1  /* DMICDAT1_PU */
4322  #define WM8994_DMICDAT1_PD                      0x0100  /* DMICDAT1_PD */
4323  #define WM8994_DMICDAT1_PD_MASK                 0x0100  /* DMICDAT1_PD */
4324  #define WM8994_DMICDAT1_PD_SHIFT                     8  /* DMICDAT1_PD */
4325  #define WM8994_DMICDAT1_PD_WIDTH                     1  /* DMICDAT1_PD */
4326  #define WM8994_MCLK1_PU                         0x0080  /* MCLK1_PU */
4327  #define WM8994_MCLK1_PU_MASK                    0x0080  /* MCLK1_PU */
4328  #define WM8994_MCLK1_PU_SHIFT                        7  /* MCLK1_PU */
4329  #define WM8994_MCLK1_PU_WIDTH                        1  /* MCLK1_PU */
4330  #define WM8994_MCLK1_PD                         0x0040  /* MCLK1_PD */
4331  #define WM8994_MCLK1_PD_MASK                    0x0040  /* MCLK1_PD */
4332  #define WM8994_MCLK1_PD_SHIFT                        6  /* MCLK1_PD */
4333  #define WM8994_MCLK1_PD_WIDTH                        1  /* MCLK1_PD */
4334  #define WM8994_DACDAT1_PU                       0x0020  /* DACDAT1_PU */
4335  #define WM8994_DACDAT1_PU_MASK                  0x0020  /* DACDAT1_PU */
4336  #define WM8994_DACDAT1_PU_SHIFT                      5  /* DACDAT1_PU */
4337  #define WM8994_DACDAT1_PU_WIDTH                      1  /* DACDAT1_PU */
4338  #define WM8994_DACDAT1_PD                       0x0010  /* DACDAT1_PD */
4339  #define WM8994_DACDAT1_PD_MASK                  0x0010  /* DACDAT1_PD */
4340  #define WM8994_DACDAT1_PD_SHIFT                      4  /* DACDAT1_PD */
4341  #define WM8994_DACDAT1_PD_WIDTH                      1  /* DACDAT1_PD */
4342  #define WM8994_DACLRCLK1_PU                     0x0008  /* DACLRCLK1_PU */
4343  #define WM8994_DACLRCLK1_PU_MASK                0x0008  /* DACLRCLK1_PU */
4344  #define WM8994_DACLRCLK1_PU_SHIFT                    3  /* DACLRCLK1_PU */
4345  #define WM8994_DACLRCLK1_PU_WIDTH                    1  /* DACLRCLK1_PU */
4346  #define WM8994_DACLRCLK1_PD                     0x0004  /* DACLRCLK1_PD */
4347  #define WM8994_DACLRCLK1_PD_MASK                0x0004  /* DACLRCLK1_PD */
4348  #define WM8994_DACLRCLK1_PD_SHIFT                    2  /* DACLRCLK1_PD */
4349  #define WM8994_DACLRCLK1_PD_WIDTH                    1  /* DACLRCLK1_PD */
4350  #define WM8994_BCLK1_PU                         0x0002  /* BCLK1_PU */
4351  #define WM8994_BCLK1_PU_MASK                    0x0002  /* BCLK1_PU */
4352  #define WM8994_BCLK1_PU_SHIFT                        1  /* BCLK1_PU */
4353  #define WM8994_BCLK1_PU_WIDTH                        1  /* BCLK1_PU */
4354  #define WM8994_BCLK1_PD                         0x0001  /* BCLK1_PD */
4355  #define WM8994_BCLK1_PD_MASK                    0x0001  /* BCLK1_PD */
4356  #define WM8994_BCLK1_PD_SHIFT                        0  /* BCLK1_PD */
4357  #define WM8994_BCLK1_PD_WIDTH                        1  /* BCLK1_PD */
4358  
4359  /*
4360   * R1825 (0x721) - Pull Control (2)
4361   */
4362  #define WM8994_CSNADDR_PD                       0x0100  /* CSNADDR_PD */
4363  #define WM8994_CSNADDR_PD_MASK                  0x0100  /* CSNADDR_PD */
4364  #define WM8994_CSNADDR_PD_SHIFT                      8  /* CSNADDR_PD */
4365  #define WM8994_CSNADDR_PD_WIDTH                      1  /* CSNADDR_PD */
4366  #define WM8994_LDO2ENA_PD                       0x0040  /* LDO2ENA_PD */
4367  #define WM8994_LDO2ENA_PD_MASK                  0x0040  /* LDO2ENA_PD */
4368  #define WM8994_LDO2ENA_PD_SHIFT                      6  /* LDO2ENA_PD */
4369  #define WM8994_LDO2ENA_PD_WIDTH                      1  /* LDO2ENA_PD */
4370  #define WM8994_LDO1ENA_PD                       0x0010  /* LDO1ENA_PD */
4371  #define WM8994_LDO1ENA_PD_MASK                  0x0010  /* LDO1ENA_PD */
4372  #define WM8994_LDO1ENA_PD_SHIFT                      4  /* LDO1ENA_PD */
4373  #define WM8994_LDO1ENA_PD_WIDTH                      1  /* LDO1ENA_PD */
4374  #define WM8994_CIFMODE_PD                       0x0004  /* CIFMODE_PD */
4375  #define WM8994_CIFMODE_PD_MASK                  0x0004  /* CIFMODE_PD */
4376  #define WM8994_CIFMODE_PD_SHIFT                      2  /* CIFMODE_PD */
4377  #define WM8994_CIFMODE_PD_WIDTH                      1  /* CIFMODE_PD */
4378  #define WM8994_SPKMODE_PU                       0x0002  /* SPKMODE_PU */
4379  #define WM8994_SPKMODE_PU_MASK                  0x0002  /* SPKMODE_PU */
4380  #define WM8994_SPKMODE_PU_SHIFT                      1  /* SPKMODE_PU */
4381  #define WM8994_SPKMODE_PU_WIDTH                      1  /* SPKMODE_PU */
4382  
4383  /*
4384   * R1840 (0x730) - Interrupt Status 1
4385   */
4386  #define WM8994_GP11_EINT                        0x0400  /* GP11_EINT */
4387  #define WM8994_GP11_EINT_MASK                   0x0400  /* GP11_EINT */
4388  #define WM8994_GP11_EINT_SHIFT                      10  /* GP11_EINT */
4389  #define WM8994_GP11_EINT_WIDTH                       1  /* GP11_EINT */
4390  #define WM8994_GP10_EINT                        0x0200  /* GP10_EINT */
4391  #define WM8994_GP10_EINT_MASK                   0x0200  /* GP10_EINT */
4392  #define WM8994_GP10_EINT_SHIFT                       9  /* GP10_EINT */
4393  #define WM8994_GP10_EINT_WIDTH                       1  /* GP10_EINT */
4394  #define WM8994_GP9_EINT                         0x0100  /* GP9_EINT */
4395  #define WM8994_GP9_EINT_MASK                    0x0100  /* GP9_EINT */
4396  #define WM8994_GP9_EINT_SHIFT                        8  /* GP9_EINT */
4397  #define WM8994_GP9_EINT_WIDTH                        1  /* GP9_EINT */
4398  #define WM8994_GP8_EINT                         0x0080  /* GP8_EINT */
4399  #define WM8994_GP8_EINT_MASK                    0x0080  /* GP8_EINT */
4400  #define WM8994_GP8_EINT_SHIFT                        7  /* GP8_EINT */
4401  #define WM8994_GP8_EINT_WIDTH                        1  /* GP8_EINT */
4402  #define WM8994_GP7_EINT                         0x0040  /* GP7_EINT */
4403  #define WM8994_GP7_EINT_MASK                    0x0040  /* GP7_EINT */
4404  #define WM8994_GP7_EINT_SHIFT                        6  /* GP7_EINT */
4405  #define WM8994_GP7_EINT_WIDTH                        1  /* GP7_EINT */
4406  #define WM8994_GP6_EINT                         0x0020  /* GP6_EINT */
4407  #define WM8994_GP6_EINT_MASK                    0x0020  /* GP6_EINT */
4408  #define WM8994_GP6_EINT_SHIFT                        5  /* GP6_EINT */
4409  #define WM8994_GP6_EINT_WIDTH                        1  /* GP6_EINT */
4410  #define WM8994_GP5_EINT                         0x0010  /* GP5_EINT */
4411  #define WM8994_GP5_EINT_MASK                    0x0010  /* GP5_EINT */
4412  #define WM8994_GP5_EINT_SHIFT                        4  /* GP5_EINT */
4413  #define WM8994_GP5_EINT_WIDTH                        1  /* GP5_EINT */
4414  #define WM8994_GP4_EINT                         0x0008  /* GP4_EINT */
4415  #define WM8994_GP4_EINT_MASK                    0x0008  /* GP4_EINT */
4416  #define WM8994_GP4_EINT_SHIFT                        3  /* GP4_EINT */
4417  #define WM8994_GP4_EINT_WIDTH                        1  /* GP4_EINT */
4418  #define WM8994_GP3_EINT                         0x0004  /* GP3_EINT */
4419  #define WM8994_GP3_EINT_MASK                    0x0004  /* GP3_EINT */
4420  #define WM8994_GP3_EINT_SHIFT                        2  /* GP3_EINT */
4421  #define WM8994_GP3_EINT_WIDTH                        1  /* GP3_EINT */
4422  #define WM8994_GP2_EINT                         0x0002  /* GP2_EINT */
4423  #define WM8994_GP2_EINT_MASK                    0x0002  /* GP2_EINT */
4424  #define WM8994_GP2_EINT_SHIFT                        1  /* GP2_EINT */
4425  #define WM8994_GP2_EINT_WIDTH                        1  /* GP2_EINT */
4426  #define WM8994_GP1_EINT                         0x0001  /* GP1_EINT */
4427  #define WM8994_GP1_EINT_MASK                    0x0001  /* GP1_EINT */
4428  #define WM8994_GP1_EINT_SHIFT                        0  /* GP1_EINT */
4429  #define WM8994_GP1_EINT_WIDTH                        1  /* GP1_EINT */
4430  
4431  /*
4432   * R1841 (0x731) - Interrupt Status 2
4433   */
4434  #define WM8994_TEMP_WARN_EINT                   0x8000  /* TEMP_WARN_EINT */
4435  #define WM8994_TEMP_WARN_EINT_MASK              0x8000  /* TEMP_WARN_EINT */
4436  #define WM8994_TEMP_WARN_EINT_SHIFT                 15  /* TEMP_WARN_EINT */
4437  #define WM8994_TEMP_WARN_EINT_WIDTH                  1  /* TEMP_WARN_EINT */
4438  #define WM8994_DCS_DONE_EINT                    0x4000  /* DCS_DONE_EINT */
4439  #define WM8994_DCS_DONE_EINT_MASK               0x4000  /* DCS_DONE_EINT */
4440  #define WM8994_DCS_DONE_EINT_SHIFT                  14  /* DCS_DONE_EINT */
4441  #define WM8994_DCS_DONE_EINT_WIDTH                   1  /* DCS_DONE_EINT */
4442  #define WM8994_WSEQ_DONE_EINT                   0x2000  /* WSEQ_DONE_EINT */
4443  #define WM8994_WSEQ_DONE_EINT_MASK              0x2000  /* WSEQ_DONE_EINT */
4444  #define WM8994_WSEQ_DONE_EINT_SHIFT                 13  /* WSEQ_DONE_EINT */
4445  #define WM8994_WSEQ_DONE_EINT_WIDTH                  1  /* WSEQ_DONE_EINT */
4446  #define WM8994_FIFOS_ERR_EINT                   0x1000  /* FIFOS_ERR_EINT */
4447  #define WM8994_FIFOS_ERR_EINT_MASK              0x1000  /* FIFOS_ERR_EINT */
4448  #define WM8994_FIFOS_ERR_EINT_SHIFT                 12  /* FIFOS_ERR_EINT */
4449  #define WM8994_FIFOS_ERR_EINT_WIDTH                  1  /* FIFOS_ERR_EINT */
4450  #define WM8994_AIF2DRC_SIG_DET_EINT             0x0800  /* AIF2DRC_SIG_DET_EINT */
4451  #define WM8994_AIF2DRC_SIG_DET_EINT_MASK        0x0800  /* AIF2DRC_SIG_DET_EINT */
4452  #define WM8994_AIF2DRC_SIG_DET_EINT_SHIFT           11  /* AIF2DRC_SIG_DET_EINT */
4453  #define WM8994_AIF2DRC_SIG_DET_EINT_WIDTH            1  /* AIF2DRC_SIG_DET_EINT */
4454  #define WM8994_AIF1DRC2_SIG_DET_EINT            0x0400  /* AIF1DRC2_SIG_DET_EINT */
4455  #define WM8994_AIF1DRC2_SIG_DET_EINT_MASK       0x0400  /* AIF1DRC2_SIG_DET_EINT */
4456  #define WM8994_AIF1DRC2_SIG_DET_EINT_SHIFT          10  /* AIF1DRC2_SIG_DET_EINT */
4457  #define WM8994_AIF1DRC2_SIG_DET_EINT_WIDTH           1  /* AIF1DRC2_SIG_DET_EINT */
4458  #define WM8994_AIF1DRC1_SIG_DET_EINT            0x0200  /* AIF1DRC1_SIG_DET_EINT */
4459  #define WM8994_AIF1DRC1_SIG_DET_EINT_MASK       0x0200  /* AIF1DRC1_SIG_DET_EINT */
4460  #define WM8994_AIF1DRC1_SIG_DET_EINT_SHIFT           9  /* AIF1DRC1_SIG_DET_EINT */
4461  #define WM8994_AIF1DRC1_SIG_DET_EINT_WIDTH           1  /* AIF1DRC1_SIG_DET_EINT */
4462  #define WM8994_SRC2_LOCK_EINT                   0x0100  /* SRC2_LOCK_EINT */
4463  #define WM8994_SRC2_LOCK_EINT_MASK              0x0100  /* SRC2_LOCK_EINT */
4464  #define WM8994_SRC2_LOCK_EINT_SHIFT                  8  /* SRC2_LOCK_EINT */
4465  #define WM8994_SRC2_LOCK_EINT_WIDTH                  1  /* SRC2_LOCK_EINT */
4466  #define WM8994_SRC1_LOCK_EINT                   0x0080  /* SRC1_LOCK_EINT */
4467  #define WM8994_SRC1_LOCK_EINT_MASK              0x0080  /* SRC1_LOCK_EINT */
4468  #define WM8994_SRC1_LOCK_EINT_SHIFT                  7  /* SRC1_LOCK_EINT */
4469  #define WM8994_SRC1_LOCK_EINT_WIDTH                  1  /* SRC1_LOCK_EINT */
4470  #define WM8994_FLL2_LOCK_EINT                   0x0040  /* FLL2_LOCK_EINT */
4471  #define WM8994_FLL2_LOCK_EINT_MASK              0x0040  /* FLL2_LOCK_EINT */
4472  #define WM8994_FLL2_LOCK_EINT_SHIFT                  6  /* FLL2_LOCK_EINT */
4473  #define WM8994_FLL2_LOCK_EINT_WIDTH                  1  /* FLL2_LOCK_EINT */
4474  #define WM8994_FLL1_LOCK_EINT                   0x0020  /* FLL1_LOCK_EINT */
4475  #define WM8994_FLL1_LOCK_EINT_MASK              0x0020  /* FLL1_LOCK_EINT */
4476  #define WM8994_FLL1_LOCK_EINT_SHIFT                  5  /* FLL1_LOCK_EINT */
4477  #define WM8994_FLL1_LOCK_EINT_WIDTH                  1  /* FLL1_LOCK_EINT */
4478  #define WM8994_MIC2_SHRT_EINT                   0x0010  /* MIC2_SHRT_EINT */
4479  #define WM8994_MIC2_SHRT_EINT_MASK              0x0010  /* MIC2_SHRT_EINT */
4480  #define WM8994_MIC2_SHRT_EINT_SHIFT                  4  /* MIC2_SHRT_EINT */
4481  #define WM8994_MIC2_SHRT_EINT_WIDTH                  1  /* MIC2_SHRT_EINT */
4482  #define WM8994_MIC2_DET_EINT                    0x0008  /* MIC2_DET_EINT */
4483  #define WM8994_MIC2_DET_EINT_MASK               0x0008  /* MIC2_DET_EINT */
4484  #define WM8994_MIC2_DET_EINT_SHIFT                   3  /* MIC2_DET_EINT */
4485  #define WM8994_MIC2_DET_EINT_WIDTH                   1  /* MIC2_DET_EINT */
4486  #define WM8994_MIC1_SHRT_EINT                   0x0004  /* MIC1_SHRT_EINT */
4487  #define WM8994_MIC1_SHRT_EINT_MASK              0x0004  /* MIC1_SHRT_EINT */
4488  #define WM8994_MIC1_SHRT_EINT_SHIFT                  2  /* MIC1_SHRT_EINT */
4489  #define WM8994_MIC1_SHRT_EINT_WIDTH                  1  /* MIC1_SHRT_EINT */
4490  #define WM8994_MIC1_DET_EINT                    0x0002  /* MIC1_DET_EINT */
4491  #define WM8994_MIC1_DET_EINT_MASK               0x0002  /* MIC1_DET_EINT */
4492  #define WM8994_MIC1_DET_EINT_SHIFT                   1  /* MIC1_DET_EINT */
4493  #define WM8994_MIC1_DET_EINT_WIDTH                   1  /* MIC1_DET_EINT */
4494  #define WM8994_TEMP_SHUT_EINT                   0x0001  /* TEMP_SHUT_EINT */
4495  #define WM8994_TEMP_SHUT_EINT_MASK              0x0001  /* TEMP_SHUT_EINT */
4496  #define WM8994_TEMP_SHUT_EINT_SHIFT                  0  /* TEMP_SHUT_EINT */
4497  #define WM8994_TEMP_SHUT_EINT_WIDTH                  1  /* TEMP_SHUT_EINT */
4498  
4499  /*
4500   * R1842 (0x732) - Interrupt Raw Status 2
4501   */
4502  #define WM8994_TEMP_WARN_STS                    0x8000  /* TEMP_WARN_STS */
4503  #define WM8994_TEMP_WARN_STS_MASK               0x8000  /* TEMP_WARN_STS */
4504  #define WM8994_TEMP_WARN_STS_SHIFT                  15  /* TEMP_WARN_STS */
4505  #define WM8994_TEMP_WARN_STS_WIDTH                   1  /* TEMP_WARN_STS */
4506  #define WM8994_DCS_DONE_STS                     0x4000  /* DCS_DONE_STS */
4507  #define WM8994_DCS_DONE_STS_MASK                0x4000  /* DCS_DONE_STS */
4508  #define WM8994_DCS_DONE_STS_SHIFT                   14  /* DCS_DONE_STS */
4509  #define WM8994_DCS_DONE_STS_WIDTH                    1  /* DCS_DONE_STS */
4510  #define WM8994_WSEQ_DONE_STS                    0x2000  /* WSEQ_DONE_STS */
4511  #define WM8994_WSEQ_DONE_STS_MASK               0x2000  /* WSEQ_DONE_STS */
4512  #define WM8994_WSEQ_DONE_STS_SHIFT                  13  /* WSEQ_DONE_STS */
4513  #define WM8994_WSEQ_DONE_STS_WIDTH                   1  /* WSEQ_DONE_STS */
4514  #define WM8994_FIFOS_ERR_STS                    0x1000  /* FIFOS_ERR_STS */
4515  #define WM8994_FIFOS_ERR_STS_MASK               0x1000  /* FIFOS_ERR_STS */
4516  #define WM8994_FIFOS_ERR_STS_SHIFT                  12  /* FIFOS_ERR_STS */
4517  #define WM8994_FIFOS_ERR_STS_WIDTH                   1  /* FIFOS_ERR_STS */
4518  #define WM8994_AIF2DRC_SIG_DET_STS              0x0800  /* AIF2DRC_SIG_DET_STS */
4519  #define WM8994_AIF2DRC_SIG_DET_STS_MASK         0x0800  /* AIF2DRC_SIG_DET_STS */
4520  #define WM8994_AIF2DRC_SIG_DET_STS_SHIFT            11  /* AIF2DRC_SIG_DET_STS */
4521  #define WM8994_AIF2DRC_SIG_DET_STS_WIDTH             1  /* AIF2DRC_SIG_DET_STS */
4522  #define WM8994_AIF1DRC2_SIG_DET_STS             0x0400  /* AIF1DRC2_SIG_DET_STS */
4523  #define WM8994_AIF1DRC2_SIG_DET_STS_MASK        0x0400  /* AIF1DRC2_SIG_DET_STS */
4524  #define WM8994_AIF1DRC2_SIG_DET_STS_SHIFT           10  /* AIF1DRC2_SIG_DET_STS */
4525  #define WM8994_AIF1DRC2_SIG_DET_STS_WIDTH            1  /* AIF1DRC2_SIG_DET_STS */
4526  #define WM8994_AIF1DRC1_SIG_DET_STS             0x0200  /* AIF1DRC1_SIG_DET_STS */
4527  #define WM8994_AIF1DRC1_SIG_DET_STS_MASK        0x0200  /* AIF1DRC1_SIG_DET_STS */
4528  #define WM8994_AIF1DRC1_SIG_DET_STS_SHIFT            9  /* AIF1DRC1_SIG_DET_STS */
4529  #define WM8994_AIF1DRC1_SIG_DET_STS_WIDTH            1  /* AIF1DRC1_SIG_DET_STS */
4530  #define WM8994_SRC2_LOCK_STS                    0x0100  /* SRC2_LOCK_STS */
4531  #define WM8994_SRC2_LOCK_STS_MASK               0x0100  /* SRC2_LOCK_STS */
4532  #define WM8994_SRC2_LOCK_STS_SHIFT                   8  /* SRC2_LOCK_STS */
4533  #define WM8994_SRC2_LOCK_STS_WIDTH                   1  /* SRC2_LOCK_STS */
4534  #define WM8994_SRC1_LOCK_STS                    0x0080  /* SRC1_LOCK_STS */
4535  #define WM8994_SRC1_LOCK_STS_MASK               0x0080  /* SRC1_LOCK_STS */
4536  #define WM8994_SRC1_LOCK_STS_SHIFT                   7  /* SRC1_LOCK_STS */
4537  #define WM8994_SRC1_LOCK_STS_WIDTH                   1  /* SRC1_LOCK_STS */
4538  #define WM8994_FLL2_LOCK_STS                    0x0040  /* FLL2_LOCK_STS */
4539  #define WM8994_FLL2_LOCK_STS_MASK               0x0040  /* FLL2_LOCK_STS */
4540  #define WM8994_FLL2_LOCK_STS_SHIFT                   6  /* FLL2_LOCK_STS */
4541  #define WM8994_FLL2_LOCK_STS_WIDTH                   1  /* FLL2_LOCK_STS */
4542  #define WM8994_FLL1_LOCK_STS                    0x0020  /* FLL1_LOCK_STS */
4543  #define WM8994_FLL1_LOCK_STS_MASK               0x0020  /* FLL1_LOCK_STS */
4544  #define WM8994_FLL1_LOCK_STS_SHIFT                   5  /* FLL1_LOCK_STS */
4545  #define WM8994_FLL1_LOCK_STS_WIDTH                   1  /* FLL1_LOCK_STS */
4546  #define WM8994_MIC2_SHRT_STS                    0x0010  /* MIC2_SHRT_STS */
4547  #define WM8994_MIC2_SHRT_STS_MASK               0x0010  /* MIC2_SHRT_STS */
4548  #define WM8994_MIC2_SHRT_STS_SHIFT                   4  /* MIC2_SHRT_STS */
4549  #define WM8994_MIC2_SHRT_STS_WIDTH                   1  /* MIC2_SHRT_STS */
4550  #define WM8994_MIC2_DET_STS                     0x0008  /* MIC2_DET_STS */
4551  #define WM8994_MIC2_DET_STS_MASK                0x0008  /* MIC2_DET_STS */
4552  #define WM8994_MIC2_DET_STS_SHIFT                    3  /* MIC2_DET_STS */
4553  #define WM8994_MIC2_DET_STS_WIDTH                    1  /* MIC2_DET_STS */
4554  #define WM8994_MIC1_SHRT_STS                    0x0004  /* MIC1_SHRT_STS */
4555  #define WM8994_MIC1_SHRT_STS_MASK               0x0004  /* MIC1_SHRT_STS */
4556  #define WM8994_MIC1_SHRT_STS_SHIFT                   2  /* MIC1_SHRT_STS */
4557  #define WM8994_MIC1_SHRT_STS_WIDTH                   1  /* MIC1_SHRT_STS */
4558  #define WM8994_MIC1_DET_STS                     0x0002  /* MIC1_DET_STS */
4559  #define WM8994_MIC1_DET_STS_MASK                0x0002  /* MIC1_DET_STS */
4560  #define WM8994_MIC1_DET_STS_SHIFT                    1  /* MIC1_DET_STS */
4561  #define WM8994_MIC1_DET_STS_WIDTH                    1  /* MIC1_DET_STS */
4562  #define WM8994_TEMP_SHUT_STS                    0x0001  /* TEMP_SHUT_STS */
4563  #define WM8994_TEMP_SHUT_STS_MASK               0x0001  /* TEMP_SHUT_STS */
4564  #define WM8994_TEMP_SHUT_STS_SHIFT                   0  /* TEMP_SHUT_STS */
4565  #define WM8994_TEMP_SHUT_STS_WIDTH                   1  /* TEMP_SHUT_STS */
4566  
4567  /*
4568   * R1848 (0x738) - Interrupt Status 1 Mask
4569   */
4570  #define WM8994_IM_GP11_EINT                     0x0400  /* IM_GP11_EINT */
4571  #define WM8994_IM_GP11_EINT_MASK                0x0400  /* IM_GP11_EINT */
4572  #define WM8994_IM_GP11_EINT_SHIFT                   10  /* IM_GP11_EINT */
4573  #define WM8994_IM_GP11_EINT_WIDTH                    1  /* IM_GP11_EINT */
4574  #define WM8994_IM_GP10_EINT                     0x0200  /* IM_GP10_EINT */
4575  #define WM8994_IM_GP10_EINT_MASK                0x0200  /* IM_GP10_EINT */
4576  #define WM8994_IM_GP10_EINT_SHIFT                    9  /* IM_GP10_EINT */
4577  #define WM8994_IM_GP10_EINT_WIDTH                    1  /* IM_GP10_EINT */
4578  #define WM8994_IM_GP9_EINT                      0x0100  /* IM_GP9_EINT */
4579  #define WM8994_IM_GP9_EINT_MASK                 0x0100  /* IM_GP9_EINT */
4580  #define WM8994_IM_GP9_EINT_SHIFT                     8  /* IM_GP9_EINT */
4581  #define WM8994_IM_GP9_EINT_WIDTH                     1  /* IM_GP9_EINT */
4582  #define WM8994_IM_GP8_EINT                      0x0080  /* IM_GP8_EINT */
4583  #define WM8994_IM_GP8_EINT_MASK                 0x0080  /* IM_GP8_EINT */
4584  #define WM8994_IM_GP8_EINT_SHIFT                     7  /* IM_GP8_EINT */
4585  #define WM8994_IM_GP8_EINT_WIDTH                     1  /* IM_GP8_EINT */
4586  #define WM8994_IM_GP7_EINT                      0x0040  /* IM_GP7_EINT */
4587  #define WM8994_IM_GP7_EINT_MASK                 0x0040  /* IM_GP7_EINT */
4588  #define WM8994_IM_GP7_EINT_SHIFT                     6  /* IM_GP7_EINT */
4589  #define WM8994_IM_GP7_EINT_WIDTH                     1  /* IM_GP7_EINT */
4590  #define WM8994_IM_GP6_EINT                      0x0020  /* IM_GP6_EINT */
4591  #define WM8994_IM_GP6_EINT_MASK                 0x0020  /* IM_GP6_EINT */
4592  #define WM8994_IM_GP6_EINT_SHIFT                     5  /* IM_GP6_EINT */
4593  #define WM8994_IM_GP6_EINT_WIDTH                     1  /* IM_GP6_EINT */
4594  #define WM8994_IM_GP5_EINT                      0x0010  /* IM_GP5_EINT */
4595  #define WM8994_IM_GP5_EINT_MASK                 0x0010  /* IM_GP5_EINT */
4596  #define WM8994_IM_GP5_EINT_SHIFT                     4  /* IM_GP5_EINT */
4597  #define WM8994_IM_GP5_EINT_WIDTH                     1  /* IM_GP5_EINT */
4598  #define WM8994_IM_GP4_EINT                      0x0008  /* IM_GP4_EINT */
4599  #define WM8994_IM_GP4_EINT_MASK                 0x0008  /* IM_GP4_EINT */
4600  #define WM8994_IM_GP4_EINT_SHIFT                     3  /* IM_GP4_EINT */
4601  #define WM8994_IM_GP4_EINT_WIDTH                     1  /* IM_GP4_EINT */
4602  #define WM8994_IM_GP3_EINT                      0x0004  /* IM_GP3_EINT */
4603  #define WM8994_IM_GP3_EINT_MASK                 0x0004  /* IM_GP3_EINT */
4604  #define WM8994_IM_GP3_EINT_SHIFT                     2  /* IM_GP3_EINT */
4605  #define WM8994_IM_GP3_EINT_WIDTH                     1  /* IM_GP3_EINT */
4606  #define WM8994_IM_GP2_EINT                      0x0002  /* IM_GP2_EINT */
4607  #define WM8994_IM_GP2_EINT_MASK                 0x0002  /* IM_GP2_EINT */
4608  #define WM8994_IM_GP2_EINT_SHIFT                     1  /* IM_GP2_EINT */
4609  #define WM8994_IM_GP2_EINT_WIDTH                     1  /* IM_GP2_EINT */
4610  #define WM8994_IM_GP1_EINT                      0x0001  /* IM_GP1_EINT */
4611  #define WM8994_IM_GP1_EINT_MASK                 0x0001  /* IM_GP1_EINT */
4612  #define WM8994_IM_GP1_EINT_SHIFT                     0  /* IM_GP1_EINT */
4613  #define WM8994_IM_GP1_EINT_WIDTH                     1  /* IM_GP1_EINT */
4614  
4615  /*
4616   * R1849 (0x739) - Interrupt Status 2 Mask
4617   */
4618  #define WM8994_IM_TEMP_WARN_EINT                0x8000  /* IM_TEMP_WARN_EINT */
4619  #define WM8994_IM_TEMP_WARN_EINT_MASK           0x8000  /* IM_TEMP_WARN_EINT */
4620  #define WM8994_IM_TEMP_WARN_EINT_SHIFT              15  /* IM_TEMP_WARN_EINT */
4621  #define WM8994_IM_TEMP_WARN_EINT_WIDTH               1  /* IM_TEMP_WARN_EINT */
4622  #define WM8994_IM_DCS_DONE_EINT                 0x4000  /* IM_DCS_DONE_EINT */
4623  #define WM8994_IM_DCS_DONE_EINT_MASK            0x4000  /* IM_DCS_DONE_EINT */
4624  #define WM8994_IM_DCS_DONE_EINT_SHIFT               14  /* IM_DCS_DONE_EINT */
4625  #define WM8994_IM_DCS_DONE_EINT_WIDTH                1  /* IM_DCS_DONE_EINT */
4626  #define WM8994_IM_WSEQ_DONE_EINT                0x2000  /* IM_WSEQ_DONE_EINT */
4627  #define WM8994_IM_WSEQ_DONE_EINT_MASK           0x2000  /* IM_WSEQ_DONE_EINT */
4628  #define WM8994_IM_WSEQ_DONE_EINT_SHIFT              13  /* IM_WSEQ_DONE_EINT */
4629  #define WM8994_IM_WSEQ_DONE_EINT_WIDTH               1  /* IM_WSEQ_DONE_EINT */
4630  #define WM8994_IM_FIFOS_ERR_EINT                0x1000  /* IM_FIFOS_ERR_EINT */
4631  #define WM8994_IM_FIFOS_ERR_EINT_MASK           0x1000  /* IM_FIFOS_ERR_EINT */
4632  #define WM8994_IM_FIFOS_ERR_EINT_SHIFT              12  /* IM_FIFOS_ERR_EINT */
4633  #define WM8994_IM_FIFOS_ERR_EINT_WIDTH               1  /* IM_FIFOS_ERR_EINT */
4634  #define WM8994_IM_AIF2DRC_SIG_DET_EINT          0x0800  /* IM_AIF2DRC_SIG_DET_EINT */
4635  #define WM8994_IM_AIF2DRC_SIG_DET_EINT_MASK     0x0800  /* IM_AIF2DRC_SIG_DET_EINT */
4636  #define WM8994_IM_AIF2DRC_SIG_DET_EINT_SHIFT        11  /* IM_AIF2DRC_SIG_DET_EINT */
4637  #define WM8994_IM_AIF2DRC_SIG_DET_EINT_WIDTH         1  /* IM_AIF2DRC_SIG_DET_EINT */
4638  #define WM8994_IM_AIF1DRC2_SIG_DET_EINT         0x0400  /* IM_AIF1DRC2_SIG_DET_EINT */
4639  #define WM8994_IM_AIF1DRC2_SIG_DET_EINT_MASK    0x0400  /* IM_AIF1DRC2_SIG_DET_EINT */
4640  #define WM8994_IM_AIF1DRC2_SIG_DET_EINT_SHIFT       10  /* IM_AIF1DRC2_SIG_DET_EINT */
4641  #define WM8994_IM_AIF1DRC2_SIG_DET_EINT_WIDTH        1  /* IM_AIF1DRC2_SIG_DET_EINT */
4642  #define WM8994_IM_AIF1DRC1_SIG_DET_EINT         0x0200  /* IM_AIF1DRC1_SIG_DET_EINT */
4643  #define WM8994_IM_AIF1DRC1_SIG_DET_EINT_MASK    0x0200  /* IM_AIF1DRC1_SIG_DET_EINT */
4644  #define WM8994_IM_AIF1DRC1_SIG_DET_EINT_SHIFT        9  /* IM_AIF1DRC1_SIG_DET_EINT */
4645  #define WM8994_IM_AIF1DRC1_SIG_DET_EINT_WIDTH        1  /* IM_AIF1DRC1_SIG_DET_EINT */
4646  #define WM8994_IM_SRC2_LOCK_EINT                0x0100  /* IM_SRC2_LOCK_EINT */
4647  #define WM8994_IM_SRC2_LOCK_EINT_MASK           0x0100  /* IM_SRC2_LOCK_EINT */
4648  #define WM8994_IM_SRC2_LOCK_EINT_SHIFT               8  /* IM_SRC2_LOCK_EINT */
4649  #define WM8994_IM_SRC2_LOCK_EINT_WIDTH               1  /* IM_SRC2_LOCK_EINT */
4650  #define WM8994_IM_SRC1_LOCK_EINT                0x0080  /* IM_SRC1_LOCK_EINT */
4651  #define WM8994_IM_SRC1_LOCK_EINT_MASK           0x0080  /* IM_SRC1_LOCK_EINT */
4652  #define WM8994_IM_SRC1_LOCK_EINT_SHIFT               7  /* IM_SRC1_LOCK_EINT */
4653  #define WM8994_IM_SRC1_LOCK_EINT_WIDTH               1  /* IM_SRC1_LOCK_EINT */
4654  #define WM8994_IM_FLL2_LOCK_EINT                0x0040  /* IM_FLL2_LOCK_EINT */
4655  #define WM8994_IM_FLL2_LOCK_EINT_MASK           0x0040  /* IM_FLL2_LOCK_EINT */
4656  #define WM8994_IM_FLL2_LOCK_EINT_SHIFT               6  /* IM_FLL2_LOCK_EINT */
4657  #define WM8994_IM_FLL2_LOCK_EINT_WIDTH               1  /* IM_FLL2_LOCK_EINT */
4658  #define WM8994_IM_FLL1_LOCK_EINT                0x0020  /* IM_FLL1_LOCK_EINT */
4659  #define WM8994_IM_FLL1_LOCK_EINT_MASK           0x0020  /* IM_FLL1_LOCK_EINT */
4660  #define WM8994_IM_FLL1_LOCK_EINT_SHIFT               5  /* IM_FLL1_LOCK_EINT */
4661  #define WM8994_IM_FLL1_LOCK_EINT_WIDTH               1  /* IM_FLL1_LOCK_EINT */
4662  #define WM8994_IM_MIC2_SHRT_EINT                0x0010  /* IM_MIC2_SHRT_EINT */
4663  #define WM8994_IM_MIC2_SHRT_EINT_MASK           0x0010  /* IM_MIC2_SHRT_EINT */
4664  #define WM8994_IM_MIC2_SHRT_EINT_SHIFT               4  /* IM_MIC2_SHRT_EINT */
4665  #define WM8994_IM_MIC2_SHRT_EINT_WIDTH               1  /* IM_MIC2_SHRT_EINT */
4666  #define WM8994_IM_MIC2_DET_EINT                 0x0008  /* IM_MIC2_DET_EINT */
4667  #define WM8994_IM_MIC2_DET_EINT_MASK            0x0008  /* IM_MIC2_DET_EINT */
4668  #define WM8994_IM_MIC2_DET_EINT_SHIFT                3  /* IM_MIC2_DET_EINT */
4669  #define WM8994_IM_MIC2_DET_EINT_WIDTH                1  /* IM_MIC2_DET_EINT */
4670  #define WM8994_IM_MIC1_SHRT_EINT                0x0004  /* IM_MIC1_SHRT_EINT */
4671  #define WM8994_IM_MIC1_SHRT_EINT_MASK           0x0004  /* IM_MIC1_SHRT_EINT */
4672  #define WM8994_IM_MIC1_SHRT_EINT_SHIFT               2  /* IM_MIC1_SHRT_EINT */
4673  #define WM8994_IM_MIC1_SHRT_EINT_WIDTH               1  /* IM_MIC1_SHRT_EINT */
4674  #define WM8994_IM_MIC1_DET_EINT                 0x0002  /* IM_MIC1_DET_EINT */
4675  #define WM8994_IM_MIC1_DET_EINT_MASK            0x0002  /* IM_MIC1_DET_EINT */
4676  #define WM8994_IM_MIC1_DET_EINT_SHIFT                1  /* IM_MIC1_DET_EINT */
4677  #define WM8994_IM_MIC1_DET_EINT_WIDTH                1  /* IM_MIC1_DET_EINT */
4678  #define WM8994_IM_TEMP_SHUT_EINT                0x0001  /* IM_TEMP_SHUT_EINT */
4679  #define WM8994_IM_TEMP_SHUT_EINT_MASK           0x0001  /* IM_TEMP_SHUT_EINT */
4680  #define WM8994_IM_TEMP_SHUT_EINT_SHIFT               0  /* IM_TEMP_SHUT_EINT */
4681  #define WM8994_IM_TEMP_SHUT_EINT_WIDTH               1  /* IM_TEMP_SHUT_EINT */
4682  
4683  /*
4684   * R1856 (0x740) - Interrupt Control
4685   */
4686  #define WM8994_IM_IRQ                           0x0001  /* IM_IRQ */
4687  #define WM8994_IM_IRQ_MASK                      0x0001  /* IM_IRQ */
4688  #define WM8994_IM_IRQ_SHIFT                          0  /* IM_IRQ */
4689  #define WM8994_IM_IRQ_WIDTH                          1  /* IM_IRQ */
4690  
4691  /*
4692   * R1864 (0x748) - IRQ Debounce
4693   */
4694  #define WM8994_TEMP_WARN_DB                     0x0020  /* TEMP_WARN_DB */
4695  #define WM8994_TEMP_WARN_DB_MASK                0x0020  /* TEMP_WARN_DB */
4696  #define WM8994_TEMP_WARN_DB_SHIFT                    5  /* TEMP_WARN_DB */
4697  #define WM8994_TEMP_WARN_DB_WIDTH                    1  /* TEMP_WARN_DB */
4698  #define WM8994_MIC2_SHRT_DB                     0x0010  /* MIC2_SHRT_DB */
4699  #define WM8994_MIC2_SHRT_DB_MASK                0x0010  /* MIC2_SHRT_DB */
4700  #define WM8994_MIC2_SHRT_DB_SHIFT                    4  /* MIC2_SHRT_DB */
4701  #define WM8994_MIC2_SHRT_DB_WIDTH                    1  /* MIC2_SHRT_DB */
4702  #define WM8994_MIC2_DET_DB                      0x0008  /* MIC2_DET_DB */
4703  #define WM8994_MIC2_DET_DB_MASK                 0x0008  /* MIC2_DET_DB */
4704  #define WM8994_MIC2_DET_DB_SHIFT                     3  /* MIC2_DET_DB */
4705  #define WM8994_MIC2_DET_DB_WIDTH                     1  /* MIC2_DET_DB */
4706  #define WM8994_MIC1_SHRT_DB                     0x0004  /* MIC1_SHRT_DB */
4707  #define WM8994_MIC1_SHRT_DB_MASK                0x0004  /* MIC1_SHRT_DB */
4708  #define WM8994_MIC1_SHRT_DB_SHIFT                    2  /* MIC1_SHRT_DB */
4709  #define WM8994_MIC1_SHRT_DB_WIDTH                    1  /* MIC1_SHRT_DB */
4710  #define WM8994_MIC1_DET_DB                      0x0002  /* MIC1_DET_DB */
4711  #define WM8994_MIC1_DET_DB_MASK                 0x0002  /* MIC1_DET_DB */
4712  #define WM8994_MIC1_DET_DB_SHIFT                     1  /* MIC1_DET_DB */
4713  #define WM8994_MIC1_DET_DB_WIDTH                     1  /* MIC1_DET_DB */
4714  #define WM8994_TEMP_SHUT_DB                     0x0001  /* TEMP_SHUT_DB */
4715  #define WM8994_TEMP_SHUT_DB_MASK                0x0001  /* TEMP_SHUT_DB */
4716  #define WM8994_TEMP_SHUT_DB_SHIFT                    0  /* TEMP_SHUT_DB */
4717  #define WM8994_TEMP_SHUT_DB_WIDTH                    1  /* TEMP_SHUT_DB */
4718  
4719  /*
4720   * R2304 (0x900) - DSP2_Program
4721   */
4722  #define WM8958_DSP2_ENA                         0x0001  /* DSP2_ENA */
4723  #define WM8958_DSP2_ENA_MASK                    0x0001  /* DSP2_ENA */
4724  #define WM8958_DSP2_ENA_SHIFT                        0  /* DSP2_ENA */
4725  #define WM8958_DSP2_ENA_WIDTH                        1  /* DSP2_ENA */
4726  
4727  /*
4728   * R2305 (0x901) - DSP2_Config
4729   */
4730  #define WM8958_MBC_SEL_MASK                     0x0030  /* MBC_SEL - [5:4] */
4731  #define WM8958_MBC_SEL_SHIFT                         4  /* MBC_SEL - [5:4] */
4732  #define WM8958_MBC_SEL_WIDTH                         2  /* MBC_SEL - [5:4] */
4733  #define WM8958_MBC_ENA                          0x0001  /* MBC_ENA */
4734  #define WM8958_MBC_ENA_MASK                     0x0001  /* MBC_ENA */
4735  #define WM8958_MBC_ENA_SHIFT                         0  /* MBC_ENA */
4736  #define WM8958_MBC_ENA_WIDTH                         1  /* MBC_ENA */
4737  
4738  /*
4739   * R2560 (0xA00) - DSP2_MagicNum
4740   */
4741  #define WM8958_DSP2_MAGIC_NUM_MASK              0xFFFF  /* DSP2_MAGIC_NUM - [15:0] */
4742  #define WM8958_DSP2_MAGIC_NUM_SHIFT                  0  /* DSP2_MAGIC_NUM - [15:0] */
4743  #define WM8958_DSP2_MAGIC_NUM_WIDTH                 16  /* DSP2_MAGIC_NUM - [15:0] */
4744  
4745  /*
4746   * R2561 (0xA01) - DSP2_ReleaseYear
4747   */
4748  #define WM8958_DSP2_RELEASE_YEAR_MASK           0xFFFF  /* DSP2_RELEASE_YEAR - [15:0] */
4749  #define WM8958_DSP2_RELEASE_YEAR_SHIFT               0  /* DSP2_RELEASE_YEAR - [15:0] */
4750  #define WM8958_DSP2_RELEASE_YEAR_WIDTH              16  /* DSP2_RELEASE_YEAR - [15:0] */
4751  
4752  /*
4753   * R2562 (0xA02) - DSP2_ReleaseMonthDay
4754   */
4755  #define WM8958_DSP2_RELEASE_MONTH_MASK          0xFF00  /* DSP2_RELEASE_MONTH - [15:8] */
4756  #define WM8958_DSP2_RELEASE_MONTH_SHIFT              8  /* DSP2_RELEASE_MONTH - [15:8] */
4757  #define WM8958_DSP2_RELEASE_MONTH_WIDTH              8  /* DSP2_RELEASE_MONTH - [15:8] */
4758  #define WM8958_DSP2_RELEASE_DAY_MASK            0x00FF  /* DSP2_RELEASE_DAY - [7:0] */
4759  #define WM8958_DSP2_RELEASE_DAY_SHIFT                0  /* DSP2_RELEASE_DAY - [7:0] */
4760  #define WM8958_DSP2_RELEASE_DAY_WIDTH                8  /* DSP2_RELEASE_DAY - [7:0] */
4761  
4762  /*
4763   * R2563 (0xA03) - DSP2_ReleaseTime
4764   */
4765  #define WM8958_DSP2_RELEASE_HOURS_MASK          0xFF00  /* DSP2_RELEASE_HOURS - [15:8] */
4766  #define WM8958_DSP2_RELEASE_HOURS_SHIFT              8  /* DSP2_RELEASE_HOURS - [15:8] */
4767  #define WM8958_DSP2_RELEASE_HOURS_WIDTH              8  /* DSP2_RELEASE_HOURS - [15:8] */
4768  #define WM8958_DSP2_RELEASE_MINS_MASK           0x00FF  /* DSP2_RELEASE_MINS - [7:0] */
4769  #define WM8958_DSP2_RELEASE_MINS_SHIFT               0  /* DSP2_RELEASE_MINS - [7:0] */
4770  #define WM8958_DSP2_RELEASE_MINS_WIDTH               8  /* DSP2_RELEASE_MINS - [7:0] */
4771  
4772  /*
4773   * R2564 (0xA04) - DSP2_VerMajMin
4774   */
4775  #define WM8958_DSP2_MAJOR_VER_MASK              0xFF00  /* DSP2_MAJOR_VER - [15:8] */
4776  #define WM8958_DSP2_MAJOR_VER_SHIFT                  8  /* DSP2_MAJOR_VER - [15:8] */
4777  #define WM8958_DSP2_MAJOR_VER_WIDTH                  8  /* DSP2_MAJOR_VER - [15:8] */
4778  #define WM8958_DSP2_MINOR_VER_MASK              0x00FF  /* DSP2_MINOR_VER - [7:0] */
4779  #define WM8958_DSP2_MINOR_VER_SHIFT                  0  /* DSP2_MINOR_VER - [7:0] */
4780  #define WM8958_DSP2_MINOR_VER_WIDTH                  8  /* DSP2_MINOR_VER - [7:0] */
4781  
4782  /*
4783   * R2565 (0xA05) - DSP2_VerBuild
4784   */
4785  #define WM8958_DSP2_BUILD_VER_MASK              0xFFFF  /* DSP2_BUILD_VER - [15:0] */
4786  #define WM8958_DSP2_BUILD_VER_SHIFT                  0  /* DSP2_BUILD_VER - [15:0] */
4787  #define WM8958_DSP2_BUILD_VER_WIDTH                 16  /* DSP2_BUILD_VER - [15:0] */
4788  
4789  /*
4790   * R2573 (0xA0D) - DSP2_ExecControl
4791   */
4792  #define WM8958_DSP2_STOPC                       0x0020  /* DSP2_STOPC */
4793  #define WM8958_DSP2_STOPC_MASK                  0x0020  /* DSP2_STOPC */
4794  #define WM8958_DSP2_STOPC_SHIFT                      5  /* DSP2_STOPC */
4795  #define WM8958_DSP2_STOPC_WIDTH                      1  /* DSP2_STOPC */
4796  #define WM8958_DSP2_STOPS                       0x0010  /* DSP2_STOPS */
4797  #define WM8958_DSP2_STOPS_MASK                  0x0010  /* DSP2_STOPS */
4798  #define WM8958_DSP2_STOPS_SHIFT                      4  /* DSP2_STOPS */
4799  #define WM8958_DSP2_STOPS_WIDTH                      1  /* DSP2_STOPS */
4800  #define WM8958_DSP2_STOPI                       0x0008  /* DSP2_STOPI */
4801  #define WM8958_DSP2_STOPI_MASK                  0x0008  /* DSP2_STOPI */
4802  #define WM8958_DSP2_STOPI_SHIFT                      3  /* DSP2_STOPI */
4803  #define WM8958_DSP2_STOPI_WIDTH                      1  /* DSP2_STOPI */
4804  #define WM8958_DSP2_STOP                        0x0004  /* DSP2_STOP */
4805  #define WM8958_DSP2_STOP_MASK                   0x0004  /* DSP2_STOP */
4806  #define WM8958_DSP2_STOP_SHIFT                       2  /* DSP2_STOP */
4807  #define WM8958_DSP2_STOP_WIDTH                       1  /* DSP2_STOP */
4808  #define WM8958_DSP2_RUNR                        0x0002  /* DSP2_RUNR */
4809  #define WM8958_DSP2_RUNR_MASK                   0x0002  /* DSP2_RUNR */
4810  #define WM8958_DSP2_RUNR_SHIFT                       1  /* DSP2_RUNR */
4811  #define WM8958_DSP2_RUNR_WIDTH                       1  /* DSP2_RUNR */
4812  #define WM8958_DSP2_RUN                         0x0001  /* DSP2_RUN */
4813  #define WM8958_DSP2_RUN_MASK                    0x0001  /* DSP2_RUN */
4814  #define WM8958_DSP2_RUN_SHIFT                        0  /* DSP2_RUN */
4815  #define WM8958_DSP2_RUN_WIDTH                        1  /* DSP2_RUN */
4816  
4817  #endif
4818