1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Driver for Motorola/Freescale IMX serial ports
4 *
5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 *
7 * Author: Sascha Hauer <sascha@saschahauer.de>
8 * Copyright (C) 2004 Pengutronix
9 */
10
11 #include <linux/module.h>
12 #include <linux/ioport.h>
13 #include <linux/init.h>
14 #include <linux/console.h>
15 #include <linux/sysrq.h>
16 #include <linux/platform_device.h>
17 #include <linux/tty.h>
18 #include <linux/tty_flip.h>
19 #include <linux/serial_core.h>
20 #include <linux/serial.h>
21 #include <linux/clk.h>
22 #include <linux/delay.h>
23 #include <linux/ktime.h>
24 #include <linux/pinctrl/consumer.h>
25 #include <linux/rational.h>
26 #include <linux/slab.h>
27 #include <linux/of.h>
28 #include <linux/io.h>
29 #include <linux/dma-mapping.h>
30
31 #include <asm/irq.h>
32 #include <linux/dma/imx-dma.h>
33
34 #include "serial_mctrl_gpio.h"
35
36 /* Register definitions */
37 #define URXD0 0x0 /* Receiver Register */
38 #define URTX0 0x40 /* Transmitter Register */
39 #define UCR1 0x80 /* Control Register 1 */
40 #define UCR2 0x84 /* Control Register 2 */
41 #define UCR3 0x88 /* Control Register 3 */
42 #define UCR4 0x8c /* Control Register 4 */
43 #define UFCR 0x90 /* FIFO Control Register */
44 #define USR1 0x94 /* Status Register 1 */
45 #define USR2 0x98 /* Status Register 2 */
46 #define UESC 0x9c /* Escape Character Register */
47 #define UTIM 0xa0 /* Escape Timer Register */
48 #define UBIR 0xa4 /* BRM Incremental Register */
49 #define UBMR 0xa8 /* BRM Modulator Register */
50 #define UBRC 0xac /* Baud Rate Count Register */
51 #define IMX21_ONEMS 0xb0 /* One Millisecond register */
52 #define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */
53 #define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/
54
55 /* UART Control Register Bit Fields.*/
56 #define URXD_DUMMY_READ (1<<16)
57 #define URXD_CHARRDY (1<<15)
58 #define URXD_ERR (1<<14)
59 #define URXD_OVRRUN (1<<13)
60 #define URXD_FRMERR (1<<12)
61 #define URXD_BRK (1<<11)
62 #define URXD_PRERR (1<<10)
63 #define URXD_RX_DATA (0xFF<<0)
64 #define UCR1_ADEN (1<<15) /* Auto detect interrupt */
65 #define UCR1_ADBR (1<<14) /* Auto detect baud rate */
66 #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
67 #define UCR1_IDEN (1<<12) /* Idle condition interrupt */
68 #define UCR1_ICD_REG(x) (((x) & 3) << 10) /* idle condition detect */
69 #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
70 #define UCR1_RXDMAEN (1<<8) /* Recv ready DMA enable */
71 #define UCR1_IREN (1<<7) /* Infrared interface enable */
72 #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
73 #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
74 #define UCR1_SNDBRK (1<<4) /* Send break */
75 #define UCR1_TXDMAEN (1<<3) /* Transmitter ready DMA enable */
76 #define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */
77 #define UCR1_ATDMAEN (1<<2) /* Aging DMA Timer Enable */
78 #define UCR1_DOZE (1<<1) /* Doze */
79 #define UCR1_UARTEN (1<<0) /* UART enabled */
80 #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
81 #define UCR2_IRTS (1<<14) /* Ignore RTS pin */
82 #define UCR2_CTSC (1<<13) /* CTS pin control */
83 #define UCR2_CTS (1<<12) /* Clear to send */
84 #define UCR2_ESCEN (1<<11) /* Escape enable */
85 #define UCR2_PREN (1<<8) /* Parity enable */
86 #define UCR2_PROE (1<<7) /* Parity odd/even */
87 #define UCR2_STPB (1<<6) /* Stop */
88 #define UCR2_WS (1<<5) /* Word size */
89 #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
90 #define UCR2_ATEN (1<<3) /* Aging Timer Enable */
91 #define UCR2_TXEN (1<<2) /* Transmitter enabled */
92 #define UCR2_RXEN (1<<1) /* Receiver enabled */
93 #define UCR2_SRST (1<<0) /* SW reset */
94 #define UCR3_DTREN (1<<13) /* DTR interrupt enable */
95 #define UCR3_PARERREN (1<<12) /* Parity enable */
96 #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
97 #define UCR3_DSR (1<<10) /* Data set ready */
98 #define UCR3_DCD (1<<9) /* Data carrier detect */
99 #define UCR3_RI (1<<8) /* Ring indicator */
100 #define UCR3_ADNIMP (1<<7) /* Autobaud Detection Not Improved */
101 #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
102 #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
103 #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
104 #define UCR3_DTRDEN (1<<3) /* Data Terminal Ready Delta Enable. */
105 #define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */
106 #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
107 #define UCR3_BPEN (1<<0) /* Preset registers enable */
108 #define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */
109 #define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */
110 #define UCR4_INVR (1<<9) /* Inverted infrared reception */
111 #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
112 #define UCR4_WKEN (1<<7) /* Wake interrupt enable */
113 #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
114 #define UCR4_IDDMAEN (1<<6) /* DMA IDLE Condition Detected */
115 #define UCR4_IRSC (1<<5) /* IR special case */
116 #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
117 #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
118 #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
119 #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
120 #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
121 #define UFCR_DCEDTE (1<<6) /* DCE/DTE mode select */
122 #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
123 #define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7)
124 #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
125 #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
126 #define USR1_RTSS (1<<14) /* RTS pin status */
127 #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
128 #define USR1_RTSD (1<<12) /* RTS delta */
129 #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
130 #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
131 #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
132 #define USR1_AGTIM (1<<8) /* Ageing timer interrupt flag */
133 #define USR1_DTRD (1<<7) /* DTR Delta */
134 #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
135 #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
136 #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
137 #define USR2_ADET (1<<15) /* Auto baud rate detect complete */
138 #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
139 #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
140 #define USR2_IDLE (1<<12) /* Idle condition */
141 #define USR2_RIDELT (1<<10) /* Ring Interrupt Delta */
142 #define USR2_RIIN (1<<9) /* Ring Indicator Input */
143 #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
144 #define USR2_WAKE (1<<7) /* Wake */
145 #define USR2_DCDIN (1<<5) /* Data Carrier Detect Input */
146 #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
147 #define USR2_TXDC (1<<3) /* Transmitter complete */
148 #define USR2_BRCD (1<<2) /* Break condition */
149 #define USR2_ORE (1<<1) /* Overrun error */
150 #define USR2_RDR (1<<0) /* Recv data ready */
151 #define UTS_FRCPERR (1<<13) /* Force parity error */
152 #define UTS_LOOP (1<<12) /* Loop tx and rx */
153 #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
154 #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
155 #define UTS_TXFULL (1<<4) /* TxFIFO full */
156 #define UTS_RXFULL (1<<3) /* RxFIFO full */
157 #define UTS_SOFTRST (1<<0) /* Software reset */
158
159 /* We've been assigned a range on the "Low-density serial ports" major */
160 #define SERIAL_IMX_MAJOR 207
161 #define MINOR_START 16
162 #define DEV_NAME "ttymxc"
163
164 /*
165 * This determines how often we check the modem status signals
166 * for any change. They generally aren't connected to an IRQ
167 * so we have to poll them. We also check immediately before
168 * filling the TX fifo incase CTS has been dropped.
169 */
170 #define MCTRL_TIMEOUT (250*HZ/1000)
171
172 #define DRIVER_NAME "IMX-uart"
173
174 #define UART_NR 8
175
176 /* i.MX21 type uart runs on all i.mx except i.MX1 and i.MX6q */
177 enum imx_uart_type {
178 IMX1_UART,
179 IMX21_UART,
180 IMX53_UART,
181 IMX6Q_UART,
182 };
183
184 /* device type dependent stuff */
185 struct imx_uart_data {
186 unsigned uts_reg;
187 enum imx_uart_type devtype;
188 };
189
190 enum imx_tx_state {
191 OFF,
192 WAIT_AFTER_RTS,
193 SEND,
194 WAIT_AFTER_SEND,
195 };
196
197 struct imx_port {
198 struct uart_port port;
199 struct timer_list timer;
200 unsigned int old_status;
201 unsigned int have_rtscts:1;
202 unsigned int have_rtsgpio:1;
203 unsigned int dte_mode:1;
204 unsigned int inverted_tx:1;
205 unsigned int inverted_rx:1;
206 struct clk *clk_ipg;
207 struct clk *clk_per;
208 const struct imx_uart_data *devdata;
209
210 struct mctrl_gpios *gpios;
211
212 /* counter to stop 0xff flood */
213 int idle_counter;
214
215 /* DMA fields */
216 unsigned int dma_is_enabled:1;
217 unsigned int dma_is_rxing:1;
218 unsigned int dma_is_txing:1;
219 struct dma_chan *dma_chan_rx, *dma_chan_tx;
220 struct scatterlist rx_sgl, tx_sgl[2];
221 void *rx_buf;
222 struct circ_buf rx_ring;
223 unsigned int rx_buf_size;
224 unsigned int rx_period_length;
225 unsigned int rx_periods;
226 dma_cookie_t rx_cookie;
227 unsigned int tx_bytes;
228 unsigned int dma_tx_nents;
229 unsigned int saved_reg[10];
230 bool context_saved;
231
232 enum imx_tx_state tx_state;
233 struct hrtimer trigger_start_tx;
234 struct hrtimer trigger_stop_tx;
235 };
236
237 struct imx_port_ucrs {
238 unsigned int ucr1;
239 unsigned int ucr2;
240 unsigned int ucr3;
241 };
242
243 static struct imx_uart_data imx_uart_devdata[] = {
244 [IMX1_UART] = {
245 .uts_reg = IMX1_UTS,
246 .devtype = IMX1_UART,
247 },
248 [IMX21_UART] = {
249 .uts_reg = IMX21_UTS,
250 .devtype = IMX21_UART,
251 },
252 [IMX53_UART] = {
253 .uts_reg = IMX21_UTS,
254 .devtype = IMX53_UART,
255 },
256 [IMX6Q_UART] = {
257 .uts_reg = IMX21_UTS,
258 .devtype = IMX6Q_UART,
259 },
260 };
261
262 static const struct of_device_id imx_uart_dt_ids[] = {
263 { .compatible = "fsl,imx6q-uart", .data = &imx_uart_devdata[IMX6Q_UART], },
264 { .compatible = "fsl,imx53-uart", .data = &imx_uart_devdata[IMX53_UART], },
265 { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], },
266 { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], },
267 { /* sentinel */ }
268 };
269 MODULE_DEVICE_TABLE(of, imx_uart_dt_ids);
270
imx_uart_writel(struct imx_port * sport,u32 val,u32 offset)271 static inline void imx_uart_writel(struct imx_port *sport, u32 val, u32 offset)
272 {
273 writel(val, sport->port.membase + offset);
274 }
275
imx_uart_readl(struct imx_port * sport,u32 offset)276 static inline u32 imx_uart_readl(struct imx_port *sport, u32 offset)
277 {
278 return readl(sport->port.membase + offset);
279 }
280
imx_uart_uts_reg(struct imx_port * sport)281 static inline unsigned imx_uart_uts_reg(struct imx_port *sport)
282 {
283 return sport->devdata->uts_reg;
284 }
285
imx_uart_is_imx1(struct imx_port * sport)286 static inline int imx_uart_is_imx1(struct imx_port *sport)
287 {
288 return sport->devdata->devtype == IMX1_UART;
289 }
290
291 /*
292 * Save and restore functions for UCR1, UCR2 and UCR3 registers
293 */
294 #if IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE)
imx_uart_ucrs_save(struct imx_port * sport,struct imx_port_ucrs * ucr)295 static void imx_uart_ucrs_save(struct imx_port *sport,
296 struct imx_port_ucrs *ucr)
297 {
298 /* save control registers */
299 ucr->ucr1 = imx_uart_readl(sport, UCR1);
300 ucr->ucr2 = imx_uart_readl(sport, UCR2);
301 ucr->ucr3 = imx_uart_readl(sport, UCR3);
302 }
303
imx_uart_ucrs_restore(struct imx_port * sport,struct imx_port_ucrs * ucr)304 static void imx_uart_ucrs_restore(struct imx_port *sport,
305 struct imx_port_ucrs *ucr)
306 {
307 /* restore control registers */
308 imx_uart_writel(sport, ucr->ucr1, UCR1);
309 imx_uart_writel(sport, ucr->ucr2, UCR2);
310 imx_uart_writel(sport, ucr->ucr3, UCR3);
311 }
312 #endif
313
314 /* called with port.lock taken and irqs caller dependent */
imx_uart_rts_active(struct imx_port * sport,u32 * ucr2)315 static void imx_uart_rts_active(struct imx_port *sport, u32 *ucr2)
316 {
317 *ucr2 &= ~(UCR2_CTSC | UCR2_CTS);
318
319 mctrl_gpio_set(sport->gpios, sport->port.mctrl | TIOCM_RTS);
320 }
321
322 /* called with port.lock taken and irqs caller dependent */
imx_uart_rts_inactive(struct imx_port * sport,u32 * ucr2)323 static void imx_uart_rts_inactive(struct imx_port *sport, u32 *ucr2)
324 {
325 *ucr2 &= ~UCR2_CTSC;
326 *ucr2 |= UCR2_CTS;
327
328 mctrl_gpio_set(sport->gpios, sport->port.mctrl & ~TIOCM_RTS);
329 }
330
start_hrtimer_ms(struct hrtimer * hrt,unsigned long msec)331 static void start_hrtimer_ms(struct hrtimer *hrt, unsigned long msec)
332 {
333 hrtimer_start(hrt, ms_to_ktime(msec), HRTIMER_MODE_REL);
334 }
335
336 /* called with port.lock taken and irqs off */
imx_uart_soft_reset(struct imx_port * sport)337 static void imx_uart_soft_reset(struct imx_port *sport)
338 {
339 int i = 10;
340 u32 ucr2, ubir, ubmr, uts;
341
342 /*
343 * According to the Reference Manual description of the UART SRST bit:
344 *
345 * "Reset the transmit and receive state machines,
346 * all FIFOs and register USR1, USR2, UBIR, UBMR, UBRC, URXD, UTXD
347 * and UTS[6-3]".
348 *
349 * We don't need to restore the old values from USR1, USR2, URXD and
350 * UTXD. UBRC is read only, so only save/restore the other three
351 * registers.
352 */
353 ubir = imx_uart_readl(sport, UBIR);
354 ubmr = imx_uart_readl(sport, UBMR);
355 uts = imx_uart_readl(sport, IMX21_UTS);
356
357 ucr2 = imx_uart_readl(sport, UCR2);
358 imx_uart_writel(sport, ucr2 & ~UCR2_SRST, UCR2);
359
360 while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0))
361 udelay(1);
362
363 /* Restore the registers */
364 imx_uart_writel(sport, ubir, UBIR);
365 imx_uart_writel(sport, ubmr, UBMR);
366 imx_uart_writel(sport, uts, IMX21_UTS);
367
368 sport->idle_counter = 0;
369 }
370
imx_uart_disable_loopback_rs485(struct imx_port * sport)371 static void imx_uart_disable_loopback_rs485(struct imx_port *sport)
372 {
373 unsigned int uts;
374
375 /* See SER_RS485_ENABLED/UTS_LOOP comment in imx_uart_probe() */
376 uts = imx_uart_readl(sport, imx_uart_uts_reg(sport));
377 uts &= ~UTS_LOOP;
378 imx_uart_writel(sport, uts, imx_uart_uts_reg(sport));
379 }
380
381 /* called with port.lock taken and irqs off */
imx_uart_start_rx(struct uart_port * port)382 static void imx_uart_start_rx(struct uart_port *port)
383 {
384 struct imx_port *sport = (struct imx_port *)port;
385 unsigned int ucr1, ucr2;
386
387 ucr1 = imx_uart_readl(sport, UCR1);
388 ucr2 = imx_uart_readl(sport, UCR2);
389
390 ucr2 |= UCR2_RXEN;
391
392 if (sport->dma_is_enabled) {
393 ucr1 |= UCR1_RXDMAEN | UCR1_ATDMAEN;
394 } else {
395 ucr1 |= UCR1_RRDYEN;
396 ucr2 |= UCR2_ATEN;
397 }
398
399 /* Write UCR2 first as it includes RXEN */
400 imx_uart_writel(sport, ucr2, UCR2);
401 imx_uart_writel(sport, ucr1, UCR1);
402 imx_uart_disable_loopback_rs485(sport);
403 }
404
405 /* called with port.lock taken and irqs off */
imx_uart_stop_tx(struct uart_port * port)406 static void imx_uart_stop_tx(struct uart_port *port)
407 {
408 struct imx_port *sport = (struct imx_port *)port;
409 u32 ucr1, ucr4, usr2;
410
411 if (sport->tx_state == OFF)
412 return;
413
414 /*
415 * We are maybe in the SMP context, so if the DMA TX thread is running
416 * on other cpu, we have to wait for it to finish.
417 */
418 if (sport->dma_is_txing)
419 return;
420
421 ucr1 = imx_uart_readl(sport, UCR1);
422 imx_uart_writel(sport, ucr1 & ~UCR1_TRDYEN, UCR1);
423
424 usr2 = imx_uart_readl(sport, USR2);
425 if (!(usr2 & USR2_TXDC)) {
426 /* The shifter is still busy, so retry once TC triggers */
427 return;
428 }
429
430 ucr4 = imx_uart_readl(sport, UCR4);
431 ucr4 &= ~UCR4_TCEN;
432 imx_uart_writel(sport, ucr4, UCR4);
433
434 /* in rs485 mode disable transmitter */
435 if (port->rs485.flags & SER_RS485_ENABLED) {
436 if (sport->tx_state == SEND) {
437 sport->tx_state = WAIT_AFTER_SEND;
438
439 if (port->rs485.delay_rts_after_send > 0) {
440 start_hrtimer_ms(&sport->trigger_stop_tx,
441 port->rs485.delay_rts_after_send);
442 return;
443 }
444
445 /* continue without any delay */
446 }
447
448 if (sport->tx_state == WAIT_AFTER_RTS ||
449 sport->tx_state == WAIT_AFTER_SEND) {
450 u32 ucr2;
451
452 hrtimer_try_to_cancel(&sport->trigger_start_tx);
453
454 ucr2 = imx_uart_readl(sport, UCR2);
455 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
456 imx_uart_rts_active(sport, &ucr2);
457 else
458 imx_uart_rts_inactive(sport, &ucr2);
459 imx_uart_writel(sport, ucr2, UCR2);
460
461 if (!port->rs485_rx_during_tx_gpio)
462 imx_uart_start_rx(port);
463
464 sport->tx_state = OFF;
465 }
466 } else {
467 sport->tx_state = OFF;
468 }
469 }
470
471 /* called with port.lock taken and irqs off */
imx_uart_stop_rx(struct uart_port * port)472 static void imx_uart_stop_rx(struct uart_port *port)
473 {
474 struct imx_port *sport = (struct imx_port *)port;
475 u32 ucr1, ucr2, ucr4, uts;
476
477 ucr1 = imx_uart_readl(sport, UCR1);
478 ucr2 = imx_uart_readl(sport, UCR2);
479 ucr4 = imx_uart_readl(sport, UCR4);
480
481 if (sport->dma_is_enabled) {
482 ucr1 &= ~(UCR1_RXDMAEN | UCR1_ATDMAEN);
483 } else {
484 ucr1 &= ~UCR1_RRDYEN;
485 ucr2 &= ~UCR2_ATEN;
486 ucr4 &= ~UCR4_OREN;
487 }
488 imx_uart_writel(sport, ucr1, UCR1);
489 imx_uart_writel(sport, ucr4, UCR4);
490
491 /* See SER_RS485_ENABLED/UTS_LOOP comment in imx_uart_probe() */
492 if (port->rs485.flags & SER_RS485_ENABLED &&
493 port->rs485.flags & SER_RS485_RTS_ON_SEND &&
494 sport->have_rtscts && !sport->have_rtsgpio) {
495 uts = imx_uart_readl(sport, imx_uart_uts_reg(sport));
496 uts |= UTS_LOOP;
497 imx_uart_writel(sport, uts, imx_uart_uts_reg(sport));
498 ucr2 |= UCR2_RXEN;
499 } else {
500 ucr2 &= ~UCR2_RXEN;
501 }
502
503 imx_uart_writel(sport, ucr2, UCR2);
504 }
505
506 /* called with port.lock taken and irqs off */
imx_uart_enable_ms(struct uart_port * port)507 static void imx_uart_enable_ms(struct uart_port *port)
508 {
509 struct imx_port *sport = (struct imx_port *)port;
510
511 mod_timer(&sport->timer, jiffies);
512
513 mctrl_gpio_enable_ms(sport->gpios);
514 }
515
516 static void imx_uart_dma_tx(struct imx_port *sport);
517
518 /* called with port.lock taken and irqs off */
imx_uart_transmit_buffer(struct imx_port * sport)519 static inline void imx_uart_transmit_buffer(struct imx_port *sport)
520 {
521 struct circ_buf *xmit = &sport->port.state->xmit;
522
523 if (sport->port.x_char) {
524 /* Send next char */
525 imx_uart_writel(sport, sport->port.x_char, URTX0);
526 sport->port.icount.tx++;
527 sport->port.x_char = 0;
528 return;
529 }
530
531 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
532 imx_uart_stop_tx(&sport->port);
533 return;
534 }
535
536 if (sport->dma_is_enabled) {
537 u32 ucr1;
538 /*
539 * We've just sent a X-char Ensure the TX DMA is enabled
540 * and the TX IRQ is disabled.
541 **/
542 ucr1 = imx_uart_readl(sport, UCR1);
543 ucr1 &= ~UCR1_TRDYEN;
544 if (sport->dma_is_txing) {
545 ucr1 |= UCR1_TXDMAEN;
546 imx_uart_writel(sport, ucr1, UCR1);
547 } else {
548 imx_uart_writel(sport, ucr1, UCR1);
549 imx_uart_dma_tx(sport);
550 }
551
552 return;
553 }
554
555 while (!uart_circ_empty(xmit) &&
556 !(imx_uart_readl(sport, imx_uart_uts_reg(sport)) & UTS_TXFULL)) {
557 /* send xmit->buf[xmit->tail]
558 * out the port here */
559 imx_uart_writel(sport, xmit->buf[xmit->tail], URTX0);
560 uart_xmit_advance(&sport->port, 1);
561 }
562
563 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
564 uart_write_wakeup(&sport->port);
565
566 if (uart_circ_empty(xmit))
567 imx_uart_stop_tx(&sport->port);
568 }
569
imx_uart_dma_tx_callback(void * data)570 static void imx_uart_dma_tx_callback(void *data)
571 {
572 struct imx_port *sport = data;
573 struct scatterlist *sgl = &sport->tx_sgl[0];
574 struct circ_buf *xmit = &sport->port.state->xmit;
575 unsigned long flags;
576 u32 ucr1;
577
578 spin_lock_irqsave(&sport->port.lock, flags);
579
580 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
581
582 ucr1 = imx_uart_readl(sport, UCR1);
583 ucr1 &= ~UCR1_TXDMAEN;
584 imx_uart_writel(sport, ucr1, UCR1);
585
586 uart_xmit_advance(&sport->port, sport->tx_bytes);
587
588 dev_dbg(sport->port.dev, "we finish the TX DMA.\n");
589
590 sport->dma_is_txing = 0;
591
592 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
593 uart_write_wakeup(&sport->port);
594
595 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&sport->port))
596 imx_uart_dma_tx(sport);
597 else if (sport->port.rs485.flags & SER_RS485_ENABLED) {
598 u32 ucr4 = imx_uart_readl(sport, UCR4);
599 ucr4 |= UCR4_TCEN;
600 imx_uart_writel(sport, ucr4, UCR4);
601 }
602
603 spin_unlock_irqrestore(&sport->port.lock, flags);
604 }
605
606 /* called with port.lock taken and irqs off */
imx_uart_dma_tx(struct imx_port * sport)607 static void imx_uart_dma_tx(struct imx_port *sport)
608 {
609 struct circ_buf *xmit = &sport->port.state->xmit;
610 struct scatterlist *sgl = sport->tx_sgl;
611 struct dma_async_tx_descriptor *desc;
612 struct dma_chan *chan = sport->dma_chan_tx;
613 struct device *dev = sport->port.dev;
614 u32 ucr1, ucr4;
615 int ret;
616
617 if (sport->dma_is_txing)
618 return;
619
620 ucr4 = imx_uart_readl(sport, UCR4);
621 ucr4 &= ~UCR4_TCEN;
622 imx_uart_writel(sport, ucr4, UCR4);
623
624 sport->tx_bytes = uart_circ_chars_pending(xmit);
625
626 if (xmit->tail < xmit->head || xmit->head == 0) {
627 sport->dma_tx_nents = 1;
628 sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes);
629 } else {
630 sport->dma_tx_nents = 2;
631 sg_init_table(sgl, 2);
632 sg_set_buf(sgl, xmit->buf + xmit->tail,
633 UART_XMIT_SIZE - xmit->tail);
634 sg_set_buf(sgl + 1, xmit->buf, xmit->head);
635 }
636
637 ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
638 if (ret == 0) {
639 dev_err(dev, "DMA mapping error for TX.\n");
640 return;
641 }
642 desc = dmaengine_prep_slave_sg(chan, sgl, ret,
643 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
644 if (!desc) {
645 dma_unmap_sg(dev, sgl, sport->dma_tx_nents,
646 DMA_TO_DEVICE);
647 dev_err(dev, "We cannot prepare for the TX slave dma!\n");
648 return;
649 }
650 desc->callback = imx_uart_dma_tx_callback;
651 desc->callback_param = sport;
652
653 dev_dbg(dev, "TX: prepare to send %lu bytes by DMA.\n",
654 uart_circ_chars_pending(xmit));
655
656 ucr1 = imx_uart_readl(sport, UCR1);
657 ucr1 |= UCR1_TXDMAEN;
658 imx_uart_writel(sport, ucr1, UCR1);
659
660 /* fire it */
661 sport->dma_is_txing = 1;
662 dmaengine_submit(desc);
663 dma_async_issue_pending(chan);
664 return;
665 }
666
667 /* called with port.lock taken and irqs off */
imx_uart_start_tx(struct uart_port * port)668 static void imx_uart_start_tx(struct uart_port *port)
669 {
670 struct imx_port *sport = (struct imx_port *)port;
671 u32 ucr1;
672
673 if (!sport->port.x_char && uart_circ_empty(&port->state->xmit))
674 return;
675
676 /*
677 * We cannot simply do nothing here if sport->tx_state == SEND already
678 * because UCR1_TXMPTYEN might already have been cleared in
679 * imx_uart_stop_tx(), but tx_state is still SEND.
680 */
681
682 if (port->rs485.flags & SER_RS485_ENABLED) {
683 if (sport->tx_state == OFF) {
684 u32 ucr2 = imx_uart_readl(sport, UCR2);
685 if (port->rs485.flags & SER_RS485_RTS_ON_SEND)
686 imx_uart_rts_active(sport, &ucr2);
687 else
688 imx_uart_rts_inactive(sport, &ucr2);
689 imx_uart_writel(sport, ucr2, UCR2);
690
691 if (!(port->rs485.flags & SER_RS485_RX_DURING_TX) &&
692 !port->rs485_rx_during_tx_gpio)
693 imx_uart_stop_rx(port);
694
695 sport->tx_state = WAIT_AFTER_RTS;
696
697 if (port->rs485.delay_rts_before_send > 0) {
698 start_hrtimer_ms(&sport->trigger_start_tx,
699 port->rs485.delay_rts_before_send);
700 return;
701 }
702
703 /* continue without any delay */
704 }
705
706 if (sport->tx_state == WAIT_AFTER_SEND
707 || sport->tx_state == WAIT_AFTER_RTS) {
708
709 hrtimer_try_to_cancel(&sport->trigger_stop_tx);
710
711 /*
712 * Enable transmitter and shifter empty irq only if DMA
713 * is off. In the DMA case this is done in the
714 * tx-callback.
715 */
716 if (!sport->dma_is_enabled) {
717 u32 ucr4 = imx_uart_readl(sport, UCR4);
718 ucr4 |= UCR4_TCEN;
719 imx_uart_writel(sport, ucr4, UCR4);
720 }
721
722 sport->tx_state = SEND;
723 }
724 } else {
725 sport->tx_state = SEND;
726 }
727
728 if (!sport->dma_is_enabled) {
729 ucr1 = imx_uart_readl(sport, UCR1);
730 imx_uart_writel(sport, ucr1 | UCR1_TRDYEN, UCR1);
731 }
732
733 if (sport->dma_is_enabled) {
734 if (sport->port.x_char) {
735 /* We have X-char to send, so enable TX IRQ and
736 * disable TX DMA to let TX interrupt to send X-char */
737 ucr1 = imx_uart_readl(sport, UCR1);
738 ucr1 &= ~UCR1_TXDMAEN;
739 ucr1 |= UCR1_TRDYEN;
740 imx_uart_writel(sport, ucr1, UCR1);
741 return;
742 }
743
744 if (!uart_circ_empty(&port->state->xmit) &&
745 !uart_tx_stopped(port))
746 imx_uart_dma_tx(sport);
747 return;
748 }
749 }
750
__imx_uart_rtsint(int irq,void * dev_id)751 static irqreturn_t __imx_uart_rtsint(int irq, void *dev_id)
752 {
753 struct imx_port *sport = dev_id;
754 u32 usr1;
755
756 imx_uart_writel(sport, USR1_RTSD, USR1);
757 usr1 = imx_uart_readl(sport, USR1) & USR1_RTSS;
758 uart_handle_cts_change(&sport->port, usr1);
759 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
760
761 return IRQ_HANDLED;
762 }
763
imx_uart_rtsint(int irq,void * dev_id)764 static irqreturn_t imx_uart_rtsint(int irq, void *dev_id)
765 {
766 struct imx_port *sport = dev_id;
767 irqreturn_t ret;
768
769 spin_lock(&sport->port.lock);
770
771 ret = __imx_uart_rtsint(irq, dev_id);
772
773 spin_unlock(&sport->port.lock);
774
775 return ret;
776 }
777
imx_uart_txint(int irq,void * dev_id)778 static irqreturn_t imx_uart_txint(int irq, void *dev_id)
779 {
780 struct imx_port *sport = dev_id;
781
782 spin_lock(&sport->port.lock);
783 imx_uart_transmit_buffer(sport);
784 spin_unlock(&sport->port.lock);
785 return IRQ_HANDLED;
786 }
787
788 /* Check if hardware Rx flood is in progress, and issue soft reset to stop it.
789 * This is to be called from Rx ISRs only when some bytes were actually
790 * received.
791 *
792 * A way to reproduce the flood (checked on iMX6SX) is: open iMX UART at 9600
793 * 8N1, and from external source send 0xf0 char at 115200 8N1. In about 90% of
794 * cases this starts a flood of "receiving" of 0xff characters by the iMX6 UART
795 * that is terminated by any activity on RxD line, or could be stopped by
796 * issuing soft reset to the UART (just stop/start of RX does not help). Note
797 * that what we do here is sending isolated start bit about 2.4 times shorter
798 * than it is to be on UART configured baud rate.
799 */
imx_uart_check_flood(struct imx_port * sport,u32 usr2)800 static void imx_uart_check_flood(struct imx_port *sport, u32 usr2)
801 {
802 /* To detect hardware 0xff flood we monitor RxD line between RX
803 * interrupts to isolate "receiving" of char(s) with no activity
804 * on RxD line, that'd never happen on actual data transfers.
805 *
806 * We use USR2_WAKE bit to check for activity on RxD line, but we have a
807 * race here if we clear USR2_WAKE when receiving of a char is in
808 * progress, so we might get RX interrupt later with USR2_WAKE bit
809 * cleared. Note though that as we don't try to clear USR2_WAKE when we
810 * detected no activity, this race may hide actual activity only once.
811 *
812 * Yet another case where receive interrupt may occur without RxD
813 * activity is expiration of aging timer, so we consider this as well.
814 *
815 * We use 'idle_counter' to ensure that we got at least so many RX
816 * interrupts without any detected activity on RxD line. 2 cases
817 * described plus 1 to be on the safe side gives us a margin of 3,
818 * below. In practice I was not able to produce a false positive to
819 * induce soft reset at regular data transfers even using 1 as the
820 * margin, so 3 is actually very strong.
821 *
822 * We count interrupts, not chars in 'idle-counter' for simplicity.
823 */
824
825 if (usr2 & USR2_WAKE) {
826 imx_uart_writel(sport, USR2_WAKE, USR2);
827 sport->idle_counter = 0;
828 } else if (++sport->idle_counter > 3) {
829 dev_warn(sport->port.dev, "RX flood detected: soft reset.");
830 imx_uart_soft_reset(sport); /* also clears 'sport->idle_counter' */
831 }
832 }
833
__imx_uart_rxint(int irq,void * dev_id)834 static irqreturn_t __imx_uart_rxint(int irq, void *dev_id)
835 {
836 struct imx_port *sport = dev_id;
837 struct tty_port *port = &sport->port.state->port;
838 u32 usr2, rx;
839
840 /* If we received something, check for 0xff flood */
841 usr2 = imx_uart_readl(sport, USR2);
842 if (usr2 & USR2_RDR)
843 imx_uart_check_flood(sport, usr2);
844
845 while ((rx = imx_uart_readl(sport, URXD0)) & URXD_CHARRDY) {
846 unsigned int flg = TTY_NORMAL;
847 sport->port.icount.rx++;
848
849 if (unlikely(rx & URXD_ERR)) {
850 if (rx & URXD_BRK) {
851 sport->port.icount.brk++;
852 if (uart_handle_break(&sport->port))
853 continue;
854 }
855 else if (rx & URXD_PRERR)
856 sport->port.icount.parity++;
857 else if (rx & URXD_FRMERR)
858 sport->port.icount.frame++;
859 if (rx & URXD_OVRRUN)
860 sport->port.icount.overrun++;
861
862 if (rx & sport->port.ignore_status_mask)
863 continue;
864
865 rx &= (sport->port.read_status_mask | 0xFF);
866
867 if (rx & URXD_BRK)
868 flg = TTY_BREAK;
869 else if (rx & URXD_PRERR)
870 flg = TTY_PARITY;
871 else if (rx & URXD_FRMERR)
872 flg = TTY_FRAME;
873 if (rx & URXD_OVRRUN)
874 flg = TTY_OVERRUN;
875
876 sport->port.sysrq = 0;
877 } else if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx)) {
878 continue;
879 }
880
881 if (sport->port.ignore_status_mask & URXD_DUMMY_READ)
882 continue;
883
884 if (tty_insert_flip_char(port, rx, flg) == 0)
885 sport->port.icount.buf_overrun++;
886 }
887
888 tty_flip_buffer_push(port);
889
890 return IRQ_HANDLED;
891 }
892
imx_uart_rxint(int irq,void * dev_id)893 static irqreturn_t imx_uart_rxint(int irq, void *dev_id)
894 {
895 struct imx_port *sport = dev_id;
896 irqreturn_t ret;
897
898 spin_lock(&sport->port.lock);
899
900 ret = __imx_uart_rxint(irq, dev_id);
901
902 spin_unlock(&sport->port.lock);
903
904 return ret;
905 }
906
907 static void imx_uart_clear_rx_errors(struct imx_port *sport);
908
909 /*
910 * We have a modem side uart, so the meanings of RTS and CTS are inverted.
911 */
imx_uart_get_hwmctrl(struct imx_port * sport)912 static unsigned int imx_uart_get_hwmctrl(struct imx_port *sport)
913 {
914 unsigned int tmp = TIOCM_DSR;
915 unsigned usr1 = imx_uart_readl(sport, USR1);
916 unsigned usr2 = imx_uart_readl(sport, USR2);
917
918 if (usr1 & USR1_RTSS)
919 tmp |= TIOCM_CTS;
920
921 /* in DCE mode DCDIN is always 0 */
922 if (!(usr2 & USR2_DCDIN))
923 tmp |= TIOCM_CAR;
924
925 if (sport->dte_mode)
926 if (!(imx_uart_readl(sport, USR2) & USR2_RIIN))
927 tmp |= TIOCM_RI;
928
929 return tmp;
930 }
931
932 /*
933 * Handle any change of modem status signal since we were last called.
934 */
imx_uart_mctrl_check(struct imx_port * sport)935 static void imx_uart_mctrl_check(struct imx_port *sport)
936 {
937 unsigned int status, changed;
938
939 status = imx_uart_get_hwmctrl(sport);
940 changed = status ^ sport->old_status;
941
942 if (changed == 0)
943 return;
944
945 sport->old_status = status;
946
947 if (changed & TIOCM_RI && status & TIOCM_RI)
948 sport->port.icount.rng++;
949 if (changed & TIOCM_DSR)
950 sport->port.icount.dsr++;
951 if (changed & TIOCM_CAR)
952 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
953 if (changed & TIOCM_CTS)
954 uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
955
956 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
957 }
958
imx_uart_int(int irq,void * dev_id)959 static irqreturn_t imx_uart_int(int irq, void *dev_id)
960 {
961 struct imx_port *sport = dev_id;
962 unsigned int usr1, usr2, ucr1, ucr2, ucr3, ucr4;
963 irqreturn_t ret = IRQ_NONE;
964
965 spin_lock(&sport->port.lock);
966
967 usr1 = imx_uart_readl(sport, USR1);
968 usr2 = imx_uart_readl(sport, USR2);
969 ucr1 = imx_uart_readl(sport, UCR1);
970 ucr2 = imx_uart_readl(sport, UCR2);
971 ucr3 = imx_uart_readl(sport, UCR3);
972 ucr4 = imx_uart_readl(sport, UCR4);
973
974 /*
975 * Even if a condition is true that can trigger an irq only handle it if
976 * the respective irq source is enabled. This prevents some undesired
977 * actions, for example if a character that sits in the RX FIFO and that
978 * should be fetched via DMA is tried to be fetched using PIO. Or the
979 * receiver is currently off and so reading from URXD0 results in an
980 * exception. So just mask the (raw) status bits for disabled irqs.
981 */
982 if ((ucr1 & UCR1_RRDYEN) == 0)
983 usr1 &= ~USR1_RRDY;
984 if ((ucr2 & UCR2_ATEN) == 0)
985 usr1 &= ~USR1_AGTIM;
986 if ((ucr1 & UCR1_TRDYEN) == 0)
987 usr1 &= ~USR1_TRDY;
988 if ((ucr4 & UCR4_TCEN) == 0)
989 usr2 &= ~USR2_TXDC;
990 if ((ucr3 & UCR3_DTRDEN) == 0)
991 usr1 &= ~USR1_DTRD;
992 if ((ucr1 & UCR1_RTSDEN) == 0)
993 usr1 &= ~USR1_RTSD;
994 if ((ucr3 & UCR3_AWAKEN) == 0)
995 usr1 &= ~USR1_AWAKE;
996 if ((ucr4 & UCR4_OREN) == 0)
997 usr2 &= ~USR2_ORE;
998
999 if (usr1 & (USR1_RRDY | USR1_AGTIM)) {
1000 imx_uart_writel(sport, USR1_AGTIM, USR1);
1001
1002 __imx_uart_rxint(irq, dev_id);
1003 ret = IRQ_HANDLED;
1004 }
1005
1006 if ((usr1 & USR1_TRDY) || (usr2 & USR2_TXDC)) {
1007 imx_uart_transmit_buffer(sport);
1008 ret = IRQ_HANDLED;
1009 }
1010
1011 if (usr1 & USR1_DTRD) {
1012 imx_uart_writel(sport, USR1_DTRD, USR1);
1013
1014 imx_uart_mctrl_check(sport);
1015
1016 ret = IRQ_HANDLED;
1017 }
1018
1019 if (usr1 & USR1_RTSD) {
1020 __imx_uart_rtsint(irq, dev_id);
1021 ret = IRQ_HANDLED;
1022 }
1023
1024 if (usr1 & USR1_AWAKE) {
1025 imx_uart_writel(sport, USR1_AWAKE, USR1);
1026 ret = IRQ_HANDLED;
1027 }
1028
1029 if (usr2 & USR2_ORE) {
1030 sport->port.icount.overrun++;
1031 imx_uart_writel(sport, USR2_ORE, USR2);
1032 ret = IRQ_HANDLED;
1033 }
1034
1035 spin_unlock(&sport->port.lock);
1036
1037 return ret;
1038 }
1039
1040 /*
1041 * Return TIOCSER_TEMT when transmitter is not busy.
1042 */
imx_uart_tx_empty(struct uart_port * port)1043 static unsigned int imx_uart_tx_empty(struct uart_port *port)
1044 {
1045 struct imx_port *sport = (struct imx_port *)port;
1046 unsigned int ret;
1047
1048 ret = (imx_uart_readl(sport, USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0;
1049
1050 /* If the TX DMA is working, return 0. */
1051 if (sport->dma_is_txing)
1052 ret = 0;
1053
1054 return ret;
1055 }
1056
1057 /* called with port.lock taken and irqs off */
imx_uart_get_mctrl(struct uart_port * port)1058 static unsigned int imx_uart_get_mctrl(struct uart_port *port)
1059 {
1060 struct imx_port *sport = (struct imx_port *)port;
1061 unsigned int ret = imx_uart_get_hwmctrl(sport);
1062
1063 mctrl_gpio_get(sport->gpios, &ret);
1064
1065 return ret;
1066 }
1067
1068 /* called with port.lock taken and irqs off */
imx_uart_set_mctrl(struct uart_port * port,unsigned int mctrl)1069 static void imx_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1070 {
1071 struct imx_port *sport = (struct imx_port *)port;
1072 u32 ucr3, uts;
1073
1074 if (!(port->rs485.flags & SER_RS485_ENABLED)) {
1075 u32 ucr2;
1076
1077 /*
1078 * Turn off autoRTS if RTS is lowered and restore autoRTS
1079 * setting if RTS is raised.
1080 */
1081 ucr2 = imx_uart_readl(sport, UCR2);
1082 ucr2 &= ~(UCR2_CTS | UCR2_CTSC);
1083 if (mctrl & TIOCM_RTS) {
1084 ucr2 |= UCR2_CTS;
1085 /*
1086 * UCR2_IRTS is unset if and only if the port is
1087 * configured for CRTSCTS, so we use inverted UCR2_IRTS
1088 * to get the state to restore to.
1089 */
1090 if (!(ucr2 & UCR2_IRTS))
1091 ucr2 |= UCR2_CTSC;
1092 }
1093 imx_uart_writel(sport, ucr2, UCR2);
1094 }
1095
1096 ucr3 = imx_uart_readl(sport, UCR3) & ~UCR3_DSR;
1097 if (!(mctrl & TIOCM_DTR))
1098 ucr3 |= UCR3_DSR;
1099 imx_uart_writel(sport, ucr3, UCR3);
1100
1101 uts = imx_uart_readl(sport, imx_uart_uts_reg(sport)) & ~UTS_LOOP;
1102 if (mctrl & TIOCM_LOOP)
1103 uts |= UTS_LOOP;
1104 imx_uart_writel(sport, uts, imx_uart_uts_reg(sport));
1105
1106 mctrl_gpio_set(sport->gpios, mctrl);
1107 }
1108
1109 /*
1110 * Interrupts always disabled.
1111 */
imx_uart_break_ctl(struct uart_port * port,int break_state)1112 static void imx_uart_break_ctl(struct uart_port *port, int break_state)
1113 {
1114 struct imx_port *sport = (struct imx_port *)port;
1115 unsigned long flags;
1116 u32 ucr1;
1117
1118 spin_lock_irqsave(&sport->port.lock, flags);
1119
1120 ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_SNDBRK;
1121
1122 if (break_state != 0)
1123 ucr1 |= UCR1_SNDBRK;
1124
1125 imx_uart_writel(sport, ucr1, UCR1);
1126
1127 spin_unlock_irqrestore(&sport->port.lock, flags);
1128 }
1129
1130 /*
1131 * This is our per-port timeout handler, for checking the
1132 * modem status signals.
1133 */
imx_uart_timeout(struct timer_list * t)1134 static void imx_uart_timeout(struct timer_list *t)
1135 {
1136 struct imx_port *sport = from_timer(sport, t, timer);
1137 unsigned long flags;
1138
1139 if (sport->port.state) {
1140 spin_lock_irqsave(&sport->port.lock, flags);
1141 imx_uart_mctrl_check(sport);
1142 spin_unlock_irqrestore(&sport->port.lock, flags);
1143
1144 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
1145 }
1146 }
1147
1148 /*
1149 * There are two kinds of RX DMA interrupts(such as in the MX6Q):
1150 * [1] the RX DMA buffer is full.
1151 * [2] the aging timer expires
1152 *
1153 * Condition [2] is triggered when a character has been sitting in the FIFO
1154 * for at least 8 byte durations.
1155 */
imx_uart_dma_rx_callback(void * data)1156 static void imx_uart_dma_rx_callback(void *data)
1157 {
1158 struct imx_port *sport = data;
1159 struct dma_chan *chan = sport->dma_chan_rx;
1160 struct scatterlist *sgl = &sport->rx_sgl;
1161 struct tty_port *port = &sport->port.state->port;
1162 struct dma_tx_state state;
1163 struct circ_buf *rx_ring = &sport->rx_ring;
1164 enum dma_status status;
1165 unsigned int w_bytes = 0;
1166 unsigned int r_bytes;
1167 unsigned int bd_size;
1168
1169 status = dmaengine_tx_status(chan, sport->rx_cookie, &state);
1170
1171 if (status == DMA_ERROR) {
1172 spin_lock(&sport->port.lock);
1173 imx_uart_clear_rx_errors(sport);
1174 spin_unlock(&sport->port.lock);
1175 return;
1176 }
1177
1178 /*
1179 * The state-residue variable represents the empty space
1180 * relative to the entire buffer. Taking this in consideration
1181 * the head is always calculated base on the buffer total
1182 * length - DMA transaction residue. The UART script from the
1183 * SDMA firmware will jump to the next buffer descriptor,
1184 * once a DMA transaction if finalized (IMX53 RM - A.4.1.2.4).
1185 * Taking this in consideration the tail is always at the
1186 * beginning of the buffer descriptor that contains the head.
1187 */
1188
1189 /* Calculate the head */
1190 rx_ring->head = sg_dma_len(sgl) - state.residue;
1191
1192 /* Calculate the tail. */
1193 bd_size = sg_dma_len(sgl) / sport->rx_periods;
1194 rx_ring->tail = ((rx_ring->head-1) / bd_size) * bd_size;
1195
1196 if (rx_ring->head <= sg_dma_len(sgl) &&
1197 rx_ring->head > rx_ring->tail) {
1198
1199 /* Move data from tail to head */
1200 r_bytes = rx_ring->head - rx_ring->tail;
1201
1202 /* If we received something, check for 0xff flood */
1203 spin_lock(&sport->port.lock);
1204 imx_uart_check_flood(sport, imx_uart_readl(sport, USR2));
1205 spin_unlock(&sport->port.lock);
1206
1207 if (!(sport->port.ignore_status_mask & URXD_DUMMY_READ)) {
1208
1209 /* CPU claims ownership of RX DMA buffer */
1210 dma_sync_sg_for_cpu(sport->port.dev, sgl, 1,
1211 DMA_FROM_DEVICE);
1212
1213 w_bytes = tty_insert_flip_string(port,
1214 sport->rx_buf + rx_ring->tail, r_bytes);
1215
1216 /* UART retrieves ownership of RX DMA buffer */
1217 dma_sync_sg_for_device(sport->port.dev, sgl, 1,
1218 DMA_FROM_DEVICE);
1219
1220 if (w_bytes != r_bytes)
1221 sport->port.icount.buf_overrun++;
1222
1223 sport->port.icount.rx += w_bytes;
1224 }
1225 } else {
1226 WARN_ON(rx_ring->head > sg_dma_len(sgl));
1227 WARN_ON(rx_ring->head <= rx_ring->tail);
1228 }
1229
1230 if (w_bytes) {
1231 tty_flip_buffer_push(port);
1232 dev_dbg(sport->port.dev, "We get %d bytes.\n", w_bytes);
1233 }
1234 }
1235
imx_uart_start_rx_dma(struct imx_port * sport)1236 static int imx_uart_start_rx_dma(struct imx_port *sport)
1237 {
1238 struct scatterlist *sgl = &sport->rx_sgl;
1239 struct dma_chan *chan = sport->dma_chan_rx;
1240 struct device *dev = sport->port.dev;
1241 struct dma_async_tx_descriptor *desc;
1242 int ret;
1243
1244 sport->rx_ring.head = 0;
1245 sport->rx_ring.tail = 0;
1246
1247 sg_init_one(sgl, sport->rx_buf, sport->rx_buf_size);
1248 ret = dma_map_sg(dev, sgl, 1, DMA_FROM_DEVICE);
1249 if (ret == 0) {
1250 dev_err(dev, "DMA mapping error for RX.\n");
1251 return -EINVAL;
1252 }
1253
1254 desc = dmaengine_prep_dma_cyclic(chan, sg_dma_address(sgl),
1255 sg_dma_len(sgl), sg_dma_len(sgl) / sport->rx_periods,
1256 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
1257
1258 if (!desc) {
1259 dma_unmap_sg(dev, sgl, 1, DMA_FROM_DEVICE);
1260 dev_err(dev, "We cannot prepare for the RX slave dma!\n");
1261 return -EINVAL;
1262 }
1263 desc->callback = imx_uart_dma_rx_callback;
1264 desc->callback_param = sport;
1265
1266 dev_dbg(dev, "RX: prepare for the DMA.\n");
1267 sport->dma_is_rxing = 1;
1268 sport->rx_cookie = dmaengine_submit(desc);
1269 dma_async_issue_pending(chan);
1270 return 0;
1271 }
1272
imx_uart_clear_rx_errors(struct imx_port * sport)1273 static void imx_uart_clear_rx_errors(struct imx_port *sport)
1274 {
1275 struct tty_port *port = &sport->port.state->port;
1276 u32 usr1, usr2;
1277
1278 usr1 = imx_uart_readl(sport, USR1);
1279 usr2 = imx_uart_readl(sport, USR2);
1280
1281 if (usr2 & USR2_BRCD) {
1282 sport->port.icount.brk++;
1283 imx_uart_writel(sport, USR2_BRCD, USR2);
1284 uart_handle_break(&sport->port);
1285 if (tty_insert_flip_char(port, 0, TTY_BREAK) == 0)
1286 sport->port.icount.buf_overrun++;
1287 tty_flip_buffer_push(port);
1288 } else {
1289 if (usr1 & USR1_FRAMERR) {
1290 sport->port.icount.frame++;
1291 imx_uart_writel(sport, USR1_FRAMERR, USR1);
1292 } else if (usr1 & USR1_PARITYERR) {
1293 sport->port.icount.parity++;
1294 imx_uart_writel(sport, USR1_PARITYERR, USR1);
1295 }
1296 }
1297
1298 if (usr2 & USR2_ORE) {
1299 sport->port.icount.overrun++;
1300 imx_uart_writel(sport, USR2_ORE, USR2);
1301 }
1302
1303 sport->idle_counter = 0;
1304
1305 }
1306
1307 #define TXTL_DEFAULT 2 /* reset default */
1308 #define RXTL_DEFAULT 8 /* 8 characters or aging timer */
1309 #define TXTL_DMA 8 /* DMA burst setting */
1310 #define RXTL_DMA 9 /* DMA burst setting */
1311
imx_uart_setup_ufcr(struct imx_port * sport,unsigned char txwl,unsigned char rxwl)1312 static void imx_uart_setup_ufcr(struct imx_port *sport,
1313 unsigned char txwl, unsigned char rxwl)
1314 {
1315 unsigned int val;
1316
1317 /* set receiver / transmitter trigger level */
1318 val = imx_uart_readl(sport, UFCR) & (UFCR_RFDIV | UFCR_DCEDTE);
1319 val |= txwl << UFCR_TXTL_SHF | rxwl;
1320 imx_uart_writel(sport, val, UFCR);
1321 }
1322
imx_uart_dma_exit(struct imx_port * sport)1323 static void imx_uart_dma_exit(struct imx_port *sport)
1324 {
1325 if (sport->dma_chan_rx) {
1326 dmaengine_terminate_sync(sport->dma_chan_rx);
1327 dma_release_channel(sport->dma_chan_rx);
1328 sport->dma_chan_rx = NULL;
1329 sport->rx_cookie = -EINVAL;
1330 kfree(sport->rx_buf);
1331 sport->rx_buf = NULL;
1332 }
1333
1334 if (sport->dma_chan_tx) {
1335 dmaengine_terminate_sync(sport->dma_chan_tx);
1336 dma_release_channel(sport->dma_chan_tx);
1337 sport->dma_chan_tx = NULL;
1338 }
1339 }
1340
imx_uart_dma_init(struct imx_port * sport)1341 static int imx_uart_dma_init(struct imx_port *sport)
1342 {
1343 struct dma_slave_config slave_config = {};
1344 struct device *dev = sport->port.dev;
1345 int ret;
1346
1347 /* Prepare for RX : */
1348 sport->dma_chan_rx = dma_request_slave_channel(dev, "rx");
1349 if (!sport->dma_chan_rx) {
1350 dev_dbg(dev, "cannot get the DMA channel.\n");
1351 ret = -EINVAL;
1352 goto err;
1353 }
1354
1355 slave_config.direction = DMA_DEV_TO_MEM;
1356 slave_config.src_addr = sport->port.mapbase + URXD0;
1357 slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1358 /* one byte less than the watermark level to enable the aging timer */
1359 slave_config.src_maxburst = RXTL_DMA - 1;
1360 ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config);
1361 if (ret) {
1362 dev_err(dev, "error in RX dma configuration.\n");
1363 goto err;
1364 }
1365
1366 sport->rx_buf_size = sport->rx_period_length * sport->rx_periods;
1367 sport->rx_buf = kzalloc(sport->rx_buf_size, GFP_KERNEL);
1368 if (!sport->rx_buf) {
1369 ret = -ENOMEM;
1370 goto err;
1371 }
1372 sport->rx_ring.buf = sport->rx_buf;
1373
1374 /* Prepare for TX : */
1375 sport->dma_chan_tx = dma_request_slave_channel(dev, "tx");
1376 if (!sport->dma_chan_tx) {
1377 dev_err(dev, "cannot get the TX DMA channel!\n");
1378 ret = -EINVAL;
1379 goto err;
1380 }
1381
1382 slave_config.direction = DMA_MEM_TO_DEV;
1383 slave_config.dst_addr = sport->port.mapbase + URTX0;
1384 slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1385 slave_config.dst_maxburst = TXTL_DMA;
1386 ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config);
1387 if (ret) {
1388 dev_err(dev, "error in TX dma configuration.");
1389 goto err;
1390 }
1391
1392 return 0;
1393 err:
1394 imx_uart_dma_exit(sport);
1395 return ret;
1396 }
1397
imx_uart_enable_dma(struct imx_port * sport)1398 static void imx_uart_enable_dma(struct imx_port *sport)
1399 {
1400 u32 ucr1;
1401
1402 imx_uart_setup_ufcr(sport, TXTL_DMA, RXTL_DMA);
1403
1404 /* set UCR1 */
1405 ucr1 = imx_uart_readl(sport, UCR1);
1406 ucr1 |= UCR1_RXDMAEN | UCR1_TXDMAEN | UCR1_ATDMAEN;
1407 imx_uart_writel(sport, ucr1, UCR1);
1408
1409 sport->dma_is_enabled = 1;
1410 }
1411
imx_uart_disable_dma(struct imx_port * sport)1412 static void imx_uart_disable_dma(struct imx_port *sport)
1413 {
1414 u32 ucr1;
1415
1416 /* clear UCR1 */
1417 ucr1 = imx_uart_readl(sport, UCR1);
1418 ucr1 &= ~(UCR1_RXDMAEN | UCR1_TXDMAEN | UCR1_ATDMAEN);
1419 imx_uart_writel(sport, ucr1, UCR1);
1420
1421 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1422
1423 sport->dma_is_enabled = 0;
1424 }
1425
1426 /* half the RX buffer size */
1427 #define CTSTL 16
1428
imx_uart_startup(struct uart_port * port)1429 static int imx_uart_startup(struct uart_port *port)
1430 {
1431 struct imx_port *sport = (struct imx_port *)port;
1432 int retval;
1433 unsigned long flags;
1434 int dma_is_inited = 0;
1435 u32 ucr1, ucr2, ucr3, ucr4;
1436
1437 retval = clk_prepare_enable(sport->clk_per);
1438 if (retval)
1439 return retval;
1440 retval = clk_prepare_enable(sport->clk_ipg);
1441 if (retval) {
1442 clk_disable_unprepare(sport->clk_per);
1443 return retval;
1444 }
1445
1446 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1447
1448 /* disable the DREN bit (Data Ready interrupt enable) before
1449 * requesting IRQs
1450 */
1451 ucr4 = imx_uart_readl(sport, UCR4);
1452
1453 /* set the trigger level for CTS */
1454 ucr4 &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF);
1455 ucr4 |= CTSTL << UCR4_CTSTL_SHF;
1456
1457 imx_uart_writel(sport, ucr4 & ~UCR4_DREN, UCR4);
1458
1459 /* Can we enable the DMA support? */
1460 if (!uart_console(port) && imx_uart_dma_init(sport) == 0)
1461 dma_is_inited = 1;
1462
1463 spin_lock_irqsave(&sport->port.lock, flags);
1464
1465 /* Reset fifo's and state machines */
1466 imx_uart_soft_reset(sport);
1467
1468 /*
1469 * Finally, clear and enable interrupts
1470 */
1471 imx_uart_writel(sport, USR1_RTSD | USR1_DTRD, USR1);
1472 imx_uart_writel(sport, USR2_ORE, USR2);
1473
1474 ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_RRDYEN;
1475 ucr1 |= UCR1_UARTEN;
1476 if (sport->have_rtscts)
1477 ucr1 |= UCR1_RTSDEN;
1478
1479 imx_uart_writel(sport, ucr1, UCR1);
1480
1481 ucr4 = imx_uart_readl(sport, UCR4) & ~(UCR4_OREN | UCR4_INVR);
1482 if (!dma_is_inited)
1483 ucr4 |= UCR4_OREN;
1484 if (sport->inverted_rx)
1485 ucr4 |= UCR4_INVR;
1486 imx_uart_writel(sport, ucr4, UCR4);
1487
1488 ucr3 = imx_uart_readl(sport, UCR3) & ~UCR3_INVT;
1489 /*
1490 * configure tx polarity before enabling tx
1491 */
1492 if (sport->inverted_tx)
1493 ucr3 |= UCR3_INVT;
1494
1495 if (!imx_uart_is_imx1(sport)) {
1496 ucr3 |= UCR3_DTRDEN | UCR3_RI | UCR3_DCD;
1497
1498 if (sport->dte_mode)
1499 /* disable broken interrupts */
1500 ucr3 &= ~(UCR3_RI | UCR3_DCD);
1501 }
1502 imx_uart_writel(sport, ucr3, UCR3);
1503
1504 ucr2 = imx_uart_readl(sport, UCR2) & ~UCR2_ATEN;
1505 ucr2 |= (UCR2_RXEN | UCR2_TXEN);
1506 if (!sport->have_rtscts)
1507 ucr2 |= UCR2_IRTS;
1508 /*
1509 * make sure the edge sensitive RTS-irq is disabled,
1510 * we're using RTSD instead.
1511 */
1512 if (!imx_uart_is_imx1(sport))
1513 ucr2 &= ~UCR2_RTSEN;
1514 imx_uart_writel(sport, ucr2, UCR2);
1515
1516 /*
1517 * Enable modem status interrupts
1518 */
1519 imx_uart_enable_ms(&sport->port);
1520
1521 if (dma_is_inited) {
1522 imx_uart_enable_dma(sport);
1523 imx_uart_start_rx_dma(sport);
1524 } else {
1525 ucr1 = imx_uart_readl(sport, UCR1);
1526 ucr1 |= UCR1_RRDYEN;
1527 imx_uart_writel(sport, ucr1, UCR1);
1528
1529 ucr2 = imx_uart_readl(sport, UCR2);
1530 ucr2 |= UCR2_ATEN;
1531 imx_uart_writel(sport, ucr2, UCR2);
1532 }
1533
1534 imx_uart_disable_loopback_rs485(sport);
1535
1536 spin_unlock_irqrestore(&sport->port.lock, flags);
1537
1538 return 0;
1539 }
1540
imx_uart_shutdown(struct uart_port * port)1541 static void imx_uart_shutdown(struct uart_port *port)
1542 {
1543 struct imx_port *sport = (struct imx_port *)port;
1544 unsigned long flags;
1545 u32 ucr1, ucr2, ucr4, uts;
1546
1547 if (sport->dma_is_enabled) {
1548 dmaengine_terminate_sync(sport->dma_chan_tx);
1549 if (sport->dma_is_txing) {
1550 dma_unmap_sg(sport->port.dev, &sport->tx_sgl[0],
1551 sport->dma_tx_nents, DMA_TO_DEVICE);
1552 sport->dma_is_txing = 0;
1553 }
1554 dmaengine_terminate_sync(sport->dma_chan_rx);
1555 if (sport->dma_is_rxing) {
1556 dma_unmap_sg(sport->port.dev, &sport->rx_sgl,
1557 1, DMA_FROM_DEVICE);
1558 sport->dma_is_rxing = 0;
1559 }
1560
1561 spin_lock_irqsave(&sport->port.lock, flags);
1562 imx_uart_stop_tx(port);
1563 imx_uart_stop_rx(port);
1564 imx_uart_disable_dma(sport);
1565 spin_unlock_irqrestore(&sport->port.lock, flags);
1566 imx_uart_dma_exit(sport);
1567 }
1568
1569 mctrl_gpio_disable_ms(sport->gpios);
1570
1571 spin_lock_irqsave(&sport->port.lock, flags);
1572 ucr2 = imx_uart_readl(sport, UCR2);
1573 ucr2 &= ~(UCR2_TXEN | UCR2_ATEN);
1574 imx_uart_writel(sport, ucr2, UCR2);
1575 spin_unlock_irqrestore(&sport->port.lock, flags);
1576
1577 /*
1578 * Stop our timer.
1579 */
1580 del_timer_sync(&sport->timer);
1581
1582 /*
1583 * Disable all interrupts, port and break condition.
1584 */
1585
1586 spin_lock_irqsave(&sport->port.lock, flags);
1587
1588 ucr1 = imx_uart_readl(sport, UCR1);
1589 ucr1 &= ~(UCR1_TRDYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_RXDMAEN |
1590 UCR1_ATDMAEN | UCR1_SNDBRK);
1591 /* See SER_RS485_ENABLED/UTS_LOOP comment in imx_uart_probe() */
1592 if (port->rs485.flags & SER_RS485_ENABLED &&
1593 port->rs485.flags & SER_RS485_RTS_ON_SEND &&
1594 sport->have_rtscts && !sport->have_rtsgpio) {
1595 uts = imx_uart_readl(sport, imx_uart_uts_reg(sport));
1596 uts |= UTS_LOOP;
1597 imx_uart_writel(sport, uts, imx_uart_uts_reg(sport));
1598 ucr1 |= UCR1_UARTEN;
1599 } else {
1600 ucr1 &= ~UCR1_UARTEN;
1601 }
1602 imx_uart_writel(sport, ucr1, UCR1);
1603
1604 ucr4 = imx_uart_readl(sport, UCR4);
1605 ucr4 &= ~UCR4_TCEN;
1606 imx_uart_writel(sport, ucr4, UCR4);
1607
1608 spin_unlock_irqrestore(&sport->port.lock, flags);
1609
1610 clk_disable_unprepare(sport->clk_per);
1611 clk_disable_unprepare(sport->clk_ipg);
1612 }
1613
1614 /* called with port.lock taken and irqs off */
imx_uart_flush_buffer(struct uart_port * port)1615 static void imx_uart_flush_buffer(struct uart_port *port)
1616 {
1617 struct imx_port *sport = (struct imx_port *)port;
1618 struct scatterlist *sgl = &sport->tx_sgl[0];
1619
1620 if (!sport->dma_chan_tx)
1621 return;
1622
1623 sport->tx_bytes = 0;
1624 dmaengine_terminate_all(sport->dma_chan_tx);
1625 if (sport->dma_is_txing) {
1626 u32 ucr1;
1627
1628 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents,
1629 DMA_TO_DEVICE);
1630 ucr1 = imx_uart_readl(sport, UCR1);
1631 ucr1 &= ~UCR1_TXDMAEN;
1632 imx_uart_writel(sport, ucr1, UCR1);
1633 sport->dma_is_txing = 0;
1634 }
1635
1636 imx_uart_soft_reset(sport);
1637
1638 }
1639
1640 static void
imx_uart_set_termios(struct uart_port * port,struct ktermios * termios,const struct ktermios * old)1641 imx_uart_set_termios(struct uart_port *port, struct ktermios *termios,
1642 const struct ktermios *old)
1643 {
1644 struct imx_port *sport = (struct imx_port *)port;
1645 unsigned long flags;
1646 u32 ucr2, old_ucr2, ufcr;
1647 unsigned int baud, quot;
1648 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
1649 unsigned long div;
1650 unsigned long num, denom, old_ubir, old_ubmr;
1651 uint64_t tdiv64;
1652
1653 /*
1654 * We only support CS7 and CS8.
1655 */
1656 while ((termios->c_cflag & CSIZE) != CS7 &&
1657 (termios->c_cflag & CSIZE) != CS8) {
1658 termios->c_cflag &= ~CSIZE;
1659 termios->c_cflag |= old_csize;
1660 old_csize = CS8;
1661 }
1662
1663 del_timer_sync(&sport->timer);
1664
1665 /*
1666 * Ask the core to calculate the divisor for us.
1667 */
1668 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
1669 quot = uart_get_divisor(port, baud);
1670
1671 spin_lock_irqsave(&sport->port.lock, flags);
1672
1673 /*
1674 * Read current UCR2 and save it for future use, then clear all the bits
1675 * except those we will or may need to preserve.
1676 */
1677 old_ucr2 = imx_uart_readl(sport, UCR2);
1678 ucr2 = old_ucr2 & (UCR2_TXEN | UCR2_RXEN | UCR2_ATEN | UCR2_CTS);
1679
1680 ucr2 |= UCR2_SRST | UCR2_IRTS;
1681 if ((termios->c_cflag & CSIZE) == CS8)
1682 ucr2 |= UCR2_WS;
1683
1684 if (!sport->have_rtscts)
1685 termios->c_cflag &= ~CRTSCTS;
1686
1687 if (port->rs485.flags & SER_RS485_ENABLED) {
1688 /*
1689 * RTS is mandatory for rs485 operation, so keep
1690 * it under manual control and keep transmitter
1691 * disabled.
1692 */
1693 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
1694 imx_uart_rts_active(sport, &ucr2);
1695 else
1696 imx_uart_rts_inactive(sport, &ucr2);
1697
1698 } else if (termios->c_cflag & CRTSCTS) {
1699 /*
1700 * Only let receiver control RTS output if we were not requested
1701 * to have RTS inactive (which then should take precedence).
1702 */
1703 if (ucr2 & UCR2_CTS)
1704 ucr2 |= UCR2_CTSC;
1705 }
1706
1707 if (termios->c_cflag & CRTSCTS)
1708 ucr2 &= ~UCR2_IRTS;
1709 if (termios->c_cflag & CSTOPB)
1710 ucr2 |= UCR2_STPB;
1711 if (termios->c_cflag & PARENB) {
1712 ucr2 |= UCR2_PREN;
1713 if (termios->c_cflag & PARODD)
1714 ucr2 |= UCR2_PROE;
1715 }
1716
1717 sport->port.read_status_mask = 0;
1718 if (termios->c_iflag & INPCK)
1719 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR);
1720 if (termios->c_iflag & (BRKINT | PARMRK))
1721 sport->port.read_status_mask |= URXD_BRK;
1722
1723 /*
1724 * Characters to ignore
1725 */
1726 sport->port.ignore_status_mask = 0;
1727 if (termios->c_iflag & IGNPAR)
1728 sport->port.ignore_status_mask |= URXD_PRERR | URXD_FRMERR;
1729 if (termios->c_iflag & IGNBRK) {
1730 sport->port.ignore_status_mask |= URXD_BRK;
1731 /*
1732 * If we're ignoring parity and break indicators,
1733 * ignore overruns too (for real raw support).
1734 */
1735 if (termios->c_iflag & IGNPAR)
1736 sport->port.ignore_status_mask |= URXD_OVRRUN;
1737 }
1738
1739 if ((termios->c_cflag & CREAD) == 0)
1740 sport->port.ignore_status_mask |= URXD_DUMMY_READ;
1741
1742 /*
1743 * Update the per-port timeout.
1744 */
1745 uart_update_timeout(port, termios->c_cflag, baud);
1746
1747 /* custom-baudrate handling */
1748 div = sport->port.uartclk / (baud * 16);
1749 if (baud == 38400 && quot != div)
1750 baud = sport->port.uartclk / (quot * 16);
1751
1752 div = sport->port.uartclk / (baud * 16);
1753 if (div > 7)
1754 div = 7;
1755 if (!div)
1756 div = 1;
1757
1758 rational_best_approximation(16 * div * baud, sport->port.uartclk,
1759 1 << 16, 1 << 16, &num, &denom);
1760
1761 tdiv64 = sport->port.uartclk;
1762 tdiv64 *= num;
1763 do_div(tdiv64, denom * 16 * div);
1764 tty_termios_encode_baud_rate(termios,
1765 (speed_t)tdiv64, (speed_t)tdiv64);
1766
1767 num -= 1;
1768 denom -= 1;
1769
1770 ufcr = imx_uart_readl(sport, UFCR);
1771 ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div);
1772 imx_uart_writel(sport, ufcr, UFCR);
1773
1774 /*
1775 * Two registers below should always be written both and in this
1776 * particular order. One consequence is that we need to check if any of
1777 * them changes and then update both. We do need the check for change
1778 * as even writing the same values seem to "restart"
1779 * transmission/receiving logic in the hardware, that leads to data
1780 * breakage even when rate doesn't in fact change. E.g., user switches
1781 * RTS/CTS handshake and suddenly gets broken bytes.
1782 */
1783 old_ubir = imx_uart_readl(sport, UBIR);
1784 old_ubmr = imx_uart_readl(sport, UBMR);
1785 if (old_ubir != num || old_ubmr != denom) {
1786 imx_uart_writel(sport, num, UBIR);
1787 imx_uart_writel(sport, denom, UBMR);
1788 }
1789
1790 if (!imx_uart_is_imx1(sport))
1791 imx_uart_writel(sport, sport->port.uartclk / div / 1000,
1792 IMX21_ONEMS);
1793
1794 imx_uart_writel(sport, ucr2, UCR2);
1795
1796 if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
1797 imx_uart_enable_ms(&sport->port);
1798
1799 spin_unlock_irqrestore(&sport->port.lock, flags);
1800 }
1801
imx_uart_type(struct uart_port * port)1802 static const char *imx_uart_type(struct uart_port *port)
1803 {
1804 return port->type == PORT_IMX ? "IMX" : NULL;
1805 }
1806
1807 /*
1808 * Configure/autoconfigure the port.
1809 */
imx_uart_config_port(struct uart_port * port,int flags)1810 static void imx_uart_config_port(struct uart_port *port, int flags)
1811 {
1812 if (flags & UART_CONFIG_TYPE)
1813 port->type = PORT_IMX;
1814 }
1815
1816 /*
1817 * Verify the new serial_struct (for TIOCSSERIAL).
1818 * The only change we allow are to the flags and type, and
1819 * even then only between PORT_IMX and PORT_UNKNOWN
1820 */
1821 static int
imx_uart_verify_port(struct uart_port * port,struct serial_struct * ser)1822 imx_uart_verify_port(struct uart_port *port, struct serial_struct *ser)
1823 {
1824 int ret = 0;
1825
1826 if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX)
1827 ret = -EINVAL;
1828 if (port->irq != ser->irq)
1829 ret = -EINVAL;
1830 if (ser->io_type != UPIO_MEM)
1831 ret = -EINVAL;
1832 if (port->uartclk / 16 != ser->baud_base)
1833 ret = -EINVAL;
1834 if (port->mapbase != (unsigned long)ser->iomem_base)
1835 ret = -EINVAL;
1836 if (port->iobase != ser->port)
1837 ret = -EINVAL;
1838 if (ser->hub6 != 0)
1839 ret = -EINVAL;
1840 return ret;
1841 }
1842
1843 #if defined(CONFIG_CONSOLE_POLL)
1844
imx_uart_poll_init(struct uart_port * port)1845 static int imx_uart_poll_init(struct uart_port *port)
1846 {
1847 struct imx_port *sport = (struct imx_port *)port;
1848 unsigned long flags;
1849 u32 ucr1, ucr2;
1850 int retval;
1851
1852 retval = clk_prepare_enable(sport->clk_ipg);
1853 if (retval)
1854 return retval;
1855 retval = clk_prepare_enable(sport->clk_per);
1856 if (retval)
1857 clk_disable_unprepare(sport->clk_ipg);
1858
1859 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1860
1861 spin_lock_irqsave(&sport->port.lock, flags);
1862
1863 /*
1864 * Be careful about the order of enabling bits here. First enable the
1865 * receiver (UARTEN + RXEN) and only then the corresponding irqs.
1866 * This prevents that a character that already sits in the RX fifo is
1867 * triggering an irq but the try to fetch it from there results in an
1868 * exception because UARTEN or RXEN is still off.
1869 */
1870 ucr1 = imx_uart_readl(sport, UCR1);
1871 ucr2 = imx_uart_readl(sport, UCR2);
1872
1873 if (imx_uart_is_imx1(sport))
1874 ucr1 |= IMX1_UCR1_UARTCLKEN;
1875
1876 ucr1 |= UCR1_UARTEN;
1877 ucr1 &= ~(UCR1_TRDYEN | UCR1_RTSDEN | UCR1_RRDYEN);
1878
1879 ucr2 |= UCR2_RXEN | UCR2_TXEN;
1880 ucr2 &= ~UCR2_ATEN;
1881
1882 imx_uart_writel(sport, ucr1, UCR1);
1883 imx_uart_writel(sport, ucr2, UCR2);
1884
1885 /* now enable irqs */
1886 imx_uart_writel(sport, ucr1 | UCR1_RRDYEN, UCR1);
1887 imx_uart_writel(sport, ucr2 | UCR2_ATEN, UCR2);
1888
1889 spin_unlock_irqrestore(&sport->port.lock, flags);
1890
1891 return 0;
1892 }
1893
imx_uart_poll_get_char(struct uart_port * port)1894 static int imx_uart_poll_get_char(struct uart_port *port)
1895 {
1896 struct imx_port *sport = (struct imx_port *)port;
1897 if (!(imx_uart_readl(sport, USR2) & USR2_RDR))
1898 return NO_POLL_CHAR;
1899
1900 return imx_uart_readl(sport, URXD0) & URXD_RX_DATA;
1901 }
1902
imx_uart_poll_put_char(struct uart_port * port,unsigned char c)1903 static void imx_uart_poll_put_char(struct uart_port *port, unsigned char c)
1904 {
1905 struct imx_port *sport = (struct imx_port *)port;
1906 unsigned int status;
1907
1908 /* drain */
1909 do {
1910 status = imx_uart_readl(sport, USR1);
1911 } while (~status & USR1_TRDY);
1912
1913 /* write */
1914 imx_uart_writel(sport, c, URTX0);
1915
1916 /* flush */
1917 do {
1918 status = imx_uart_readl(sport, USR2);
1919 } while (~status & USR2_TXDC);
1920 }
1921 #endif
1922
1923 /* called with port.lock taken and irqs off or from .probe without locking */
imx_uart_rs485_config(struct uart_port * port,struct ktermios * termios,struct serial_rs485 * rs485conf)1924 static int imx_uart_rs485_config(struct uart_port *port, struct ktermios *termios,
1925 struct serial_rs485 *rs485conf)
1926 {
1927 struct imx_port *sport = (struct imx_port *)port;
1928 u32 ucr2;
1929
1930 if (rs485conf->flags & SER_RS485_ENABLED) {
1931 /* Enable receiver if low-active RTS signal is requested */
1932 if (sport->have_rtscts && !sport->have_rtsgpio &&
1933 !(rs485conf->flags & SER_RS485_RTS_ON_SEND))
1934 rs485conf->flags |= SER_RS485_RX_DURING_TX;
1935
1936 /* disable transmitter */
1937 ucr2 = imx_uart_readl(sport, UCR2);
1938 if (rs485conf->flags & SER_RS485_RTS_AFTER_SEND)
1939 imx_uart_rts_active(sport, &ucr2);
1940 else
1941 imx_uart_rts_inactive(sport, &ucr2);
1942 imx_uart_writel(sport, ucr2, UCR2);
1943 }
1944
1945 /* Make sure Rx is enabled in case Tx is active with Rx disabled */
1946 if (!(rs485conf->flags & SER_RS485_ENABLED) ||
1947 rs485conf->flags & SER_RS485_RX_DURING_TX)
1948 imx_uart_start_rx(port);
1949
1950 if (port->rs485_rx_during_tx_gpio)
1951 gpiod_set_value_cansleep(port->rs485_rx_during_tx_gpio,
1952 !!(rs485conf->flags & SER_RS485_RX_DURING_TX));
1953
1954 return 0;
1955 }
1956
1957 static const struct uart_ops imx_uart_pops = {
1958 .tx_empty = imx_uart_tx_empty,
1959 .set_mctrl = imx_uart_set_mctrl,
1960 .get_mctrl = imx_uart_get_mctrl,
1961 .stop_tx = imx_uart_stop_tx,
1962 .start_tx = imx_uart_start_tx,
1963 .stop_rx = imx_uart_stop_rx,
1964 .enable_ms = imx_uart_enable_ms,
1965 .break_ctl = imx_uart_break_ctl,
1966 .startup = imx_uart_startup,
1967 .shutdown = imx_uart_shutdown,
1968 .flush_buffer = imx_uart_flush_buffer,
1969 .set_termios = imx_uart_set_termios,
1970 .type = imx_uart_type,
1971 .config_port = imx_uart_config_port,
1972 .verify_port = imx_uart_verify_port,
1973 #if defined(CONFIG_CONSOLE_POLL)
1974 .poll_init = imx_uart_poll_init,
1975 .poll_get_char = imx_uart_poll_get_char,
1976 .poll_put_char = imx_uart_poll_put_char,
1977 #endif
1978 };
1979
1980 static struct imx_port *imx_uart_ports[UART_NR];
1981
1982 #if IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE)
imx_uart_console_putchar(struct uart_port * port,unsigned char ch)1983 static void imx_uart_console_putchar(struct uart_port *port, unsigned char ch)
1984 {
1985 struct imx_port *sport = (struct imx_port *)port;
1986
1987 while (imx_uart_readl(sport, imx_uart_uts_reg(sport)) & UTS_TXFULL)
1988 barrier();
1989
1990 imx_uart_writel(sport, ch, URTX0);
1991 }
1992
1993 /*
1994 * Interrupts are disabled on entering
1995 */
1996 static void
imx_uart_console_write(struct console * co,const char * s,unsigned int count)1997 imx_uart_console_write(struct console *co, const char *s, unsigned int count)
1998 {
1999 struct imx_port *sport = imx_uart_ports[co->index];
2000 struct imx_port_ucrs old_ucr;
2001 unsigned long flags;
2002 unsigned int ucr1;
2003 int locked = 1;
2004
2005 if (sport->port.sysrq)
2006 locked = 0;
2007 else if (oops_in_progress)
2008 locked = spin_trylock_irqsave(&sport->port.lock, flags);
2009 else
2010 spin_lock_irqsave(&sport->port.lock, flags);
2011
2012 /*
2013 * First, save UCR1/2/3 and then disable interrupts
2014 */
2015 imx_uart_ucrs_save(sport, &old_ucr);
2016 ucr1 = old_ucr.ucr1;
2017
2018 if (imx_uart_is_imx1(sport))
2019 ucr1 |= IMX1_UCR1_UARTCLKEN;
2020 ucr1 |= UCR1_UARTEN;
2021 ucr1 &= ~(UCR1_TRDYEN | UCR1_RRDYEN | UCR1_RTSDEN);
2022
2023 imx_uart_writel(sport, ucr1, UCR1);
2024
2025 imx_uart_writel(sport, old_ucr.ucr2 | UCR2_TXEN, UCR2);
2026
2027 uart_console_write(&sport->port, s, count, imx_uart_console_putchar);
2028
2029 /*
2030 * Finally, wait for transmitter to become empty
2031 * and restore UCR1/2/3
2032 */
2033 while (!(imx_uart_readl(sport, USR2) & USR2_TXDC));
2034
2035 imx_uart_ucrs_restore(sport, &old_ucr);
2036
2037 if (locked)
2038 spin_unlock_irqrestore(&sport->port.lock, flags);
2039 }
2040
2041 /*
2042 * If the port was already initialised (eg, by a boot loader),
2043 * try to determine the current setup.
2044 */
2045 static void
imx_uart_console_get_options(struct imx_port * sport,int * baud,int * parity,int * bits)2046 imx_uart_console_get_options(struct imx_port *sport, int *baud,
2047 int *parity, int *bits)
2048 {
2049
2050 if (imx_uart_readl(sport, UCR1) & UCR1_UARTEN) {
2051 /* ok, the port was enabled */
2052 unsigned int ucr2, ubir, ubmr, uartclk;
2053 unsigned int baud_raw;
2054 unsigned int ucfr_rfdiv;
2055
2056 ucr2 = imx_uart_readl(sport, UCR2);
2057
2058 *parity = 'n';
2059 if (ucr2 & UCR2_PREN) {
2060 if (ucr2 & UCR2_PROE)
2061 *parity = 'o';
2062 else
2063 *parity = 'e';
2064 }
2065
2066 if (ucr2 & UCR2_WS)
2067 *bits = 8;
2068 else
2069 *bits = 7;
2070
2071 ubir = imx_uart_readl(sport, UBIR) & 0xffff;
2072 ubmr = imx_uart_readl(sport, UBMR) & 0xffff;
2073
2074 ucfr_rfdiv = (imx_uart_readl(sport, UFCR) & UFCR_RFDIV) >> 7;
2075 if (ucfr_rfdiv == 6)
2076 ucfr_rfdiv = 7;
2077 else
2078 ucfr_rfdiv = 6 - ucfr_rfdiv;
2079
2080 uartclk = clk_get_rate(sport->clk_per);
2081 uartclk /= ucfr_rfdiv;
2082
2083 { /*
2084 * The next code provides exact computation of
2085 * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1))
2086 * without need of float support or long long division,
2087 * which would be required to prevent 32bit arithmetic overflow
2088 */
2089 unsigned int mul = ubir + 1;
2090 unsigned int div = 16 * (ubmr + 1);
2091 unsigned int rem = uartclk % div;
2092
2093 baud_raw = (uartclk / div) * mul;
2094 baud_raw += (rem * mul + div / 2) / div;
2095 *baud = (baud_raw + 50) / 100 * 100;
2096 }
2097
2098 if (*baud != baud_raw)
2099 dev_info(sport->port.dev, "Console IMX rounded baud rate from %d to %d\n",
2100 baud_raw, *baud);
2101 }
2102 }
2103
2104 static int
imx_uart_console_setup(struct console * co,char * options)2105 imx_uart_console_setup(struct console *co, char *options)
2106 {
2107 struct imx_port *sport;
2108 int baud = 9600;
2109 int bits = 8;
2110 int parity = 'n';
2111 int flow = 'n';
2112 int retval;
2113
2114 /*
2115 * Check whether an invalid uart number has been specified, and
2116 * if so, search for the first available port that does have
2117 * console support.
2118 */
2119 if (co->index == -1 || co->index >= ARRAY_SIZE(imx_uart_ports))
2120 co->index = 0;
2121 sport = imx_uart_ports[co->index];
2122 if (sport == NULL)
2123 return -ENODEV;
2124
2125 /* For setting the registers, we only need to enable the ipg clock. */
2126 retval = clk_prepare_enable(sport->clk_ipg);
2127 if (retval)
2128 goto error_console;
2129
2130 if (options)
2131 uart_parse_options(options, &baud, &parity, &bits, &flow);
2132 else
2133 imx_uart_console_get_options(sport, &baud, &parity, &bits);
2134
2135 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
2136
2137 retval = uart_set_options(&sport->port, co, baud, parity, bits, flow);
2138
2139 if (retval) {
2140 clk_disable_unprepare(sport->clk_ipg);
2141 goto error_console;
2142 }
2143
2144 retval = clk_prepare_enable(sport->clk_per);
2145 if (retval)
2146 clk_disable_unprepare(sport->clk_ipg);
2147
2148 error_console:
2149 return retval;
2150 }
2151
2152 static int
imx_uart_console_exit(struct console * co)2153 imx_uart_console_exit(struct console *co)
2154 {
2155 struct imx_port *sport = imx_uart_ports[co->index];
2156
2157 clk_disable_unprepare(sport->clk_per);
2158 clk_disable_unprepare(sport->clk_ipg);
2159
2160 return 0;
2161 }
2162
2163 static struct uart_driver imx_uart_uart_driver;
2164 static struct console imx_uart_console = {
2165 .name = DEV_NAME,
2166 .write = imx_uart_console_write,
2167 .device = uart_console_device,
2168 .setup = imx_uart_console_setup,
2169 .exit = imx_uart_console_exit,
2170 .flags = CON_PRINTBUFFER,
2171 .index = -1,
2172 .data = &imx_uart_uart_driver,
2173 };
2174
2175 #define IMX_CONSOLE &imx_uart_console
2176
2177 #else
2178 #define IMX_CONSOLE NULL
2179 #endif
2180
2181 static struct uart_driver imx_uart_uart_driver = {
2182 .owner = THIS_MODULE,
2183 .driver_name = DRIVER_NAME,
2184 .dev_name = DEV_NAME,
2185 .major = SERIAL_IMX_MAJOR,
2186 .minor = MINOR_START,
2187 .nr = ARRAY_SIZE(imx_uart_ports),
2188 .cons = IMX_CONSOLE,
2189 };
2190
imx_trigger_start_tx(struct hrtimer * t)2191 static enum hrtimer_restart imx_trigger_start_tx(struct hrtimer *t)
2192 {
2193 struct imx_port *sport = container_of(t, struct imx_port, trigger_start_tx);
2194 unsigned long flags;
2195
2196 spin_lock_irqsave(&sport->port.lock, flags);
2197 if (sport->tx_state == WAIT_AFTER_RTS)
2198 imx_uart_start_tx(&sport->port);
2199 spin_unlock_irqrestore(&sport->port.lock, flags);
2200
2201 return HRTIMER_NORESTART;
2202 }
2203
imx_trigger_stop_tx(struct hrtimer * t)2204 static enum hrtimer_restart imx_trigger_stop_tx(struct hrtimer *t)
2205 {
2206 struct imx_port *sport = container_of(t, struct imx_port, trigger_stop_tx);
2207 unsigned long flags;
2208
2209 spin_lock_irqsave(&sport->port.lock, flags);
2210 if (sport->tx_state == WAIT_AFTER_SEND)
2211 imx_uart_stop_tx(&sport->port);
2212 spin_unlock_irqrestore(&sport->port.lock, flags);
2213
2214 return HRTIMER_NORESTART;
2215 }
2216
2217 static const struct serial_rs485 imx_no_rs485 = {}; /* No RS485 if no RTS */
2218 static const struct serial_rs485 imx_rs485_supported = {
2219 .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | SER_RS485_RTS_AFTER_SEND |
2220 SER_RS485_RX_DURING_TX,
2221 .delay_rts_before_send = 1,
2222 .delay_rts_after_send = 1,
2223 };
2224
2225 /* Default RX DMA buffer configuration */
2226 #define RX_DMA_PERIODS 16
2227 #define RX_DMA_PERIOD_LEN (PAGE_SIZE / 4)
2228
imx_uart_probe(struct platform_device * pdev)2229 static int imx_uart_probe(struct platform_device *pdev)
2230 {
2231 struct device_node *np = pdev->dev.of_node;
2232 struct imx_port *sport;
2233 void __iomem *base;
2234 u32 dma_buf_conf[2];
2235 int ret = 0;
2236 u32 ucr1, ucr2, uts;
2237 struct resource *res;
2238 int txirq, rxirq, rtsirq;
2239
2240 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
2241 if (!sport)
2242 return -ENOMEM;
2243
2244 sport->devdata = of_device_get_match_data(&pdev->dev);
2245
2246 ret = of_alias_get_id(np, "serial");
2247 if (ret < 0) {
2248 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
2249 return ret;
2250 }
2251 sport->port.line = ret;
2252
2253 sport->have_rtscts = of_property_read_bool(np, "uart-has-rtscts") ||
2254 of_property_read_bool(np, "fsl,uart-has-rtscts"); /* deprecated */
2255
2256 sport->dte_mode = of_property_read_bool(np, "fsl,dte-mode");
2257
2258 sport->have_rtsgpio = of_property_present(np, "rts-gpios");
2259
2260 sport->inverted_tx = of_property_read_bool(np, "fsl,inverted-tx");
2261
2262 sport->inverted_rx = of_property_read_bool(np, "fsl,inverted-rx");
2263
2264 if (!of_property_read_u32_array(np, "fsl,dma-info", dma_buf_conf, 2)) {
2265 sport->rx_period_length = dma_buf_conf[0];
2266 sport->rx_periods = dma_buf_conf[1];
2267 } else {
2268 sport->rx_period_length = RX_DMA_PERIOD_LEN;
2269 sport->rx_periods = RX_DMA_PERIODS;
2270 }
2271
2272 if (sport->port.line >= ARRAY_SIZE(imx_uart_ports)) {
2273 dev_err(&pdev->dev, "serial%d out of range\n",
2274 sport->port.line);
2275 return -EINVAL;
2276 }
2277
2278 base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
2279 if (IS_ERR(base))
2280 return PTR_ERR(base);
2281
2282 rxirq = platform_get_irq(pdev, 0);
2283 if (rxirq < 0)
2284 return rxirq;
2285 txirq = platform_get_irq_optional(pdev, 1);
2286 rtsirq = platform_get_irq_optional(pdev, 2);
2287
2288 sport->port.dev = &pdev->dev;
2289 sport->port.mapbase = res->start;
2290 sport->port.membase = base;
2291 sport->port.type = PORT_IMX;
2292 sport->port.iotype = UPIO_MEM;
2293 sport->port.irq = rxirq;
2294 sport->port.fifosize = 32;
2295 sport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE);
2296 sport->port.ops = &imx_uart_pops;
2297 sport->port.rs485_config = imx_uart_rs485_config;
2298 /* RTS is required to control the RS485 transmitter */
2299 if (sport->have_rtscts || sport->have_rtsgpio)
2300 sport->port.rs485_supported = imx_rs485_supported;
2301 else
2302 sport->port.rs485_supported = imx_no_rs485;
2303 sport->port.flags = UPF_BOOT_AUTOCONF;
2304 timer_setup(&sport->timer, imx_uart_timeout, 0);
2305
2306 sport->gpios = mctrl_gpio_init(&sport->port, 0);
2307 if (IS_ERR(sport->gpios))
2308 return PTR_ERR(sport->gpios);
2309
2310 sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
2311 if (IS_ERR(sport->clk_ipg)) {
2312 ret = PTR_ERR(sport->clk_ipg);
2313 dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret);
2314 return ret;
2315 }
2316
2317 sport->clk_per = devm_clk_get(&pdev->dev, "per");
2318 if (IS_ERR(sport->clk_per)) {
2319 ret = PTR_ERR(sport->clk_per);
2320 dev_err(&pdev->dev, "failed to get per clk: %d\n", ret);
2321 return ret;
2322 }
2323
2324 sport->port.uartclk = clk_get_rate(sport->clk_per);
2325
2326 /* For register access, we only need to enable the ipg clock. */
2327 ret = clk_prepare_enable(sport->clk_ipg);
2328 if (ret) {
2329 dev_err(&pdev->dev, "failed to enable per clk: %d\n", ret);
2330 return ret;
2331 }
2332
2333 ret = uart_get_rs485_mode(&sport->port);
2334 if (ret) {
2335 clk_disable_unprepare(sport->clk_ipg);
2336 return ret;
2337 }
2338
2339 if (sport->port.rs485.flags & SER_RS485_ENABLED &&
2340 (!sport->have_rtscts && !sport->have_rtsgpio))
2341 dev_err(&pdev->dev, "no RTS control, disabling rs485\n");
2342
2343 /*
2344 * If using the i.MX UART RTS/CTS control then the RTS (CTS_B)
2345 * signal cannot be set low during transmission in case the
2346 * receiver is off (limitation of the i.MX UART IP).
2347 */
2348 if (sport->port.rs485.flags & SER_RS485_ENABLED &&
2349 sport->have_rtscts && !sport->have_rtsgpio &&
2350 (!(sport->port.rs485.flags & SER_RS485_RTS_ON_SEND) &&
2351 !(sport->port.rs485.flags & SER_RS485_RX_DURING_TX)))
2352 dev_err(&pdev->dev,
2353 "low-active RTS not possible when receiver is off, enabling receiver\n");
2354
2355 /* Disable interrupts before requesting them */
2356 ucr1 = imx_uart_readl(sport, UCR1);
2357 ucr1 &= ~(UCR1_ADEN | UCR1_TRDYEN | UCR1_IDEN | UCR1_RRDYEN | UCR1_RTSDEN);
2358 imx_uart_writel(sport, ucr1, UCR1);
2359
2360 /* Disable Ageing Timer interrupt */
2361 ucr2 = imx_uart_readl(sport, UCR2);
2362 ucr2 &= ~UCR2_ATEN;
2363 imx_uart_writel(sport, ucr2, UCR2);
2364
2365 /*
2366 * In case RS485 is enabled without GPIO RTS control, the UART IP
2367 * is used to control CTS signal. Keep both the UART and Receiver
2368 * enabled, otherwise the UART IP pulls CTS signal always HIGH no
2369 * matter how the UCR2 CTSC and CTS bits are set. To prevent any
2370 * data from being fed into the RX FIFO, enable loopback mode in
2371 * UTS register, which disconnects the RX path from external RXD
2372 * pin and connects it to the Transceiver, which is disabled, so
2373 * no data can be fed to the RX FIFO that way.
2374 */
2375 if (sport->port.rs485.flags & SER_RS485_ENABLED &&
2376 sport->have_rtscts && !sport->have_rtsgpio) {
2377 uts = imx_uart_readl(sport, imx_uart_uts_reg(sport));
2378 uts |= UTS_LOOP;
2379 imx_uart_writel(sport, uts, imx_uart_uts_reg(sport));
2380
2381 ucr1 = imx_uart_readl(sport, UCR1);
2382 ucr1 |= UCR1_UARTEN;
2383 imx_uart_writel(sport, ucr1, UCR1);
2384
2385 ucr2 = imx_uart_readl(sport, UCR2);
2386 ucr2 |= UCR2_RXEN;
2387 imx_uart_writel(sport, ucr2, UCR2);
2388 }
2389
2390 if (!imx_uart_is_imx1(sport) && sport->dte_mode) {
2391 /*
2392 * The DCEDTE bit changes the direction of DSR, DCD, DTR and RI
2393 * and influences if UCR3_RI and UCR3_DCD changes the level of RI
2394 * and DCD (when they are outputs) or enables the respective
2395 * irqs. So set this bit early, i.e. before requesting irqs.
2396 */
2397 u32 ufcr = imx_uart_readl(sport, UFCR);
2398 if (!(ufcr & UFCR_DCEDTE))
2399 imx_uart_writel(sport, ufcr | UFCR_DCEDTE, UFCR);
2400
2401 /*
2402 * Disable UCR3_RI and UCR3_DCD irqs. They are also not
2403 * enabled later because they cannot be cleared
2404 * (confirmed on i.MX25) which makes them unusable.
2405 */
2406 imx_uart_writel(sport,
2407 IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP | UCR3_DSR,
2408 UCR3);
2409
2410 } else {
2411 u32 ucr3 = UCR3_DSR;
2412 u32 ufcr = imx_uart_readl(sport, UFCR);
2413 if (ufcr & UFCR_DCEDTE)
2414 imx_uart_writel(sport, ufcr & ~UFCR_DCEDTE, UFCR);
2415
2416 if (!imx_uart_is_imx1(sport))
2417 ucr3 |= IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP;
2418 imx_uart_writel(sport, ucr3, UCR3);
2419 }
2420
2421 clk_disable_unprepare(sport->clk_ipg);
2422
2423 hrtimer_init(&sport->trigger_start_tx, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
2424 hrtimer_init(&sport->trigger_stop_tx, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
2425 sport->trigger_start_tx.function = imx_trigger_start_tx;
2426 sport->trigger_stop_tx.function = imx_trigger_stop_tx;
2427
2428 /*
2429 * Allocate the IRQ(s) i.MX1 has three interrupts whereas later
2430 * chips only have one interrupt.
2431 */
2432 if (txirq > 0) {
2433 ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_rxint, 0,
2434 dev_name(&pdev->dev), sport);
2435 if (ret) {
2436 dev_err(&pdev->dev, "failed to request rx irq: %d\n",
2437 ret);
2438 return ret;
2439 }
2440
2441 ret = devm_request_irq(&pdev->dev, txirq, imx_uart_txint, 0,
2442 dev_name(&pdev->dev), sport);
2443 if (ret) {
2444 dev_err(&pdev->dev, "failed to request tx irq: %d\n",
2445 ret);
2446 return ret;
2447 }
2448
2449 ret = devm_request_irq(&pdev->dev, rtsirq, imx_uart_rtsint, 0,
2450 dev_name(&pdev->dev), sport);
2451 if (ret) {
2452 dev_err(&pdev->dev, "failed to request rts irq: %d\n",
2453 ret);
2454 return ret;
2455 }
2456 } else {
2457 ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_int, 0,
2458 dev_name(&pdev->dev), sport);
2459 if (ret) {
2460 dev_err(&pdev->dev, "failed to request irq: %d\n", ret);
2461 return ret;
2462 }
2463 }
2464
2465 imx_uart_ports[sport->port.line] = sport;
2466
2467 platform_set_drvdata(pdev, sport);
2468
2469 return uart_add_one_port(&imx_uart_uart_driver, &sport->port);
2470 }
2471
imx_uart_remove(struct platform_device * pdev)2472 static int imx_uart_remove(struct platform_device *pdev)
2473 {
2474 struct imx_port *sport = platform_get_drvdata(pdev);
2475
2476 uart_remove_one_port(&imx_uart_uart_driver, &sport->port);
2477
2478 return 0;
2479 }
2480
imx_uart_restore_context(struct imx_port * sport)2481 static void imx_uart_restore_context(struct imx_port *sport)
2482 {
2483 unsigned long flags;
2484
2485 spin_lock_irqsave(&sport->port.lock, flags);
2486 if (!sport->context_saved) {
2487 spin_unlock_irqrestore(&sport->port.lock, flags);
2488 return;
2489 }
2490
2491 imx_uart_writel(sport, sport->saved_reg[4], UFCR);
2492 imx_uart_writel(sport, sport->saved_reg[5], UESC);
2493 imx_uart_writel(sport, sport->saved_reg[6], UTIM);
2494 imx_uart_writel(sport, sport->saved_reg[7], UBIR);
2495 imx_uart_writel(sport, sport->saved_reg[8], UBMR);
2496 imx_uart_writel(sport, sport->saved_reg[9], IMX21_UTS);
2497 imx_uart_writel(sport, sport->saved_reg[0], UCR1);
2498 imx_uart_writel(sport, sport->saved_reg[1] | UCR2_SRST, UCR2);
2499 imx_uart_writel(sport, sport->saved_reg[2], UCR3);
2500 imx_uart_writel(sport, sport->saved_reg[3], UCR4);
2501 sport->context_saved = false;
2502 spin_unlock_irqrestore(&sport->port.lock, flags);
2503 }
2504
imx_uart_save_context(struct imx_port * sport)2505 static void imx_uart_save_context(struct imx_port *sport)
2506 {
2507 unsigned long flags;
2508
2509 /* Save necessary regs */
2510 spin_lock_irqsave(&sport->port.lock, flags);
2511 sport->saved_reg[0] = imx_uart_readl(sport, UCR1);
2512 sport->saved_reg[1] = imx_uart_readl(sport, UCR2);
2513 sport->saved_reg[2] = imx_uart_readl(sport, UCR3);
2514 sport->saved_reg[3] = imx_uart_readl(sport, UCR4);
2515 sport->saved_reg[4] = imx_uart_readl(sport, UFCR);
2516 sport->saved_reg[5] = imx_uart_readl(sport, UESC);
2517 sport->saved_reg[6] = imx_uart_readl(sport, UTIM);
2518 sport->saved_reg[7] = imx_uart_readl(sport, UBIR);
2519 sport->saved_reg[8] = imx_uart_readl(sport, UBMR);
2520 sport->saved_reg[9] = imx_uart_readl(sport, IMX21_UTS);
2521 sport->context_saved = true;
2522 spin_unlock_irqrestore(&sport->port.lock, flags);
2523 }
2524
imx_uart_enable_wakeup(struct imx_port * sport,bool on)2525 static void imx_uart_enable_wakeup(struct imx_port *sport, bool on)
2526 {
2527 u32 ucr3;
2528
2529 ucr3 = imx_uart_readl(sport, UCR3);
2530 if (on) {
2531 imx_uart_writel(sport, USR1_AWAKE, USR1);
2532 ucr3 |= UCR3_AWAKEN;
2533 } else {
2534 ucr3 &= ~UCR3_AWAKEN;
2535 }
2536 imx_uart_writel(sport, ucr3, UCR3);
2537
2538 if (sport->have_rtscts) {
2539 u32 ucr1 = imx_uart_readl(sport, UCR1);
2540 if (on) {
2541 imx_uart_writel(sport, USR1_RTSD, USR1);
2542 ucr1 |= UCR1_RTSDEN;
2543 } else {
2544 ucr1 &= ~UCR1_RTSDEN;
2545 }
2546 imx_uart_writel(sport, ucr1, UCR1);
2547 }
2548 }
2549
imx_uart_suspend_noirq(struct device * dev)2550 static int imx_uart_suspend_noirq(struct device *dev)
2551 {
2552 struct imx_port *sport = dev_get_drvdata(dev);
2553
2554 imx_uart_save_context(sport);
2555
2556 clk_disable(sport->clk_ipg);
2557
2558 pinctrl_pm_select_sleep_state(dev);
2559
2560 return 0;
2561 }
2562
imx_uart_resume_noirq(struct device * dev)2563 static int imx_uart_resume_noirq(struct device *dev)
2564 {
2565 struct imx_port *sport = dev_get_drvdata(dev);
2566 int ret;
2567
2568 pinctrl_pm_select_default_state(dev);
2569
2570 ret = clk_enable(sport->clk_ipg);
2571 if (ret)
2572 return ret;
2573
2574 imx_uart_restore_context(sport);
2575
2576 return 0;
2577 }
2578
imx_uart_suspend(struct device * dev)2579 static int imx_uart_suspend(struct device *dev)
2580 {
2581 struct imx_port *sport = dev_get_drvdata(dev);
2582 int ret;
2583
2584 uart_suspend_port(&imx_uart_uart_driver, &sport->port);
2585 disable_irq(sport->port.irq);
2586
2587 ret = clk_prepare_enable(sport->clk_ipg);
2588 if (ret)
2589 return ret;
2590
2591 /* enable wakeup from i.MX UART */
2592 imx_uart_enable_wakeup(sport, true);
2593
2594 return 0;
2595 }
2596
imx_uart_resume(struct device * dev)2597 static int imx_uart_resume(struct device *dev)
2598 {
2599 struct imx_port *sport = dev_get_drvdata(dev);
2600
2601 /* disable wakeup from i.MX UART */
2602 imx_uart_enable_wakeup(sport, false);
2603
2604 uart_resume_port(&imx_uart_uart_driver, &sport->port);
2605 enable_irq(sport->port.irq);
2606
2607 clk_disable_unprepare(sport->clk_ipg);
2608
2609 return 0;
2610 }
2611
imx_uart_freeze(struct device * dev)2612 static int imx_uart_freeze(struct device *dev)
2613 {
2614 struct imx_port *sport = dev_get_drvdata(dev);
2615
2616 uart_suspend_port(&imx_uart_uart_driver, &sport->port);
2617
2618 return clk_prepare_enable(sport->clk_ipg);
2619 }
2620
imx_uart_thaw(struct device * dev)2621 static int imx_uart_thaw(struct device *dev)
2622 {
2623 struct imx_port *sport = dev_get_drvdata(dev);
2624
2625 uart_resume_port(&imx_uart_uart_driver, &sport->port);
2626
2627 clk_disable_unprepare(sport->clk_ipg);
2628
2629 return 0;
2630 }
2631
2632 static const struct dev_pm_ops imx_uart_pm_ops = {
2633 .suspend_noirq = imx_uart_suspend_noirq,
2634 .resume_noirq = imx_uart_resume_noirq,
2635 .freeze_noirq = imx_uart_suspend_noirq,
2636 .thaw_noirq = imx_uart_resume_noirq,
2637 .restore_noirq = imx_uart_resume_noirq,
2638 .suspend = imx_uart_suspend,
2639 .resume = imx_uart_resume,
2640 .freeze = imx_uart_freeze,
2641 .thaw = imx_uart_thaw,
2642 .restore = imx_uart_thaw,
2643 };
2644
2645 static struct platform_driver imx_uart_platform_driver = {
2646 .probe = imx_uart_probe,
2647 .remove = imx_uart_remove,
2648
2649 .driver = {
2650 .name = "imx-uart",
2651 .of_match_table = imx_uart_dt_ids,
2652 .pm = &imx_uart_pm_ops,
2653 },
2654 };
2655
imx_uart_init(void)2656 static int __init imx_uart_init(void)
2657 {
2658 int ret = uart_register_driver(&imx_uart_uart_driver);
2659
2660 if (ret)
2661 return ret;
2662
2663 ret = platform_driver_register(&imx_uart_platform_driver);
2664 if (ret != 0)
2665 uart_unregister_driver(&imx_uart_uart_driver);
2666
2667 return ret;
2668 }
2669
imx_uart_exit(void)2670 static void __exit imx_uart_exit(void)
2671 {
2672 platform_driver_unregister(&imx_uart_platform_driver);
2673 uart_unregister_driver(&imx_uart_uart_driver);
2674 }
2675
2676 module_init(imx_uart_init);
2677 module_exit(imx_uart_exit);
2678
2679 MODULE_AUTHOR("Sascha Hauer");
2680 MODULE_DESCRIPTION("IMX generic serial port driver");
2681 MODULE_LICENSE("GPL");
2682 MODULE_ALIAS("platform:imx-uart");
2683
