1 /*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23 #include <linux/firmware.h>
24 #include <linux/slab.h>
25 #include <linux/module.h>
26 #include <linux/pci.h>
27
28 #include <drm/amdgpu_drm.h>
29
30 #include "amdgpu.h"
31 #include "amdgpu_atombios.h"
32 #include "amdgpu_ih.h"
33 #include "amdgpu_uvd.h"
34 #include "amdgpu_vce.h"
35 #include "amdgpu_ucode.h"
36 #include "amdgpu_psp.h"
37 #include "atom.h"
38 #include "amd_pcie.h"
39
40 #include "gc/gc_10_1_0_offset.h"
41 #include "gc/gc_10_1_0_sh_mask.h"
42 #include "mp/mp_11_0_offset.h"
43
44 #include "soc15.h"
45 #include "soc15_common.h"
46 #include "gmc_v10_0.h"
47 #include "gfxhub_v2_0.h"
48 #include "mmhub_v2_0.h"
49 #include "nbio_v2_3.h"
50 #include "nbio_v7_2.h"
51 #include "hdp_v5_0.h"
52 #include "nv.h"
53 #include "navi10_ih.h"
54 #include "gfx_v10_0.h"
55 #include "sdma_v5_0.h"
56 #include "sdma_v5_2.h"
57 #include "vcn_v2_0.h"
58 #include "jpeg_v2_0.h"
59 #include "vcn_v3_0.h"
60 #include "jpeg_v3_0.h"
61 #include "amdgpu_vkms.h"
62 #include "mes_v10_1.h"
63 #include "mxgpu_nv.h"
64 #include "smuio_v11_0.h"
65 #include "smuio_v11_0_6.h"
66
67 static const struct amd_ip_funcs nv_common_ip_funcs;
68
69 /* Navi */
70 static const struct amdgpu_video_codec_info nv_video_codecs_encode_array[] = {
71 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)},
72 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)},
73 };
74
75 static const struct amdgpu_video_codecs nv_video_codecs_encode = {
76 .codec_count = ARRAY_SIZE(nv_video_codecs_encode_array),
77 .codec_array = nv_video_codecs_encode_array,
78 };
79
80 /* Navi1x */
81 static const struct amdgpu_video_codec_info nv_video_codecs_decode_array[] = {
82 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)},
83 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)},
84 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
85 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)},
86 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
87 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
88 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
89 };
90
91 static const struct amdgpu_video_codecs nv_video_codecs_decode = {
92 .codec_count = ARRAY_SIZE(nv_video_codecs_decode_array),
93 .codec_array = nv_video_codecs_decode_array,
94 };
95
96 /* Sienna Cichlid */
97 static const struct amdgpu_video_codec_info sc_video_codecs_encode_array[] = {
98 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2160, 0)},
99 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 7680, 4352, 0)},
100 };
101
102 static const struct amdgpu_video_codecs sc_video_codecs_encode = {
103 .codec_count = ARRAY_SIZE(sc_video_codecs_encode_array),
104 .codec_array = sc_video_codecs_encode_array,
105 };
106
107 static const struct amdgpu_video_codec_info sc_video_codecs_decode_array_vcn0[] = {
108 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)},
109 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)},
110 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
111 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)},
112 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
113 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
114 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
115 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},
116 };
117
118 static const struct amdgpu_video_codec_info sc_video_codecs_decode_array_vcn1[] = {
119 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)},
120 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)},
121 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
122 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)},
123 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
124 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
125 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
126 };
127
128 static const struct amdgpu_video_codecs sc_video_codecs_decode_vcn0 = {
129 .codec_count = ARRAY_SIZE(sc_video_codecs_decode_array_vcn0),
130 .codec_array = sc_video_codecs_decode_array_vcn0,
131 };
132
133 static const struct amdgpu_video_codecs sc_video_codecs_decode_vcn1 = {
134 .codec_count = ARRAY_SIZE(sc_video_codecs_decode_array_vcn1),
135 .codec_array = sc_video_codecs_decode_array_vcn1,
136 };
137
138 /* SRIOV Sienna Cichlid, not const since data is controlled by host */
139 static struct amdgpu_video_codec_info sriov_sc_video_codecs_encode_array[] = {
140 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2160, 0)},
141 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 7680, 4352, 0)},
142 };
143
144 static struct amdgpu_video_codec_info sriov_sc_video_codecs_decode_array_vcn0[] = {
145 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)},
146 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)},
147 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
148 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)},
149 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
150 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
151 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
152 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},
153 };
154
155 static struct amdgpu_video_codec_info sriov_sc_video_codecs_decode_array_vcn1[] = {
156 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)},
157 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)},
158 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
159 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)},
160 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
161 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
162 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
163 };
164
165 static struct amdgpu_video_codecs sriov_sc_video_codecs_encode = {
166 .codec_count = ARRAY_SIZE(sriov_sc_video_codecs_encode_array),
167 .codec_array = sriov_sc_video_codecs_encode_array,
168 };
169
170 static struct amdgpu_video_codecs sriov_sc_video_codecs_decode_vcn0 = {
171 .codec_count = ARRAY_SIZE(sriov_sc_video_codecs_decode_array_vcn0),
172 .codec_array = sriov_sc_video_codecs_decode_array_vcn0,
173 };
174
175 static struct amdgpu_video_codecs sriov_sc_video_codecs_decode_vcn1 = {
176 .codec_count = ARRAY_SIZE(sriov_sc_video_codecs_decode_array_vcn1),
177 .codec_array = sriov_sc_video_codecs_decode_array_vcn1,
178 };
179
180 /* Beige Goby*/
181 static const struct amdgpu_video_codec_info bg_video_codecs_decode_array[] = {
182 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
183 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
184 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
185 };
186
187 static const struct amdgpu_video_codecs bg_video_codecs_decode = {
188 .codec_count = ARRAY_SIZE(bg_video_codecs_decode_array),
189 .codec_array = bg_video_codecs_decode_array,
190 };
191
192 static const struct amdgpu_video_codecs bg_video_codecs_encode = {
193 .codec_count = 0,
194 .codec_array = NULL,
195 };
196
197 /* Yellow Carp*/
198 static const struct amdgpu_video_codec_info yc_video_codecs_decode_array[] = {
199 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
200 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
201 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
202 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
203 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},
204 };
205
206 static const struct amdgpu_video_codecs yc_video_codecs_decode = {
207 .codec_count = ARRAY_SIZE(yc_video_codecs_decode_array),
208 .codec_array = yc_video_codecs_decode_array,
209 };
210
nv_query_video_codecs(struct amdgpu_device * adev,bool encode,const struct amdgpu_video_codecs ** codecs)211 static int nv_query_video_codecs(struct amdgpu_device *adev, bool encode,
212 const struct amdgpu_video_codecs **codecs)
213 {
214 if (adev->vcn.num_vcn_inst == hweight8(adev->vcn.harvest_config))
215 return -EINVAL;
216
217 switch (adev->ip_versions[UVD_HWIP][0]) {
218 case IP_VERSION(3, 0, 0):
219 case IP_VERSION(3, 0, 64):
220 case IP_VERSION(3, 0, 192):
221 if (amdgpu_sriov_vf(adev)) {
222 if (adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) {
223 if (encode)
224 *codecs = &sriov_sc_video_codecs_encode;
225 else
226 *codecs = &sriov_sc_video_codecs_decode_vcn1;
227 } else {
228 if (encode)
229 *codecs = &sriov_sc_video_codecs_encode;
230 else
231 *codecs = &sriov_sc_video_codecs_decode_vcn0;
232 }
233 } else {
234 if (adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) {
235 if (encode)
236 *codecs = &sc_video_codecs_encode;
237 else
238 *codecs = &sc_video_codecs_decode_vcn1;
239 } else {
240 if (encode)
241 *codecs = &sc_video_codecs_encode;
242 else
243 *codecs = &sc_video_codecs_decode_vcn0;
244 }
245 }
246 return 0;
247 case IP_VERSION(3, 0, 16):
248 case IP_VERSION(3, 0, 2):
249 if (encode)
250 *codecs = &sc_video_codecs_encode;
251 else
252 *codecs = &sc_video_codecs_decode_vcn0;
253 return 0;
254 case IP_VERSION(3, 1, 1):
255 case IP_VERSION(3, 1, 2):
256 if (encode)
257 *codecs = &sc_video_codecs_encode;
258 else
259 *codecs = &yc_video_codecs_decode;
260 return 0;
261 case IP_VERSION(3, 0, 33):
262 if (encode)
263 *codecs = &bg_video_codecs_encode;
264 else
265 *codecs = &bg_video_codecs_decode;
266 return 0;
267 case IP_VERSION(2, 0, 0):
268 case IP_VERSION(2, 0, 2):
269 if (encode)
270 *codecs = &nv_video_codecs_encode;
271 else
272 *codecs = &nv_video_codecs_decode;
273 return 0;
274 default:
275 return -EINVAL;
276 }
277 }
278
nv_didt_rreg(struct amdgpu_device * adev,u32 reg)279 static u32 nv_didt_rreg(struct amdgpu_device *adev, u32 reg)
280 {
281 unsigned long flags, address, data;
282 u32 r;
283
284 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
285 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
286
287 spin_lock_irqsave(&adev->didt_idx_lock, flags);
288 WREG32(address, (reg));
289 r = RREG32(data);
290 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
291 return r;
292 }
293
nv_didt_wreg(struct amdgpu_device * adev,u32 reg,u32 v)294 static void nv_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
295 {
296 unsigned long flags, address, data;
297
298 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
299 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
300
301 spin_lock_irqsave(&adev->didt_idx_lock, flags);
302 WREG32(address, (reg));
303 WREG32(data, (v));
304 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
305 }
306
nv_get_config_memsize(struct amdgpu_device * adev)307 static u32 nv_get_config_memsize(struct amdgpu_device *adev)
308 {
309 return adev->nbio.funcs->get_memsize(adev);
310 }
311
nv_get_xclk(struct amdgpu_device * adev)312 static u32 nv_get_xclk(struct amdgpu_device *adev)
313 {
314 return adev->clock.spll.reference_freq;
315 }
316
317
nv_grbm_select(struct amdgpu_device * adev,u32 me,u32 pipe,u32 queue,u32 vmid)318 void nv_grbm_select(struct amdgpu_device *adev,
319 u32 me, u32 pipe, u32 queue, u32 vmid)
320 {
321 u32 grbm_gfx_cntl = 0;
322 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);
323 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me);
324 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);
325 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);
326
327 WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, grbm_gfx_cntl);
328 }
329
nv_read_disabled_bios(struct amdgpu_device * adev)330 static bool nv_read_disabled_bios(struct amdgpu_device *adev)
331 {
332 /* todo */
333 return false;
334 }
335
336 static struct soc15_allowed_register_entry nv_allowed_read_registers[] = {
337 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)},
338 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)},
339 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)},
340 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)},
341 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)},
342 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)},
343 { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)},
344 { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)},
345 { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)},
346 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)},
347 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)},
348 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)},
349 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)},
350 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)},
351 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)},
352 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)},
353 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)},
354 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)},
355 { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)},
356 };
357
nv_read_indexed_register(struct amdgpu_device * adev,u32 se_num,u32 sh_num,u32 reg_offset)358 static uint32_t nv_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
359 u32 sh_num, u32 reg_offset)
360 {
361 uint32_t val;
362
363 mutex_lock(&adev->grbm_idx_mutex);
364 if (se_num != 0xffffffff || sh_num != 0xffffffff)
365 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff, 0);
366
367 val = RREG32(reg_offset);
368
369 if (se_num != 0xffffffff || sh_num != 0xffffffff)
370 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
371 mutex_unlock(&adev->grbm_idx_mutex);
372 return val;
373 }
374
nv_get_register_value(struct amdgpu_device * adev,bool indexed,u32 se_num,u32 sh_num,u32 reg_offset)375 static uint32_t nv_get_register_value(struct amdgpu_device *adev,
376 bool indexed, u32 se_num,
377 u32 sh_num, u32 reg_offset)
378 {
379 if (indexed) {
380 return nv_read_indexed_register(adev, se_num, sh_num, reg_offset);
381 } else {
382 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG))
383 return adev->gfx.config.gb_addr_config;
384 return RREG32(reg_offset);
385 }
386 }
387
nv_read_register(struct amdgpu_device * adev,u32 se_num,u32 sh_num,u32 reg_offset,u32 * value)388 static int nv_read_register(struct amdgpu_device *adev, u32 se_num,
389 u32 sh_num, u32 reg_offset, u32 *value)
390 {
391 uint32_t i;
392 struct soc15_allowed_register_entry *en;
393
394 *value = 0;
395 for (i = 0; i < ARRAY_SIZE(nv_allowed_read_registers); i++) {
396 en = &nv_allowed_read_registers[i];
397 if (!adev->reg_offset[en->hwip][en->inst])
398 continue;
399 else if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg]
400 + en->reg_offset))
401 continue;
402
403 *value = nv_get_register_value(adev,
404 nv_allowed_read_registers[i].grbm_indexed,
405 se_num, sh_num, reg_offset);
406 return 0;
407 }
408 return -EINVAL;
409 }
410
nv_asic_mode2_reset(struct amdgpu_device * adev)411 static int nv_asic_mode2_reset(struct amdgpu_device *adev)
412 {
413 u32 i;
414 int ret = 0;
415
416 amdgpu_atombios_scratch_regs_engine_hung(adev, true);
417
418 /* disable BM */
419 pci_clear_master(adev->pdev);
420
421 amdgpu_device_cache_pci_state(adev->pdev);
422
423 ret = amdgpu_dpm_mode2_reset(adev);
424 if (ret)
425 dev_err(adev->dev, "GPU mode2 reset failed\n");
426
427 amdgpu_device_load_pci_state(adev->pdev);
428
429 /* wait for asic to come out of reset */
430 for (i = 0; i < adev->usec_timeout; i++) {
431 u32 memsize = adev->nbio.funcs->get_memsize(adev);
432
433 if (memsize != 0xffffffff)
434 break;
435 udelay(1);
436 }
437
438 amdgpu_atombios_scratch_regs_engine_hung(adev, false);
439
440 return ret;
441 }
442
443 static enum amd_reset_method
nv_asic_reset_method(struct amdgpu_device * adev)444 nv_asic_reset_method(struct amdgpu_device *adev)
445 {
446 if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 ||
447 amdgpu_reset_method == AMD_RESET_METHOD_MODE2 ||
448 amdgpu_reset_method == AMD_RESET_METHOD_BACO ||
449 amdgpu_reset_method == AMD_RESET_METHOD_PCI)
450 return amdgpu_reset_method;
451
452 if (amdgpu_reset_method != -1)
453 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n",
454 amdgpu_reset_method);
455
456 switch (adev->ip_versions[MP1_HWIP][0]) {
457 case IP_VERSION(11, 5, 0):
458 case IP_VERSION(13, 0, 1):
459 case IP_VERSION(13, 0, 3):
460 case IP_VERSION(13, 0, 5):
461 case IP_VERSION(13, 0, 8):
462 return AMD_RESET_METHOD_MODE2;
463 case IP_VERSION(11, 0, 7):
464 case IP_VERSION(11, 0, 11):
465 case IP_VERSION(11, 0, 12):
466 case IP_VERSION(11, 0, 13):
467 return AMD_RESET_METHOD_MODE1;
468 default:
469 if (amdgpu_dpm_is_baco_supported(adev))
470 return AMD_RESET_METHOD_BACO;
471 else
472 return AMD_RESET_METHOD_MODE1;
473 }
474 }
475
nv_asic_reset(struct amdgpu_device * adev)476 static int nv_asic_reset(struct amdgpu_device *adev)
477 {
478 int ret = 0;
479
480 switch (nv_asic_reset_method(adev)) {
481 case AMD_RESET_METHOD_PCI:
482 dev_info(adev->dev, "PCI reset\n");
483 ret = amdgpu_device_pci_reset(adev);
484 break;
485 case AMD_RESET_METHOD_BACO:
486 dev_info(adev->dev, "BACO reset\n");
487 ret = amdgpu_dpm_baco_reset(adev);
488 break;
489 case AMD_RESET_METHOD_MODE2:
490 dev_info(adev->dev, "MODE2 reset\n");
491 ret = nv_asic_mode2_reset(adev);
492 break;
493 default:
494 dev_info(adev->dev, "MODE1 reset\n");
495 ret = amdgpu_device_mode1_reset(adev);
496 break;
497 }
498
499 return ret;
500 }
501
nv_set_uvd_clocks(struct amdgpu_device * adev,u32 vclk,u32 dclk)502 static int nv_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
503 {
504 /* todo */
505 return 0;
506 }
507
nv_set_vce_clocks(struct amdgpu_device * adev,u32 evclk,u32 ecclk)508 static int nv_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
509 {
510 /* todo */
511 return 0;
512 }
513
nv_program_aspm(struct amdgpu_device * adev)514 static void nv_program_aspm(struct amdgpu_device *adev)
515 {
516 if (!amdgpu_device_should_use_aspm(adev) || !amdgpu_device_aspm_support_quirk())
517 return;
518
519 if (!(adev->flags & AMD_IS_APU) &&
520 (adev->nbio.funcs->program_aspm))
521 adev->nbio.funcs->program_aspm(adev);
522
523 }
524
525 const struct amdgpu_ip_block_version nv_common_ip_block = {
526 .type = AMD_IP_BLOCK_TYPE_COMMON,
527 .major = 1,
528 .minor = 0,
529 .rev = 0,
530 .funcs = &nv_common_ip_funcs,
531 };
532
nv_set_virt_ops(struct amdgpu_device * adev)533 void nv_set_virt_ops(struct amdgpu_device *adev)
534 {
535 adev->virt.ops = &xgpu_nv_virt_ops;
536 }
537
nv_need_full_reset(struct amdgpu_device * adev)538 static bool nv_need_full_reset(struct amdgpu_device *adev)
539 {
540 return true;
541 }
542
nv_need_reset_on_init(struct amdgpu_device * adev)543 static bool nv_need_reset_on_init(struct amdgpu_device *adev)
544 {
545 u32 sol_reg;
546
547 if (adev->flags & AMD_IS_APU)
548 return false;
549
550 /* Check sOS sign of life register to confirm sys driver and sOS
551 * are already been loaded.
552 */
553 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
554 if (sol_reg)
555 return true;
556
557 return false;
558 }
559
nv_init_doorbell_index(struct amdgpu_device * adev)560 static void nv_init_doorbell_index(struct amdgpu_device *adev)
561 {
562 adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ;
563 adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0;
564 adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1;
565 adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2;
566 adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3;
567 adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4;
568 adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5;
569 adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6;
570 adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7;
571 adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START;
572 adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END;
573 adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0;
574 adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1;
575 adev->doorbell_index.gfx_userqueue_start =
576 AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_START;
577 adev->doorbell_index.gfx_userqueue_end =
578 AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_END;
579 adev->doorbell_index.mes_ring0 = AMDGPU_NAVI10_DOORBELL_MES_RING0;
580 adev->doorbell_index.mes_ring1 = AMDGPU_NAVI10_DOORBELL_MES_RING1;
581 adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0;
582 adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1;
583 adev->doorbell_index.sdma_engine[2] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE2;
584 adev->doorbell_index.sdma_engine[3] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE3;
585 adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH;
586 adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1;
587 adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3;
588 adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5;
589 adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7;
590 adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP;
591 adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP;
592
593 adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1;
594 adev->doorbell_index.sdma_doorbell_range = 20;
595 }
596
nv_pre_asic_init(struct amdgpu_device * adev)597 static void nv_pre_asic_init(struct amdgpu_device *adev)
598 {
599 }
600
nv_update_umd_stable_pstate(struct amdgpu_device * adev,bool enter)601 static int nv_update_umd_stable_pstate(struct amdgpu_device *adev,
602 bool enter)
603 {
604 if (enter)
605 amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
606 else
607 amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
608
609 if (adev->gfx.funcs->update_perfmon_mgcg)
610 adev->gfx.funcs->update_perfmon_mgcg(adev, !enter);
611
612 if (!(adev->flags & AMD_IS_APU) &&
613 (adev->nbio.funcs->enable_aspm) &&
614 amdgpu_device_should_use_aspm(adev))
615 adev->nbio.funcs->enable_aspm(adev, !enter);
616
617 return 0;
618 }
619
620 static const struct amdgpu_asic_funcs nv_asic_funcs = {
621 .read_disabled_bios = &nv_read_disabled_bios,
622 .read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom,
623 .read_register = &nv_read_register,
624 .reset = &nv_asic_reset,
625 .reset_method = &nv_asic_reset_method,
626 .get_xclk = &nv_get_xclk,
627 .set_uvd_clocks = &nv_set_uvd_clocks,
628 .set_vce_clocks = &nv_set_vce_clocks,
629 .get_config_memsize = &nv_get_config_memsize,
630 .init_doorbell_index = &nv_init_doorbell_index,
631 .need_full_reset = &nv_need_full_reset,
632 .need_reset_on_init = &nv_need_reset_on_init,
633 .get_pcie_replay_count = &amdgpu_nbio_get_pcie_replay_count,
634 .supports_baco = &amdgpu_dpm_is_baco_supported,
635 .pre_asic_init = &nv_pre_asic_init,
636 .update_umd_stable_pstate = &nv_update_umd_stable_pstate,
637 .query_video_codecs = &nv_query_video_codecs,
638 };
639
nv_common_early_init(void * handle)640 static int nv_common_early_init(void *handle)
641 {
642 #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE)
643 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
644
645 if (!amdgpu_sriov_vf(adev)) {
646 adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;
647 adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET;
648 }
649 adev->smc_rreg = NULL;
650 adev->smc_wreg = NULL;
651 adev->pcie_rreg = &amdgpu_device_indirect_rreg;
652 adev->pcie_wreg = &amdgpu_device_indirect_wreg;
653 adev->pcie_rreg64 = &amdgpu_device_indirect_rreg64;
654 adev->pcie_wreg64 = &amdgpu_device_indirect_wreg64;
655 adev->pciep_rreg = amdgpu_device_pcie_port_rreg;
656 adev->pciep_wreg = amdgpu_device_pcie_port_wreg;
657
658 /* TODO: will add them during VCN v2 implementation */
659 adev->uvd_ctx_rreg = NULL;
660 adev->uvd_ctx_wreg = NULL;
661
662 adev->didt_rreg = &nv_didt_rreg;
663 adev->didt_wreg = &nv_didt_wreg;
664
665 adev->asic_funcs = &nv_asic_funcs;
666
667 adev->rev_id = amdgpu_device_get_rev_id(adev);
668 adev->external_rev_id = 0xff;
669 /* TODO: split the GC and PG flags based on the relevant IP version for which
670 * they are relevant.
671 */
672 switch (adev->ip_versions[GC_HWIP][0]) {
673 case IP_VERSION(10, 1, 10):
674 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
675 AMD_CG_SUPPORT_GFX_CGCG |
676 AMD_CG_SUPPORT_IH_CG |
677 AMD_CG_SUPPORT_HDP_MGCG |
678 AMD_CG_SUPPORT_HDP_LS |
679 AMD_CG_SUPPORT_SDMA_MGCG |
680 AMD_CG_SUPPORT_SDMA_LS |
681 AMD_CG_SUPPORT_MC_MGCG |
682 AMD_CG_SUPPORT_MC_LS |
683 AMD_CG_SUPPORT_ATHUB_MGCG |
684 AMD_CG_SUPPORT_ATHUB_LS |
685 AMD_CG_SUPPORT_VCN_MGCG |
686 AMD_CG_SUPPORT_JPEG_MGCG |
687 AMD_CG_SUPPORT_BIF_MGCG |
688 AMD_CG_SUPPORT_BIF_LS;
689 adev->pg_flags = AMD_PG_SUPPORT_VCN |
690 AMD_PG_SUPPORT_VCN_DPG |
691 AMD_PG_SUPPORT_JPEG |
692 AMD_PG_SUPPORT_ATHUB;
693 adev->external_rev_id = adev->rev_id + 0x1;
694 break;
695 case IP_VERSION(10, 1, 1):
696 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
697 AMD_CG_SUPPORT_GFX_CGCG |
698 AMD_CG_SUPPORT_IH_CG |
699 AMD_CG_SUPPORT_HDP_MGCG |
700 AMD_CG_SUPPORT_HDP_LS |
701 AMD_CG_SUPPORT_SDMA_MGCG |
702 AMD_CG_SUPPORT_SDMA_LS |
703 AMD_CG_SUPPORT_MC_MGCG |
704 AMD_CG_SUPPORT_MC_LS |
705 AMD_CG_SUPPORT_ATHUB_MGCG |
706 AMD_CG_SUPPORT_ATHUB_LS |
707 AMD_CG_SUPPORT_VCN_MGCG |
708 AMD_CG_SUPPORT_JPEG_MGCG |
709 AMD_CG_SUPPORT_BIF_MGCG |
710 AMD_CG_SUPPORT_BIF_LS;
711 adev->pg_flags = AMD_PG_SUPPORT_VCN |
712 AMD_PG_SUPPORT_JPEG |
713 AMD_PG_SUPPORT_VCN_DPG;
714 adev->external_rev_id = adev->rev_id + 20;
715 break;
716 case IP_VERSION(10, 1, 2):
717 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
718 AMD_CG_SUPPORT_GFX_MGLS |
719 AMD_CG_SUPPORT_GFX_CGCG |
720 AMD_CG_SUPPORT_GFX_CP_LS |
721 AMD_CG_SUPPORT_GFX_RLC_LS |
722 AMD_CG_SUPPORT_IH_CG |
723 AMD_CG_SUPPORT_HDP_MGCG |
724 AMD_CG_SUPPORT_HDP_LS |
725 AMD_CG_SUPPORT_SDMA_MGCG |
726 AMD_CG_SUPPORT_SDMA_LS |
727 AMD_CG_SUPPORT_MC_MGCG |
728 AMD_CG_SUPPORT_MC_LS |
729 AMD_CG_SUPPORT_ATHUB_MGCG |
730 AMD_CG_SUPPORT_ATHUB_LS |
731 AMD_CG_SUPPORT_VCN_MGCG |
732 AMD_CG_SUPPORT_JPEG_MGCG;
733 adev->pg_flags = AMD_PG_SUPPORT_VCN |
734 AMD_PG_SUPPORT_VCN_DPG |
735 AMD_PG_SUPPORT_JPEG |
736 AMD_PG_SUPPORT_ATHUB;
737 /* guest vm gets 0xffffffff when reading RCC_DEV0_EPF0_STRAP0,
738 * as a consequence, the rev_id and external_rev_id are wrong.
739 * workaround it by hardcoding rev_id to 0 (default value).
740 */
741 if (amdgpu_sriov_vf(adev))
742 adev->rev_id = 0;
743 adev->external_rev_id = adev->rev_id + 0xa;
744 break;
745 case IP_VERSION(10, 3, 0):
746 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
747 AMD_CG_SUPPORT_GFX_CGCG |
748 AMD_CG_SUPPORT_GFX_CGLS |
749 AMD_CG_SUPPORT_GFX_3D_CGCG |
750 AMD_CG_SUPPORT_MC_MGCG |
751 AMD_CG_SUPPORT_VCN_MGCG |
752 AMD_CG_SUPPORT_JPEG_MGCG |
753 AMD_CG_SUPPORT_HDP_MGCG |
754 AMD_CG_SUPPORT_HDP_LS |
755 AMD_CG_SUPPORT_IH_CG |
756 AMD_CG_SUPPORT_MC_LS;
757 adev->pg_flags = AMD_PG_SUPPORT_VCN |
758 AMD_PG_SUPPORT_VCN_DPG |
759 AMD_PG_SUPPORT_JPEG |
760 AMD_PG_SUPPORT_ATHUB |
761 AMD_PG_SUPPORT_MMHUB;
762 if (amdgpu_sriov_vf(adev)) {
763 /* hypervisor control CG and PG enablement */
764 adev->cg_flags = 0;
765 adev->pg_flags = 0;
766 }
767 adev->external_rev_id = adev->rev_id + 0x28;
768 break;
769 case IP_VERSION(10, 3, 2):
770 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
771 AMD_CG_SUPPORT_GFX_CGCG |
772 AMD_CG_SUPPORT_GFX_CGLS |
773 AMD_CG_SUPPORT_GFX_3D_CGCG |
774 AMD_CG_SUPPORT_VCN_MGCG |
775 AMD_CG_SUPPORT_JPEG_MGCG |
776 AMD_CG_SUPPORT_MC_MGCG |
777 AMD_CG_SUPPORT_MC_LS |
778 AMD_CG_SUPPORT_HDP_MGCG |
779 AMD_CG_SUPPORT_HDP_LS |
780 AMD_CG_SUPPORT_IH_CG;
781 adev->pg_flags = AMD_PG_SUPPORT_VCN |
782 AMD_PG_SUPPORT_VCN_DPG |
783 AMD_PG_SUPPORT_JPEG |
784 AMD_PG_SUPPORT_ATHUB |
785 AMD_PG_SUPPORT_MMHUB;
786 adev->external_rev_id = adev->rev_id + 0x32;
787 break;
788 case IP_VERSION(10, 3, 1):
789 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
790 AMD_CG_SUPPORT_GFX_MGLS |
791 AMD_CG_SUPPORT_GFX_CP_LS |
792 AMD_CG_SUPPORT_GFX_RLC_LS |
793 AMD_CG_SUPPORT_GFX_CGCG |
794 AMD_CG_SUPPORT_GFX_CGLS |
795 AMD_CG_SUPPORT_GFX_3D_CGCG |
796 AMD_CG_SUPPORT_GFX_3D_CGLS |
797 AMD_CG_SUPPORT_MC_MGCG |
798 AMD_CG_SUPPORT_MC_LS |
799 AMD_CG_SUPPORT_GFX_FGCG |
800 AMD_CG_SUPPORT_VCN_MGCG |
801 AMD_CG_SUPPORT_SDMA_MGCG |
802 AMD_CG_SUPPORT_SDMA_LS |
803 AMD_CG_SUPPORT_JPEG_MGCG;
804 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG |
805 AMD_PG_SUPPORT_VCN |
806 AMD_PG_SUPPORT_VCN_DPG |
807 AMD_PG_SUPPORT_JPEG;
808 if (adev->apu_flags & AMD_APU_IS_VANGOGH)
809 adev->external_rev_id = adev->rev_id + 0x01;
810 break;
811 case IP_VERSION(10, 3, 4):
812 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
813 AMD_CG_SUPPORT_GFX_CGCG |
814 AMD_CG_SUPPORT_GFX_CGLS |
815 AMD_CG_SUPPORT_GFX_3D_CGCG |
816 AMD_CG_SUPPORT_VCN_MGCG |
817 AMD_CG_SUPPORT_JPEG_MGCG |
818 AMD_CG_SUPPORT_MC_MGCG |
819 AMD_CG_SUPPORT_MC_LS |
820 AMD_CG_SUPPORT_HDP_MGCG |
821 AMD_CG_SUPPORT_HDP_LS |
822 AMD_CG_SUPPORT_IH_CG;
823 adev->pg_flags = AMD_PG_SUPPORT_VCN |
824 AMD_PG_SUPPORT_VCN_DPG |
825 AMD_PG_SUPPORT_JPEG |
826 AMD_PG_SUPPORT_ATHUB |
827 AMD_PG_SUPPORT_MMHUB;
828 adev->external_rev_id = adev->rev_id + 0x3c;
829 break;
830 case IP_VERSION(10, 3, 5):
831 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
832 AMD_CG_SUPPORT_GFX_CGCG |
833 AMD_CG_SUPPORT_GFX_CGLS |
834 AMD_CG_SUPPORT_GFX_3D_CGCG |
835 AMD_CG_SUPPORT_MC_MGCG |
836 AMD_CG_SUPPORT_MC_LS |
837 AMD_CG_SUPPORT_HDP_MGCG |
838 AMD_CG_SUPPORT_HDP_LS |
839 AMD_CG_SUPPORT_IH_CG |
840 AMD_CG_SUPPORT_VCN_MGCG;
841 adev->pg_flags = AMD_PG_SUPPORT_VCN |
842 AMD_PG_SUPPORT_VCN_DPG |
843 AMD_PG_SUPPORT_ATHUB |
844 AMD_PG_SUPPORT_MMHUB;
845 adev->external_rev_id = adev->rev_id + 0x46;
846 break;
847 case IP_VERSION(10, 3, 3):
848 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
849 AMD_CG_SUPPORT_GFX_MGLS |
850 AMD_CG_SUPPORT_GFX_CGCG |
851 AMD_CG_SUPPORT_GFX_CGLS |
852 AMD_CG_SUPPORT_GFX_3D_CGCG |
853 AMD_CG_SUPPORT_GFX_3D_CGLS |
854 AMD_CG_SUPPORT_GFX_RLC_LS |
855 AMD_CG_SUPPORT_GFX_CP_LS |
856 AMD_CG_SUPPORT_GFX_FGCG |
857 AMD_CG_SUPPORT_MC_MGCG |
858 AMD_CG_SUPPORT_MC_LS |
859 AMD_CG_SUPPORT_SDMA_LS |
860 AMD_CG_SUPPORT_HDP_MGCG |
861 AMD_CG_SUPPORT_HDP_LS |
862 AMD_CG_SUPPORT_ATHUB_MGCG |
863 AMD_CG_SUPPORT_ATHUB_LS |
864 AMD_CG_SUPPORT_IH_CG |
865 AMD_CG_SUPPORT_VCN_MGCG |
866 AMD_CG_SUPPORT_JPEG_MGCG |
867 AMD_CG_SUPPORT_SDMA_MGCG;
868 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG |
869 AMD_PG_SUPPORT_VCN |
870 AMD_PG_SUPPORT_VCN_DPG |
871 AMD_PG_SUPPORT_JPEG;
872 if (adev->pdev->device == 0x1681)
873 adev->external_rev_id = 0x20;
874 else
875 adev->external_rev_id = adev->rev_id + 0x01;
876 break;
877 case IP_VERSION(10, 1, 3):
878 case IP_VERSION(10, 1, 4):
879 adev->cg_flags = 0;
880 adev->pg_flags = 0;
881 adev->external_rev_id = adev->rev_id + 0x82;
882 break;
883 case IP_VERSION(10, 3, 6):
884 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
885 AMD_CG_SUPPORT_GFX_MGLS |
886 AMD_CG_SUPPORT_GFX_CGCG |
887 AMD_CG_SUPPORT_GFX_CGLS |
888 AMD_CG_SUPPORT_GFX_3D_CGCG |
889 AMD_CG_SUPPORT_GFX_3D_CGLS |
890 AMD_CG_SUPPORT_GFX_RLC_LS |
891 AMD_CG_SUPPORT_GFX_CP_LS |
892 AMD_CG_SUPPORT_GFX_FGCG |
893 AMD_CG_SUPPORT_MC_MGCG |
894 AMD_CG_SUPPORT_MC_LS |
895 AMD_CG_SUPPORT_SDMA_LS |
896 AMD_CG_SUPPORT_HDP_MGCG |
897 AMD_CG_SUPPORT_HDP_LS |
898 AMD_CG_SUPPORT_ATHUB_MGCG |
899 AMD_CG_SUPPORT_ATHUB_LS |
900 AMD_CG_SUPPORT_IH_CG |
901 AMD_CG_SUPPORT_VCN_MGCG |
902 AMD_CG_SUPPORT_JPEG_MGCG;
903 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG |
904 AMD_PG_SUPPORT_VCN |
905 AMD_PG_SUPPORT_VCN_DPG |
906 AMD_PG_SUPPORT_JPEG;
907 adev->external_rev_id = adev->rev_id + 0x01;
908 break;
909 case IP_VERSION(10, 3, 7):
910 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
911 AMD_CG_SUPPORT_GFX_MGLS |
912 AMD_CG_SUPPORT_GFX_CGCG |
913 AMD_CG_SUPPORT_GFX_CGLS |
914 AMD_CG_SUPPORT_GFX_3D_CGCG |
915 AMD_CG_SUPPORT_GFX_3D_CGLS |
916 AMD_CG_SUPPORT_GFX_RLC_LS |
917 AMD_CG_SUPPORT_GFX_CP_LS |
918 AMD_CG_SUPPORT_GFX_FGCG |
919 AMD_CG_SUPPORT_MC_MGCG |
920 AMD_CG_SUPPORT_MC_LS |
921 AMD_CG_SUPPORT_SDMA_LS |
922 AMD_CG_SUPPORT_HDP_MGCG |
923 AMD_CG_SUPPORT_HDP_LS |
924 AMD_CG_SUPPORT_ATHUB_MGCG |
925 AMD_CG_SUPPORT_ATHUB_LS |
926 AMD_CG_SUPPORT_IH_CG |
927 AMD_CG_SUPPORT_VCN_MGCG |
928 AMD_CG_SUPPORT_JPEG_MGCG |
929 AMD_CG_SUPPORT_SDMA_MGCG;
930 adev->pg_flags = AMD_PG_SUPPORT_VCN |
931 AMD_PG_SUPPORT_VCN_DPG |
932 AMD_PG_SUPPORT_JPEG |
933 AMD_PG_SUPPORT_GFX_PG;
934 adev->external_rev_id = adev->rev_id + 0x01;
935 break;
936 default:
937 /* FIXME: not supported yet */
938 return -EINVAL;
939 }
940
941 if (adev->harvest_ip_mask & AMD_HARVEST_IP_VCN_MASK)
942 adev->pg_flags &= ~(AMD_PG_SUPPORT_VCN |
943 AMD_PG_SUPPORT_VCN_DPG |
944 AMD_PG_SUPPORT_JPEG);
945
946 if (amdgpu_sriov_vf(adev)) {
947 amdgpu_virt_init_setting(adev);
948 xgpu_nv_mailbox_set_irq_funcs(adev);
949 }
950
951 return 0;
952 }
953
nv_common_late_init(void * handle)954 static int nv_common_late_init(void *handle)
955 {
956 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
957
958 if (amdgpu_sriov_vf(adev)) {
959 xgpu_nv_mailbox_get_irq(adev);
960 if (adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) {
961 amdgpu_virt_update_sriov_video_codec(adev,
962 sriov_sc_video_codecs_encode_array,
963 ARRAY_SIZE(sriov_sc_video_codecs_encode_array),
964 sriov_sc_video_codecs_decode_array_vcn1,
965 ARRAY_SIZE(sriov_sc_video_codecs_decode_array_vcn1));
966 } else {
967 amdgpu_virt_update_sriov_video_codec(adev,
968 sriov_sc_video_codecs_encode_array,
969 ARRAY_SIZE(sriov_sc_video_codecs_encode_array),
970 sriov_sc_video_codecs_decode_array_vcn0,
971 ARRAY_SIZE(sriov_sc_video_codecs_decode_array_vcn0));
972 }
973 }
974
975 /* Enable selfring doorbell aperture late because doorbell BAR
976 * aperture will change if resize BAR successfully in gmc sw_init.
977 */
978 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, true);
979
980 return 0;
981 }
982
nv_common_sw_init(void * handle)983 static int nv_common_sw_init(void *handle)
984 {
985 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
986
987 if (amdgpu_sriov_vf(adev))
988 xgpu_nv_mailbox_add_irq_id(adev);
989
990 return 0;
991 }
992
nv_common_sw_fini(void * handle)993 static int nv_common_sw_fini(void *handle)
994 {
995 return 0;
996 }
997
nv_common_hw_init(void * handle)998 static int nv_common_hw_init(void *handle)
999 {
1000 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1001
1002 if (adev->nbio.funcs->apply_lc_spc_mode_wa)
1003 adev->nbio.funcs->apply_lc_spc_mode_wa(adev);
1004
1005 if (adev->nbio.funcs->apply_l1_link_width_reconfig_wa)
1006 adev->nbio.funcs->apply_l1_link_width_reconfig_wa(adev);
1007
1008 /* enable aspm */
1009 nv_program_aspm(adev);
1010 /* setup nbio registers */
1011 adev->nbio.funcs->init_registers(adev);
1012 /* remap HDP registers to a hole in mmio space,
1013 * for the purpose of expose those registers
1014 * to process space
1015 */
1016 if (adev->nbio.funcs->remap_hdp_registers && !amdgpu_sriov_vf(adev))
1017 adev->nbio.funcs->remap_hdp_registers(adev);
1018 /* enable the doorbell aperture */
1019 adev->nbio.funcs->enable_doorbell_aperture(adev, true);
1020
1021 return 0;
1022 }
1023
nv_common_hw_fini(void * handle)1024 static int nv_common_hw_fini(void *handle)
1025 {
1026 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1027
1028 /* Disable the doorbell aperture and selfring doorbell aperture
1029 * separately in hw_fini because nv_enable_doorbell_aperture
1030 * has been removed and there is no need to delay disabling
1031 * selfring doorbell.
1032 */
1033 adev->nbio.funcs->enable_doorbell_aperture(adev, false);
1034 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, false);
1035
1036 return 0;
1037 }
1038
nv_common_suspend(void * handle)1039 static int nv_common_suspend(void *handle)
1040 {
1041 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1042
1043 return nv_common_hw_fini(adev);
1044 }
1045
nv_common_resume(void * handle)1046 static int nv_common_resume(void *handle)
1047 {
1048 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1049
1050 return nv_common_hw_init(adev);
1051 }
1052
nv_common_is_idle(void * handle)1053 static bool nv_common_is_idle(void *handle)
1054 {
1055 return true;
1056 }
1057
nv_common_wait_for_idle(void * handle)1058 static int nv_common_wait_for_idle(void *handle)
1059 {
1060 return 0;
1061 }
1062
nv_common_soft_reset(void * handle)1063 static int nv_common_soft_reset(void *handle)
1064 {
1065 return 0;
1066 }
1067
nv_common_set_clockgating_state(void * handle,enum amd_clockgating_state state)1068 static int nv_common_set_clockgating_state(void *handle,
1069 enum amd_clockgating_state state)
1070 {
1071 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1072
1073 if (amdgpu_sriov_vf(adev))
1074 return 0;
1075
1076 switch (adev->ip_versions[NBIO_HWIP][0]) {
1077 case IP_VERSION(2, 3, 0):
1078 case IP_VERSION(2, 3, 1):
1079 case IP_VERSION(2, 3, 2):
1080 case IP_VERSION(3, 3, 0):
1081 case IP_VERSION(3, 3, 1):
1082 case IP_VERSION(3, 3, 2):
1083 case IP_VERSION(3, 3, 3):
1084 adev->nbio.funcs->update_medium_grain_clock_gating(adev,
1085 state == AMD_CG_STATE_GATE);
1086 adev->nbio.funcs->update_medium_grain_light_sleep(adev,
1087 state == AMD_CG_STATE_GATE);
1088 adev->hdp.funcs->update_clock_gating(adev,
1089 state == AMD_CG_STATE_GATE);
1090 adev->smuio.funcs->update_rom_clock_gating(adev,
1091 state == AMD_CG_STATE_GATE);
1092 break;
1093 default:
1094 break;
1095 }
1096 return 0;
1097 }
1098
nv_common_set_powergating_state(void * handle,enum amd_powergating_state state)1099 static int nv_common_set_powergating_state(void *handle,
1100 enum amd_powergating_state state)
1101 {
1102 /* TODO */
1103 return 0;
1104 }
1105
nv_common_get_clockgating_state(void * handle,u64 * flags)1106 static void nv_common_get_clockgating_state(void *handle, u64 *flags)
1107 {
1108 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1109
1110 if (amdgpu_sriov_vf(adev))
1111 *flags = 0;
1112
1113 adev->nbio.funcs->get_clockgating_state(adev, flags);
1114
1115 adev->hdp.funcs->get_clock_gating_state(adev, flags);
1116
1117 adev->smuio.funcs->get_clock_gating_state(adev, flags);
1118
1119 return;
1120 }
1121
1122 static const struct amd_ip_funcs nv_common_ip_funcs = {
1123 .name = "nv_common",
1124 .early_init = nv_common_early_init,
1125 .late_init = nv_common_late_init,
1126 .sw_init = nv_common_sw_init,
1127 .sw_fini = nv_common_sw_fini,
1128 .hw_init = nv_common_hw_init,
1129 .hw_fini = nv_common_hw_fini,
1130 .suspend = nv_common_suspend,
1131 .resume = nv_common_resume,
1132 .is_idle = nv_common_is_idle,
1133 .wait_for_idle = nv_common_wait_for_idle,
1134 .soft_reset = nv_common_soft_reset,
1135 .set_clockgating_state = nv_common_set_clockgating_state,
1136 .set_powergating_state = nv_common_set_powergating_state,
1137 .get_clockgating_state = nv_common_get_clockgating_state,
1138 };
1139
