1  /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2  /*
3   * Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved.
4   */
5  
6  #ifndef _DT_BINDINGS_CLK_QCOM_GCC_SDX65_H
7  #define _DT_BINDINGS_CLK_QCOM_GCC_SDX65_H
8  
9  /* GCC clocks */
10  #define GPLL0							0
11  #define GPLL0_OUT_EVEN						1
12  #define GCC_AHB_PCIE_LINK_CLK					2
13  #define GCC_BLSP1_AHB_CLK					3
14  #define GCC_BLSP1_QUP1_I2C_APPS_CLK				4
15  #define GCC_BLSP1_QUP1_I2C_APPS_CLK_SRC				5
16  #define GCC_BLSP1_QUP1_SPI_APPS_CLK				6
17  #define GCC_BLSP1_QUP1_SPI_APPS_CLK_SRC				7
18  #define GCC_BLSP1_QUP2_I2C_APPS_CLK				8
19  #define GCC_BLSP1_QUP2_I2C_APPS_CLK_SRC				9
20  #define GCC_BLSP1_QUP2_SPI_APPS_CLK				10
21  #define GCC_BLSP1_QUP2_SPI_APPS_CLK_SRC				11
22  #define GCC_BLSP1_QUP3_I2C_APPS_CLK				12
23  #define GCC_BLSP1_QUP3_I2C_APPS_CLK_SRC				13
24  #define GCC_BLSP1_QUP3_SPI_APPS_CLK				14
25  #define GCC_BLSP1_QUP3_SPI_APPS_CLK_SRC				15
26  #define GCC_BLSP1_QUP4_I2C_APPS_CLK				16
27  #define GCC_BLSP1_QUP4_I2C_APPS_CLK_SRC				17
28  #define GCC_BLSP1_QUP4_SPI_APPS_CLK				18
29  #define GCC_BLSP1_QUP4_SPI_APPS_CLK_SRC				19
30  #define GCC_BLSP1_SLEEP_CLK					20
31  #define GCC_BLSP1_UART1_APPS_CLK				21
32  #define GCC_BLSP1_UART1_APPS_CLK_SRC				22
33  #define GCC_BLSP1_UART2_APPS_CLK				23
34  #define GCC_BLSP1_UART2_APPS_CLK_SRC				24
35  #define GCC_BLSP1_UART3_APPS_CLK				25
36  #define GCC_BLSP1_UART3_APPS_CLK_SRC				26
37  #define GCC_BLSP1_UART4_APPS_CLK				27
38  #define GCC_BLSP1_UART4_APPS_CLK_SRC				28
39  #define GCC_BOOT_ROM_AHB_CLK					29
40  #define GCC_CPUSS_AHB_CLK					30
41  #define GCC_CPUSS_AHB_CLK_SRC					31
42  #define GCC_CPUSS_AHB_POSTDIV_CLK_SRC				32
43  #define GCC_CPUSS_GNOC_CLK					33
44  #define GCC_GP1_CLK						34
45  #define GCC_GP1_CLK_SRC						35
46  #define GCC_GP2_CLK						36
47  #define GCC_GP2_CLK_SRC						37
48  #define GCC_GP3_CLK						38
49  #define GCC_GP3_CLK_SRC						39
50  #define GCC_PCIE_0_CLKREF_EN					40
51  #define GCC_PCIE_AUX_CLK					41
52  #define GCC_PCIE_AUX_CLK_SRC					42
53  #define GCC_PCIE_AUX_PHY_CLK_SRC				43
54  #define GCC_PCIE_CFG_AHB_CLK					44
55  #define GCC_PCIE_MSTR_AXI_CLK					45
56  #define GCC_PCIE_PIPE_CLK					46
57  #define GCC_PCIE_PIPE_CLK_SRC					47
58  #define GCC_PCIE_RCHNG_PHY_CLK					48
59  #define GCC_PCIE_RCHNG_PHY_CLK_SRC				49
60  #define GCC_PCIE_SLEEP_CLK					50
61  #define GCC_PCIE_SLV_AXI_CLK					51
62  #define GCC_PCIE_SLV_Q2A_AXI_CLK				52
63  #define GCC_PDM2_CLK						53
64  #define GCC_PDM2_CLK_SRC					54
65  #define GCC_PDM_AHB_CLK						55
66  #define GCC_PDM_XO4_CLK						56
67  #define GCC_RX1_USB2_CLKREF_EN					57
68  #define GCC_SDCC1_AHB_CLK					58
69  #define GCC_SDCC1_APPS_CLK					59
70  #define GCC_SDCC1_APPS_CLK_SRC					60
71  #define GCC_SPMI_FETCHER_AHB_CLK				61
72  #define GCC_SPMI_FETCHER_CLK					62
73  #define GCC_SPMI_FETCHER_CLK_SRC				63
74  #define GCC_SYS_NOC_CPUSS_AHB_CLK				64
75  #define GCC_USB30_MASTER_CLK					65
76  #define GCC_USB30_MASTER_CLK_SRC				66
77  #define GCC_USB30_MOCK_UTMI_CLK					67
78  #define GCC_USB30_MOCK_UTMI_CLK_SRC				68
79  #define GCC_USB30_MOCK_UTMI_POSTDIV_CLK_SRC			69
80  #define GCC_USB30_MSTR_AXI_CLK					70
81  #define GCC_USB30_SLEEP_CLK					71
82  #define GCC_USB30_SLV_AHB_CLK					72
83  #define GCC_USB3_PHY_AUX_CLK					73
84  #define GCC_USB3_PHY_AUX_CLK_SRC				74
85  #define GCC_USB3_PHY_PIPE_CLK					75
86  #define GCC_USB3_PHY_PIPE_CLK_SRC				76
87  #define GCC_USB3_PRIM_CLKREF_EN					77
88  #define GCC_USB_PHY_CFG_AHB2PHY_CLK				78
89  #define GCC_XO_DIV4_CLK						79
90  #define GCC_XO_PCIE_LINK_CLK					80
91  
92  /* GCC resets */
93  #define GCC_BLSP1_QUP1_BCR					0
94  #define GCC_BLSP1_QUP2_BCR					1
95  #define GCC_BLSP1_QUP3_BCR					2
96  #define GCC_BLSP1_QUP4_BCR					3
97  #define GCC_BLSP1_UART1_BCR					4
98  #define GCC_BLSP1_UART2_BCR					5
99  #define GCC_BLSP1_UART3_BCR					6
100  #define GCC_BLSP1_UART4_BCR					7
101  #define GCC_PCIE_BCR						8
102  #define GCC_PCIE_LINK_DOWN_BCR					9
103  #define GCC_PCIE_NOCSR_COM_PHY_BCR				10
104  #define GCC_PCIE_PHY_BCR					11
105  #define GCC_PCIE_PHY_CFG_AHB_BCR				12
106  #define GCC_PCIE_PHY_COM_BCR					13
107  #define GCC_PCIE_PHY_NOCSR_COM_PHY_BCR				14
108  #define GCC_PDM_BCR						15
109  #define GCC_QUSB2PHY_BCR					16
110  #define GCC_SDCC1_BCR						17
111  #define GCC_SPMI_FETCHER_BCR					18
112  #define GCC_TCSR_PCIE_BCR					19
113  #define GCC_USB30_BCR						20
114  #define GCC_USB3_PHY_BCR					21
115  #define GCC_USB3PHY_PHY_BCR					22
116  #define GCC_USB_PHY_CFG_AHB2PHY_BCR				23
117  
118  /* GCC power domains */
119  #define USB30_GDSC                                              0
120  #define PCIE_GDSC                                               1
121  
122  #endif
123