1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __LINUX_UHCI_HCD_H 3 #define __LINUX_UHCI_HCD_H 4 5 #include <linux/list.h> 6 #include <linux/usb.h> 7 #include <linux/clk.h> 8 9 #define usb_packetid(pipe) (usb_pipein(pipe) ? USB_PID_IN : USB_PID_OUT) 10 #define PIPE_DEVEP_MASK 0x0007ff00 11 12 13 /* 14 * Universal Host Controller Interface data structures and defines 15 */ 16 17 /* Command register */ 18 #define USBCMD 0 19 #define USBCMD_RS 0x0001 /* Run/Stop */ 20 #define USBCMD_HCRESET 0x0002 /* Host reset */ 21 #define USBCMD_GRESET 0x0004 /* Global reset */ 22 #define USBCMD_EGSM 0x0008 /* Global Suspend Mode */ 23 #define USBCMD_FGR 0x0010 /* Force Global Resume */ 24 #define USBCMD_SWDBG 0x0020 /* SW Debug mode */ 25 #define USBCMD_CF 0x0040 /* Config Flag (sw only) */ 26 #define USBCMD_MAXP 0x0080 /* Max Packet (0 = 32, 1 = 64) */ 27 28 /* Status register */ 29 #define USBSTS 2 30 #define USBSTS_USBINT 0x0001 /* Interrupt due to IOC */ 31 #define USBSTS_ERROR 0x0002 /* Interrupt due to error */ 32 #define USBSTS_RD 0x0004 /* Resume Detect */ 33 #define USBSTS_HSE 0x0008 /* Host System Error: PCI problems */ 34 #define USBSTS_HCPE 0x0010 /* Host Controller Process Error: 35 * the schedule is buggy */ 36 #define USBSTS_HCH 0x0020 /* HC Halted */ 37 38 /* Interrupt enable register */ 39 #define USBINTR 4 40 #define USBINTR_TIMEOUT 0x0001 /* Timeout/CRC error enable */ 41 #define USBINTR_RESUME 0x0002 /* Resume interrupt enable */ 42 #define USBINTR_IOC 0x0004 /* Interrupt On Complete enable */ 43 #define USBINTR_SP 0x0008 /* Short packet interrupt enable */ 44 45 #define USBFRNUM 6 46 #define USBFLBASEADD 8 47 #define USBSOF 12 48 #define USBSOF_DEFAULT 64 /* Frame length is exactly 1 ms */ 49 50 /* USB port status and control registers */ 51 #define USBPORTSC1 16 52 #define USBPORTSC2 18 53 #define USBPORTSC3 20 54 #define USBPORTSC4 22 55 #define USBPORTSC_CCS 0x0001 /* Current Connect Status 56 * ("device present") */ 57 #define USBPORTSC_CSC 0x0002 /* Connect Status Change */ 58 #define USBPORTSC_PE 0x0004 /* Port Enable */ 59 #define USBPORTSC_PEC 0x0008 /* Port Enable Change */ 60 #define USBPORTSC_DPLUS 0x0010 /* D+ high (line status) */ 61 #define USBPORTSC_DMINUS 0x0020 /* D- high (line status) */ 62 #define USBPORTSC_RD 0x0040 /* Resume Detect */ 63 #define USBPORTSC_RES1 0x0080 /* reserved, always 1 */ 64 #define USBPORTSC_LSDA 0x0100 /* Low Speed Device Attached */ 65 #define USBPORTSC_PR 0x0200 /* Port Reset */ 66 /* OC and OCC from Intel 430TX and later (not UHCI 1.1d spec) */ 67 #define USBPORTSC_OC 0x0400 /* Over Current condition */ 68 #define USBPORTSC_OCC 0x0800 /* Over Current Change R/WC */ 69 #define USBPORTSC_SUSP 0x1000 /* Suspend */ 70 #define USBPORTSC_RES2 0x2000 /* reserved, write zeroes */ 71 #define USBPORTSC_RES3 0x4000 /* reserved, write zeroes */ 72 #define USBPORTSC_RES4 0x8000 /* reserved, write zeroes */ 73 74 /* PCI legacy support register */ 75 #define USBLEGSUP 0xc0 76 #define USBLEGSUP_DEFAULT 0x2000 /* only PIRQ enable set */ 77 #define USBLEGSUP_RWC 0x8f00 /* the R/WC bits */ 78 #define USBLEGSUP_RO 0x5040 /* R/O and reserved bits */ 79 80 /* PCI Intel-specific resume-enable register */ 81 #define USBRES_INTEL 0xc4 82 #define USBPORT1EN 0x01 83 #define USBPORT2EN 0x02 84 85 #define UHCI_PTR_BITS(uhci) cpu_to_hc32((uhci), 0x000F) 86 #define UHCI_PTR_TERM(uhci) cpu_to_hc32((uhci), 0x0001) 87 #define UHCI_PTR_QH(uhci) cpu_to_hc32((uhci), 0x0002) 88 #define UHCI_PTR_DEPTH(uhci) cpu_to_hc32((uhci), 0x0004) 89 #define UHCI_PTR_BREADTH(uhci) cpu_to_hc32((uhci), 0x0000) 90 91 #define UHCI_NUMFRAMES 1024 /* in the frame list [array] */ 92 #define UHCI_MAX_SOF_NUMBER 2047 /* in an SOF packet */ 93 #define CAN_SCHEDULE_FRAMES 1000 /* how far in the future frames 94 * can be scheduled */ 95 #define MAX_PHASE 32 /* Periodic scheduling length */ 96 97 /* When no queues need Full-Speed Bandwidth Reclamation, 98 * delay this long before turning FSBR off */ 99 #define FSBR_OFF_DELAY msecs_to_jiffies(10) 100 101 /* If a queue hasn't advanced after this much time, assume it is stuck */ 102 #define QH_WAIT_TIMEOUT msecs_to_jiffies(200) 103 104 105 /* 106 * __hc32 and __hc16 are "Host Controller" types, they may be equivalent to 107 * __leXX (normally) or __beXX (given UHCI_BIG_ENDIAN_DESC), depending on 108 * the host controller implementation. 109 * 110 * To facilitate the strongest possible byte-order checking from "sparse" 111 * and so on, we use __leXX unless that's not practical. 112 */ 113 #ifdef CONFIG_USB_UHCI_BIG_ENDIAN_DESC 114 typedef __u32 __bitwise __hc32; 115 typedef __u16 __bitwise __hc16; 116 #else 117 #define __hc32 __le32 118 #define __hc16 __le16 119 #endif 120 121 /* 122 * Queue Headers 123 */ 124 125 /* 126 * One role of a QH is to hold a queue of TDs for some endpoint. One QH goes 127 * with each endpoint, and qh->element (updated by the HC) is either: 128 * - the next unprocessed TD in the endpoint's queue, or 129 * - UHCI_PTR_TERM (when there's no more traffic for this endpoint). 130 * 131 * The other role of a QH is to serve as a "skeleton" framelist entry, so we 132 * can easily splice a QH for some endpoint into the schedule at the right 133 * place. Then qh->element is UHCI_PTR_TERM. 134 * 135 * In the schedule, qh->link maintains a list of QHs seen by the HC: 136 * skel1 --> ep1-qh --> ep2-qh --> ... --> skel2 --> ... 137 * 138 * qh->node is the software equivalent of qh->link. The differences 139 * are that the software list is doubly-linked and QHs in the UNLINKING 140 * state are on the software list but not the hardware schedule. 141 * 142 * For bookkeeping purposes we maintain QHs even for Isochronous endpoints, 143 * but they never get added to the hardware schedule. 144 */ 145 #define QH_STATE_IDLE 1 /* QH is not being used */ 146 #define QH_STATE_UNLINKING 2 /* QH has been removed from the 147 * schedule but the hardware may 148 * still be using it */ 149 #define QH_STATE_ACTIVE 3 /* QH is on the schedule */ 150 151 struct uhci_qh { 152 /* Hardware fields */ 153 __hc32 link; /* Next QH in the schedule */ 154 __hc32 element; /* Queue element (TD) pointer */ 155 156 /* Software fields */ 157 dma_addr_t dma_handle; 158 159 struct list_head node; /* Node in the list of QHs */ 160 struct usb_host_endpoint *hep; /* Endpoint information */ 161 struct usb_device *udev; 162 struct list_head queue; /* Queue of urbps for this QH */ 163 struct uhci_td *dummy_td; /* Dummy TD to end the queue */ 164 struct uhci_td *post_td; /* Last TD completed */ 165 166 struct usb_iso_packet_descriptor *iso_packet_desc; 167 /* Next urb->iso_frame_desc entry */ 168 unsigned long advance_jiffies; /* Time of last queue advance */ 169 unsigned int unlink_frame; /* When the QH was unlinked */ 170 unsigned int period; /* For Interrupt and Isochronous QHs */ 171 short phase; /* Between 0 and period-1 */ 172 short load; /* Periodic time requirement, in us */ 173 unsigned int iso_frame; /* Frame # for iso_packet_desc */ 174 175 int state; /* QH_STATE_xxx; see above */ 176 int type; /* Queue type (control, bulk, etc) */ 177 int skel; /* Skeleton queue number */ 178 179 unsigned int initial_toggle:1; /* Endpoint's current toggle value */ 180 unsigned int needs_fixup:1; /* Must fix the TD toggle values */ 181 unsigned int is_stopped:1; /* Queue was stopped by error/unlink */ 182 unsigned int wait_expired:1; /* QH_WAIT_TIMEOUT has expired */ 183 unsigned int bandwidth_reserved:1; /* Periodic bandwidth has 184 * been allocated */ 185 } __attribute__((aligned(16))); 186 187 /* 188 * We need a special accessor for the element pointer because it is 189 * subject to asynchronous updates by the controller. 190 */ 191 #define qh_element(qh) READ_ONCE((qh)->element) 192 193 #define LINK_TO_QH(uhci, qh) (UHCI_PTR_QH((uhci)) | \ 194 cpu_to_hc32((uhci), (qh)->dma_handle)) 195 196 197 /* 198 * Transfer Descriptors 199 */ 200 201 /* 202 * for TD <status>: 203 */ 204 #define TD_CTRL_SPD (1 << 29) /* Short Packet Detect */ 205 #define TD_CTRL_C_ERR_MASK (3 << 27) /* Error Counter bits */ 206 #define TD_CTRL_C_ERR_SHIFT 27 207 #define TD_CTRL_LS (1 << 26) /* Low Speed Device */ 208 #define TD_CTRL_IOS (1 << 25) /* Isochronous Select */ 209 #define TD_CTRL_IOC (1 << 24) /* Interrupt on Complete */ 210 #define TD_CTRL_ACTIVE (1 << 23) /* TD Active */ 211 #define TD_CTRL_STALLED (1 << 22) /* TD Stalled */ 212 #define TD_CTRL_DBUFERR (1 << 21) /* Data Buffer Error */ 213 #define TD_CTRL_BABBLE (1 << 20) /* Babble Detected */ 214 #define TD_CTRL_NAK (1 << 19) /* NAK Received */ 215 #define TD_CTRL_CRCTIMEO (1 << 18) /* CRC/Time Out Error */ 216 #define TD_CTRL_BITSTUFF (1 << 17) /* Bit Stuff Error */ 217 #define TD_CTRL_ACTLEN_MASK 0x7FF /* actual length, encoded as n - 1 */ 218 219 #define uhci_maxerr(err) ((err) << TD_CTRL_C_ERR_SHIFT) 220 #define uhci_status_bits(ctrl_sts) ((ctrl_sts) & 0xF60000) 221 #define uhci_actual_length(ctrl_sts) (((ctrl_sts) + 1) & \ 222 TD_CTRL_ACTLEN_MASK) /* 1-based */ 223 224 /* 225 * for TD <info>: (a.k.a. Token) 226 */ 227 #define td_token(uhci, td) hc32_to_cpu((uhci), (td)->token) 228 #define TD_TOKEN_DEVADDR_SHIFT 8 229 #define TD_TOKEN_TOGGLE_SHIFT 19 230 #define TD_TOKEN_TOGGLE (1 << 19) 231 #define TD_TOKEN_EXPLEN_SHIFT 21 232 #define TD_TOKEN_EXPLEN_MASK 0x7FF /* expected length, encoded as n-1 */ 233 #define TD_TOKEN_PID_MASK 0xFF 234 235 #define uhci_explen(len) ((((len) - 1) & TD_TOKEN_EXPLEN_MASK) << \ 236 TD_TOKEN_EXPLEN_SHIFT) 237 238 #define uhci_expected_length(token) ((((token) >> TD_TOKEN_EXPLEN_SHIFT) + \ 239 1) & TD_TOKEN_EXPLEN_MASK) 240 #define uhci_toggle(token) (((token) >> TD_TOKEN_TOGGLE_SHIFT) & 1) 241 #define uhci_endpoint(token) (((token) >> 15) & 0xf) 242 #define uhci_devaddr(token) (((token) >> TD_TOKEN_DEVADDR_SHIFT) & 0x7f) 243 #define uhci_devep(token) (((token) >> TD_TOKEN_DEVADDR_SHIFT) & 0x7ff) 244 #define uhci_packetid(token) ((token) & TD_TOKEN_PID_MASK) 245 #define uhci_packetout(token) (uhci_packetid(token) != USB_PID_IN) 246 #define uhci_packetin(token) (uhci_packetid(token) == USB_PID_IN) 247 248 /* 249 * The documentation says "4 words for hardware, 4 words for software". 250 * 251 * That's silly, the hardware doesn't care. The hardware only cares that 252 * the hardware words are 16-byte aligned, and we can have any amount of 253 * sw space after the TD entry. 254 * 255 * td->link points to either another TD (not necessarily for the same urb or 256 * even the same endpoint), or nothing (PTR_TERM), or a QH. 257 */ 258 struct uhci_td { 259 /* Hardware fields */ 260 __hc32 link; 261 __hc32 status; 262 __hc32 token; 263 __hc32 buffer; 264 265 /* Software fields */ 266 dma_addr_t dma_handle; 267 268 struct list_head list; 269 270 int frame; /* for iso: what frame? */ 271 struct list_head fl_list; 272 } __attribute__((aligned(16))); 273 274 /* 275 * We need a special accessor for the control/status word because it is 276 * subject to asynchronous updates by the controller. 277 */ 278 #define td_status(uhci, td) hc32_to_cpu((uhci), \ 279 READ_ONCE((td)->status)) 280 281 #define LINK_TO_TD(uhci, td) (cpu_to_hc32((uhci), (td)->dma_handle)) 282 283 284 /* 285 * Skeleton Queue Headers 286 */ 287 288 /* 289 * The UHCI driver uses QHs with Interrupt, Control and Bulk URBs for 290 * automatic queuing. To make it easy to insert entries into the schedule, 291 * we have a skeleton of QHs for each predefined Interrupt latency. 292 * Asynchronous QHs (low-speed control, full-speed control, and bulk) 293 * go onto the period-1 interrupt list, since they all get accessed on 294 * every frame. 295 * 296 * When we want to add a new QH, we add it to the list starting from the 297 * appropriate skeleton QH. For instance, the schedule can look like this: 298 * 299 * skel int128 QH 300 * dev 1 interrupt QH 301 * dev 5 interrupt QH 302 * skel int64 QH 303 * skel int32 QH 304 * ... 305 * skel int1 + async QH 306 * dev 5 low-speed control QH 307 * dev 1 bulk QH 308 * dev 2 bulk QH 309 * 310 * There is a special terminating QH used to keep full-speed bandwidth 311 * reclamation active when no full-speed control or bulk QHs are linked 312 * into the schedule. It has an inactive TD (to work around a PIIX bug, 313 * see the Intel errata) and it points back to itself. 314 * 315 * There's a special skeleton QH for Isochronous QHs which never appears 316 * on the schedule. Isochronous TDs go on the schedule before the 317 * skeleton QHs. The hardware accesses them directly rather than 318 * through their QH, which is used only for bookkeeping purposes. 319 * While the UHCI spec doesn't forbid the use of QHs for Isochronous, 320 * it doesn't use them either. And the spec says that queues never 321 * advance on an error completion status, which makes them totally 322 * unsuitable for Isochronous transfers. 323 * 324 * There's also a special skeleton QH used for QHs which are in the process 325 * of unlinking and so may still be in use by the hardware. It too never 326 * appears on the schedule. 327 */ 328 329 #define UHCI_NUM_SKELQH 11 330 #define SKEL_UNLINK 0 331 #define skel_unlink_qh skelqh[SKEL_UNLINK] 332 #define SKEL_ISO 1 333 #define skel_iso_qh skelqh[SKEL_ISO] 334 /* int128, int64, ..., int1 = 2, 3, ..., 9 */ 335 #define SKEL_INDEX(exponent) (9 - exponent) 336 #define SKEL_ASYNC 9 337 #define skel_async_qh skelqh[SKEL_ASYNC] 338 #define SKEL_TERM 10 339 #define skel_term_qh skelqh[SKEL_TERM] 340 341 /* The following entries refer to sublists of skel_async_qh */ 342 #define SKEL_LS_CONTROL 20 343 #define SKEL_FS_CONTROL 21 344 #define SKEL_FSBR SKEL_FS_CONTROL 345 #define SKEL_BULK 22 346 347 /* 348 * The UHCI controller and root hub 349 */ 350 351 /* 352 * States for the root hub: 353 * 354 * To prevent "bouncing" in the presence of electrical noise, 355 * when there are no devices attached we delay for 1 second in the 356 * RUNNING_NODEVS state before switching to the AUTO_STOPPED state. 357 * 358 * (Note that the AUTO_STOPPED state won't be necessary once the hub 359 * driver learns to autosuspend.) 360 */ 361 enum uhci_rh_state { 362 /* In the following states the HC must be halted. 363 * These two must come first. */ 364 UHCI_RH_RESET, 365 UHCI_RH_SUSPENDED, 366 367 UHCI_RH_AUTO_STOPPED, 368 UHCI_RH_RESUMING, 369 370 /* In this state the HC changes from running to halted, 371 * so it can legally appear either way. */ 372 UHCI_RH_SUSPENDING, 373 374 /* In the following states it's an error if the HC is halted. 375 * These two must come last. */ 376 UHCI_RH_RUNNING, /* The normal state */ 377 UHCI_RH_RUNNING_NODEVS, /* Running with no devices attached */ 378 }; 379 380 /* 381 * The full UHCI controller information: 382 */ 383 struct uhci_hcd { 384 /* Grabbed from PCI */ 385 unsigned long io_addr; 386 387 /* Used when registers are memory mapped */ 388 void __iomem *regs; 389 390 struct dma_pool *qh_pool; 391 struct dma_pool *td_pool; 392 393 struct uhci_td *term_td; /* Terminating TD, see UHCI bug */ 394 struct uhci_qh *skelqh[UHCI_NUM_SKELQH]; /* Skeleton QHs */ 395 struct uhci_qh *next_qh; /* Next QH to scan */ 396 397 spinlock_t lock; 398 399 dma_addr_t frame_dma_handle; /* Hardware frame list */ 400 __hc32 *frame; 401 void **frame_cpu; /* CPU's frame list */ 402 403 enum uhci_rh_state rh_state; 404 unsigned long auto_stop_time; /* When to AUTO_STOP */ 405 406 unsigned int frame_number; /* As of last check */ 407 unsigned int is_stopped; 408 #define UHCI_IS_STOPPED 9999 /* Larger than a frame # */ 409 unsigned int last_iso_frame; /* Frame of last scan */ 410 unsigned int cur_iso_frame; /* Frame for current scan */ 411 412 unsigned int scan_in_progress:1; /* Schedule scan is running */ 413 unsigned int need_rescan:1; /* Redo the schedule scan */ 414 unsigned int dead:1; /* Controller has died */ 415 unsigned int RD_enable:1; /* Suspended root hub with 416 Resume-Detect interrupts 417 enabled */ 418 unsigned int is_initialized:1; /* Data structure is usable */ 419 unsigned int fsbr_is_on:1; /* FSBR is turned on */ 420 unsigned int fsbr_is_wanted:1; /* Does any URB want FSBR? */ 421 unsigned int fsbr_expiring:1; /* FSBR is timing out */ 422 423 struct timer_list fsbr_timer; /* For turning off FBSR */ 424 425 /* Silicon quirks */ 426 unsigned int oc_low:1; /* OverCurrent bit active low */ 427 unsigned int wait_for_hp:1; /* Wait for HP port reset */ 428 unsigned int big_endian_mmio:1; /* Big endian registers */ 429 unsigned int big_endian_desc:1; /* Big endian descriptors */ 430 unsigned int is_aspeed:1; /* Aspeed impl. workarounds */ 431 432 /* Support for port suspend/resume/reset */ 433 unsigned long port_c_suspend; /* Bit-arrays of ports */ 434 unsigned long resuming_ports; 435 unsigned long ports_timeout; /* Time to stop signalling */ 436 437 struct list_head idle_qh_list; /* Where the idle QHs live */ 438 439 int rh_numports; /* Number of root-hub ports */ 440 441 wait_queue_head_t waitqh; /* endpoint_disable waiters */ 442 int num_waiting; /* Number of waiters */ 443 444 int total_load; /* Sum of array values */ 445 short load[MAX_PHASE]; /* Periodic allocations */ 446 447 struct clk *clk; /* (optional) clock source */ 448 449 /* Reset host controller */ 450 void (*reset_hc) (struct uhci_hcd *uhci); 451 int (*check_and_reset_hc) (struct uhci_hcd *uhci); 452 /* configure_hc should perform arch specific settings, if needed */ 453 void (*configure_hc) (struct uhci_hcd *uhci); 454 /* Check for broken resume detect interrupts */ 455 int (*resume_detect_interrupts_are_broken) (struct uhci_hcd *uhci); 456 /* Check for broken global suspend */ 457 int (*global_suspend_mode_is_broken) (struct uhci_hcd *uhci); 458 }; 459 460 /* Convert between a usb_hcd pointer and the corresponding uhci_hcd */ hcd_to_uhci(struct usb_hcd * hcd)461 static inline struct uhci_hcd *hcd_to_uhci(struct usb_hcd *hcd) 462 { 463 return (struct uhci_hcd *) (hcd->hcd_priv); 464 } uhci_to_hcd(struct uhci_hcd * uhci)465 static inline struct usb_hcd *uhci_to_hcd(struct uhci_hcd *uhci) 466 { 467 return container_of((void *) uhci, struct usb_hcd, hcd_priv); 468 } 469 470 #define uhci_dev(u) (uhci_to_hcd(u)->self.controller) 471 472 /* Utility macro for comparing frame numbers */ 473 #define uhci_frame_before_eq(f1, f2) (0 <= (int) ((f2) - (f1))) 474 475 476 /* 477 * Private per-URB data 478 */ 479 struct urb_priv { 480 struct list_head node; /* Node in the QH's urbp list */ 481 482 struct urb *urb; 483 484 struct uhci_qh *qh; /* QH for this URB */ 485 struct list_head td_list; 486 487 unsigned fsbr:1; /* URB wants FSBR */ 488 }; 489 490 491 /* Some special IDs */ 492 493 #define PCI_VENDOR_ID_GENESYS 0x17a0 494 #define PCI_DEVICE_ID_GL880S_UHCI 0x8083 495 496 /* Aspeed SoC needs some quirks */ uhci_is_aspeed(const struct uhci_hcd * uhci)497 static inline bool uhci_is_aspeed(const struct uhci_hcd *uhci) 498 { 499 return IS_ENABLED(CONFIG_USB_UHCI_ASPEED) && uhci->is_aspeed; 500 } 501 502 /* 503 * Functions used to access controller registers. The UCHI spec says that host 504 * controller I/O registers are mapped into PCI I/O space. For non-PCI hosts 505 * we use memory mapped registers. 506 */ 507 508 #ifndef CONFIG_USB_UHCI_SUPPORT_NON_PCI_HC 509 /* Support PCI only */ uhci_readl(const struct uhci_hcd * uhci,int reg)510 static inline u32 uhci_readl(const struct uhci_hcd *uhci, int reg) 511 { 512 return inl(uhci->io_addr + reg); 513 } 514 uhci_writel(const struct uhci_hcd * uhci,u32 val,int reg)515 static inline void uhci_writel(const struct uhci_hcd *uhci, u32 val, int reg) 516 { 517 outl(val, uhci->io_addr + reg); 518 } 519 uhci_readw(const struct uhci_hcd * uhci,int reg)520 static inline u16 uhci_readw(const struct uhci_hcd *uhci, int reg) 521 { 522 return inw(uhci->io_addr + reg); 523 } 524 uhci_writew(const struct uhci_hcd * uhci,u16 val,int reg)525 static inline void uhci_writew(const struct uhci_hcd *uhci, u16 val, int reg) 526 { 527 outw(val, uhci->io_addr + reg); 528 } 529 uhci_readb(const struct uhci_hcd * uhci,int reg)530 static inline u8 uhci_readb(const struct uhci_hcd *uhci, int reg) 531 { 532 return inb(uhci->io_addr + reg); 533 } 534 uhci_writeb(const struct uhci_hcd * uhci,u8 val,int reg)535 static inline void uhci_writeb(const struct uhci_hcd *uhci, u8 val, int reg) 536 { 537 outb(val, uhci->io_addr + reg); 538 } 539 540 #else 541 /* Support non-PCI host controllers */ 542 #ifdef CONFIG_USB_PCI 543 /* Support PCI and non-PCI host controllers */ 544 #define uhci_has_pci_registers(u) ((u)->io_addr != 0) 545 #else 546 /* Support non-PCI host controllers only */ 547 #define uhci_has_pci_registers(u) 0 548 #endif 549 550 #ifdef CONFIG_USB_UHCI_BIG_ENDIAN_MMIO 551 /* Support (non-PCI) big endian host controllers */ 552 #define uhci_big_endian_mmio(u) ((u)->big_endian_mmio) 553 #else 554 #define uhci_big_endian_mmio(u) 0 555 #endif 556 uhci_aspeed_reg(unsigned int reg)557 static inline int uhci_aspeed_reg(unsigned int reg) 558 { 559 switch (reg) { 560 case USBCMD: 561 return 00; 562 case USBSTS: 563 return 0x04; 564 case USBINTR: 565 return 0x08; 566 case USBFRNUM: 567 return 0x80; 568 case USBFLBASEADD: 569 return 0x0c; 570 case USBSOF: 571 return 0x84; 572 case USBPORTSC1: 573 return 0x88; 574 case USBPORTSC2: 575 return 0x8c; 576 case USBPORTSC3: 577 return 0x90; 578 case USBPORTSC4: 579 return 0x94; 580 default: 581 pr_warn("UHCI: Unsupported register 0x%02x on Aspeed\n", reg); 582 /* Return an unimplemented register */ 583 return 0x10; 584 } 585 } 586 uhci_readl(const struct uhci_hcd * uhci,int reg)587 static inline u32 uhci_readl(const struct uhci_hcd *uhci, int reg) 588 { 589 if (uhci_has_pci_registers(uhci)) 590 return inl(uhci->io_addr + reg); 591 else if (uhci_is_aspeed(uhci)) 592 return readl(uhci->regs + uhci_aspeed_reg(reg)); 593 #ifdef CONFIG_USB_UHCI_BIG_ENDIAN_MMIO 594 else if (uhci_big_endian_mmio(uhci)) 595 return readl_be(uhci->regs + reg); 596 #endif 597 else 598 return readl(uhci->regs + reg); 599 } 600 uhci_writel(const struct uhci_hcd * uhci,u32 val,int reg)601 static inline void uhci_writel(const struct uhci_hcd *uhci, u32 val, int reg) 602 { 603 if (uhci_has_pci_registers(uhci)) 604 outl(val, uhci->io_addr + reg); 605 else if (uhci_is_aspeed(uhci)) 606 writel(val, uhci->regs + uhci_aspeed_reg(reg)); 607 #ifdef CONFIG_USB_UHCI_BIG_ENDIAN_MMIO 608 else if (uhci_big_endian_mmio(uhci)) 609 writel_be(val, uhci->regs + reg); 610 #endif 611 else 612 writel(val, uhci->regs + reg); 613 } 614 uhci_readw(const struct uhci_hcd * uhci,int reg)615 static inline u16 uhci_readw(const struct uhci_hcd *uhci, int reg) 616 { 617 if (uhci_has_pci_registers(uhci)) 618 return inw(uhci->io_addr + reg); 619 else if (uhci_is_aspeed(uhci)) 620 return readl(uhci->regs + uhci_aspeed_reg(reg)); 621 #ifdef CONFIG_USB_UHCI_BIG_ENDIAN_MMIO 622 else if (uhci_big_endian_mmio(uhci)) 623 return readw_be(uhci->regs + reg); 624 #endif 625 else 626 return readw(uhci->regs + reg); 627 } 628 uhci_writew(const struct uhci_hcd * uhci,u16 val,int reg)629 static inline void uhci_writew(const struct uhci_hcd *uhci, u16 val, int reg) 630 { 631 if (uhci_has_pci_registers(uhci)) 632 outw(val, uhci->io_addr + reg); 633 else if (uhci_is_aspeed(uhci)) 634 writel(val, uhci->regs + uhci_aspeed_reg(reg)); 635 #ifdef CONFIG_USB_UHCI_BIG_ENDIAN_MMIO 636 else if (uhci_big_endian_mmio(uhci)) 637 writew_be(val, uhci->regs + reg); 638 #endif 639 else 640 writew(val, uhci->regs + reg); 641 } 642 uhci_readb(const struct uhci_hcd * uhci,int reg)643 static inline u8 uhci_readb(const struct uhci_hcd *uhci, int reg) 644 { 645 if (uhci_has_pci_registers(uhci)) 646 return inb(uhci->io_addr + reg); 647 else if (uhci_is_aspeed(uhci)) 648 return readl(uhci->regs + uhci_aspeed_reg(reg)); 649 #ifdef CONFIG_USB_UHCI_BIG_ENDIAN_MMIO 650 else if (uhci_big_endian_mmio(uhci)) 651 return readb_be(uhci->regs + reg); 652 #endif 653 else 654 return readb(uhci->regs + reg); 655 } 656 uhci_writeb(const struct uhci_hcd * uhci,u8 val,int reg)657 static inline void uhci_writeb(const struct uhci_hcd *uhci, u8 val, int reg) 658 { 659 if (uhci_has_pci_registers(uhci)) 660 outb(val, uhci->io_addr + reg); 661 else if (uhci_is_aspeed(uhci)) 662 writel(val, uhci->regs + uhci_aspeed_reg(reg)); 663 #ifdef CONFIG_USB_UHCI_BIG_ENDIAN_MMIO 664 else if (uhci_big_endian_mmio(uhci)) 665 writeb_be(val, uhci->regs + reg); 666 #endif 667 else 668 writeb(val, uhci->regs + reg); 669 } 670 #endif /* CONFIG_USB_UHCI_SUPPORT_NON_PCI_HC */ 671 672 /* 673 * The GRLIB GRUSBHC controller can use big endian format for its descriptors. 674 * 675 * UHCI controllers accessed through PCI work normally (little-endian 676 * everywhere), so we don't bother supporting a BE-only mode. 677 */ 678 #ifdef CONFIG_USB_UHCI_BIG_ENDIAN_DESC 679 #define uhci_big_endian_desc(u) ((u)->big_endian_desc) 680 681 /* cpu to uhci */ cpu_to_hc32(const struct uhci_hcd * uhci,const u32 x)682 static inline __hc32 cpu_to_hc32(const struct uhci_hcd *uhci, const u32 x) 683 { 684 return uhci_big_endian_desc(uhci) 685 ? (__force __hc32)cpu_to_be32(x) 686 : (__force __hc32)cpu_to_le32(x); 687 } 688 689 /* uhci to cpu */ hc32_to_cpu(const struct uhci_hcd * uhci,const __hc32 x)690 static inline u32 hc32_to_cpu(const struct uhci_hcd *uhci, const __hc32 x) 691 { 692 return uhci_big_endian_desc(uhci) 693 ? be32_to_cpu((__force __be32)x) 694 : le32_to_cpu((__force __le32)x); 695 } 696 697 #else 698 /* cpu to uhci */ cpu_to_hc32(const struct uhci_hcd * uhci,const u32 x)699 static inline __hc32 cpu_to_hc32(const struct uhci_hcd *uhci, const u32 x) 700 { 701 return cpu_to_le32(x); 702 } 703 704 /* uhci to cpu */ hc32_to_cpu(const struct uhci_hcd * uhci,const __hc32 x)705 static inline u32 hc32_to_cpu(const struct uhci_hcd *uhci, const __hc32 x) 706 { 707 return le32_to_cpu(x); 708 } 709 #endif 710 711 #endif 712
