1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Driver for PowerMac Z85c30 based ESCC cell found in the
4 * "macio" ASICs of various PowerMac models
5 *
6 * Copyright (C) 2003 Ben. Herrenschmidt (benh@kernel.crashing.org)
7 *
8 * Derived from drivers/macintosh/macserial.c by Paul Mackerras
9 * and drivers/serial/sunzilog.c by David S. Miller
10 *
11 * Hrm... actually, I ripped most of sunzilog (Thanks David !) and
12 * adapted special tweaks needed for us. I don't think it's worth
13 * merging back those though. The DMA code still has to get in
14 * and once done, I expect that driver to remain fairly stable in
15 * the long term, unless we change the driver model again...
16 *
17 * 2004-08-06 Harald Welte <laforge@gnumonks.org>
18 * - Enable BREAK interrupt
19 * - Add support for sysreq
20 *
21 * TODO: - Add DMA support
22 * - Defer port shutdown to a few seconds after close
23 * - maybe put something right into uap->clk_divisor
24 */
25
26 #undef DEBUG
27 #undef USE_CTRL_O_SYSRQ
28
29 #include <linux/module.h>
30 #include <linux/tty.h>
31
32 #include <linux/tty_flip.h>
33 #include <linux/major.h>
34 #include <linux/string.h>
35 #include <linux/fcntl.h>
36 #include <linux/mm.h>
37 #include <linux/kernel.h>
38 #include <linux/delay.h>
39 #include <linux/init.h>
40 #include <linux/console.h>
41 #include <linux/adb.h>
42 #include <linux/pmu.h>
43 #include <linux/bitops.h>
44 #include <linux/sysrq.h>
45 #include <linux/mutex.h>
46 #include <linux/of_address.h>
47 #include <linux/of_irq.h>
48 #include <asm/sections.h>
49 #include <linux/io.h>
50 #include <asm/irq.h>
51
52 #ifdef CONFIG_PPC_PMAC
53 #include <asm/machdep.h>
54 #include <asm/pmac_feature.h>
55 #include <asm/macio.h>
56 #else
57 #include <linux/platform_device.h>
58 #define of_machine_is_compatible(x) (0)
59 #endif
60
61 #include <linux/serial.h>
62 #include <linux/serial_core.h>
63
64 #include "pmac_zilog.h"
65
66 MODULE_AUTHOR("Benjamin Herrenschmidt <benh@kernel.crashing.org>");
67 MODULE_DESCRIPTION("Driver for the Mac and PowerMac serial ports.");
68 MODULE_LICENSE("GPL");
69
70 #ifdef CONFIG_SERIAL_PMACZILOG_TTYS
71 #define PMACZILOG_MAJOR TTY_MAJOR
72 #define PMACZILOG_MINOR 64
73 #define PMACZILOG_NAME "ttyS"
74 #else
75 #define PMACZILOG_MAJOR 204
76 #define PMACZILOG_MINOR 192
77 #define PMACZILOG_NAME "ttyPZ"
78 #endif
79
80 #define pmz_debug(fmt, arg...) pr_debug("ttyPZ%d: " fmt, uap->port.line, ## arg)
81 #define pmz_error(fmt, arg...) pr_err("ttyPZ%d: " fmt, uap->port.line, ## arg)
82 #define pmz_info(fmt, arg...) pr_info("ttyPZ%d: " fmt, uap->port.line, ## arg)
83
84 /*
85 * For the sake of early serial console, we can do a pre-probe
86 * (optional) of the ports at rather early boot time.
87 */
88 static struct uart_pmac_port pmz_ports[MAX_ZS_PORTS];
89 static int pmz_ports_count;
90
91 static struct uart_driver pmz_uart_reg = {
92 .owner = THIS_MODULE,
93 .driver_name = PMACZILOG_NAME,
94 .dev_name = PMACZILOG_NAME,
95 .major = PMACZILOG_MAJOR,
96 .minor = PMACZILOG_MINOR,
97 };
98
99
100 /*
101 * Load all registers to reprogram the port
102 * This function must only be called when the TX is not busy. The UART
103 * port lock must be held and local interrupts disabled.
104 */
pmz_load_zsregs(struct uart_pmac_port * uap,u8 * regs)105 static void pmz_load_zsregs(struct uart_pmac_port *uap, u8 *regs)
106 {
107 int i;
108
109 /* Let pending transmits finish. */
110 for (i = 0; i < 1000; i++) {
111 unsigned char stat = read_zsreg(uap, R1);
112 if (stat & ALL_SNT)
113 break;
114 udelay(100);
115 }
116
117 ZS_CLEARERR(uap);
118 zssync(uap);
119 ZS_CLEARFIFO(uap);
120 zssync(uap);
121 ZS_CLEARERR(uap);
122
123 /* Disable all interrupts. */
124 write_zsreg(uap, R1,
125 regs[R1] & ~(RxINT_MASK | TxINT_ENAB | EXT_INT_ENAB));
126
127 /* Set parity, sync config, stop bits, and clock divisor. */
128 write_zsreg(uap, R4, regs[R4]);
129
130 /* Set misc. TX/RX control bits. */
131 write_zsreg(uap, R10, regs[R10]);
132
133 /* Set TX/RX controls sans the enable bits. */
134 write_zsreg(uap, R3, regs[R3] & ~RxENABLE);
135 write_zsreg(uap, R5, regs[R5] & ~TxENABLE);
136
137 /* now set R7 "prime" on ESCC */
138 write_zsreg(uap, R15, regs[R15] | EN85C30);
139 write_zsreg(uap, R7, regs[R7P]);
140
141 /* make sure we use R7 "non-prime" on ESCC */
142 write_zsreg(uap, R15, regs[R15] & ~EN85C30);
143
144 /* Synchronous mode config. */
145 write_zsreg(uap, R6, regs[R6]);
146 write_zsreg(uap, R7, regs[R7]);
147
148 /* Disable baud generator. */
149 write_zsreg(uap, R14, regs[R14] & ~BRENAB);
150
151 /* Clock mode control. */
152 write_zsreg(uap, R11, regs[R11]);
153
154 /* Lower and upper byte of baud rate generator divisor. */
155 write_zsreg(uap, R12, regs[R12]);
156 write_zsreg(uap, R13, regs[R13]);
157
158 /* Now rewrite R14, with BRENAB (if set). */
159 write_zsreg(uap, R14, regs[R14]);
160
161 /* Reset external status interrupts. */
162 write_zsreg(uap, R0, RES_EXT_INT);
163 write_zsreg(uap, R0, RES_EXT_INT);
164
165 /* Rewrite R3/R5, this time without enables masked. */
166 write_zsreg(uap, R3, regs[R3]);
167 write_zsreg(uap, R5, regs[R5]);
168
169 /* Rewrite R1, this time without IRQ enabled masked. */
170 write_zsreg(uap, R1, regs[R1]);
171
172 /* Enable interrupts */
173 write_zsreg(uap, R9, regs[R9]);
174 }
175
176 /*
177 * We do like sunzilog to avoid disrupting pending Tx
178 * Reprogram the Zilog channel HW registers with the copies found in the
179 * software state struct. If the transmitter is busy, we defer this update
180 * until the next TX complete interrupt. Else, we do it right now.
181 *
182 * The UART port lock must be held and local interrupts disabled.
183 */
pmz_maybe_update_regs(struct uart_pmac_port * uap)184 static void pmz_maybe_update_regs(struct uart_pmac_port *uap)
185 {
186 if (!ZS_REGS_HELD(uap)) {
187 if (ZS_TX_ACTIVE(uap)) {
188 uap->flags |= PMACZILOG_FLAG_REGS_HELD;
189 } else {
190 pmz_debug("pmz: maybe_update_regs: updating\n");
191 pmz_load_zsregs(uap, uap->curregs);
192 }
193 }
194 }
195
pmz_interrupt_control(struct uart_pmac_port * uap,int enable)196 static void pmz_interrupt_control(struct uart_pmac_port *uap, int enable)
197 {
198 if (enable) {
199 uap->curregs[1] |= INT_ALL_Rx | TxINT_ENAB;
200 if (!ZS_IS_EXTCLK(uap))
201 uap->curregs[1] |= EXT_INT_ENAB;
202 } else {
203 uap->curregs[1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK);
204 }
205 write_zsreg(uap, R1, uap->curregs[1]);
206 }
207
pmz_receive_chars(struct uart_pmac_port * uap)208 static bool pmz_receive_chars(struct uart_pmac_port *uap)
209 __must_hold(&uap->port.lock)
210 {
211 struct tty_port *port;
212 unsigned char ch, r1, drop, flag;
213 int loops = 0;
214
215 /* Sanity check, make sure the old bug is no longer happening */
216 if (uap->port.state == NULL) {
217 WARN_ON(1);
218 (void)read_zsdata(uap);
219 return false;
220 }
221 port = &uap->port.state->port;
222
223 while (1) {
224 drop = 0;
225
226 r1 = read_zsreg(uap, R1);
227 ch = read_zsdata(uap);
228
229 if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR)) {
230 write_zsreg(uap, R0, ERR_RES);
231 zssync(uap);
232 }
233
234 ch &= uap->parity_mask;
235 if (ch == 0 && uap->flags & PMACZILOG_FLAG_BREAK) {
236 uap->flags &= ~PMACZILOG_FLAG_BREAK;
237 }
238
239 #if defined(CONFIG_MAGIC_SYSRQ) && defined(CONFIG_SERIAL_CORE_CONSOLE)
240 #ifdef USE_CTRL_O_SYSRQ
241 /* Handle the SysRq ^O Hack */
242 if (ch == '\x0f') {
243 uap->port.sysrq = jiffies + HZ*5;
244 goto next_char;
245 }
246 #endif /* USE_CTRL_O_SYSRQ */
247 if (uap->port.sysrq) {
248 int swallow;
249 spin_unlock(&uap->port.lock);
250 swallow = uart_handle_sysrq_char(&uap->port, ch);
251 spin_lock(&uap->port.lock);
252 if (swallow)
253 goto next_char;
254 }
255 #endif /* CONFIG_MAGIC_SYSRQ && CONFIG_SERIAL_CORE_CONSOLE */
256
257 /* A real serial line, record the character and status. */
258 if (drop)
259 goto next_char;
260
261 flag = TTY_NORMAL;
262 uap->port.icount.rx++;
263
264 if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR | BRK_ABRT)) {
265 if (r1 & BRK_ABRT) {
266 pmz_debug("pmz: got break !\n");
267 r1 &= ~(PAR_ERR | CRC_ERR);
268 uap->port.icount.brk++;
269 if (uart_handle_break(&uap->port))
270 goto next_char;
271 }
272 else if (r1 & PAR_ERR)
273 uap->port.icount.parity++;
274 else if (r1 & CRC_ERR)
275 uap->port.icount.frame++;
276 if (r1 & Rx_OVR)
277 uap->port.icount.overrun++;
278 r1 &= uap->port.read_status_mask;
279 if (r1 & BRK_ABRT)
280 flag = TTY_BREAK;
281 else if (r1 & PAR_ERR)
282 flag = TTY_PARITY;
283 else if (r1 & CRC_ERR)
284 flag = TTY_FRAME;
285 }
286
287 if (uap->port.ignore_status_mask == 0xff ||
288 (r1 & uap->port.ignore_status_mask) == 0) {
289 tty_insert_flip_char(port, ch, flag);
290 }
291 if (r1 & Rx_OVR)
292 tty_insert_flip_char(port, 0, TTY_OVERRUN);
293 next_char:
294 /* We can get stuck in an infinite loop getting char 0 when the
295 * line is in a wrong HW state, we break that here.
296 * When that happens, I disable the receive side of the driver.
297 * Note that what I've been experiencing is a real irq loop where
298 * I'm getting flooded regardless of the actual port speed.
299 * Something strange is going on with the HW
300 */
301 if ((++loops) > 1000)
302 goto flood;
303 ch = read_zsreg(uap, R0);
304 if (!(ch & Rx_CH_AV))
305 break;
306 }
307
308 return true;
309 flood:
310 pmz_interrupt_control(uap, 0);
311 pmz_error("pmz: rx irq flood !\n");
312 return true;
313 }
314
pmz_status_handle(struct uart_pmac_port * uap)315 static void pmz_status_handle(struct uart_pmac_port *uap)
316 {
317 unsigned char status;
318
319 status = read_zsreg(uap, R0);
320 write_zsreg(uap, R0, RES_EXT_INT);
321 zssync(uap);
322
323 if (ZS_IS_OPEN(uap) && ZS_WANTS_MODEM_STATUS(uap)) {
324 if (status & SYNC_HUNT)
325 uap->port.icount.dsr++;
326
327 /* The Zilog just gives us an interrupt when DCD/CTS/etc. change.
328 * But it does not tell us which bit has changed, we have to keep
329 * track of this ourselves.
330 * The CTS input is inverted for some reason. -- paulus
331 */
332 if ((status ^ uap->prev_status) & DCD)
333 uart_handle_dcd_change(&uap->port,
334 (status & DCD));
335 if ((status ^ uap->prev_status) & CTS)
336 uart_handle_cts_change(&uap->port,
337 !(status & CTS));
338
339 wake_up_interruptible(&uap->port.state->port.delta_msr_wait);
340 }
341
342 if (status & BRK_ABRT)
343 uap->flags |= PMACZILOG_FLAG_BREAK;
344
345 uap->prev_status = status;
346 }
347
pmz_transmit_chars(struct uart_pmac_port * uap)348 static void pmz_transmit_chars(struct uart_pmac_port *uap)
349 {
350 struct circ_buf *xmit;
351
352 if (ZS_IS_CONS(uap)) {
353 unsigned char status = read_zsreg(uap, R0);
354
355 /* TX still busy? Just wait for the next TX done interrupt.
356 *
357 * It can occur because of how we do serial console writes. It would
358 * be nice to transmit console writes just like we normally would for
359 * a TTY line. (ie. buffered and TX interrupt driven). That is not
360 * easy because console writes cannot sleep. One solution might be
361 * to poll on enough port->xmit space becoming free. -DaveM
362 */
363 if (!(status & Tx_BUF_EMP))
364 return;
365 }
366
367 uap->flags &= ~PMACZILOG_FLAG_TX_ACTIVE;
368
369 if (ZS_REGS_HELD(uap)) {
370 pmz_load_zsregs(uap, uap->curregs);
371 uap->flags &= ~PMACZILOG_FLAG_REGS_HELD;
372 }
373
374 if (ZS_TX_STOPPED(uap)) {
375 uap->flags &= ~PMACZILOG_FLAG_TX_STOPPED;
376 goto ack_tx_int;
377 }
378
379 /* Under some circumstances, we see interrupts reported for
380 * a closed channel. The interrupt mask in R1 is clear, but
381 * R3 still signals the interrupts and we see them when taking
382 * an interrupt for the other channel (this could be a qemu
383 * bug but since the ESCC doc doesn't specify precsiely whether
384 * R3 interrup status bits are masked by R1 interrupt enable
385 * bits, better safe than sorry). --BenH.
386 */
387 if (!ZS_IS_OPEN(uap))
388 goto ack_tx_int;
389
390 if (uap->port.x_char) {
391 uap->flags |= PMACZILOG_FLAG_TX_ACTIVE;
392 write_zsdata(uap, uap->port.x_char);
393 zssync(uap);
394 uap->port.icount.tx++;
395 uap->port.x_char = 0;
396 return;
397 }
398
399 if (uap->port.state == NULL)
400 goto ack_tx_int;
401 xmit = &uap->port.state->xmit;
402 if (uart_circ_empty(xmit)) {
403 uart_write_wakeup(&uap->port);
404 goto ack_tx_int;
405 }
406 if (uart_tx_stopped(&uap->port))
407 goto ack_tx_int;
408
409 uap->flags |= PMACZILOG_FLAG_TX_ACTIVE;
410 write_zsdata(uap, xmit->buf[xmit->tail]);
411 zssync(uap);
412
413 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
414 uap->port.icount.tx++;
415
416 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
417 uart_write_wakeup(&uap->port);
418
419 return;
420
421 ack_tx_int:
422 write_zsreg(uap, R0, RES_Tx_P);
423 zssync(uap);
424 }
425
426 /* Hrm... we register that twice, fixme later.... */
pmz_interrupt(int irq,void * dev_id)427 static irqreturn_t pmz_interrupt(int irq, void *dev_id)
428 {
429 struct uart_pmac_port *uap = dev_id;
430 struct uart_pmac_port *uap_a;
431 struct uart_pmac_port *uap_b;
432 int rc = IRQ_NONE;
433 bool push;
434 u8 r3;
435
436 uap_a = pmz_get_port_A(uap);
437 uap_b = uap_a->mate;
438
439 spin_lock(&uap_a->port.lock);
440 r3 = read_zsreg(uap_a, R3);
441
442 /* Channel A */
443 push = false;
444 if (r3 & (CHAEXT | CHATxIP | CHARxIP)) {
445 if (!ZS_IS_OPEN(uap_a)) {
446 pmz_debug("ChanA interrupt while not open !\n");
447 goto skip_a;
448 }
449 write_zsreg(uap_a, R0, RES_H_IUS);
450 zssync(uap_a);
451 if (r3 & CHAEXT)
452 pmz_status_handle(uap_a);
453 if (r3 & CHARxIP)
454 push = pmz_receive_chars(uap_a);
455 if (r3 & CHATxIP)
456 pmz_transmit_chars(uap_a);
457 rc = IRQ_HANDLED;
458 }
459 skip_a:
460 spin_unlock(&uap_a->port.lock);
461 if (push)
462 tty_flip_buffer_push(&uap->port.state->port);
463
464 if (!uap_b)
465 goto out;
466
467 spin_lock(&uap_b->port.lock);
468 push = false;
469 if (r3 & (CHBEXT | CHBTxIP | CHBRxIP)) {
470 if (!ZS_IS_OPEN(uap_b)) {
471 pmz_debug("ChanB interrupt while not open !\n");
472 goto skip_b;
473 }
474 write_zsreg(uap_b, R0, RES_H_IUS);
475 zssync(uap_b);
476 if (r3 & CHBEXT)
477 pmz_status_handle(uap_b);
478 if (r3 & CHBRxIP)
479 push = pmz_receive_chars(uap_b);
480 if (r3 & CHBTxIP)
481 pmz_transmit_chars(uap_b);
482 rc = IRQ_HANDLED;
483 }
484 skip_b:
485 spin_unlock(&uap_b->port.lock);
486 if (push)
487 tty_flip_buffer_push(&uap->port.state->port);
488
489 out:
490 return rc;
491 }
492
493 /*
494 * Peek the status register, lock not held by caller
495 */
pmz_peek_status(struct uart_pmac_port * uap)496 static inline u8 pmz_peek_status(struct uart_pmac_port *uap)
497 {
498 unsigned long flags;
499 u8 status;
500
501 spin_lock_irqsave(&uap->port.lock, flags);
502 status = read_zsreg(uap, R0);
503 spin_unlock_irqrestore(&uap->port.lock, flags);
504
505 return status;
506 }
507
508 /*
509 * Check if transmitter is empty
510 * The port lock is not held.
511 */
pmz_tx_empty(struct uart_port * port)512 static unsigned int pmz_tx_empty(struct uart_port *port)
513 {
514 unsigned char status;
515
516 status = pmz_peek_status(to_pmz(port));
517 if (status & Tx_BUF_EMP)
518 return TIOCSER_TEMT;
519 return 0;
520 }
521
522 /*
523 * Set Modem Control (RTS & DTR) bits
524 * The port lock is held and interrupts are disabled.
525 * Note: Shall we really filter out RTS on external ports or
526 * should that be dealt at higher level only ?
527 */
pmz_set_mctrl(struct uart_port * port,unsigned int mctrl)528 static void pmz_set_mctrl(struct uart_port *port, unsigned int mctrl)
529 {
530 struct uart_pmac_port *uap = to_pmz(port);
531 unsigned char set_bits, clear_bits;
532
533 /* Do nothing for irda for now... */
534 if (ZS_IS_IRDA(uap))
535 return;
536 /* We get called during boot with a port not up yet */
537 if (!(ZS_IS_OPEN(uap) || ZS_IS_CONS(uap)))
538 return;
539
540 set_bits = clear_bits = 0;
541
542 if (ZS_IS_INTMODEM(uap)) {
543 if (mctrl & TIOCM_RTS)
544 set_bits |= RTS;
545 else
546 clear_bits |= RTS;
547 }
548 if (mctrl & TIOCM_DTR)
549 set_bits |= DTR;
550 else
551 clear_bits |= DTR;
552
553 /* NOTE: Not subject to 'transmitter active' rule. */
554 uap->curregs[R5] |= set_bits;
555 uap->curregs[R5] &= ~clear_bits;
556
557 write_zsreg(uap, R5, uap->curregs[R5]);
558 pmz_debug("pmz_set_mctrl: set bits: %x, clear bits: %x -> %x\n",
559 set_bits, clear_bits, uap->curregs[R5]);
560 zssync(uap);
561 }
562
563 /*
564 * Get Modem Control bits (only the input ones, the core will
565 * or that with a cached value of the control ones)
566 * The port lock is held and interrupts are disabled.
567 */
pmz_get_mctrl(struct uart_port * port)568 static unsigned int pmz_get_mctrl(struct uart_port *port)
569 {
570 struct uart_pmac_port *uap = to_pmz(port);
571 unsigned char status;
572 unsigned int ret;
573
574 status = read_zsreg(uap, R0);
575
576 ret = 0;
577 if (status & DCD)
578 ret |= TIOCM_CAR;
579 if (status & SYNC_HUNT)
580 ret |= TIOCM_DSR;
581 if (!(status & CTS))
582 ret |= TIOCM_CTS;
583
584 return ret;
585 }
586
587 /*
588 * Stop TX side. Dealt like sunzilog at next Tx interrupt,
589 * though for DMA, we will have to do a bit more.
590 * The port lock is held and interrupts are disabled.
591 */
pmz_stop_tx(struct uart_port * port)592 static void pmz_stop_tx(struct uart_port *port)
593 {
594 to_pmz(port)->flags |= PMACZILOG_FLAG_TX_STOPPED;
595 }
596
597 /*
598 * Kick the Tx side.
599 * The port lock is held and interrupts are disabled.
600 */
pmz_start_tx(struct uart_port * port)601 static void pmz_start_tx(struct uart_port *port)
602 {
603 struct uart_pmac_port *uap = to_pmz(port);
604 unsigned char status;
605
606 uap->flags |= PMACZILOG_FLAG_TX_ACTIVE;
607 uap->flags &= ~PMACZILOG_FLAG_TX_STOPPED;
608
609 status = read_zsreg(uap, R0);
610
611 /* TX busy? Just wait for the TX done interrupt. */
612 if (!(status & Tx_BUF_EMP))
613 return;
614
615 /* Send the first character to jump-start the TX done
616 * IRQ sending engine.
617 */
618 if (port->x_char) {
619 write_zsdata(uap, port->x_char);
620 zssync(uap);
621 port->icount.tx++;
622 port->x_char = 0;
623 } else {
624 struct circ_buf *xmit = &port->state->xmit;
625
626 if (uart_circ_empty(xmit))
627 return;
628 write_zsdata(uap, xmit->buf[xmit->tail]);
629 zssync(uap);
630 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
631 port->icount.tx++;
632
633 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
634 uart_write_wakeup(&uap->port);
635 }
636 }
637
638 /*
639 * Stop Rx side, basically disable emitting of
640 * Rx interrupts on the port. We don't disable the rx
641 * side of the chip proper though
642 * The port lock is held.
643 */
pmz_stop_rx(struct uart_port * port)644 static void pmz_stop_rx(struct uart_port *port)
645 {
646 struct uart_pmac_port *uap = to_pmz(port);
647
648 /* Disable all RX interrupts. */
649 uap->curregs[R1] &= ~RxINT_MASK;
650 pmz_maybe_update_regs(uap);
651 }
652
653 /*
654 * Enable modem status change interrupts
655 * The port lock is held.
656 */
pmz_enable_ms(struct uart_port * port)657 static void pmz_enable_ms(struct uart_port *port)
658 {
659 struct uart_pmac_port *uap = to_pmz(port);
660 unsigned char new_reg;
661
662 if (ZS_IS_IRDA(uap))
663 return;
664 new_reg = uap->curregs[R15] | (DCDIE | SYNCIE | CTSIE);
665 if (new_reg != uap->curregs[R15]) {
666 uap->curregs[R15] = new_reg;
667
668 /* NOTE: Not subject to 'transmitter active' rule. */
669 write_zsreg(uap, R15, uap->curregs[R15]);
670 }
671 }
672
673 /*
674 * Control break state emission
675 * The port lock is not held.
676 */
pmz_break_ctl(struct uart_port * port,int break_state)677 static void pmz_break_ctl(struct uart_port *port, int break_state)
678 {
679 struct uart_pmac_port *uap = to_pmz(port);
680 unsigned char set_bits, clear_bits, new_reg;
681 unsigned long flags;
682
683 set_bits = clear_bits = 0;
684
685 if (break_state)
686 set_bits |= SND_BRK;
687 else
688 clear_bits |= SND_BRK;
689
690 spin_lock_irqsave(&port->lock, flags);
691
692 new_reg = (uap->curregs[R5] | set_bits) & ~clear_bits;
693 if (new_reg != uap->curregs[R5]) {
694 uap->curregs[R5] = new_reg;
695 write_zsreg(uap, R5, uap->curregs[R5]);
696 }
697
698 spin_unlock_irqrestore(&port->lock, flags);
699 }
700
701 #ifdef CONFIG_PPC_PMAC
702
703 /*
704 * Turn power on or off to the SCC and associated stuff
705 * (port drivers, modem, IR port, etc.)
706 * Returns the number of milliseconds we should wait before
707 * trying to use the port.
708 */
pmz_set_scc_power(struct uart_pmac_port * uap,int state)709 static int pmz_set_scc_power(struct uart_pmac_port *uap, int state)
710 {
711 int delay = 0;
712 int rc;
713
714 if (state) {
715 rc = pmac_call_feature(
716 PMAC_FTR_SCC_ENABLE, uap->node, uap->port_type, 1);
717 pmz_debug("port power on result: %d\n", rc);
718 if (ZS_IS_INTMODEM(uap)) {
719 rc = pmac_call_feature(
720 PMAC_FTR_MODEM_ENABLE, uap->node, 0, 1);
721 delay = 2500; /* wait for 2.5s before using */
722 pmz_debug("modem power result: %d\n", rc);
723 }
724 } else {
725 /* TODO: Make that depend on a timer, don't power down
726 * immediately
727 */
728 if (ZS_IS_INTMODEM(uap)) {
729 rc = pmac_call_feature(
730 PMAC_FTR_MODEM_ENABLE, uap->node, 0, 0);
731 pmz_debug("port power off result: %d\n", rc);
732 }
733 pmac_call_feature(PMAC_FTR_SCC_ENABLE, uap->node, uap->port_type, 0);
734 }
735 return delay;
736 }
737
738 #else
739
pmz_set_scc_power(struct uart_pmac_port * uap,int state)740 static int pmz_set_scc_power(struct uart_pmac_port *uap, int state)
741 {
742 return 0;
743 }
744
745 #endif /* !CONFIG_PPC_PMAC */
746
747 /*
748 * FixZeroBug....Works around a bug in the SCC receiving channel.
749 * Inspired from Darwin code, 15 Sept. 2000 -DanM
750 *
751 * The following sequence prevents a problem that is seen with O'Hare ASICs
752 * (most versions -- also with some Heathrow and Hydra ASICs) where a zero
753 * at the input to the receiver becomes 'stuck' and locks up the receiver.
754 * This problem can occur as a result of a zero bit at the receiver input
755 * coincident with any of the following events:
756 *
757 * The SCC is initialized (hardware or software).
758 * A framing error is detected.
759 * The clocking option changes from synchronous or X1 asynchronous
760 * clocking to X16, X32, or X64 asynchronous clocking.
761 * The decoding mode is changed among NRZ, NRZI, FM0, or FM1.
762 *
763 * This workaround attempts to recover from the lockup condition by placing
764 * the SCC in synchronous loopback mode with a fast clock before programming
765 * any of the asynchronous modes.
766 */
pmz_fix_zero_bug_scc(struct uart_pmac_port * uap)767 static void pmz_fix_zero_bug_scc(struct uart_pmac_port *uap)
768 {
769 write_zsreg(uap, 9, ZS_IS_CHANNEL_A(uap) ? CHRA : CHRB);
770 zssync(uap);
771 udelay(10);
772 write_zsreg(uap, 9, (ZS_IS_CHANNEL_A(uap) ? CHRA : CHRB) | NV);
773 zssync(uap);
774
775 write_zsreg(uap, 4, X1CLK | MONSYNC);
776 write_zsreg(uap, 3, Rx8);
777 write_zsreg(uap, 5, Tx8 | RTS);
778 write_zsreg(uap, 9, NV); /* Didn't we already do this? */
779 write_zsreg(uap, 11, RCBR | TCBR);
780 write_zsreg(uap, 12, 0);
781 write_zsreg(uap, 13, 0);
782 write_zsreg(uap, 14, (LOOPBAK | BRSRC));
783 write_zsreg(uap, 14, (LOOPBAK | BRSRC | BRENAB));
784 write_zsreg(uap, 3, Rx8 | RxENABLE);
785 write_zsreg(uap, 0, RES_EXT_INT);
786 write_zsreg(uap, 0, RES_EXT_INT);
787 write_zsreg(uap, 0, RES_EXT_INT); /* to kill some time */
788
789 /* The channel should be OK now, but it is probably receiving
790 * loopback garbage.
791 * Switch to asynchronous mode, disable the receiver,
792 * and discard everything in the receive buffer.
793 */
794 write_zsreg(uap, 9, NV);
795 write_zsreg(uap, 4, X16CLK | SB_MASK);
796 write_zsreg(uap, 3, Rx8);
797
798 while (read_zsreg(uap, 0) & Rx_CH_AV) {
799 (void)read_zsreg(uap, 8);
800 write_zsreg(uap, 0, RES_EXT_INT);
801 write_zsreg(uap, 0, ERR_RES);
802 }
803 }
804
805 /*
806 * Real startup routine, powers up the hardware and sets up
807 * the SCC. Returns a delay in ms where you need to wait before
808 * actually using the port, this is typically the internal modem
809 * powerup delay. This routine expect the lock to be taken.
810 */
__pmz_startup(struct uart_pmac_port * uap)811 static int __pmz_startup(struct uart_pmac_port *uap)
812 {
813 int pwr_delay = 0;
814
815 memset(&uap->curregs, 0, sizeof(uap->curregs));
816
817 /* Power up the SCC & underlying hardware (modem/irda) */
818 pwr_delay = pmz_set_scc_power(uap, 1);
819
820 /* Nice buggy HW ... */
821 pmz_fix_zero_bug_scc(uap);
822
823 /* Reset the channel */
824 uap->curregs[R9] = 0;
825 write_zsreg(uap, 9, ZS_IS_CHANNEL_A(uap) ? CHRA : CHRB);
826 zssync(uap);
827 udelay(10);
828 write_zsreg(uap, 9, 0);
829 zssync(uap);
830
831 /* Clear the interrupt registers */
832 write_zsreg(uap, R1, 0);
833 write_zsreg(uap, R0, ERR_RES);
834 write_zsreg(uap, R0, ERR_RES);
835 write_zsreg(uap, R0, RES_H_IUS);
836 write_zsreg(uap, R0, RES_H_IUS);
837
838 /* Setup some valid baud rate */
839 uap->curregs[R4] = X16CLK | SB1;
840 uap->curregs[R3] = Rx8;
841 uap->curregs[R5] = Tx8 | RTS;
842 if (!ZS_IS_IRDA(uap))
843 uap->curregs[R5] |= DTR;
844 uap->curregs[R12] = 0;
845 uap->curregs[R13] = 0;
846 uap->curregs[R14] = BRENAB;
847
848 /* Clear handshaking, enable BREAK interrupts */
849 uap->curregs[R15] = BRKIE;
850
851 /* Master interrupt enable */
852 uap->curregs[R9] |= NV | MIE;
853
854 pmz_load_zsregs(uap, uap->curregs);
855
856 /* Enable receiver and transmitter. */
857 write_zsreg(uap, R3, uap->curregs[R3] |= RxENABLE);
858 write_zsreg(uap, R5, uap->curregs[R5] |= TxENABLE);
859
860 /* Remember status for DCD/CTS changes */
861 uap->prev_status = read_zsreg(uap, R0);
862
863 return pwr_delay;
864 }
865
pmz_irda_reset(struct uart_pmac_port * uap)866 static void pmz_irda_reset(struct uart_pmac_port *uap)
867 {
868 unsigned long flags;
869
870 spin_lock_irqsave(&uap->port.lock, flags);
871 uap->curregs[R5] |= DTR;
872 write_zsreg(uap, R5, uap->curregs[R5]);
873 zssync(uap);
874 spin_unlock_irqrestore(&uap->port.lock, flags);
875 msleep(110);
876
877 spin_lock_irqsave(&uap->port.lock, flags);
878 uap->curregs[R5] &= ~DTR;
879 write_zsreg(uap, R5, uap->curregs[R5]);
880 zssync(uap);
881 spin_unlock_irqrestore(&uap->port.lock, flags);
882 msleep(10);
883 }
884
885 /*
886 * This is the "normal" startup routine, using the above one
887 * wrapped with the lock and doing a schedule delay
888 */
pmz_startup(struct uart_port * port)889 static int pmz_startup(struct uart_port *port)
890 {
891 struct uart_pmac_port *uap = to_pmz(port);
892 unsigned long flags;
893 int pwr_delay = 0;
894
895 uap->flags |= PMACZILOG_FLAG_IS_OPEN;
896
897 /* A console is never powered down. Else, power up and
898 * initialize the chip
899 */
900 if (!ZS_IS_CONS(uap)) {
901 spin_lock_irqsave(&port->lock, flags);
902 pwr_delay = __pmz_startup(uap);
903 spin_unlock_irqrestore(&port->lock, flags);
904 }
905 sprintf(uap->irq_name, PMACZILOG_NAME"%d", uap->port.line);
906 if (request_irq(uap->port.irq, pmz_interrupt, IRQF_SHARED,
907 uap->irq_name, uap)) {
908 pmz_error("Unable to register zs interrupt handler.\n");
909 pmz_set_scc_power(uap, 0);
910 return -ENXIO;
911 }
912
913 /* Right now, we deal with delay by blocking here, I'll be
914 * smarter later on
915 */
916 if (pwr_delay != 0) {
917 pmz_debug("pmz: delaying %d ms\n", pwr_delay);
918 msleep(pwr_delay);
919 }
920
921 /* IrDA reset is done now */
922 if (ZS_IS_IRDA(uap))
923 pmz_irda_reset(uap);
924
925 /* Enable interrupt requests for the channel */
926 spin_lock_irqsave(&port->lock, flags);
927 pmz_interrupt_control(uap, 1);
928 spin_unlock_irqrestore(&port->lock, flags);
929
930 return 0;
931 }
932
pmz_shutdown(struct uart_port * port)933 static void pmz_shutdown(struct uart_port *port)
934 {
935 struct uart_pmac_port *uap = to_pmz(port);
936 unsigned long flags;
937
938 spin_lock_irqsave(&port->lock, flags);
939
940 /* Disable interrupt requests for the channel */
941 pmz_interrupt_control(uap, 0);
942
943 if (!ZS_IS_CONS(uap)) {
944 /* Disable receiver and transmitter */
945 uap->curregs[R3] &= ~RxENABLE;
946 uap->curregs[R5] &= ~TxENABLE;
947
948 /* Disable break assertion */
949 uap->curregs[R5] &= ~SND_BRK;
950 pmz_maybe_update_regs(uap);
951 }
952
953 spin_unlock_irqrestore(&port->lock, flags);
954
955 /* Release interrupt handler */
956 free_irq(uap->port.irq, uap);
957
958 spin_lock_irqsave(&port->lock, flags);
959
960 uap->flags &= ~PMACZILOG_FLAG_IS_OPEN;
961
962 if (!ZS_IS_CONS(uap))
963 pmz_set_scc_power(uap, 0); /* Shut the chip down */
964
965 spin_unlock_irqrestore(&port->lock, flags);
966 }
967
968 /* Shared by TTY driver and serial console setup. The port lock is held
969 * and local interrupts are disabled.
970 */
pmz_convert_to_zs(struct uart_pmac_port * uap,unsigned int cflag,unsigned int iflag,unsigned long baud)971 static void pmz_convert_to_zs(struct uart_pmac_port *uap, unsigned int cflag,
972 unsigned int iflag, unsigned long baud)
973 {
974 int brg;
975
976 /* Switch to external clocking for IrDA high clock rates. That
977 * code could be re-used for Midi interfaces with different
978 * multipliers
979 */
980 if (baud >= 115200 && ZS_IS_IRDA(uap)) {
981 uap->curregs[R4] = X1CLK;
982 uap->curregs[R11] = RCTRxCP | TCTRxCP;
983 uap->curregs[R14] = 0; /* BRG off */
984 uap->curregs[R12] = 0;
985 uap->curregs[R13] = 0;
986 uap->flags |= PMACZILOG_FLAG_IS_EXTCLK;
987 } else {
988 switch (baud) {
989 case ZS_CLOCK/16: /* 230400 */
990 uap->curregs[R4] = X16CLK;
991 uap->curregs[R11] = 0;
992 uap->curregs[R14] = 0;
993 break;
994 case ZS_CLOCK/32: /* 115200 */
995 uap->curregs[R4] = X32CLK;
996 uap->curregs[R11] = 0;
997 uap->curregs[R14] = 0;
998 break;
999 default:
1000 uap->curregs[R4] = X16CLK;
1001 uap->curregs[R11] = TCBR | RCBR;
1002 brg = BPS_TO_BRG(baud, ZS_CLOCK / 16);
1003 uap->curregs[R12] = (brg & 255);
1004 uap->curregs[R13] = ((brg >> 8) & 255);
1005 uap->curregs[R14] = BRENAB;
1006 }
1007 uap->flags &= ~PMACZILOG_FLAG_IS_EXTCLK;
1008 }
1009
1010 /* Character size, stop bits, and parity. */
1011 uap->curregs[3] &= ~RxN_MASK;
1012 uap->curregs[5] &= ~TxN_MASK;
1013
1014 switch (cflag & CSIZE) {
1015 case CS5:
1016 uap->curregs[3] |= Rx5;
1017 uap->curregs[5] |= Tx5;
1018 uap->parity_mask = 0x1f;
1019 break;
1020 case CS6:
1021 uap->curregs[3] |= Rx6;
1022 uap->curregs[5] |= Tx6;
1023 uap->parity_mask = 0x3f;
1024 break;
1025 case CS7:
1026 uap->curregs[3] |= Rx7;
1027 uap->curregs[5] |= Tx7;
1028 uap->parity_mask = 0x7f;
1029 break;
1030 case CS8:
1031 default:
1032 uap->curregs[3] |= Rx8;
1033 uap->curregs[5] |= Tx8;
1034 uap->parity_mask = 0xff;
1035 break;
1036 }
1037 uap->curregs[4] &= ~(SB_MASK);
1038 if (cflag & CSTOPB)
1039 uap->curregs[4] |= SB2;
1040 else
1041 uap->curregs[4] |= SB1;
1042 if (cflag & PARENB)
1043 uap->curregs[4] |= PAR_ENAB;
1044 else
1045 uap->curregs[4] &= ~PAR_ENAB;
1046 if (!(cflag & PARODD))
1047 uap->curregs[4] |= PAR_EVEN;
1048 else
1049 uap->curregs[4] &= ~PAR_EVEN;
1050
1051 uap->port.read_status_mask = Rx_OVR;
1052 if (iflag & INPCK)
1053 uap->port.read_status_mask |= CRC_ERR | PAR_ERR;
1054 if (iflag & (IGNBRK | BRKINT | PARMRK))
1055 uap->port.read_status_mask |= BRK_ABRT;
1056
1057 uap->port.ignore_status_mask = 0;
1058 if (iflag & IGNPAR)
1059 uap->port.ignore_status_mask |= CRC_ERR | PAR_ERR;
1060 if (iflag & IGNBRK) {
1061 uap->port.ignore_status_mask |= BRK_ABRT;
1062 if (iflag & IGNPAR)
1063 uap->port.ignore_status_mask |= Rx_OVR;
1064 }
1065
1066 if ((cflag & CREAD) == 0)
1067 uap->port.ignore_status_mask = 0xff;
1068 }
1069
1070
1071 /*
1072 * Set the irda codec on the imac to the specified baud rate.
1073 */
pmz_irda_setup(struct uart_pmac_port * uap,unsigned long * baud)1074 static void pmz_irda_setup(struct uart_pmac_port *uap, unsigned long *baud)
1075 {
1076 u8 cmdbyte;
1077 int t, version;
1078
1079 switch (*baud) {
1080 /* SIR modes */
1081 case 2400:
1082 cmdbyte = 0x53;
1083 break;
1084 case 4800:
1085 cmdbyte = 0x52;
1086 break;
1087 case 9600:
1088 cmdbyte = 0x51;
1089 break;
1090 case 19200:
1091 cmdbyte = 0x50;
1092 break;
1093 case 38400:
1094 cmdbyte = 0x4f;
1095 break;
1096 case 57600:
1097 cmdbyte = 0x4e;
1098 break;
1099 case 115200:
1100 cmdbyte = 0x4d;
1101 break;
1102 /* The FIR modes aren't really supported at this point, how
1103 * do we select the speed ? via the FCR on KeyLargo ?
1104 */
1105 case 1152000:
1106 cmdbyte = 0;
1107 break;
1108 case 4000000:
1109 cmdbyte = 0;
1110 break;
1111 default: /* 9600 */
1112 cmdbyte = 0x51;
1113 *baud = 9600;
1114 break;
1115 }
1116
1117 /* Wait for transmitter to drain */
1118 t = 10000;
1119 while ((read_zsreg(uap, R0) & Tx_BUF_EMP) == 0
1120 || (read_zsreg(uap, R1) & ALL_SNT) == 0) {
1121 if (--t <= 0) {
1122 pmz_error("transmitter didn't drain\n");
1123 return;
1124 }
1125 udelay(10);
1126 }
1127
1128 /* Drain the receiver too */
1129 t = 100;
1130 (void)read_zsdata(uap);
1131 (void)read_zsdata(uap);
1132 (void)read_zsdata(uap);
1133 mdelay(10);
1134 while (read_zsreg(uap, R0) & Rx_CH_AV) {
1135 read_zsdata(uap);
1136 mdelay(10);
1137 if (--t <= 0) {
1138 pmz_error("receiver didn't drain\n");
1139 return;
1140 }
1141 }
1142
1143 /* Switch to command mode */
1144 uap->curregs[R5] |= DTR;
1145 write_zsreg(uap, R5, uap->curregs[R5]);
1146 zssync(uap);
1147 mdelay(1);
1148
1149 /* Switch SCC to 19200 */
1150 pmz_convert_to_zs(uap, CS8, 0, 19200);
1151 pmz_load_zsregs(uap, uap->curregs);
1152 mdelay(1);
1153
1154 /* Write get_version command byte */
1155 write_zsdata(uap, 1);
1156 t = 5000;
1157 while ((read_zsreg(uap, R0) & Rx_CH_AV) == 0) {
1158 if (--t <= 0) {
1159 pmz_error("irda_setup timed out on get_version byte\n");
1160 goto out;
1161 }
1162 udelay(10);
1163 }
1164 version = read_zsdata(uap);
1165
1166 if (version < 4) {
1167 pmz_info("IrDA: dongle version %d not supported\n", version);
1168 goto out;
1169 }
1170
1171 /* Send speed mode */
1172 write_zsdata(uap, cmdbyte);
1173 t = 5000;
1174 while ((read_zsreg(uap, R0) & Rx_CH_AV) == 0) {
1175 if (--t <= 0) {
1176 pmz_error("irda_setup timed out on speed mode byte\n");
1177 goto out;
1178 }
1179 udelay(10);
1180 }
1181 t = read_zsdata(uap);
1182 if (t != cmdbyte)
1183 pmz_error("irda_setup speed mode byte = %x (%x)\n", t, cmdbyte);
1184
1185 pmz_info("IrDA setup for %ld bps, dongle version: %d\n",
1186 *baud, version);
1187
1188 (void)read_zsdata(uap);
1189 (void)read_zsdata(uap);
1190 (void)read_zsdata(uap);
1191
1192 out:
1193 /* Switch back to data mode */
1194 uap->curregs[R5] &= ~DTR;
1195 write_zsreg(uap, R5, uap->curregs[R5]);
1196 zssync(uap);
1197
1198 (void)read_zsdata(uap);
1199 (void)read_zsdata(uap);
1200 (void)read_zsdata(uap);
1201 }
1202
1203
__pmz_set_termios(struct uart_port * port,struct ktermios * termios,const struct ktermios * old)1204 static void __pmz_set_termios(struct uart_port *port, struct ktermios *termios,
1205 const struct ktermios *old)
1206 {
1207 struct uart_pmac_port *uap = to_pmz(port);
1208 unsigned long baud;
1209
1210 /* XXX Check which revs of machines actually allow 1 and 4Mb speeds
1211 * on the IR dongle. Note that the IRTTY driver currently doesn't know
1212 * about the FIR mode and high speed modes. So these are unused. For
1213 * implementing proper support for these, we should probably add some
1214 * DMA as well, at least on the Rx side, which isn't a simple thing
1215 * at this point.
1216 */
1217 if (ZS_IS_IRDA(uap)) {
1218 /* Calc baud rate */
1219 baud = uart_get_baud_rate(port, termios, old, 1200, 4000000);
1220 pmz_debug("pmz: switch IRDA to %ld bauds\n", baud);
1221 /* Cet the irda codec to the right rate */
1222 pmz_irda_setup(uap, &baud);
1223 /* Set final baud rate */
1224 pmz_convert_to_zs(uap, termios->c_cflag, termios->c_iflag, baud);
1225 pmz_load_zsregs(uap, uap->curregs);
1226 zssync(uap);
1227 } else {
1228 baud = uart_get_baud_rate(port, termios, old, 1200, 230400);
1229 pmz_convert_to_zs(uap, termios->c_cflag, termios->c_iflag, baud);
1230 /* Make sure modem status interrupts are correctly configured */
1231 if (UART_ENABLE_MS(&uap->port, termios->c_cflag)) {
1232 uap->curregs[R15] |= DCDIE | SYNCIE | CTSIE;
1233 uap->flags |= PMACZILOG_FLAG_MODEM_STATUS;
1234 } else {
1235 uap->curregs[R15] &= ~(DCDIE | SYNCIE | CTSIE);
1236 uap->flags &= ~PMACZILOG_FLAG_MODEM_STATUS;
1237 }
1238
1239 /* Load registers to the chip */
1240 pmz_maybe_update_regs(uap);
1241 }
1242 uart_update_timeout(port, termios->c_cflag, baud);
1243 }
1244
1245 /* The port lock is not held. */
pmz_set_termios(struct uart_port * port,struct ktermios * termios,const struct ktermios * old)1246 static void pmz_set_termios(struct uart_port *port, struct ktermios *termios,
1247 const struct ktermios *old)
1248 {
1249 struct uart_pmac_port *uap = to_pmz(port);
1250 unsigned long flags;
1251
1252 spin_lock_irqsave(&port->lock, flags);
1253
1254 /* Disable IRQs on the port */
1255 pmz_interrupt_control(uap, 0);
1256
1257 /* Setup new port configuration */
1258 __pmz_set_termios(port, termios, old);
1259
1260 /* Re-enable IRQs on the port */
1261 if (ZS_IS_OPEN(uap))
1262 pmz_interrupt_control(uap, 1);
1263
1264 spin_unlock_irqrestore(&port->lock, flags);
1265 }
1266
pmz_type(struct uart_port * port)1267 static const char *pmz_type(struct uart_port *port)
1268 {
1269 struct uart_pmac_port *uap = to_pmz(port);
1270
1271 if (ZS_IS_IRDA(uap))
1272 return "Z85c30 ESCC - Infrared port";
1273 else if (ZS_IS_INTMODEM(uap))
1274 return "Z85c30 ESCC - Internal modem";
1275 return "Z85c30 ESCC - Serial port";
1276 }
1277
1278 /* We do not request/release mappings of the registers here, this
1279 * happens at early serial probe time.
1280 */
pmz_release_port(struct uart_port * port)1281 static void pmz_release_port(struct uart_port *port)
1282 {
1283 }
1284
pmz_request_port(struct uart_port * port)1285 static int pmz_request_port(struct uart_port *port)
1286 {
1287 return 0;
1288 }
1289
1290 /* These do not need to do anything interesting either. */
pmz_config_port(struct uart_port * port,int flags)1291 static void pmz_config_port(struct uart_port *port, int flags)
1292 {
1293 }
1294
1295 /* We do not support letting the user mess with the divisor, IRQ, etc. */
pmz_verify_port(struct uart_port * port,struct serial_struct * ser)1296 static int pmz_verify_port(struct uart_port *port, struct serial_struct *ser)
1297 {
1298 return -EINVAL;
1299 }
1300
1301 #ifdef CONFIG_CONSOLE_POLL
1302
pmz_poll_get_char(struct uart_port * port)1303 static int pmz_poll_get_char(struct uart_port *port)
1304 {
1305 struct uart_pmac_port *uap =
1306 container_of(port, struct uart_pmac_port, port);
1307 int tries = 2;
1308
1309 while (tries) {
1310 if ((read_zsreg(uap, R0) & Rx_CH_AV) != 0)
1311 return read_zsdata(uap);
1312 if (tries--)
1313 udelay(5);
1314 }
1315
1316 return NO_POLL_CHAR;
1317 }
1318
pmz_poll_put_char(struct uart_port * port,unsigned char c)1319 static void pmz_poll_put_char(struct uart_port *port, unsigned char c)
1320 {
1321 struct uart_pmac_port *uap =
1322 container_of(port, struct uart_pmac_port, port);
1323
1324 /* Wait for the transmit buffer to empty. */
1325 while ((read_zsreg(uap, R0) & Tx_BUF_EMP) == 0)
1326 udelay(5);
1327 write_zsdata(uap, c);
1328 }
1329
1330 #endif /* CONFIG_CONSOLE_POLL */
1331
1332 static const struct uart_ops pmz_pops = {
1333 .tx_empty = pmz_tx_empty,
1334 .set_mctrl = pmz_set_mctrl,
1335 .get_mctrl = pmz_get_mctrl,
1336 .stop_tx = pmz_stop_tx,
1337 .start_tx = pmz_start_tx,
1338 .stop_rx = pmz_stop_rx,
1339 .enable_ms = pmz_enable_ms,
1340 .break_ctl = pmz_break_ctl,
1341 .startup = pmz_startup,
1342 .shutdown = pmz_shutdown,
1343 .set_termios = pmz_set_termios,
1344 .type = pmz_type,
1345 .release_port = pmz_release_port,
1346 .request_port = pmz_request_port,
1347 .config_port = pmz_config_port,
1348 .verify_port = pmz_verify_port,
1349 #ifdef CONFIG_CONSOLE_POLL
1350 .poll_get_char = pmz_poll_get_char,
1351 .poll_put_char = pmz_poll_put_char,
1352 #endif
1353 };
1354
1355 #ifdef CONFIG_PPC_PMAC
1356
1357 /*
1358 * Setup one port structure after probing, HW is down at this point,
1359 * Unlike sunzilog, we don't need to pre-init the spinlock as we don't
1360 * register our console before uart_add_one_port() is called
1361 */
pmz_init_port(struct uart_pmac_port * uap)1362 static int __init pmz_init_port(struct uart_pmac_port *uap)
1363 {
1364 struct device_node *np = uap->node;
1365 const char *conn;
1366 const struct slot_names_prop {
1367 int count;
1368 char name[1];
1369 } *slots;
1370 int len;
1371 struct resource r_ports;
1372
1373 /*
1374 * Request & map chip registers
1375 */
1376 if (of_address_to_resource(np, 0, &r_ports))
1377 return -ENODEV;
1378 uap->port.mapbase = r_ports.start;
1379 uap->port.membase = ioremap(uap->port.mapbase, 0x1000);
1380
1381 uap->control_reg = uap->port.membase;
1382 uap->data_reg = uap->control_reg + 0x10;
1383
1384 /*
1385 * Detect port type
1386 */
1387 if (of_device_is_compatible(np, "cobalt"))
1388 uap->flags |= PMACZILOG_FLAG_IS_INTMODEM;
1389 conn = of_get_property(np, "AAPL,connector", &len);
1390 if (conn && (strcmp(conn, "infrared") == 0))
1391 uap->flags |= PMACZILOG_FLAG_IS_IRDA;
1392 uap->port_type = PMAC_SCC_ASYNC;
1393 /* 1999 Powerbook G3 has slot-names property instead */
1394 slots = of_get_property(np, "slot-names", &len);
1395 if (slots && slots->count > 0) {
1396 if (strcmp(slots->name, "IrDA") == 0)
1397 uap->flags |= PMACZILOG_FLAG_IS_IRDA;
1398 else if (strcmp(slots->name, "Modem") == 0)
1399 uap->flags |= PMACZILOG_FLAG_IS_INTMODEM;
1400 }
1401 if (ZS_IS_IRDA(uap))
1402 uap->port_type = PMAC_SCC_IRDA;
1403 if (ZS_IS_INTMODEM(uap)) {
1404 struct device_node* i2c_modem =
1405 of_find_node_by_name(NULL, "i2c-modem");
1406 if (i2c_modem) {
1407 const char* mid =
1408 of_get_property(i2c_modem, "modem-id", NULL);
1409 if (mid) switch(*mid) {
1410 case 0x04 :
1411 case 0x05 :
1412 case 0x07 :
1413 case 0x08 :
1414 case 0x0b :
1415 case 0x0c :
1416 uap->port_type = PMAC_SCC_I2S1;
1417 }
1418 printk(KERN_INFO "pmac_zilog: i2c-modem detected, id: %d\n",
1419 mid ? (*mid) : 0);
1420 of_node_put(i2c_modem);
1421 } else {
1422 printk(KERN_INFO "pmac_zilog: serial modem detected\n");
1423 }
1424 }
1425
1426 /*
1427 * Init remaining bits of "port" structure
1428 */
1429 uap->port.iotype = UPIO_MEM;
1430 uap->port.irq = irq_of_parse_and_map(np, 0);
1431 uap->port.uartclk = ZS_CLOCK;
1432 uap->port.fifosize = 1;
1433 uap->port.ops = &pmz_pops;
1434 uap->port.type = PORT_PMAC_ZILOG;
1435 uap->port.flags = 0;
1436
1437 /*
1438 * Fixup for the port on Gatwick for which the device-tree has
1439 * missing interrupts. Normally, the macio_dev would contain
1440 * fixed up interrupt info, but we use the device-tree directly
1441 * here due to early probing so we need the fixup too.
1442 */
1443 if (uap->port.irq == 0 &&
1444 np->parent && np->parent->parent &&
1445 of_device_is_compatible(np->parent->parent, "gatwick")) {
1446 /* IRQs on gatwick are offset by 64 */
1447 uap->port.irq = irq_create_mapping(NULL, 64 + 15);
1448 }
1449
1450 /* Setup some valid baud rate information in the register
1451 * shadows so we don't write crap there before baud rate is
1452 * first initialized.
1453 */
1454 pmz_convert_to_zs(uap, CS8, 0, 9600);
1455
1456 return 0;
1457 }
1458
1459 /*
1460 * Get rid of a port on module removal
1461 */
pmz_dispose_port(struct uart_pmac_port * uap)1462 static void pmz_dispose_port(struct uart_pmac_port *uap)
1463 {
1464 struct device_node *np;
1465
1466 np = uap->node;
1467 iounmap(uap->control_reg);
1468 uap->node = NULL;
1469 of_node_put(np);
1470 memset(uap, 0, sizeof(struct uart_pmac_port));
1471 }
1472
1473 /*
1474 * Called upon match with an escc node in the device-tree.
1475 */
pmz_attach(struct macio_dev * mdev,const struct of_device_id * match)1476 static int pmz_attach(struct macio_dev *mdev, const struct of_device_id *match)
1477 {
1478 struct uart_pmac_port *uap;
1479 int i;
1480
1481 /* Iterate the pmz_ports array to find a matching entry
1482 */
1483 for (i = 0; i < MAX_ZS_PORTS; i++)
1484 if (pmz_ports[i].node == mdev->ofdev.dev.of_node)
1485 break;
1486 if (i >= MAX_ZS_PORTS)
1487 return -ENODEV;
1488
1489
1490 uap = &pmz_ports[i];
1491 uap->dev = mdev;
1492 uap->port.dev = &mdev->ofdev.dev;
1493 dev_set_drvdata(&mdev->ofdev.dev, uap);
1494
1495 /* We still activate the port even when failing to request resources
1496 * to work around bugs in ancient Apple device-trees
1497 */
1498 if (macio_request_resources(uap->dev, "pmac_zilog"))
1499 printk(KERN_WARNING "%pOFn: Failed to request resource"
1500 ", port still active\n",
1501 uap->node);
1502 else
1503 uap->flags |= PMACZILOG_FLAG_RSRC_REQUESTED;
1504
1505 return uart_add_one_port(&pmz_uart_reg, &uap->port);
1506 }
1507
1508 /*
1509 * That one should not be called, macio isn't really a hotswap device,
1510 * we don't expect one of those serial ports to go away...
1511 */
pmz_detach(struct macio_dev * mdev)1512 static int pmz_detach(struct macio_dev *mdev)
1513 {
1514 struct uart_pmac_port *uap = dev_get_drvdata(&mdev->ofdev.dev);
1515
1516 if (!uap)
1517 return -ENODEV;
1518
1519 uart_remove_one_port(&pmz_uart_reg, &uap->port);
1520
1521 if (uap->flags & PMACZILOG_FLAG_RSRC_REQUESTED) {
1522 macio_release_resources(uap->dev);
1523 uap->flags &= ~PMACZILOG_FLAG_RSRC_REQUESTED;
1524 }
1525 dev_set_drvdata(&mdev->ofdev.dev, NULL);
1526 uap->dev = NULL;
1527 uap->port.dev = NULL;
1528
1529 return 0;
1530 }
1531
1532
pmz_suspend(struct macio_dev * mdev,pm_message_t pm_state)1533 static int pmz_suspend(struct macio_dev *mdev, pm_message_t pm_state)
1534 {
1535 struct uart_pmac_port *uap = dev_get_drvdata(&mdev->ofdev.dev);
1536
1537 if (uap == NULL) {
1538 printk("HRM... pmz_suspend with NULL uap\n");
1539 return 0;
1540 }
1541
1542 uart_suspend_port(&pmz_uart_reg, &uap->port);
1543
1544 return 0;
1545 }
1546
1547
pmz_resume(struct macio_dev * mdev)1548 static int pmz_resume(struct macio_dev *mdev)
1549 {
1550 struct uart_pmac_port *uap = dev_get_drvdata(&mdev->ofdev.dev);
1551
1552 if (uap == NULL)
1553 return 0;
1554
1555 uart_resume_port(&pmz_uart_reg, &uap->port);
1556
1557 return 0;
1558 }
1559
1560 /*
1561 * Probe all ports in the system and build the ports array, we register
1562 * with the serial layer later, so we get a proper struct device which
1563 * allows the tty to attach properly. This is later than it used to be
1564 * but the tty layer really wants it that way.
1565 */
pmz_probe(void)1566 static int __init pmz_probe(void)
1567 {
1568 struct device_node *node_p, *node_a, *node_b, *np;
1569 int count = 0;
1570 int rc;
1571
1572 /*
1573 * Find all escc chips in the system
1574 */
1575 for_each_node_by_name(node_p, "escc") {
1576 /*
1577 * First get channel A/B node pointers
1578 *
1579 * TODO: Add routines with proper locking to do that...
1580 */
1581 node_a = node_b = NULL;
1582 for_each_child_of_node(node_p, np) {
1583 if (of_node_name_prefix(np, "ch-a"))
1584 node_a = of_node_get(np);
1585 else if (of_node_name_prefix(np, "ch-b"))
1586 node_b = of_node_get(np);
1587 }
1588 if (!node_a && !node_b) {
1589 of_node_put(node_a);
1590 of_node_put(node_b);
1591 printk(KERN_ERR "pmac_zilog: missing node %c for escc %pOF\n",
1592 (!node_a) ? 'a' : 'b', node_p);
1593 continue;
1594 }
1595
1596 /*
1597 * Fill basic fields in the port structures
1598 */
1599 if (node_b != NULL) {
1600 pmz_ports[count].mate = &pmz_ports[count+1];
1601 pmz_ports[count+1].mate = &pmz_ports[count];
1602 }
1603 pmz_ports[count].flags = PMACZILOG_FLAG_IS_CHANNEL_A;
1604 pmz_ports[count].node = node_a;
1605 pmz_ports[count+1].node = node_b;
1606 pmz_ports[count].port.line = count;
1607 pmz_ports[count+1].port.line = count+1;
1608
1609 /*
1610 * Setup the ports for real
1611 */
1612 rc = pmz_init_port(&pmz_ports[count]);
1613 if (rc == 0 && node_b != NULL)
1614 rc = pmz_init_port(&pmz_ports[count+1]);
1615 if (rc != 0) {
1616 of_node_put(node_a);
1617 of_node_put(node_b);
1618 memset(&pmz_ports[count], 0, sizeof(struct uart_pmac_port));
1619 memset(&pmz_ports[count+1], 0, sizeof(struct uart_pmac_port));
1620 continue;
1621 }
1622 count += 2;
1623 }
1624 pmz_ports_count = count;
1625
1626 return 0;
1627 }
1628
1629 #else
1630
1631 /* On PCI PowerMacs, pmz_probe() does an explicit search of the OpenFirmware
1632 * tree to obtain the device_nodes needed to start the console before the
1633 * macio driver. On Macs without OpenFirmware, global platform_devices take
1634 * the place of those device_nodes.
1635 */
1636 extern struct platform_device scc_a_pdev, scc_b_pdev;
1637
pmz_init_port(struct uart_pmac_port * uap)1638 static int __init pmz_init_port(struct uart_pmac_port *uap)
1639 {
1640 struct resource *r_ports;
1641 int irq;
1642
1643 r_ports = platform_get_resource(uap->pdev, IORESOURCE_MEM, 0);
1644 if (!r_ports)
1645 return -ENODEV;
1646
1647 irq = platform_get_irq(uap->pdev, 0);
1648 if (irq < 0)
1649 return irq;
1650
1651 uap->port.mapbase = r_ports->start;
1652 uap->port.membase = (unsigned char __iomem *) r_ports->start;
1653 uap->port.iotype = UPIO_MEM;
1654 uap->port.irq = irq;
1655 uap->port.uartclk = ZS_CLOCK;
1656 uap->port.fifosize = 1;
1657 uap->port.ops = &pmz_pops;
1658 uap->port.type = PORT_PMAC_ZILOG;
1659 uap->port.flags = 0;
1660
1661 uap->control_reg = uap->port.membase;
1662 uap->data_reg = uap->control_reg + 4;
1663 uap->port_type = 0;
1664 uap->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_PMACZILOG_CONSOLE);
1665
1666 pmz_convert_to_zs(uap, CS8, 0, 9600);
1667
1668 return 0;
1669 }
1670
pmz_probe(void)1671 static int __init pmz_probe(void)
1672 {
1673 int err;
1674
1675 pmz_ports_count = 0;
1676
1677 pmz_ports[0].port.line = 0;
1678 pmz_ports[0].flags = PMACZILOG_FLAG_IS_CHANNEL_A;
1679 pmz_ports[0].pdev = &scc_a_pdev;
1680 err = pmz_init_port(&pmz_ports[0]);
1681 if (err)
1682 return err;
1683 pmz_ports_count++;
1684
1685 pmz_ports[0].mate = &pmz_ports[1];
1686 pmz_ports[1].mate = &pmz_ports[0];
1687 pmz_ports[1].port.line = 1;
1688 pmz_ports[1].flags = 0;
1689 pmz_ports[1].pdev = &scc_b_pdev;
1690 err = pmz_init_port(&pmz_ports[1]);
1691 if (err)
1692 return err;
1693 pmz_ports_count++;
1694
1695 return 0;
1696 }
1697
pmz_dispose_port(struct uart_pmac_port * uap)1698 static void pmz_dispose_port(struct uart_pmac_port *uap)
1699 {
1700 memset(uap, 0, sizeof(struct uart_pmac_port));
1701 }
1702
pmz_attach(struct platform_device * pdev)1703 static int __init pmz_attach(struct platform_device *pdev)
1704 {
1705 struct uart_pmac_port *uap;
1706 int i;
1707
1708 /* Iterate the pmz_ports array to find a matching entry */
1709 for (i = 0; i < pmz_ports_count; i++)
1710 if (pmz_ports[i].pdev == pdev)
1711 break;
1712 if (i >= pmz_ports_count)
1713 return -ENODEV;
1714
1715 uap = &pmz_ports[i];
1716 uap->port.dev = &pdev->dev;
1717 platform_set_drvdata(pdev, uap);
1718
1719 return uart_add_one_port(&pmz_uart_reg, &uap->port);
1720 }
1721
pmz_detach(struct platform_device * pdev)1722 static int __exit pmz_detach(struct platform_device *pdev)
1723 {
1724 struct uart_pmac_port *uap = platform_get_drvdata(pdev);
1725
1726 if (!uap)
1727 return -ENODEV;
1728
1729 uart_remove_one_port(&pmz_uart_reg, &uap->port);
1730
1731 uap->port.dev = NULL;
1732
1733 return 0;
1734 }
1735
1736 #endif /* !CONFIG_PPC_PMAC */
1737
1738 #ifdef CONFIG_SERIAL_PMACZILOG_CONSOLE
1739
1740 static void pmz_console_write(struct console *con, const char *s, unsigned int count);
1741 static int __init pmz_console_setup(struct console *co, char *options);
1742
1743 static struct console pmz_console = {
1744 .name = PMACZILOG_NAME,
1745 .write = pmz_console_write,
1746 .device = uart_console_device,
1747 .setup = pmz_console_setup,
1748 .flags = CON_PRINTBUFFER,
1749 .index = -1,
1750 .data = &pmz_uart_reg,
1751 };
1752
1753 #define PMACZILOG_CONSOLE &pmz_console
1754 #else /* CONFIG_SERIAL_PMACZILOG_CONSOLE */
1755 #define PMACZILOG_CONSOLE (NULL)
1756 #endif /* CONFIG_SERIAL_PMACZILOG_CONSOLE */
1757
1758 /*
1759 * Register the driver, console driver and ports with the serial
1760 * core
1761 */
pmz_register(void)1762 static int __init pmz_register(void)
1763 {
1764 pmz_uart_reg.nr = pmz_ports_count;
1765 pmz_uart_reg.cons = PMACZILOG_CONSOLE;
1766
1767 /*
1768 * Register this driver with the serial core
1769 */
1770 return uart_register_driver(&pmz_uart_reg);
1771 }
1772
1773 #ifdef CONFIG_PPC_PMAC
1774
1775 static const struct of_device_id pmz_match[] =
1776 {
1777 {
1778 .name = "ch-a",
1779 },
1780 {
1781 .name = "ch-b",
1782 },
1783 {},
1784 };
1785 MODULE_DEVICE_TABLE (of, pmz_match);
1786
1787 static struct macio_driver pmz_driver = {
1788 .driver = {
1789 .name = "pmac_zilog",
1790 .owner = THIS_MODULE,
1791 .of_match_table = pmz_match,
1792 },
1793 .probe = pmz_attach,
1794 .remove = pmz_detach,
1795 .suspend = pmz_suspend,
1796 .resume = pmz_resume,
1797 };
1798
1799 #else
1800
1801 static struct platform_driver pmz_driver = {
1802 .remove = __exit_p(pmz_detach),
1803 .driver = {
1804 .name = "scc",
1805 },
1806 };
1807
1808 #endif /* !CONFIG_PPC_PMAC */
1809
init_pmz(void)1810 static int __init init_pmz(void)
1811 {
1812 int rc, i;
1813
1814 /*
1815 * First, we need to do a direct OF-based probe pass. We
1816 * do that because we want serial console up before the
1817 * macio stuffs calls us back, and since that makes it
1818 * easier to pass the proper number of channels to
1819 * uart_register_driver()
1820 */
1821 if (pmz_ports_count == 0)
1822 pmz_probe();
1823
1824 /*
1825 * Bail early if no port found
1826 */
1827 if (pmz_ports_count == 0)
1828 return -ENODEV;
1829
1830 /*
1831 * Now we register with the serial layer
1832 */
1833 rc = pmz_register();
1834 if (rc) {
1835 printk(KERN_ERR
1836 "pmac_zilog: Error registering serial device, disabling pmac_zilog.\n"
1837 "pmac_zilog: Did another serial driver already claim the minors?\n");
1838 /* effectively "pmz_unprobe()" */
1839 for (i=0; i < pmz_ports_count; i++)
1840 pmz_dispose_port(&pmz_ports[i]);
1841 return rc;
1842 }
1843
1844 /*
1845 * Then we register the macio driver itself
1846 */
1847 #ifdef CONFIG_PPC_PMAC
1848 return macio_register_driver(&pmz_driver);
1849 #else
1850 return platform_driver_probe(&pmz_driver, pmz_attach);
1851 #endif
1852 }
1853
exit_pmz(void)1854 static void __exit exit_pmz(void)
1855 {
1856 int i;
1857
1858 #ifdef CONFIG_PPC_PMAC
1859 /* Get rid of macio-driver (detach from macio) */
1860 macio_unregister_driver(&pmz_driver);
1861 #else
1862 platform_driver_unregister(&pmz_driver);
1863 #endif
1864
1865 for (i = 0; i < pmz_ports_count; i++) {
1866 struct uart_pmac_port *uport = &pmz_ports[i];
1867 #ifdef CONFIG_PPC_PMAC
1868 if (uport->node != NULL)
1869 pmz_dispose_port(uport);
1870 #else
1871 if (uport->pdev != NULL)
1872 pmz_dispose_port(uport);
1873 #endif
1874 }
1875 /* Unregister UART driver */
1876 uart_unregister_driver(&pmz_uart_reg);
1877 }
1878
1879 #ifdef CONFIG_SERIAL_PMACZILOG_CONSOLE
1880
pmz_console_putchar(struct uart_port * port,unsigned char ch)1881 static void pmz_console_putchar(struct uart_port *port, unsigned char ch)
1882 {
1883 struct uart_pmac_port *uap =
1884 container_of(port, struct uart_pmac_port, port);
1885
1886 /* Wait for the transmit buffer to empty. */
1887 while ((read_zsreg(uap, R0) & Tx_BUF_EMP) == 0)
1888 udelay(5);
1889 write_zsdata(uap, ch);
1890 }
1891
1892 /*
1893 * Print a string to the serial port trying not to disturb
1894 * any possible real use of the port...
1895 */
pmz_console_write(struct console * con,const char * s,unsigned int count)1896 static void pmz_console_write(struct console *con, const char *s, unsigned int count)
1897 {
1898 struct uart_pmac_port *uap = &pmz_ports[con->index];
1899 unsigned long flags;
1900
1901 spin_lock_irqsave(&uap->port.lock, flags);
1902
1903 /* Turn of interrupts and enable the transmitter. */
1904 write_zsreg(uap, R1, uap->curregs[1] & ~TxINT_ENAB);
1905 write_zsreg(uap, R5, uap->curregs[5] | TxENABLE | RTS | DTR);
1906
1907 uart_console_write(&uap->port, s, count, pmz_console_putchar);
1908
1909 /* Restore the values in the registers. */
1910 write_zsreg(uap, R1, uap->curregs[1]);
1911 /* Don't disable the transmitter. */
1912
1913 spin_unlock_irqrestore(&uap->port.lock, flags);
1914 }
1915
1916 /*
1917 * Setup the serial console
1918 */
pmz_console_setup(struct console * co,char * options)1919 static int __init pmz_console_setup(struct console *co, char *options)
1920 {
1921 struct uart_pmac_port *uap;
1922 struct uart_port *port;
1923 int baud = 38400;
1924 int bits = 8;
1925 int parity = 'n';
1926 int flow = 'n';
1927 unsigned long pwr_delay;
1928
1929 /*
1930 * XServe's default to 57600 bps
1931 */
1932 if (of_machine_is_compatible("RackMac1,1")
1933 || of_machine_is_compatible("RackMac1,2")
1934 || of_machine_is_compatible("MacRISC4"))
1935 baud = 57600;
1936
1937 /*
1938 * Check whether an invalid uart number has been specified, and
1939 * if so, search for the first available port that does have
1940 * console support.
1941 */
1942 if (co->index >= pmz_ports_count)
1943 co->index = 0;
1944 uap = &pmz_ports[co->index];
1945 #ifdef CONFIG_PPC_PMAC
1946 if (uap->node == NULL)
1947 return -ENODEV;
1948 #else
1949 if (uap->pdev == NULL)
1950 return -ENODEV;
1951 #endif
1952 port = &uap->port;
1953
1954 /*
1955 * Mark port as beeing a console
1956 */
1957 uap->flags |= PMACZILOG_FLAG_IS_CONS;
1958
1959 /*
1960 * Temporary fix for uart layer who didn't setup the spinlock yet
1961 */
1962 spin_lock_init(&port->lock);
1963
1964 /*
1965 * Enable the hardware
1966 */
1967 pwr_delay = __pmz_startup(uap);
1968 if (pwr_delay)
1969 mdelay(pwr_delay);
1970
1971 if (options)
1972 uart_parse_options(options, &baud, &parity, &bits, &flow);
1973
1974 return uart_set_options(port, co, baud, parity, bits, flow);
1975 }
1976
pmz_console_init(void)1977 static int __init pmz_console_init(void)
1978 {
1979 /* Probe ports */
1980 pmz_probe();
1981
1982 if (pmz_ports_count == 0)
1983 return -ENODEV;
1984
1985 /* TODO: Autoprobe console based on OF */
1986 /* pmz_console.index = i; */
1987 register_console(&pmz_console);
1988
1989 return 0;
1990
1991 }
1992 console_initcall(pmz_console_init);
1993 #endif /* CONFIG_SERIAL_PMACZILOG_CONSOLE */
1994
1995 module_init(init_pmz);
1996 module_exit(exit_pmz);
1997
