1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2017-2018, The Linux foundation. All rights reserved.
3
4 #include <linux/clk.h>
5 #include <linux/dmaengine.h>
6 #include <linux/dma-mapping.h>
7 #include <linux/dma/qcom-gpi-dma.h>
8 #include <linux/interrupt.h>
9 #include <linux/io.h>
10 #include <linux/log2.h>
11 #include <linux/module.h>
12 #include <linux/platform_device.h>
13 #include <linux/pm_opp.h>
14 #include <linux/pm_runtime.h>
15 #include <linux/qcom-geni-se.h>
16 #include <linux/spi/spi.h>
17 #include <linux/spinlock.h>
18
19 /* SPI SE specific registers and respective register fields */
20 #define SE_SPI_CPHA 0x224
21 #define CPHA BIT(0)
22
23 #define SE_SPI_LOOPBACK 0x22c
24 #define LOOPBACK_ENABLE 0x1
25 #define NORMAL_MODE 0x0
26 #define LOOPBACK_MSK GENMASK(1, 0)
27
28 #define SE_SPI_CPOL 0x230
29 #define CPOL BIT(2)
30
31 #define SE_SPI_DEMUX_OUTPUT_INV 0x24c
32 #define CS_DEMUX_OUTPUT_INV_MSK GENMASK(3, 0)
33
34 #define SE_SPI_DEMUX_SEL 0x250
35 #define CS_DEMUX_OUTPUT_SEL GENMASK(3, 0)
36
37 #define SE_SPI_TRANS_CFG 0x25c
38 #define CS_TOGGLE BIT(0)
39
40 #define SE_SPI_WORD_LEN 0x268
41 #define WORD_LEN_MSK GENMASK(9, 0)
42 #define MIN_WORD_LEN 4
43
44 #define SE_SPI_TX_TRANS_LEN 0x26c
45 #define SE_SPI_RX_TRANS_LEN 0x270
46 #define TRANS_LEN_MSK GENMASK(23, 0)
47
48 #define SE_SPI_PRE_POST_CMD_DLY 0x274
49
50 #define SE_SPI_DELAY_COUNTERS 0x278
51 #define SPI_INTER_WORDS_DELAY_MSK GENMASK(9, 0)
52 #define SPI_CS_CLK_DELAY_MSK GENMASK(19, 10)
53 #define SPI_CS_CLK_DELAY_SHFT 10
54
55 /* M_CMD OP codes for SPI */
56 #define SPI_TX_ONLY 1
57 #define SPI_RX_ONLY 2
58 #define SPI_TX_RX 7
59 #define SPI_CS_ASSERT 8
60 #define SPI_CS_DEASSERT 9
61 #define SPI_SCK_ONLY 10
62 /* M_CMD params for SPI */
63 #define SPI_PRE_CMD_DELAY BIT(0)
64 #define TIMESTAMP_BEFORE BIT(1)
65 #define FRAGMENTATION BIT(2)
66 #define TIMESTAMP_AFTER BIT(3)
67 #define POST_CMD_DELAY BIT(4)
68
69 #define GSI_LOOPBACK_EN BIT(0)
70 #define GSI_CS_TOGGLE BIT(3)
71 #define GSI_CPHA BIT(4)
72 #define GSI_CPOL BIT(5)
73
74 struct spi_geni_master {
75 struct geni_se se;
76 struct device *dev;
77 u32 tx_fifo_depth;
78 u32 fifo_width_bits;
79 u32 tx_wm;
80 u32 last_mode;
81 unsigned long cur_speed_hz;
82 unsigned long cur_sclk_hz;
83 unsigned int cur_bits_per_word;
84 unsigned int tx_rem_bytes;
85 unsigned int rx_rem_bytes;
86 const struct spi_transfer *cur_xfer;
87 struct completion cs_done;
88 struct completion cancel_done;
89 struct completion abort_done;
90 unsigned int oversampling;
91 spinlock_t lock;
92 int irq;
93 bool cs_flag;
94 bool abort_failed;
95 struct dma_chan *tx;
96 struct dma_chan *rx;
97 int cur_xfer_mode;
98 };
99
get_spi_clk_cfg(unsigned int speed_hz,struct spi_geni_master * mas,unsigned int * clk_idx,unsigned int * clk_div)100 static int get_spi_clk_cfg(unsigned int speed_hz,
101 struct spi_geni_master *mas,
102 unsigned int *clk_idx,
103 unsigned int *clk_div)
104 {
105 unsigned long sclk_freq;
106 unsigned int actual_hz;
107 int ret;
108
109 ret = geni_se_clk_freq_match(&mas->se,
110 speed_hz * mas->oversampling,
111 clk_idx, &sclk_freq, false);
112 if (ret) {
113 dev_err(mas->dev, "Failed(%d) to find src clk for %dHz\n",
114 ret, speed_hz);
115 return ret;
116 }
117
118 *clk_div = DIV_ROUND_UP(sclk_freq, mas->oversampling * speed_hz);
119 actual_hz = sclk_freq / (mas->oversampling * *clk_div);
120
121 dev_dbg(mas->dev, "req %u=>%u sclk %lu, idx %d, div %d\n", speed_hz,
122 actual_hz, sclk_freq, *clk_idx, *clk_div);
123 ret = dev_pm_opp_set_rate(mas->dev, sclk_freq);
124 if (ret)
125 dev_err(mas->dev, "dev_pm_opp_set_rate failed %d\n", ret);
126 else
127 mas->cur_sclk_hz = sclk_freq;
128
129 return ret;
130 }
131
handle_fifo_timeout(struct spi_master * spi,struct spi_message * msg)132 static void handle_fifo_timeout(struct spi_master *spi,
133 struct spi_message *msg)
134 {
135 struct spi_geni_master *mas = spi_master_get_devdata(spi);
136 unsigned long time_left;
137 struct geni_se *se = &mas->se;
138
139 spin_lock_irq(&mas->lock);
140 reinit_completion(&mas->cancel_done);
141 writel(0, se->base + SE_GENI_TX_WATERMARK_REG);
142 mas->cur_xfer = NULL;
143 geni_se_cancel_m_cmd(se);
144 spin_unlock_irq(&mas->lock);
145
146 time_left = wait_for_completion_timeout(&mas->cancel_done, HZ);
147 if (time_left)
148 return;
149
150 spin_lock_irq(&mas->lock);
151 reinit_completion(&mas->abort_done);
152 geni_se_abort_m_cmd(se);
153 spin_unlock_irq(&mas->lock);
154
155 time_left = wait_for_completion_timeout(&mas->abort_done, HZ);
156 if (!time_left) {
157 dev_err(mas->dev, "Failed to cancel/abort m_cmd\n");
158
159 /*
160 * No need for a lock since SPI core has a lock and we never
161 * access this from an interrupt.
162 */
163 mas->abort_failed = true;
164 }
165 }
166
handle_gpi_timeout(struct spi_master * spi,struct spi_message * msg)167 static void handle_gpi_timeout(struct spi_master *spi, struct spi_message *msg)
168 {
169 struct spi_geni_master *mas = spi_master_get_devdata(spi);
170
171 dmaengine_terminate_sync(mas->tx);
172 dmaengine_terminate_sync(mas->rx);
173 }
174
spi_geni_handle_err(struct spi_master * spi,struct spi_message * msg)175 static void spi_geni_handle_err(struct spi_master *spi, struct spi_message *msg)
176 {
177 struct spi_geni_master *mas = spi_master_get_devdata(spi);
178
179 switch (mas->cur_xfer_mode) {
180 case GENI_SE_FIFO:
181 handle_fifo_timeout(spi, msg);
182 break;
183 case GENI_GPI_DMA:
184 handle_gpi_timeout(spi, msg);
185 break;
186 default:
187 dev_err(mas->dev, "Abort on Mode:%d not supported", mas->cur_xfer_mode);
188 }
189 }
190
spi_geni_is_abort_still_pending(struct spi_geni_master * mas)191 static bool spi_geni_is_abort_still_pending(struct spi_geni_master *mas)
192 {
193 struct geni_se *se = &mas->se;
194 u32 m_irq, m_irq_en;
195
196 if (!mas->abort_failed)
197 return false;
198
199 /*
200 * The only known case where a transfer times out and then a cancel
201 * times out then an abort times out is if something is blocking our
202 * interrupt handler from running. Avoid starting any new transfers
203 * until that sorts itself out.
204 */
205 spin_lock_irq(&mas->lock);
206 m_irq = readl(se->base + SE_GENI_M_IRQ_STATUS);
207 m_irq_en = readl(se->base + SE_GENI_M_IRQ_EN);
208 spin_unlock_irq(&mas->lock);
209
210 if (m_irq & m_irq_en) {
211 dev_err(mas->dev, "Interrupts pending after abort: %#010x\n",
212 m_irq & m_irq_en);
213 return true;
214 }
215
216 /*
217 * If we're here the problem resolved itself so no need to check more
218 * on future transfers.
219 */
220 mas->abort_failed = false;
221
222 return false;
223 }
224
spi_geni_set_cs(struct spi_device * slv,bool set_flag)225 static void spi_geni_set_cs(struct spi_device *slv, bool set_flag)
226 {
227 struct spi_geni_master *mas = spi_master_get_devdata(slv->master);
228 struct spi_master *spi = dev_get_drvdata(mas->dev);
229 struct geni_se *se = &mas->se;
230 unsigned long time_left;
231
232 if (!(slv->mode & SPI_CS_HIGH))
233 set_flag = !set_flag;
234
235 if (set_flag == mas->cs_flag)
236 return;
237
238 pm_runtime_get_sync(mas->dev);
239
240 if (spi_geni_is_abort_still_pending(mas)) {
241 dev_err(mas->dev, "Can't set chip select\n");
242 goto exit;
243 }
244
245 spin_lock_irq(&mas->lock);
246 if (mas->cur_xfer) {
247 dev_err(mas->dev, "Can't set CS when prev xfer running\n");
248 spin_unlock_irq(&mas->lock);
249 goto exit;
250 }
251
252 mas->cs_flag = set_flag;
253 reinit_completion(&mas->cs_done);
254 if (set_flag)
255 geni_se_setup_m_cmd(se, SPI_CS_ASSERT, 0);
256 else
257 geni_se_setup_m_cmd(se, SPI_CS_DEASSERT, 0);
258 spin_unlock_irq(&mas->lock);
259
260 time_left = wait_for_completion_timeout(&mas->cs_done, HZ);
261 if (!time_left) {
262 dev_warn(mas->dev, "Timeout setting chip select\n");
263 handle_fifo_timeout(spi, NULL);
264 }
265
266 exit:
267 pm_runtime_put(mas->dev);
268 }
269
spi_setup_word_len(struct spi_geni_master * mas,u16 mode,unsigned int bits_per_word)270 static void spi_setup_word_len(struct spi_geni_master *mas, u16 mode,
271 unsigned int bits_per_word)
272 {
273 unsigned int pack_words;
274 bool msb_first = (mode & SPI_LSB_FIRST) ? false : true;
275 struct geni_se *se = &mas->se;
276 u32 word_len;
277
278 /*
279 * If bits_per_word isn't a byte aligned value, set the packing to be
280 * 1 SPI word per FIFO word.
281 */
282 if (!(mas->fifo_width_bits % bits_per_word))
283 pack_words = mas->fifo_width_bits / bits_per_word;
284 else
285 pack_words = 1;
286 geni_se_config_packing(&mas->se, bits_per_word, pack_words, msb_first,
287 true, true);
288 word_len = (bits_per_word - MIN_WORD_LEN) & WORD_LEN_MSK;
289 writel(word_len, se->base + SE_SPI_WORD_LEN);
290 }
291
geni_spi_set_clock_and_bw(struct spi_geni_master * mas,unsigned long clk_hz)292 static int geni_spi_set_clock_and_bw(struct spi_geni_master *mas,
293 unsigned long clk_hz)
294 {
295 u32 clk_sel, m_clk_cfg, idx, div;
296 struct geni_se *se = &mas->se;
297 int ret;
298
299 if (clk_hz == mas->cur_speed_hz)
300 return 0;
301
302 ret = get_spi_clk_cfg(clk_hz, mas, &idx, &div);
303 if (ret) {
304 dev_err(mas->dev, "Err setting clk to %lu: %d\n", clk_hz, ret);
305 return ret;
306 }
307
308 /*
309 * SPI core clock gets configured with the requested frequency
310 * or the frequency closer to the requested frequency.
311 * For that reason requested frequency is stored in the
312 * cur_speed_hz and referred in the consecutive transfer instead
313 * of calling clk_get_rate() API.
314 */
315 mas->cur_speed_hz = clk_hz;
316
317 clk_sel = idx & CLK_SEL_MSK;
318 m_clk_cfg = (div << CLK_DIV_SHFT) | SER_CLK_EN;
319 writel(clk_sel, se->base + SE_GENI_CLK_SEL);
320 writel(m_clk_cfg, se->base + GENI_SER_M_CLK_CFG);
321
322 /* Set BW quota for CPU as driver supports FIFO mode only. */
323 se->icc_paths[CPU_TO_GENI].avg_bw = Bps_to_icc(mas->cur_speed_hz);
324 ret = geni_icc_set_bw(se);
325 if (ret)
326 return ret;
327
328 return 0;
329 }
330
setup_fifo_params(struct spi_device * spi_slv,struct spi_master * spi)331 static int setup_fifo_params(struct spi_device *spi_slv,
332 struct spi_master *spi)
333 {
334 struct spi_geni_master *mas = spi_master_get_devdata(spi);
335 struct geni_se *se = &mas->se;
336 u32 loopback_cfg = 0, cpol = 0, cpha = 0, demux_output_inv = 0;
337 u32 demux_sel;
338
339 if (mas->last_mode != spi_slv->mode) {
340 if (spi_slv->mode & SPI_LOOP)
341 loopback_cfg = LOOPBACK_ENABLE;
342
343 if (spi_slv->mode & SPI_CPOL)
344 cpol = CPOL;
345
346 if (spi_slv->mode & SPI_CPHA)
347 cpha = CPHA;
348
349 if (spi_slv->mode & SPI_CS_HIGH)
350 demux_output_inv = BIT(spi_slv->chip_select);
351
352 demux_sel = spi_slv->chip_select;
353 mas->cur_bits_per_word = spi_slv->bits_per_word;
354
355 spi_setup_word_len(mas, spi_slv->mode, spi_slv->bits_per_word);
356 writel(loopback_cfg, se->base + SE_SPI_LOOPBACK);
357 writel(demux_sel, se->base + SE_SPI_DEMUX_SEL);
358 writel(cpha, se->base + SE_SPI_CPHA);
359 writel(cpol, se->base + SE_SPI_CPOL);
360 writel(demux_output_inv, se->base + SE_SPI_DEMUX_OUTPUT_INV);
361
362 mas->last_mode = spi_slv->mode;
363 }
364
365 return geni_spi_set_clock_and_bw(mas, spi_slv->max_speed_hz);
366 }
367
368 static void
spi_gsi_callback_result(void * cb,const struct dmaengine_result * result)369 spi_gsi_callback_result(void *cb, const struct dmaengine_result *result)
370 {
371 struct spi_master *spi = cb;
372
373 spi->cur_msg->status = -EIO;
374 if (result->result != DMA_TRANS_NOERROR) {
375 dev_err(&spi->dev, "DMA txn failed: %d\n", result->result);
376 spi_finalize_current_transfer(spi);
377 return;
378 }
379
380 if (!result->residue) {
381 spi->cur_msg->status = 0;
382 dev_dbg(&spi->dev, "DMA txn completed\n");
383 } else {
384 dev_err(&spi->dev, "DMA xfer has pending: %d\n", result->residue);
385 }
386
387 spi_finalize_current_transfer(spi);
388 }
389
setup_gsi_xfer(struct spi_transfer * xfer,struct spi_geni_master * mas,struct spi_device * spi_slv,struct spi_master * spi)390 static int setup_gsi_xfer(struct spi_transfer *xfer, struct spi_geni_master *mas,
391 struct spi_device *spi_slv, struct spi_master *spi)
392 {
393 unsigned long flags = DMA_PREP_INTERRUPT | DMA_CTRL_ACK;
394 struct dma_slave_config config = {};
395 struct gpi_spi_config peripheral = {};
396 struct dma_async_tx_descriptor *tx_desc, *rx_desc;
397 int ret;
398
399 config.peripheral_config = &peripheral;
400 config.peripheral_size = sizeof(peripheral);
401 peripheral.set_config = true;
402
403 if (xfer->bits_per_word != mas->cur_bits_per_word ||
404 xfer->speed_hz != mas->cur_speed_hz) {
405 mas->cur_bits_per_word = xfer->bits_per_word;
406 mas->cur_speed_hz = xfer->speed_hz;
407 }
408
409 if (xfer->tx_buf && xfer->rx_buf) {
410 peripheral.cmd = SPI_DUPLEX;
411 } else if (xfer->tx_buf) {
412 peripheral.cmd = SPI_TX;
413 peripheral.rx_len = 0;
414 } else if (xfer->rx_buf) {
415 peripheral.cmd = SPI_RX;
416 if (!(mas->cur_bits_per_word % MIN_WORD_LEN)) {
417 peripheral.rx_len = ((xfer->len << 3) / mas->cur_bits_per_word);
418 } else {
419 int bytes_per_word = (mas->cur_bits_per_word / BITS_PER_BYTE) + 1;
420
421 peripheral.rx_len = (xfer->len / bytes_per_word);
422 }
423 }
424
425 peripheral.loopback_en = !!(spi_slv->mode & SPI_LOOP);
426 peripheral.clock_pol_high = !!(spi_slv->mode & SPI_CPOL);
427 peripheral.data_pol_high = !!(spi_slv->mode & SPI_CPHA);
428 peripheral.cs = spi_slv->chip_select;
429 peripheral.pack_en = true;
430 peripheral.word_len = xfer->bits_per_word - MIN_WORD_LEN;
431
432 ret = get_spi_clk_cfg(mas->cur_speed_hz, mas,
433 &peripheral.clk_src, &peripheral.clk_div);
434 if (ret) {
435 dev_err(mas->dev, "Err in get_spi_clk_cfg() :%d\n", ret);
436 return ret;
437 }
438
439 if (!xfer->cs_change) {
440 if (!list_is_last(&xfer->transfer_list, &spi->cur_msg->transfers))
441 peripheral.fragmentation = FRAGMENTATION;
442 }
443
444 if (peripheral.cmd & SPI_RX) {
445 dmaengine_slave_config(mas->rx, &config);
446 rx_desc = dmaengine_prep_slave_sg(mas->rx, xfer->rx_sg.sgl, xfer->rx_sg.nents,
447 DMA_DEV_TO_MEM, flags);
448 if (!rx_desc) {
449 dev_err(mas->dev, "Err setting up rx desc\n");
450 return -EIO;
451 }
452 }
453
454 /*
455 * Prepare the TX always, even for RX or tx_buf being null, we would
456 * need TX to be prepared per GSI spec
457 */
458 dmaengine_slave_config(mas->tx, &config);
459 tx_desc = dmaengine_prep_slave_sg(mas->tx, xfer->tx_sg.sgl, xfer->tx_sg.nents,
460 DMA_MEM_TO_DEV, flags);
461 if (!tx_desc) {
462 dev_err(mas->dev, "Err setting up tx desc\n");
463 return -EIO;
464 }
465
466 tx_desc->callback_result = spi_gsi_callback_result;
467 tx_desc->callback_param = spi;
468
469 if (peripheral.cmd & SPI_RX)
470 dmaengine_submit(rx_desc);
471 dmaengine_submit(tx_desc);
472
473 if (peripheral.cmd & SPI_RX)
474 dma_async_issue_pending(mas->rx);
475
476 dma_async_issue_pending(mas->tx);
477 return 1;
478 }
479
geni_can_dma(struct spi_controller * ctlr,struct spi_device * slv,struct spi_transfer * xfer)480 static bool geni_can_dma(struct spi_controller *ctlr,
481 struct spi_device *slv, struct spi_transfer *xfer)
482 {
483 struct spi_geni_master *mas = spi_master_get_devdata(slv->master);
484
485 /* check if dma is supported */
486 return mas->cur_xfer_mode != GENI_SE_FIFO;
487 }
488
spi_geni_prepare_message(struct spi_master * spi,struct spi_message * spi_msg)489 static int spi_geni_prepare_message(struct spi_master *spi,
490 struct spi_message *spi_msg)
491 {
492 struct spi_geni_master *mas = spi_master_get_devdata(spi);
493 int ret;
494
495 switch (mas->cur_xfer_mode) {
496 case GENI_SE_FIFO:
497 if (spi_geni_is_abort_still_pending(mas))
498 return -EBUSY;
499 ret = setup_fifo_params(spi_msg->spi, spi);
500 if (ret)
501 dev_err(mas->dev, "Couldn't select mode %d\n", ret);
502 return ret;
503
504 case GENI_GPI_DMA:
505 /* nothing to do for GPI DMA */
506 return 0;
507 }
508
509 dev_err(mas->dev, "Mode not supported %d", mas->cur_xfer_mode);
510 return -EINVAL;
511 }
512
spi_geni_grab_gpi_chan(struct spi_geni_master * mas)513 static int spi_geni_grab_gpi_chan(struct spi_geni_master *mas)
514 {
515 int ret;
516
517 mas->tx = dma_request_chan(mas->dev, "tx");
518 if (IS_ERR(mas->tx)) {
519 ret = dev_err_probe(mas->dev, PTR_ERR(mas->tx),
520 "Failed to get tx DMA ch\n");
521 goto err_tx;
522 }
523
524 mas->rx = dma_request_chan(mas->dev, "rx");
525 if (IS_ERR(mas->rx)) {
526 ret = dev_err_probe(mas->dev, PTR_ERR(mas->rx),
527 "Failed to get rx DMA ch\n");
528 goto err_rx;
529 }
530
531 return 0;
532
533 err_rx:
534 mas->rx = NULL;
535 dma_release_channel(mas->tx);
536 err_tx:
537 mas->tx = NULL;
538 return ret;
539 }
540
spi_geni_release_dma_chan(struct spi_geni_master * mas)541 static void spi_geni_release_dma_chan(struct spi_geni_master *mas)
542 {
543 if (mas->rx) {
544 dma_release_channel(mas->rx);
545 mas->rx = NULL;
546 }
547
548 if (mas->tx) {
549 dma_release_channel(mas->tx);
550 mas->tx = NULL;
551 }
552 }
553
spi_geni_init(struct spi_geni_master * mas)554 static int spi_geni_init(struct spi_geni_master *mas)
555 {
556 struct geni_se *se = &mas->se;
557 unsigned int proto, major, minor, ver;
558 u32 spi_tx_cfg, fifo_disable;
559 int ret = -ENXIO;
560
561 pm_runtime_get_sync(mas->dev);
562
563 proto = geni_se_read_proto(se);
564 if (proto != GENI_SE_SPI) {
565 dev_err(mas->dev, "Invalid proto %d\n", proto);
566 goto out_pm;
567 }
568 mas->tx_fifo_depth = geni_se_get_tx_fifo_depth(se);
569
570 /* Width of Tx and Rx FIFO is same */
571 mas->fifo_width_bits = geni_se_get_tx_fifo_width(se);
572
573 /*
574 * Hardware programming guide suggests to configure
575 * RX FIFO RFR level to fifo_depth-2.
576 */
577 geni_se_init(se, mas->tx_fifo_depth - 3, mas->tx_fifo_depth - 2);
578 /* Transmit an entire FIFO worth of data per IRQ */
579 mas->tx_wm = 1;
580 ver = geni_se_get_qup_hw_version(se);
581 major = GENI_SE_VERSION_MAJOR(ver);
582 minor = GENI_SE_VERSION_MINOR(ver);
583
584 if (major == 1 && minor == 0)
585 mas->oversampling = 2;
586 else
587 mas->oversampling = 1;
588
589 fifo_disable = readl(se->base + GENI_IF_DISABLE_RO) & FIFO_IF_DISABLE;
590 switch (fifo_disable) {
591 case 1:
592 ret = spi_geni_grab_gpi_chan(mas);
593 if (!ret) { /* success case */
594 mas->cur_xfer_mode = GENI_GPI_DMA;
595 geni_se_select_mode(se, GENI_GPI_DMA);
596 dev_dbg(mas->dev, "Using GPI DMA mode for SPI\n");
597 break;
598 }
599 /*
600 * in case of failure to get dma channel, we can still do the
601 * FIFO mode, so fallthrough
602 */
603 dev_warn(mas->dev, "FIFO mode disabled, but couldn't get DMA, fall back to FIFO mode\n");
604 fallthrough;
605
606 case 0:
607 mas->cur_xfer_mode = GENI_SE_FIFO;
608 geni_se_select_mode(se, GENI_SE_FIFO);
609 ret = 0;
610 break;
611 }
612
613 /* We always control CS manually */
614 spi_tx_cfg = readl(se->base + SE_SPI_TRANS_CFG);
615 spi_tx_cfg &= ~CS_TOGGLE;
616 writel(spi_tx_cfg, se->base + SE_SPI_TRANS_CFG);
617
618 out_pm:
619 pm_runtime_put(mas->dev);
620 return ret;
621 }
622
geni_byte_per_fifo_word(struct spi_geni_master * mas)623 static unsigned int geni_byte_per_fifo_word(struct spi_geni_master *mas)
624 {
625 /*
626 * Calculate how many bytes we'll put in each FIFO word. If the
627 * transfer words don't pack cleanly into a FIFO word we'll just put
628 * one transfer word in each FIFO word. If they do pack we'll pack 'em.
629 */
630 if (mas->fifo_width_bits % mas->cur_bits_per_word)
631 return roundup_pow_of_two(DIV_ROUND_UP(mas->cur_bits_per_word,
632 BITS_PER_BYTE));
633
634 return mas->fifo_width_bits / BITS_PER_BYTE;
635 }
636
geni_spi_handle_tx(struct spi_geni_master * mas)637 static bool geni_spi_handle_tx(struct spi_geni_master *mas)
638 {
639 struct geni_se *se = &mas->se;
640 unsigned int max_bytes;
641 const u8 *tx_buf;
642 unsigned int bytes_per_fifo_word = geni_byte_per_fifo_word(mas);
643 unsigned int i = 0;
644
645 /* Stop the watermark IRQ if nothing to send */
646 if (!mas->cur_xfer) {
647 writel(0, se->base + SE_GENI_TX_WATERMARK_REG);
648 return false;
649 }
650
651 max_bytes = (mas->tx_fifo_depth - mas->tx_wm) * bytes_per_fifo_word;
652 if (mas->tx_rem_bytes < max_bytes)
653 max_bytes = mas->tx_rem_bytes;
654
655 tx_buf = mas->cur_xfer->tx_buf + mas->cur_xfer->len - mas->tx_rem_bytes;
656 while (i < max_bytes) {
657 unsigned int j;
658 unsigned int bytes_to_write;
659 u32 fifo_word = 0;
660 u8 *fifo_byte = (u8 *)&fifo_word;
661
662 bytes_to_write = min(bytes_per_fifo_word, max_bytes - i);
663 for (j = 0; j < bytes_to_write; j++)
664 fifo_byte[j] = tx_buf[i++];
665 iowrite32_rep(se->base + SE_GENI_TX_FIFOn, &fifo_word, 1);
666 }
667 mas->tx_rem_bytes -= max_bytes;
668 if (!mas->tx_rem_bytes) {
669 writel(0, se->base + SE_GENI_TX_WATERMARK_REG);
670 return false;
671 }
672 return true;
673 }
674
geni_spi_handle_rx(struct spi_geni_master * mas)675 static void geni_spi_handle_rx(struct spi_geni_master *mas)
676 {
677 struct geni_se *se = &mas->se;
678 u32 rx_fifo_status;
679 unsigned int rx_bytes;
680 unsigned int rx_last_byte_valid;
681 u8 *rx_buf;
682 unsigned int bytes_per_fifo_word = geni_byte_per_fifo_word(mas);
683 unsigned int i = 0;
684
685 rx_fifo_status = readl(se->base + SE_GENI_RX_FIFO_STATUS);
686 rx_bytes = (rx_fifo_status & RX_FIFO_WC_MSK) * bytes_per_fifo_word;
687 if (rx_fifo_status & RX_LAST) {
688 rx_last_byte_valid = rx_fifo_status & RX_LAST_BYTE_VALID_MSK;
689 rx_last_byte_valid >>= RX_LAST_BYTE_VALID_SHFT;
690 if (rx_last_byte_valid && rx_last_byte_valid < 4)
691 rx_bytes -= bytes_per_fifo_word - rx_last_byte_valid;
692 }
693
694 /* Clear out the FIFO and bail if nowhere to put it */
695 if (!mas->cur_xfer) {
696 for (i = 0; i < DIV_ROUND_UP(rx_bytes, bytes_per_fifo_word); i++)
697 readl(se->base + SE_GENI_RX_FIFOn);
698 return;
699 }
700
701 if (mas->rx_rem_bytes < rx_bytes)
702 rx_bytes = mas->rx_rem_bytes;
703
704 rx_buf = mas->cur_xfer->rx_buf + mas->cur_xfer->len - mas->rx_rem_bytes;
705 while (i < rx_bytes) {
706 u32 fifo_word = 0;
707 u8 *fifo_byte = (u8 *)&fifo_word;
708 unsigned int bytes_to_read;
709 unsigned int j;
710
711 bytes_to_read = min(bytes_per_fifo_word, rx_bytes - i);
712 ioread32_rep(se->base + SE_GENI_RX_FIFOn, &fifo_word, 1);
713 for (j = 0; j < bytes_to_read; j++)
714 rx_buf[i++] = fifo_byte[j];
715 }
716 mas->rx_rem_bytes -= rx_bytes;
717 }
718
setup_fifo_xfer(struct spi_transfer * xfer,struct spi_geni_master * mas,u16 mode,struct spi_master * spi)719 static void setup_fifo_xfer(struct spi_transfer *xfer,
720 struct spi_geni_master *mas,
721 u16 mode, struct spi_master *spi)
722 {
723 u32 m_cmd = 0;
724 u32 len;
725 struct geni_se *se = &mas->se;
726 int ret;
727
728 /*
729 * Ensure that our interrupt handler isn't still running from some
730 * prior command before we start messing with the hardware behind
731 * its back. We don't need to _keep_ the lock here since we're only
732 * worried about racing with out interrupt handler. The SPI core
733 * already handles making sure that we're not trying to do two
734 * transfers at once or setting a chip select and doing a transfer
735 * concurrently.
736 *
737 * NOTE: we actually _can't_ hold the lock here because possibly we
738 * might call clk_set_rate() which needs to be able to sleep.
739 */
740 spin_lock_irq(&mas->lock);
741 spin_unlock_irq(&mas->lock);
742
743 if (xfer->bits_per_word != mas->cur_bits_per_word) {
744 spi_setup_word_len(mas, mode, xfer->bits_per_word);
745 mas->cur_bits_per_word = xfer->bits_per_word;
746 }
747
748 /* Speed and bits per word can be overridden per transfer */
749 ret = geni_spi_set_clock_and_bw(mas, xfer->speed_hz);
750 if (ret)
751 return;
752
753 mas->tx_rem_bytes = 0;
754 mas->rx_rem_bytes = 0;
755
756 if (!(mas->cur_bits_per_word % MIN_WORD_LEN))
757 len = xfer->len * BITS_PER_BYTE / mas->cur_bits_per_word;
758 else
759 len = xfer->len / (mas->cur_bits_per_word / BITS_PER_BYTE + 1);
760 len &= TRANS_LEN_MSK;
761
762 mas->cur_xfer = xfer;
763 if (xfer->tx_buf) {
764 m_cmd |= SPI_TX_ONLY;
765 mas->tx_rem_bytes = xfer->len;
766 writel(len, se->base + SE_SPI_TX_TRANS_LEN);
767 }
768
769 if (xfer->rx_buf) {
770 m_cmd |= SPI_RX_ONLY;
771 writel(len, se->base + SE_SPI_RX_TRANS_LEN);
772 mas->rx_rem_bytes = xfer->len;
773 }
774
775 /*
776 * Lock around right before we start the transfer since our
777 * interrupt could come in at any time now.
778 */
779 spin_lock_irq(&mas->lock);
780 geni_se_setup_m_cmd(se, m_cmd, FRAGMENTATION);
781 if (m_cmd & SPI_TX_ONLY) {
782 if (geni_spi_handle_tx(mas))
783 writel(mas->tx_wm, se->base + SE_GENI_TX_WATERMARK_REG);
784 }
785 spin_unlock_irq(&mas->lock);
786 }
787
spi_geni_transfer_one(struct spi_master * spi,struct spi_device * slv,struct spi_transfer * xfer)788 static int spi_geni_transfer_one(struct spi_master *spi,
789 struct spi_device *slv,
790 struct spi_transfer *xfer)
791 {
792 struct spi_geni_master *mas = spi_master_get_devdata(spi);
793
794 if (spi_geni_is_abort_still_pending(mas))
795 return -EBUSY;
796
797 /* Terminate and return success for 0 byte length transfer */
798 if (!xfer->len)
799 return 0;
800
801 if (mas->cur_xfer_mode == GENI_SE_FIFO) {
802 setup_fifo_xfer(xfer, mas, slv->mode, spi);
803 return 1;
804 }
805 return setup_gsi_xfer(xfer, mas, slv, spi);
806 }
807
geni_spi_isr(int irq,void * data)808 static irqreturn_t geni_spi_isr(int irq, void *data)
809 {
810 struct spi_master *spi = data;
811 struct spi_geni_master *mas = spi_master_get_devdata(spi);
812 struct geni_se *se = &mas->se;
813 u32 m_irq;
814
815 m_irq = readl(se->base + SE_GENI_M_IRQ_STATUS);
816 if (!m_irq)
817 return IRQ_NONE;
818
819 if (m_irq & (M_CMD_OVERRUN_EN | M_ILLEGAL_CMD_EN | M_CMD_FAILURE_EN |
820 M_RX_FIFO_RD_ERR_EN | M_RX_FIFO_WR_ERR_EN |
821 M_TX_FIFO_RD_ERR_EN | M_TX_FIFO_WR_ERR_EN))
822 dev_warn(mas->dev, "Unexpected IRQ err status %#010x\n", m_irq);
823
824 spin_lock(&mas->lock);
825
826 if ((m_irq & M_RX_FIFO_WATERMARK_EN) || (m_irq & M_RX_FIFO_LAST_EN))
827 geni_spi_handle_rx(mas);
828
829 if (m_irq & M_TX_FIFO_WATERMARK_EN)
830 geni_spi_handle_tx(mas);
831
832 if (m_irq & M_CMD_DONE_EN) {
833 if (mas->cur_xfer) {
834 spi_finalize_current_transfer(spi);
835 mas->cur_xfer = NULL;
836 /*
837 * If this happens, then a CMD_DONE came before all the
838 * Tx buffer bytes were sent out. This is unusual, log
839 * this condition and disable the WM interrupt to
840 * prevent the system from stalling due an interrupt
841 * storm.
842 *
843 * If this happens when all Rx bytes haven't been
844 * received, log the condition. The only known time
845 * this can happen is if bits_per_word != 8 and some
846 * registers that expect xfer lengths in num spi_words
847 * weren't written correctly.
848 */
849 if (mas->tx_rem_bytes) {
850 writel(0, se->base + SE_GENI_TX_WATERMARK_REG);
851 dev_err(mas->dev, "Premature done. tx_rem = %d bpw%d\n",
852 mas->tx_rem_bytes, mas->cur_bits_per_word);
853 }
854 if (mas->rx_rem_bytes)
855 dev_err(mas->dev, "Premature done. rx_rem = %d bpw%d\n",
856 mas->rx_rem_bytes, mas->cur_bits_per_word);
857 } else {
858 complete(&mas->cs_done);
859 }
860 }
861
862 if (m_irq & M_CMD_CANCEL_EN)
863 complete(&mas->cancel_done);
864 if (m_irq & M_CMD_ABORT_EN)
865 complete(&mas->abort_done);
866
867 /*
868 * It's safe or a good idea to Ack all of our interrupts at the end
869 * of the function. Specifically:
870 * - M_CMD_DONE_EN / M_RX_FIFO_LAST_EN: Edge triggered interrupts and
871 * clearing Acks. Clearing at the end relies on nobody else having
872 * started a new transfer yet or else we could be clearing _their_
873 * done bit, but everyone grabs the spinlock before starting a new
874 * transfer.
875 * - M_RX_FIFO_WATERMARK_EN / M_TX_FIFO_WATERMARK_EN: These appear
876 * to be "latched level" interrupts so it's important to clear them
877 * _after_ you've handled the condition and always safe to do so
878 * since they'll re-assert if they're still happening.
879 */
880 writel(m_irq, se->base + SE_GENI_M_IRQ_CLEAR);
881
882 spin_unlock(&mas->lock);
883
884 return IRQ_HANDLED;
885 }
886
spi_geni_probe(struct platform_device * pdev)887 static int spi_geni_probe(struct platform_device *pdev)
888 {
889 int ret, irq;
890 struct spi_master *spi;
891 struct spi_geni_master *mas;
892 void __iomem *base;
893 struct clk *clk;
894 struct device *dev = &pdev->dev;
895
896 irq = platform_get_irq(pdev, 0);
897 if (irq < 0)
898 return irq;
899
900 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));
901 if (ret)
902 return dev_err_probe(dev, ret, "could not set DMA mask\n");
903
904 base = devm_platform_ioremap_resource(pdev, 0);
905 if (IS_ERR(base))
906 return PTR_ERR(base);
907
908 clk = devm_clk_get(dev, "se");
909 if (IS_ERR(clk))
910 return PTR_ERR(clk);
911
912 spi = devm_spi_alloc_master(dev, sizeof(*mas));
913 if (!spi)
914 return -ENOMEM;
915
916 platform_set_drvdata(pdev, spi);
917 mas = spi_master_get_devdata(spi);
918 mas->irq = irq;
919 mas->dev = dev;
920 mas->se.dev = dev;
921 mas->se.wrapper = dev_get_drvdata(dev->parent);
922 mas->se.base = base;
923 mas->se.clk = clk;
924
925 ret = devm_pm_opp_set_clkname(&pdev->dev, "se");
926 if (ret)
927 return ret;
928 /* OPP table is optional */
929 ret = devm_pm_opp_of_add_table(&pdev->dev);
930 if (ret && ret != -ENODEV) {
931 dev_err(&pdev->dev, "invalid OPP table in device tree\n");
932 return ret;
933 }
934
935 spi->bus_num = -1;
936 spi->dev.of_node = dev->of_node;
937 spi->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP | SPI_CS_HIGH;
938 spi->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
939 spi->num_chipselect = 4;
940 spi->max_speed_hz = 50000000;
941 spi->prepare_message = spi_geni_prepare_message;
942 spi->transfer_one = spi_geni_transfer_one;
943 spi->can_dma = geni_can_dma;
944 spi->dma_map_dev = dev->parent;
945 spi->auto_runtime_pm = true;
946 spi->handle_err = spi_geni_handle_err;
947 spi->use_gpio_descriptors = true;
948
949 init_completion(&mas->cs_done);
950 init_completion(&mas->cancel_done);
951 init_completion(&mas->abort_done);
952 spin_lock_init(&mas->lock);
953 pm_runtime_use_autosuspend(&pdev->dev);
954 pm_runtime_set_autosuspend_delay(&pdev->dev, 250);
955 pm_runtime_enable(dev);
956
957 ret = geni_icc_get(&mas->se, NULL);
958 if (ret)
959 goto spi_geni_probe_runtime_disable;
960 /* Set the bus quota to a reasonable value for register access */
961 mas->se.icc_paths[GENI_TO_CORE].avg_bw = Bps_to_icc(CORE_2X_50_MHZ);
962 mas->se.icc_paths[CPU_TO_GENI].avg_bw = GENI_DEFAULT_BW;
963
964 ret = geni_icc_set_bw(&mas->se);
965 if (ret)
966 goto spi_geni_probe_runtime_disable;
967
968 ret = spi_geni_init(mas);
969 if (ret)
970 goto spi_geni_probe_runtime_disable;
971
972 /*
973 * check the mode supported and set_cs for fifo mode only
974 * for dma (gsi) mode, the gsi will set cs based on params passed in
975 * TRE
976 */
977 if (mas->cur_xfer_mode == GENI_SE_FIFO)
978 spi->set_cs = spi_geni_set_cs;
979
980 ret = request_irq(mas->irq, geni_spi_isr, 0, dev_name(dev), spi);
981 if (ret)
982 goto spi_geni_release_dma;
983
984 ret = spi_register_master(spi);
985 if (ret)
986 goto spi_geni_probe_free_irq;
987
988 return 0;
989 spi_geni_probe_free_irq:
990 free_irq(mas->irq, spi);
991 spi_geni_release_dma:
992 spi_geni_release_dma_chan(mas);
993 spi_geni_probe_runtime_disable:
994 pm_runtime_disable(dev);
995 return ret;
996 }
997
spi_geni_remove(struct platform_device * pdev)998 static int spi_geni_remove(struct platform_device *pdev)
999 {
1000 struct spi_master *spi = platform_get_drvdata(pdev);
1001 struct spi_geni_master *mas = spi_master_get_devdata(spi);
1002
1003 /* Unregister _before_ disabling pm_runtime() so we stop transfers */
1004 spi_unregister_master(spi);
1005
1006 spi_geni_release_dma_chan(mas);
1007
1008 free_irq(mas->irq, spi);
1009 pm_runtime_disable(&pdev->dev);
1010 return 0;
1011 }
1012
spi_geni_runtime_suspend(struct device * dev)1013 static int __maybe_unused spi_geni_runtime_suspend(struct device *dev)
1014 {
1015 struct spi_master *spi = dev_get_drvdata(dev);
1016 struct spi_geni_master *mas = spi_master_get_devdata(spi);
1017 int ret;
1018
1019 /* Drop the performance state vote */
1020 dev_pm_opp_set_rate(dev, 0);
1021
1022 ret = geni_se_resources_off(&mas->se);
1023 if (ret)
1024 return ret;
1025
1026 return geni_icc_disable(&mas->se);
1027 }
1028
spi_geni_runtime_resume(struct device * dev)1029 static int __maybe_unused spi_geni_runtime_resume(struct device *dev)
1030 {
1031 struct spi_master *spi = dev_get_drvdata(dev);
1032 struct spi_geni_master *mas = spi_master_get_devdata(spi);
1033 int ret;
1034
1035 ret = geni_icc_enable(&mas->se);
1036 if (ret)
1037 return ret;
1038
1039 ret = geni_se_resources_on(&mas->se);
1040 if (ret)
1041 return ret;
1042
1043 return dev_pm_opp_set_rate(mas->dev, mas->cur_sclk_hz);
1044 }
1045
spi_geni_suspend(struct device * dev)1046 static int __maybe_unused spi_geni_suspend(struct device *dev)
1047 {
1048 struct spi_master *spi = dev_get_drvdata(dev);
1049 int ret;
1050
1051 ret = spi_master_suspend(spi);
1052 if (ret)
1053 return ret;
1054
1055 ret = pm_runtime_force_suspend(dev);
1056 if (ret)
1057 spi_master_resume(spi);
1058
1059 return ret;
1060 }
1061
spi_geni_resume(struct device * dev)1062 static int __maybe_unused spi_geni_resume(struct device *dev)
1063 {
1064 struct spi_master *spi = dev_get_drvdata(dev);
1065 int ret;
1066
1067 ret = pm_runtime_force_resume(dev);
1068 if (ret)
1069 return ret;
1070
1071 ret = spi_master_resume(spi);
1072 if (ret)
1073 pm_runtime_force_suspend(dev);
1074
1075 return ret;
1076 }
1077
1078 static const struct dev_pm_ops spi_geni_pm_ops = {
1079 SET_RUNTIME_PM_OPS(spi_geni_runtime_suspend,
1080 spi_geni_runtime_resume, NULL)
1081 SET_SYSTEM_SLEEP_PM_OPS(spi_geni_suspend, spi_geni_resume)
1082 };
1083
1084 static const struct of_device_id spi_geni_dt_match[] = {
1085 { .compatible = "qcom,geni-spi" },
1086 {}
1087 };
1088 MODULE_DEVICE_TABLE(of, spi_geni_dt_match);
1089
1090 static struct platform_driver spi_geni_driver = {
1091 .probe = spi_geni_probe,
1092 .remove = spi_geni_remove,
1093 .driver = {
1094 .name = "geni_spi",
1095 .pm = &spi_geni_pm_ops,
1096 .of_match_table = spi_geni_dt_match,
1097 },
1098 };
1099 module_platform_driver(spi_geni_driver);
1100
1101 MODULE_DESCRIPTION("SPI driver for GENI based QUP cores");
1102 MODULE_LICENSE("GPL v2");
1103
