1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Renesas RZ/V2M Pin Control and GPIO driver core
4 *
5 * Based on:
6 * Renesas RZ/G2L Pin Control and GPIO driver core
7 *
8 * Copyright (C) 2022 Renesas Electronics Corporation.
9 */
10
11 #include <linux/bitfield.h>
12 #include <linux/bitops.h>
13 #include <linux/clk.h>
14 #include <linux/gpio/driver.h>
15 #include <linux/io.h>
16 #include <linux/module.h>
17 #include <linux/of_device.h>
18 #include <linux/pinctrl/pinconf-generic.h>
19 #include <linux/pinctrl/pinconf.h>
20 #include <linux/pinctrl/pinctrl.h>
21 #include <linux/pinctrl/pinmux.h>
22 #include <linux/spinlock.h>
23
24 #include <dt-bindings/pinctrl/rzv2m-pinctrl.h>
25
26 #include "../core.h"
27 #include "../pinconf.h"
28 #include "../pinmux.h"
29
30 #define DRV_NAME "pinctrl-rzv2m"
31
32 /*
33 * Use 16 lower bits [15:0] for pin identifier
34 * Use 16 higher bits [31:16] for pin mux function
35 */
36 #define MUX_PIN_ID_MASK GENMASK(15, 0)
37 #define MUX_FUNC_MASK GENMASK(31, 16)
38 #define MUX_FUNC(pinconf) FIELD_GET(MUX_FUNC_MASK, (pinconf))
39
40 /* PIN capabilities */
41 #define PIN_CFG_GRP_1_8V_2 1
42 #define PIN_CFG_GRP_1_8V_3 2
43 #define PIN_CFG_GRP_SWIO_1 3
44 #define PIN_CFG_GRP_SWIO_2 4
45 #define PIN_CFG_GRP_3_3V 5
46 #define PIN_CFG_GRP_MASK GENMASK(2, 0)
47 #define PIN_CFG_BIAS BIT(3)
48 #define PIN_CFG_DRV BIT(4)
49 #define PIN_CFG_SLEW BIT(5)
50
51 #define RZV2M_MPXED_PIN_FUNCS (PIN_CFG_BIAS | \
52 PIN_CFG_DRV | \
53 PIN_CFG_SLEW)
54
55 /*
56 * n indicates number of pins in the port, a is the register index
57 * and f is pin configuration capabilities supported.
58 */
59 #define RZV2M_GPIO_PORT_PACK(n, a, f) (((n) << 24) | ((a) << 16) | (f))
60 #define RZV2M_GPIO_PORT_GET_PINCNT(x) FIELD_GET(GENMASK(31, 24), (x))
61 #define RZV2M_GPIO_PORT_GET_INDEX(x) FIELD_GET(GENMASK(23, 16), (x))
62 #define RZV2M_GPIO_PORT_GET_CFGS(x) FIELD_GET(GENMASK(15, 0), (x))
63
64 #define RZV2M_DEDICATED_PORT_IDX 22
65
66 /*
67 * BIT(31) indicates dedicated pin, b is the register bits (b * 16)
68 * and f is the pin configuration capabilities supported.
69 */
70 #define RZV2M_SINGLE_PIN BIT(31)
71 #define RZV2M_SINGLE_PIN_PACK(b, f) (RZV2M_SINGLE_PIN | \
72 ((RZV2M_DEDICATED_PORT_IDX) << 24) | \
73 ((b) << 16) | (f))
74 #define RZV2M_SINGLE_PIN_GET_PORT(x) FIELD_GET(GENMASK(30, 24), (x))
75 #define RZV2M_SINGLE_PIN_GET_BIT(x) FIELD_GET(GENMASK(23, 16), (x))
76 #define RZV2M_SINGLE_PIN_GET_CFGS(x) FIELD_GET(GENMASK(15, 0), (x))
77
78 #define RZV2M_PIN_ID_TO_PORT(id) ((id) / RZV2M_PINS_PER_PORT)
79 #define RZV2M_PIN_ID_TO_PIN(id) ((id) % RZV2M_PINS_PER_PORT)
80
81 #define DO(n) (0x00 + (n) * 0x40)
82 #define OE(n) (0x04 + (n) * 0x40)
83 #define IE(n) (0x08 + (n) * 0x40)
84 #define PFSEL(n) (0x10 + (n) * 0x40)
85 #define DI(n) (0x20 + (n) * 0x40)
86 #define PUPD(n) (0x24 + (n) * 0x40)
87 #define DRV(n) ((n) < RZV2M_DEDICATED_PORT_IDX ? (0x28 + (n) * 0x40) \
88 : 0x590)
89 #define SR(n) ((n) < RZV2M_DEDICATED_PORT_IDX ? (0x2c + (n) * 0x40) \
90 : 0x594)
91 #define DI_MSK(n) (0x30 + (n) * 0x40)
92 #define EN_MSK(n) (0x34 + (n) * 0x40)
93
94 #define PFC_MASK 0x07
95 #define PUPD_MASK 0x03
96 #define DRV_MASK 0x03
97
98 struct rzv2m_dedicated_configs {
99 const char *name;
100 u32 config;
101 };
102
103 struct rzv2m_pinctrl_data {
104 const char * const *port_pins;
105 const u32 *port_pin_configs;
106 const struct rzv2m_dedicated_configs *dedicated_pins;
107 unsigned int n_port_pins;
108 unsigned int n_dedicated_pins;
109 };
110
111 struct rzv2m_pinctrl {
112 struct pinctrl_dev *pctl;
113 struct pinctrl_desc desc;
114 struct pinctrl_pin_desc *pins;
115
116 const struct rzv2m_pinctrl_data *data;
117 void __iomem *base;
118 struct device *dev;
119 struct clk *clk;
120
121 struct gpio_chip gpio_chip;
122 struct pinctrl_gpio_range gpio_range;
123
124 spinlock_t lock;
125 };
126
127 static const unsigned int drv_1_8V_group2_uA[] = { 1800, 3800, 7800, 11000 };
128 static const unsigned int drv_1_8V_group3_uA[] = { 1600, 3200, 6400, 9600 };
129 static const unsigned int drv_SWIO_group2_3_3V_uA[] = { 9000, 11000, 13000, 18000 };
130 static const unsigned int drv_3_3V_group_uA[] = { 2000, 4000, 8000, 12000 };
131
132 /* Helper for registers that have a write enable bit in the upper word */
rzv2m_writel_we(void __iomem * addr,u8 shift,u8 value)133 static void rzv2m_writel_we(void __iomem *addr, u8 shift, u8 value)
134 {
135 writel((BIT(16) | value) << shift, addr);
136 }
137
rzv2m_pinctrl_set_pfc_mode(struct rzv2m_pinctrl * pctrl,u8 port,u8 pin,u8 func)138 static void rzv2m_pinctrl_set_pfc_mode(struct rzv2m_pinctrl *pctrl,
139 u8 port, u8 pin, u8 func)
140 {
141 void __iomem *addr;
142
143 /* Mask input/output */
144 rzv2m_writel_we(pctrl->base + DI_MSK(port), pin, 1);
145 rzv2m_writel_we(pctrl->base + EN_MSK(port), pin, 1);
146
147 /* Select the function and set the write enable bits */
148 addr = pctrl->base + PFSEL(port) + (pin / 4) * 4;
149 writel(((PFC_MASK << 16) | func) << ((pin % 4) * 4), addr);
150
151 /* Unmask input/output */
152 rzv2m_writel_we(pctrl->base + EN_MSK(port), pin, 0);
153 rzv2m_writel_we(pctrl->base + DI_MSK(port), pin, 0);
154 };
155
rzv2m_pinctrl_set_mux(struct pinctrl_dev * pctldev,unsigned int func_selector,unsigned int group_selector)156 static int rzv2m_pinctrl_set_mux(struct pinctrl_dev *pctldev,
157 unsigned int func_selector,
158 unsigned int group_selector)
159 {
160 struct rzv2m_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
161 struct function_desc *func;
162 unsigned int i, *psel_val;
163 struct group_desc *group;
164 int *pins;
165
166 func = pinmux_generic_get_function(pctldev, func_selector);
167 if (!func)
168 return -EINVAL;
169 group = pinctrl_generic_get_group(pctldev, group_selector);
170 if (!group)
171 return -EINVAL;
172
173 psel_val = func->data;
174 pins = group->pins;
175
176 for (i = 0; i < group->num_pins; i++) {
177 dev_dbg(pctrl->dev, "port:%u pin: %u PSEL:%u\n",
178 RZV2M_PIN_ID_TO_PORT(pins[i]), RZV2M_PIN_ID_TO_PIN(pins[i]),
179 psel_val[i]);
180 rzv2m_pinctrl_set_pfc_mode(pctrl, RZV2M_PIN_ID_TO_PORT(pins[i]),
181 RZV2M_PIN_ID_TO_PIN(pins[i]), psel_val[i]);
182 }
183
184 return 0;
185 };
186
rzv2m_map_add_config(struct pinctrl_map * map,const char * group_or_pin,enum pinctrl_map_type type,unsigned long * configs,unsigned int num_configs)187 static int rzv2m_map_add_config(struct pinctrl_map *map,
188 const char *group_or_pin,
189 enum pinctrl_map_type type,
190 unsigned long *configs,
191 unsigned int num_configs)
192 {
193 unsigned long *cfgs;
194
195 cfgs = kmemdup(configs, num_configs * sizeof(*cfgs),
196 GFP_KERNEL);
197 if (!cfgs)
198 return -ENOMEM;
199
200 map->type = type;
201 map->data.configs.group_or_pin = group_or_pin;
202 map->data.configs.configs = cfgs;
203 map->data.configs.num_configs = num_configs;
204
205 return 0;
206 }
207
rzv2m_dt_subnode_to_map(struct pinctrl_dev * pctldev,struct device_node * np,struct pinctrl_map ** map,unsigned int * num_maps,unsigned int * index)208 static int rzv2m_dt_subnode_to_map(struct pinctrl_dev *pctldev,
209 struct device_node *np,
210 struct pinctrl_map **map,
211 unsigned int *num_maps,
212 unsigned int *index)
213 {
214 struct rzv2m_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
215 struct pinctrl_map *maps = *map;
216 unsigned int nmaps = *num_maps;
217 unsigned long *configs = NULL;
218 unsigned int *pins, *psel_val;
219 unsigned int num_pinmux = 0;
220 unsigned int idx = *index;
221 unsigned int num_pins, i;
222 unsigned int num_configs;
223 struct property *pinmux;
224 struct property *prop;
225 int ret, gsel, fsel;
226 const char **pin_fn;
227 const char *pin;
228
229 pinmux = of_find_property(np, "pinmux", NULL);
230 if (pinmux)
231 num_pinmux = pinmux->length / sizeof(u32);
232
233 ret = of_property_count_strings(np, "pins");
234 if (ret == -EINVAL) {
235 num_pins = 0;
236 } else if (ret < 0) {
237 dev_err(pctrl->dev, "Invalid pins list in DT\n");
238 return ret;
239 } else {
240 num_pins = ret;
241 }
242
243 if (!num_pinmux && !num_pins)
244 return 0;
245
246 if (num_pinmux && num_pins) {
247 dev_err(pctrl->dev,
248 "DT node must contain either a pinmux or pins and not both\n");
249 return -EINVAL;
250 }
251
252 ret = pinconf_generic_parse_dt_config(np, NULL, &configs, &num_configs);
253 if (ret < 0)
254 return ret;
255
256 if (num_pins && !num_configs) {
257 dev_err(pctrl->dev, "DT node must contain a config\n");
258 ret = -ENODEV;
259 goto done;
260 }
261
262 if (num_pinmux)
263 nmaps += 1;
264
265 if (num_pins)
266 nmaps += num_pins;
267
268 maps = krealloc_array(maps, nmaps, sizeof(*maps), GFP_KERNEL);
269 if (!maps) {
270 ret = -ENOMEM;
271 goto done;
272 }
273
274 *map = maps;
275 *num_maps = nmaps;
276 if (num_pins) {
277 of_property_for_each_string(np, "pins", prop, pin) {
278 ret = rzv2m_map_add_config(&maps[idx], pin,
279 PIN_MAP_TYPE_CONFIGS_PIN,
280 configs, num_configs);
281 if (ret < 0)
282 goto done;
283
284 idx++;
285 }
286 ret = 0;
287 goto done;
288 }
289
290 pins = devm_kcalloc(pctrl->dev, num_pinmux, sizeof(*pins), GFP_KERNEL);
291 psel_val = devm_kcalloc(pctrl->dev, num_pinmux, sizeof(*psel_val),
292 GFP_KERNEL);
293 pin_fn = devm_kzalloc(pctrl->dev, sizeof(*pin_fn), GFP_KERNEL);
294 if (!pins || !psel_val || !pin_fn) {
295 ret = -ENOMEM;
296 goto done;
297 }
298
299 /* Collect pin locations and mux settings from DT properties */
300 for (i = 0; i < num_pinmux; ++i) {
301 u32 value;
302
303 ret = of_property_read_u32_index(np, "pinmux", i, &value);
304 if (ret)
305 goto done;
306 pins[i] = value & MUX_PIN_ID_MASK;
307 psel_val[i] = MUX_FUNC(value);
308 }
309
310 /* Register a single pin group listing all the pins we read from DT */
311 gsel = pinctrl_generic_add_group(pctldev, np->name, pins, num_pinmux, NULL);
312 if (gsel < 0) {
313 ret = gsel;
314 goto done;
315 }
316
317 /*
318 * Register a single group function where the 'data' is an array PSEL
319 * register values read from DT.
320 */
321 pin_fn[0] = np->name;
322 fsel = pinmux_generic_add_function(pctldev, np->name, pin_fn, 1,
323 psel_val);
324 if (fsel < 0) {
325 ret = fsel;
326 goto remove_group;
327 }
328
329 maps[idx].type = PIN_MAP_TYPE_MUX_GROUP;
330 maps[idx].data.mux.group = np->name;
331 maps[idx].data.mux.function = np->name;
332 idx++;
333
334 dev_dbg(pctrl->dev, "Parsed %pOF with %d pins\n", np, num_pinmux);
335 ret = 0;
336 goto done;
337
338 remove_group:
339 pinctrl_generic_remove_group(pctldev, gsel);
340 done:
341 *index = idx;
342 kfree(configs);
343 return ret;
344 }
345
rzv2m_dt_free_map(struct pinctrl_dev * pctldev,struct pinctrl_map * map,unsigned int num_maps)346 static void rzv2m_dt_free_map(struct pinctrl_dev *pctldev,
347 struct pinctrl_map *map,
348 unsigned int num_maps)
349 {
350 unsigned int i;
351
352 if (!map)
353 return;
354
355 for (i = 0; i < num_maps; ++i) {
356 if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP ||
357 map[i].type == PIN_MAP_TYPE_CONFIGS_PIN)
358 kfree(map[i].data.configs.configs);
359 }
360 kfree(map);
361 }
362
rzv2m_dt_node_to_map(struct pinctrl_dev * pctldev,struct device_node * np,struct pinctrl_map ** map,unsigned int * num_maps)363 static int rzv2m_dt_node_to_map(struct pinctrl_dev *pctldev,
364 struct device_node *np,
365 struct pinctrl_map **map,
366 unsigned int *num_maps)
367 {
368 struct rzv2m_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
369 struct device_node *child;
370 unsigned int index;
371 int ret;
372
373 *map = NULL;
374 *num_maps = 0;
375 index = 0;
376
377 for_each_child_of_node(np, child) {
378 ret = rzv2m_dt_subnode_to_map(pctldev, child, map,
379 num_maps, &index);
380 if (ret < 0) {
381 of_node_put(child);
382 goto done;
383 }
384 }
385
386 if (*num_maps == 0) {
387 ret = rzv2m_dt_subnode_to_map(pctldev, np, map,
388 num_maps, &index);
389 if (ret < 0)
390 goto done;
391 }
392
393 if (*num_maps)
394 return 0;
395
396 dev_err(pctrl->dev, "no mapping found in node %pOF\n", np);
397 ret = -EINVAL;
398
399 done:
400 if (ret < 0)
401 rzv2m_dt_free_map(pctldev, *map, *num_maps);
402
403 return ret;
404 }
405
rzv2m_validate_gpio_pin(struct rzv2m_pinctrl * pctrl,u32 cfg,u32 port,u8 bit)406 static int rzv2m_validate_gpio_pin(struct rzv2m_pinctrl *pctrl,
407 u32 cfg, u32 port, u8 bit)
408 {
409 u8 pincount = RZV2M_GPIO_PORT_GET_PINCNT(cfg);
410 u32 port_index = RZV2M_GPIO_PORT_GET_INDEX(cfg);
411 u32 data;
412
413 if (bit >= pincount || port >= pctrl->data->n_port_pins)
414 return -EINVAL;
415
416 data = pctrl->data->port_pin_configs[port];
417 if (port_index != RZV2M_GPIO_PORT_GET_INDEX(data))
418 return -EINVAL;
419
420 return 0;
421 }
422
rzv2m_rmw_pin_config(struct rzv2m_pinctrl * pctrl,u32 offset,u8 shift,u32 mask,u32 val)423 static void rzv2m_rmw_pin_config(struct rzv2m_pinctrl *pctrl, u32 offset,
424 u8 shift, u32 mask, u32 val)
425 {
426 void __iomem *addr = pctrl->base + offset;
427 unsigned long flags;
428 u32 reg;
429
430 spin_lock_irqsave(&pctrl->lock, flags);
431 reg = readl(addr) & ~(mask << shift);
432 writel(reg | (val << shift), addr);
433 spin_unlock_irqrestore(&pctrl->lock, flags);
434 }
435
rzv2m_pinctrl_pinconf_get(struct pinctrl_dev * pctldev,unsigned int _pin,unsigned long * config)436 static int rzv2m_pinctrl_pinconf_get(struct pinctrl_dev *pctldev,
437 unsigned int _pin,
438 unsigned long *config)
439 {
440 struct rzv2m_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
441 enum pin_config_param param = pinconf_to_config_param(*config);
442 const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin];
443 unsigned int *pin_data = pin->drv_data;
444 unsigned int arg = 0;
445 u32 port;
446 u32 cfg;
447 u8 bit;
448 u32 val;
449
450 if (!pin_data)
451 return -EINVAL;
452
453 if (*pin_data & RZV2M_SINGLE_PIN) {
454 port = RZV2M_SINGLE_PIN_GET_PORT(*pin_data);
455 cfg = RZV2M_SINGLE_PIN_GET_CFGS(*pin_data);
456 bit = RZV2M_SINGLE_PIN_GET_BIT(*pin_data);
457 } else {
458 cfg = RZV2M_GPIO_PORT_GET_CFGS(*pin_data);
459 port = RZV2M_PIN_ID_TO_PORT(_pin);
460 bit = RZV2M_PIN_ID_TO_PIN(_pin);
461
462 if (rzv2m_validate_gpio_pin(pctrl, *pin_data, RZV2M_PIN_ID_TO_PORT(_pin), bit))
463 return -EINVAL;
464 }
465
466 switch (param) {
467 case PIN_CONFIG_BIAS_DISABLE:
468 case PIN_CONFIG_BIAS_PULL_UP:
469 case PIN_CONFIG_BIAS_PULL_DOWN: {
470 enum pin_config_param bias;
471
472 if (!(cfg & PIN_CFG_BIAS))
473 return -EINVAL;
474
475 /* PUPD uses 2-bits per pin */
476 bit *= 2;
477
478 switch ((readl(pctrl->base + PUPD(port)) >> bit) & PUPD_MASK) {
479 case 0:
480 bias = PIN_CONFIG_BIAS_PULL_DOWN;
481 break;
482 case 2:
483 bias = PIN_CONFIG_BIAS_PULL_UP;
484 break;
485 default:
486 bias = PIN_CONFIG_BIAS_DISABLE;
487 }
488
489 if (bias != param)
490 return -EINVAL;
491 break;
492 }
493
494 case PIN_CONFIG_DRIVE_STRENGTH_UA:
495 if (!(cfg & PIN_CFG_DRV))
496 return -EINVAL;
497
498 /* DRV uses 2-bits per pin */
499 bit *= 2;
500
501 val = (readl(pctrl->base + DRV(port)) >> bit) & DRV_MASK;
502
503 switch (cfg & PIN_CFG_GRP_MASK) {
504 case PIN_CFG_GRP_1_8V_2:
505 arg = drv_1_8V_group2_uA[val];
506 break;
507 case PIN_CFG_GRP_1_8V_3:
508 arg = drv_1_8V_group3_uA[val];
509 break;
510 case PIN_CFG_GRP_SWIO_2:
511 arg = drv_SWIO_group2_3_3V_uA[val];
512 break;
513 case PIN_CFG_GRP_SWIO_1:
514 case PIN_CFG_GRP_3_3V:
515 arg = drv_3_3V_group_uA[val];
516 break;
517 default:
518 return -EINVAL;
519 }
520
521 break;
522
523 case PIN_CONFIG_SLEW_RATE:
524 if (!(cfg & PIN_CFG_SLEW))
525 return -EINVAL;
526
527 arg = readl(pctrl->base + SR(port)) & BIT(bit);
528 break;
529
530 default:
531 return -ENOTSUPP;
532 }
533
534 *config = pinconf_to_config_packed(param, arg);
535
536 return 0;
537 };
538
rzv2m_pinctrl_pinconf_set(struct pinctrl_dev * pctldev,unsigned int _pin,unsigned long * _configs,unsigned int num_configs)539 static int rzv2m_pinctrl_pinconf_set(struct pinctrl_dev *pctldev,
540 unsigned int _pin,
541 unsigned long *_configs,
542 unsigned int num_configs)
543 {
544 struct rzv2m_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
545 const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin];
546 unsigned int *pin_data = pin->drv_data;
547 enum pin_config_param param;
548 u32 port;
549 unsigned int i;
550 u32 cfg;
551 u8 bit;
552 u32 val;
553
554 if (!pin_data)
555 return -EINVAL;
556
557 if (*pin_data & RZV2M_SINGLE_PIN) {
558 port = RZV2M_SINGLE_PIN_GET_PORT(*pin_data);
559 cfg = RZV2M_SINGLE_PIN_GET_CFGS(*pin_data);
560 bit = RZV2M_SINGLE_PIN_GET_BIT(*pin_data);
561 } else {
562 cfg = RZV2M_GPIO_PORT_GET_CFGS(*pin_data);
563 port = RZV2M_PIN_ID_TO_PORT(_pin);
564 bit = RZV2M_PIN_ID_TO_PIN(_pin);
565
566 if (rzv2m_validate_gpio_pin(pctrl, *pin_data, RZV2M_PIN_ID_TO_PORT(_pin), bit))
567 return -EINVAL;
568 }
569
570 for (i = 0; i < num_configs; i++) {
571 param = pinconf_to_config_param(_configs[i]);
572 switch (param) {
573 case PIN_CONFIG_BIAS_DISABLE:
574 case PIN_CONFIG_BIAS_PULL_UP:
575 case PIN_CONFIG_BIAS_PULL_DOWN:
576 if (!(cfg & PIN_CFG_BIAS))
577 return -EINVAL;
578
579 /* PUPD uses 2-bits per pin */
580 bit *= 2;
581
582 switch (param) {
583 case PIN_CONFIG_BIAS_PULL_DOWN:
584 val = 0;
585 break;
586 case PIN_CONFIG_BIAS_PULL_UP:
587 val = 2;
588 break;
589 default:
590 val = 1;
591 }
592
593 rzv2m_rmw_pin_config(pctrl, PUPD(port), bit, PUPD_MASK, val);
594 break;
595
596 case PIN_CONFIG_DRIVE_STRENGTH_UA: {
597 unsigned int arg = pinconf_to_config_argument(_configs[i]);
598 const unsigned int *drv_strengths;
599 unsigned int index;
600
601 if (!(cfg & PIN_CFG_DRV))
602 return -EINVAL;
603
604 switch (cfg & PIN_CFG_GRP_MASK) {
605 case PIN_CFG_GRP_1_8V_2:
606 drv_strengths = drv_1_8V_group2_uA;
607 break;
608 case PIN_CFG_GRP_1_8V_3:
609 drv_strengths = drv_1_8V_group3_uA;
610 break;
611 case PIN_CFG_GRP_SWIO_2:
612 drv_strengths = drv_SWIO_group2_3_3V_uA;
613 break;
614 case PIN_CFG_GRP_SWIO_1:
615 case PIN_CFG_GRP_3_3V:
616 drv_strengths = drv_3_3V_group_uA;
617 break;
618 default:
619 return -EINVAL;
620 }
621
622 for (index = 0; index < 4; index++) {
623 if (arg == drv_strengths[index])
624 break;
625 }
626 if (index >= 4)
627 return -EINVAL;
628
629 /* DRV uses 2-bits per pin */
630 bit *= 2;
631
632 rzv2m_rmw_pin_config(pctrl, DRV(port), bit, DRV_MASK, index);
633 break;
634 }
635
636 case PIN_CONFIG_SLEW_RATE: {
637 unsigned int arg = pinconf_to_config_argument(_configs[i]);
638
639 if (!(cfg & PIN_CFG_SLEW))
640 return -EINVAL;
641
642 rzv2m_writel_we(pctrl->base + SR(port), bit, !arg);
643 break;
644 }
645
646 default:
647 return -EOPNOTSUPP;
648 }
649 }
650
651 return 0;
652 }
653
rzv2m_pinctrl_pinconf_group_set(struct pinctrl_dev * pctldev,unsigned int group,unsigned long * configs,unsigned int num_configs)654 static int rzv2m_pinctrl_pinconf_group_set(struct pinctrl_dev *pctldev,
655 unsigned int group,
656 unsigned long *configs,
657 unsigned int num_configs)
658 {
659 const unsigned int *pins;
660 unsigned int i, npins;
661 int ret;
662
663 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
664 if (ret)
665 return ret;
666
667 for (i = 0; i < npins; i++) {
668 ret = rzv2m_pinctrl_pinconf_set(pctldev, pins[i], configs,
669 num_configs);
670 if (ret)
671 return ret;
672 }
673
674 return 0;
675 };
676
rzv2m_pinctrl_pinconf_group_get(struct pinctrl_dev * pctldev,unsigned int group,unsigned long * config)677 static int rzv2m_pinctrl_pinconf_group_get(struct pinctrl_dev *pctldev,
678 unsigned int group,
679 unsigned long *config)
680 {
681 const unsigned int *pins;
682 unsigned int i, npins, prev_config = 0;
683 int ret;
684
685 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
686 if (ret)
687 return ret;
688
689 for (i = 0; i < npins; i++) {
690 ret = rzv2m_pinctrl_pinconf_get(pctldev, pins[i], config);
691 if (ret)
692 return ret;
693
694 /* Check config matches previous pins */
695 if (i && prev_config != *config)
696 return -EOPNOTSUPP;
697
698 prev_config = *config;
699 }
700
701 return 0;
702 };
703
704 static const struct pinctrl_ops rzv2m_pinctrl_pctlops = {
705 .get_groups_count = pinctrl_generic_get_group_count,
706 .get_group_name = pinctrl_generic_get_group_name,
707 .get_group_pins = pinctrl_generic_get_group_pins,
708 .dt_node_to_map = rzv2m_dt_node_to_map,
709 .dt_free_map = rzv2m_dt_free_map,
710 };
711
712 static const struct pinmux_ops rzv2m_pinctrl_pmxops = {
713 .get_functions_count = pinmux_generic_get_function_count,
714 .get_function_name = pinmux_generic_get_function_name,
715 .get_function_groups = pinmux_generic_get_function_groups,
716 .set_mux = rzv2m_pinctrl_set_mux,
717 .strict = true,
718 };
719
720 static const struct pinconf_ops rzv2m_pinctrl_confops = {
721 .is_generic = true,
722 .pin_config_get = rzv2m_pinctrl_pinconf_get,
723 .pin_config_set = rzv2m_pinctrl_pinconf_set,
724 .pin_config_group_set = rzv2m_pinctrl_pinconf_group_set,
725 .pin_config_group_get = rzv2m_pinctrl_pinconf_group_get,
726 .pin_config_config_dbg_show = pinconf_generic_dump_config,
727 };
728
rzv2m_gpio_request(struct gpio_chip * chip,unsigned int offset)729 static int rzv2m_gpio_request(struct gpio_chip *chip, unsigned int offset)
730 {
731 struct rzv2m_pinctrl *pctrl = gpiochip_get_data(chip);
732 u32 port = RZV2M_PIN_ID_TO_PORT(offset);
733 u8 bit = RZV2M_PIN_ID_TO_PIN(offset);
734 int ret;
735
736 ret = pinctrl_gpio_request(chip->base + offset);
737 if (ret)
738 return ret;
739
740 rzv2m_pinctrl_set_pfc_mode(pctrl, port, bit, 0);
741
742 return 0;
743 }
744
rzv2m_gpio_set_direction(struct rzv2m_pinctrl * pctrl,u32 port,u8 bit,bool output)745 static void rzv2m_gpio_set_direction(struct rzv2m_pinctrl *pctrl, u32 port,
746 u8 bit, bool output)
747 {
748 rzv2m_writel_we(pctrl->base + OE(port), bit, output);
749 rzv2m_writel_we(pctrl->base + IE(port), bit, !output);
750 }
751
rzv2m_gpio_get_direction(struct gpio_chip * chip,unsigned int offset)752 static int rzv2m_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
753 {
754 struct rzv2m_pinctrl *pctrl = gpiochip_get_data(chip);
755 u32 port = RZV2M_PIN_ID_TO_PORT(offset);
756 u8 bit = RZV2M_PIN_ID_TO_PIN(offset);
757
758 if (!(readl(pctrl->base + IE(port)) & BIT(bit)))
759 return GPIO_LINE_DIRECTION_OUT;
760
761 return GPIO_LINE_DIRECTION_IN;
762 }
763
rzv2m_gpio_direction_input(struct gpio_chip * chip,unsigned int offset)764 static int rzv2m_gpio_direction_input(struct gpio_chip *chip,
765 unsigned int offset)
766 {
767 struct rzv2m_pinctrl *pctrl = gpiochip_get_data(chip);
768 u32 port = RZV2M_PIN_ID_TO_PORT(offset);
769 u8 bit = RZV2M_PIN_ID_TO_PIN(offset);
770
771 rzv2m_gpio_set_direction(pctrl, port, bit, false);
772
773 return 0;
774 }
775
rzv2m_gpio_set(struct gpio_chip * chip,unsigned int offset,int value)776 static void rzv2m_gpio_set(struct gpio_chip *chip, unsigned int offset,
777 int value)
778 {
779 struct rzv2m_pinctrl *pctrl = gpiochip_get_data(chip);
780 u32 port = RZV2M_PIN_ID_TO_PORT(offset);
781 u8 bit = RZV2M_PIN_ID_TO_PIN(offset);
782
783 rzv2m_writel_we(pctrl->base + DO(port), bit, !!value);
784 }
785
rzv2m_gpio_direction_output(struct gpio_chip * chip,unsigned int offset,int value)786 static int rzv2m_gpio_direction_output(struct gpio_chip *chip,
787 unsigned int offset, int value)
788 {
789 struct rzv2m_pinctrl *pctrl = gpiochip_get_data(chip);
790 u32 port = RZV2M_PIN_ID_TO_PORT(offset);
791 u8 bit = RZV2M_PIN_ID_TO_PIN(offset);
792
793 rzv2m_gpio_set(chip, offset, value);
794 rzv2m_gpio_set_direction(pctrl, port, bit, true);
795
796 return 0;
797 }
798
rzv2m_gpio_get(struct gpio_chip * chip,unsigned int offset)799 static int rzv2m_gpio_get(struct gpio_chip *chip, unsigned int offset)
800 {
801 struct rzv2m_pinctrl *pctrl = gpiochip_get_data(chip);
802 u32 port = RZV2M_PIN_ID_TO_PORT(offset);
803 u8 bit = RZV2M_PIN_ID_TO_PIN(offset);
804 int direction = rzv2m_gpio_get_direction(chip, offset);
805
806 if (direction == GPIO_LINE_DIRECTION_IN)
807 return !!(readl(pctrl->base + DI(port)) & BIT(bit));
808 else
809 return !!(readl(pctrl->base + DO(port)) & BIT(bit));
810 }
811
rzv2m_gpio_free(struct gpio_chip * chip,unsigned int offset)812 static void rzv2m_gpio_free(struct gpio_chip *chip, unsigned int offset)
813 {
814 pinctrl_gpio_free(chip->base + offset);
815
816 /*
817 * Set the GPIO as an input to ensure that the next GPIO request won't
818 * drive the GPIO pin as an output.
819 */
820 rzv2m_gpio_direction_input(chip, offset);
821 }
822
823 static const char * const rzv2m_gpio_names[] = {
824 "P0_0", "P0_1", "P0_2", "P0_3", "P0_4", "P0_5", "P0_6", "P0_7",
825 "P0_8", "P0_9", "P0_10", "P0_11", "P0_12", "P0_13", "P0_14", "P0_15",
826 "P1_0", "P1_1", "P1_2", "P1_3", "P1_4", "P1_5", "P1_6", "P1_7",
827 "P1_8", "P1_9", "P1_10", "P1_11", "P1_12", "P1_13", "P1_14", "P1_15",
828 "P2_0", "P2_1", "P2_2", "P2_3", "P2_4", "P2_5", "P2_6", "P2_7",
829 "P2_8", "P2_9", "P2_10", "P2_11", "P2_12", "P2_13", "P2_14", "P2_15",
830 "P3_0", "P3_1", "P3_2", "P3_3", "P3_4", "P3_5", "P3_6", "P3_7",
831 "P3_8", "P3_9", "P3_10", "P3_11", "P3_12", "P3_13", "P3_14", "P3_15",
832 "P4_0", "P4_1", "P4_2", "P4_3", "P4_4", "P4_5", "P4_6", "P4_7",
833 "P4_8", "P4_9", "P4_10", "P4_11", "P4_12", "P4_13", "P4_14", "P4_15",
834 "P5_0", "P5_1", "P5_2", "P5_3", "P5_4", "P5_5", "P5_6", "P5_7",
835 "P5_8", "P5_9", "P5_10", "P5_11", "P5_12", "P5_13", "P5_14", "P5_15",
836 "P6_0", "P6_1", "P6_2", "P6_3", "P6_4", "P6_5", "P6_6", "P6_7",
837 "P6_8", "P6_9", "P6_10", "P6_11", "P6_12", "P6_13", "P6_14", "P6_15",
838 "P7_0", "P7_1", "P7_2", "P7_3", "P7_4", "P7_5", "P7_6", "P7_7",
839 "P7_8", "P7_9", "P7_10", "P7_11", "P7_12", "P7_13", "P7_14", "P7_15",
840 "P8_0", "P8_1", "P8_2", "P8_3", "P8_4", "P8_5", "P8_6", "P8_7",
841 "P8_8", "P8_9", "P8_10", "P8_11", "P8_12", "P8_13", "P8_14", "P8_15",
842 "P9_0", "P9_1", "P9_2", "P9_3", "P9_4", "P9_5", "P9_6", "P9_7",
843 "P9_8", "P9_9", "P9_10", "P9_11", "P9_12", "P9_13", "P9_14", "P9_15",
844 "P10_0", "P10_1", "P10_2", "P10_3", "P10_4", "P10_5", "P10_6", "P10_7",
845 "P10_8", "P10_9", "P10_10", "P10_11", "P10_12", "P10_13", "P10_14", "P10_15",
846 "P11_0", "P11_1", "P11_2", "P11_3", "P11_4", "P11_5", "P11_6", "P11_7",
847 "P11_8", "P11_9", "P11_10", "P11_11", "P11_12", "P11_13", "P11_14", "P11_15",
848 "P12_0", "P12_1", "P12_2", "P12_3", "P12_4", "P12_5", "P12_6", "P12_7",
849 "P12_8", "P12_9", "P12_10", "P12_11", "P12_12", "P12_13", "P12_14", "P12_15",
850 "P13_0", "P13_1", "P13_2", "P13_3", "P13_4", "P13_5", "P13_6", "P13_7",
851 "P13_8", "P13_9", "P13_10", "P13_11", "P13_12", "P13_13", "P13_14", "P13_15",
852 "P14_0", "P14_1", "P14_2", "P14_3", "P14_4", "P14_5", "P14_6", "P14_7",
853 "P14_8", "P14_9", "P14_10", "P14_11", "P14_12", "P14_13", "P14_14", "P14_15",
854 "P15_0", "P15_1", "P15_2", "P15_3", "P15_4", "P15_5", "P15_6", "P15_7",
855 "P15_8", "P15_9", "P15_10", "P15_11", "P15_12", "P15_13", "P15_14", "P15_15",
856 "P16_0", "P16_1", "P16_2", "P16_3", "P16_4", "P16_5", "P16_6", "P16_7",
857 "P16_8", "P16_9", "P16_10", "P16_11", "P16_12", "P16_13", "P16_14", "P16_15",
858 "P17_0", "P17_1", "P17_2", "P17_3", "P17_4", "P17_5", "P17_6", "P17_7",
859 "P17_8", "P17_9", "P17_10", "P17_11", "P17_12", "P17_13", "P17_14", "P17_15",
860 "P18_0", "P18_1", "P18_2", "P18_3", "P18_4", "P18_5", "P18_6", "P18_7",
861 "P18_8", "P18_9", "P18_10", "P18_11", "P18_12", "P18_13", "P18_14", "P18_15",
862 "P19_0", "P19_1", "P19_2", "P19_3", "P19_4", "P19_5", "P19_6", "P19_7",
863 "P19_8", "P19_9", "P19_10", "P19_11", "P19_12", "P19_13", "P19_14", "P19_15",
864 "P20_0", "P20_1", "P20_2", "P20_3", "P20_4", "P20_5", "P20_6", "P20_7",
865 "P20_8", "P20_9", "P20_10", "P20_11", "P20_12", "P20_13", "P20_14", "P20_15",
866 "P21_0", "P21_1", "P21_2", "P21_3", "P21_4", "P21_5", "P21_6", "P21_7",
867 "P21_8", "P21_9", "P21_10", "P21_11", "P21_12", "P21_13", "P21_14", "P21_15",
868 };
869
870 static const u32 rzv2m_gpio_configs[] = {
871 RZV2M_GPIO_PORT_PACK(14, 0, PIN_CFG_GRP_SWIO_2 | RZV2M_MPXED_PIN_FUNCS),
872 RZV2M_GPIO_PORT_PACK(16, 1, PIN_CFG_GRP_SWIO_1 | RZV2M_MPXED_PIN_FUNCS),
873 RZV2M_GPIO_PORT_PACK(8, 2, PIN_CFG_GRP_1_8V_3 | RZV2M_MPXED_PIN_FUNCS),
874 RZV2M_GPIO_PORT_PACK(16, 3, PIN_CFG_GRP_SWIO_1 | RZV2M_MPXED_PIN_FUNCS),
875 RZV2M_GPIO_PORT_PACK(8, 4, PIN_CFG_GRP_SWIO_1 | RZV2M_MPXED_PIN_FUNCS),
876 RZV2M_GPIO_PORT_PACK(4, 5, PIN_CFG_GRP_1_8V_3 | RZV2M_MPXED_PIN_FUNCS),
877 RZV2M_GPIO_PORT_PACK(12, 6, PIN_CFG_GRP_SWIO_1 | RZV2M_MPXED_PIN_FUNCS),
878 RZV2M_GPIO_PORT_PACK(6, 7, PIN_CFG_GRP_SWIO_1 | RZV2M_MPXED_PIN_FUNCS),
879 RZV2M_GPIO_PORT_PACK(8, 8, PIN_CFG_GRP_SWIO_2 | RZV2M_MPXED_PIN_FUNCS),
880 RZV2M_GPIO_PORT_PACK(8, 9, PIN_CFG_GRP_SWIO_2 | RZV2M_MPXED_PIN_FUNCS),
881 RZV2M_GPIO_PORT_PACK(9, 10, PIN_CFG_GRP_SWIO_1 | RZV2M_MPXED_PIN_FUNCS),
882 RZV2M_GPIO_PORT_PACK(9, 11, PIN_CFG_GRP_SWIO_1 | RZV2M_MPXED_PIN_FUNCS),
883 RZV2M_GPIO_PORT_PACK(4, 12, PIN_CFG_GRP_3_3V | RZV2M_MPXED_PIN_FUNCS),
884 RZV2M_GPIO_PORT_PACK(12, 13, PIN_CFG_GRP_3_3V | RZV2M_MPXED_PIN_FUNCS),
885 RZV2M_GPIO_PORT_PACK(8, 14, PIN_CFG_GRP_3_3V | RZV2M_MPXED_PIN_FUNCS),
886 RZV2M_GPIO_PORT_PACK(16, 15, PIN_CFG_GRP_SWIO_2 | RZV2M_MPXED_PIN_FUNCS),
887 RZV2M_GPIO_PORT_PACK(14, 16, PIN_CFG_GRP_SWIO_2 | RZV2M_MPXED_PIN_FUNCS),
888 RZV2M_GPIO_PORT_PACK(1, 17, PIN_CFG_GRP_SWIO_2 | RZV2M_MPXED_PIN_FUNCS),
889 RZV2M_GPIO_PORT_PACK(0, 18, 0),
890 RZV2M_GPIO_PORT_PACK(0, 19, 0),
891 RZV2M_GPIO_PORT_PACK(3, 20, PIN_CFG_GRP_1_8V_2 | PIN_CFG_DRV),
892 RZV2M_GPIO_PORT_PACK(1, 21, PIN_CFG_GRP_SWIO_1 | PIN_CFG_DRV | PIN_CFG_SLEW),
893 };
894
895 static const struct rzv2m_dedicated_configs rzv2m_dedicated_pins[] = {
896 { "NAWPN", RZV2M_SINGLE_PIN_PACK(0,
897 (PIN_CFG_GRP_SWIO_2 | PIN_CFG_DRV | PIN_CFG_SLEW)) },
898 { "IM0CLK", RZV2M_SINGLE_PIN_PACK(1,
899 (PIN_CFG_GRP_SWIO_1 | PIN_CFG_DRV | PIN_CFG_SLEW)) },
900 { "IM1CLK", RZV2M_SINGLE_PIN_PACK(2,
901 (PIN_CFG_GRP_SWIO_1 | PIN_CFG_DRV | PIN_CFG_SLEW)) },
902 { "DETDO", RZV2M_SINGLE_PIN_PACK(5,
903 (PIN_CFG_GRP_1_8V_3 | PIN_CFG_DRV | PIN_CFG_SLEW)) },
904 { "DETMS", RZV2M_SINGLE_PIN_PACK(6,
905 (PIN_CFG_GRP_1_8V_3 | PIN_CFG_DRV | PIN_CFG_SLEW)) },
906 { "PCRSTOUTB", RZV2M_SINGLE_PIN_PACK(12,
907 (PIN_CFG_GRP_3_3V | PIN_CFG_DRV | PIN_CFG_SLEW)) },
908 { "USPWEN", RZV2M_SINGLE_PIN_PACK(14,
909 (PIN_CFG_GRP_3_3V | PIN_CFG_DRV | PIN_CFG_SLEW)) },
910 };
911
rzv2m_gpio_register(struct rzv2m_pinctrl * pctrl)912 static int rzv2m_gpio_register(struct rzv2m_pinctrl *pctrl)
913 {
914 struct device_node *np = pctrl->dev->of_node;
915 struct gpio_chip *chip = &pctrl->gpio_chip;
916 const char *name = dev_name(pctrl->dev);
917 struct of_phandle_args of_args;
918 int ret;
919
920 ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &of_args);
921 if (ret) {
922 dev_err(pctrl->dev, "Unable to parse gpio-ranges\n");
923 return ret;
924 }
925
926 if (of_args.args[0] != 0 || of_args.args[1] != 0 ||
927 of_args.args[2] != pctrl->data->n_port_pins) {
928 dev_err(pctrl->dev, "gpio-ranges does not match selected SOC\n");
929 return -EINVAL;
930 }
931
932 chip->names = pctrl->data->port_pins;
933 chip->request = rzv2m_gpio_request;
934 chip->free = rzv2m_gpio_free;
935 chip->get_direction = rzv2m_gpio_get_direction;
936 chip->direction_input = rzv2m_gpio_direction_input;
937 chip->direction_output = rzv2m_gpio_direction_output;
938 chip->get = rzv2m_gpio_get;
939 chip->set = rzv2m_gpio_set;
940 chip->label = name;
941 chip->parent = pctrl->dev;
942 chip->owner = THIS_MODULE;
943 chip->base = -1;
944 chip->ngpio = of_args.args[2];
945
946 pctrl->gpio_range.id = 0;
947 pctrl->gpio_range.pin_base = 0;
948 pctrl->gpio_range.base = 0;
949 pctrl->gpio_range.npins = chip->ngpio;
950 pctrl->gpio_range.name = chip->label;
951 pctrl->gpio_range.gc = chip;
952 ret = devm_gpiochip_add_data(pctrl->dev, chip, pctrl);
953 if (ret) {
954 dev_err(pctrl->dev, "failed to add GPIO controller\n");
955 return ret;
956 }
957
958 dev_dbg(pctrl->dev, "Registered gpio controller\n");
959
960 return 0;
961 }
962
rzv2m_pinctrl_register(struct rzv2m_pinctrl * pctrl)963 static int rzv2m_pinctrl_register(struct rzv2m_pinctrl *pctrl)
964 {
965 struct pinctrl_pin_desc *pins;
966 unsigned int i, j;
967 u32 *pin_data;
968 int ret;
969
970 pctrl->desc.name = DRV_NAME;
971 pctrl->desc.npins = pctrl->data->n_port_pins + pctrl->data->n_dedicated_pins;
972 pctrl->desc.pctlops = &rzv2m_pinctrl_pctlops;
973 pctrl->desc.pmxops = &rzv2m_pinctrl_pmxops;
974 pctrl->desc.confops = &rzv2m_pinctrl_confops;
975 pctrl->desc.owner = THIS_MODULE;
976
977 pins = devm_kcalloc(pctrl->dev, pctrl->desc.npins, sizeof(*pins), GFP_KERNEL);
978 if (!pins)
979 return -ENOMEM;
980
981 pin_data = devm_kcalloc(pctrl->dev, pctrl->desc.npins,
982 sizeof(*pin_data), GFP_KERNEL);
983 if (!pin_data)
984 return -ENOMEM;
985
986 pctrl->pins = pins;
987 pctrl->desc.pins = pins;
988
989 for (i = 0, j = 0; i < pctrl->data->n_port_pins; i++) {
990 pins[i].number = i;
991 pins[i].name = pctrl->data->port_pins[i];
992 if (i && !(i % RZV2M_PINS_PER_PORT))
993 j++;
994 pin_data[i] = pctrl->data->port_pin_configs[j];
995 pins[i].drv_data = &pin_data[i];
996 }
997
998 for (i = 0; i < pctrl->data->n_dedicated_pins; i++) {
999 unsigned int index = pctrl->data->n_port_pins + i;
1000
1001 pins[index].number = index;
1002 pins[index].name = pctrl->data->dedicated_pins[i].name;
1003 pin_data[index] = pctrl->data->dedicated_pins[i].config;
1004 pins[index].drv_data = &pin_data[index];
1005 }
1006
1007 ret = devm_pinctrl_register_and_init(pctrl->dev, &pctrl->desc, pctrl,
1008 &pctrl->pctl);
1009 if (ret) {
1010 dev_err(pctrl->dev, "pinctrl registration failed\n");
1011 return ret;
1012 }
1013
1014 ret = pinctrl_enable(pctrl->pctl);
1015 if (ret) {
1016 dev_err(pctrl->dev, "pinctrl enable failed\n");
1017 return ret;
1018 }
1019
1020 ret = rzv2m_gpio_register(pctrl);
1021 if (ret) {
1022 dev_err(pctrl->dev, "failed to add GPIO chip: %i\n", ret);
1023 return ret;
1024 }
1025
1026 return 0;
1027 }
1028
rzv2m_pinctrl_clk_disable(void * data)1029 static void rzv2m_pinctrl_clk_disable(void *data)
1030 {
1031 clk_disable_unprepare(data);
1032 }
1033
rzv2m_pinctrl_probe(struct platform_device * pdev)1034 static int rzv2m_pinctrl_probe(struct platform_device *pdev)
1035 {
1036 struct rzv2m_pinctrl *pctrl;
1037 int ret;
1038
1039 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
1040 if (!pctrl)
1041 return -ENOMEM;
1042
1043 pctrl->dev = &pdev->dev;
1044
1045 pctrl->data = of_device_get_match_data(&pdev->dev);
1046 if (!pctrl->data)
1047 return -EINVAL;
1048
1049 pctrl->base = devm_platform_ioremap_resource(pdev, 0);
1050 if (IS_ERR(pctrl->base))
1051 return PTR_ERR(pctrl->base);
1052
1053 pctrl->clk = devm_clk_get(pctrl->dev, NULL);
1054 if (IS_ERR(pctrl->clk)) {
1055 ret = PTR_ERR(pctrl->clk);
1056 dev_err(pctrl->dev, "failed to get GPIO clk : %i\n", ret);
1057 return ret;
1058 }
1059
1060 spin_lock_init(&pctrl->lock);
1061
1062 platform_set_drvdata(pdev, pctrl);
1063
1064 ret = clk_prepare_enable(pctrl->clk);
1065 if (ret) {
1066 dev_err(pctrl->dev, "failed to enable GPIO clk: %i\n", ret);
1067 return ret;
1068 }
1069
1070 ret = devm_add_action_or_reset(&pdev->dev, rzv2m_pinctrl_clk_disable,
1071 pctrl->clk);
1072 if (ret) {
1073 dev_err(pctrl->dev,
1074 "failed to register GPIO clk disable action, %i\n",
1075 ret);
1076 return ret;
1077 }
1078
1079 ret = rzv2m_pinctrl_register(pctrl);
1080 if (ret)
1081 return ret;
1082
1083 dev_info(pctrl->dev, "%s support registered\n", DRV_NAME);
1084 return 0;
1085 }
1086
1087 static struct rzv2m_pinctrl_data r9a09g011_data = {
1088 .port_pins = rzv2m_gpio_names,
1089 .port_pin_configs = rzv2m_gpio_configs,
1090 .dedicated_pins = rzv2m_dedicated_pins,
1091 .n_port_pins = ARRAY_SIZE(rzv2m_gpio_configs) * RZV2M_PINS_PER_PORT,
1092 .n_dedicated_pins = ARRAY_SIZE(rzv2m_dedicated_pins),
1093 };
1094
1095 static const struct of_device_id rzv2m_pinctrl_of_table[] = {
1096 {
1097 .compatible = "renesas,r9a09g011-pinctrl",
1098 .data = &r9a09g011_data,
1099 },
1100 { /* sentinel */ }
1101 };
1102
1103 static struct platform_driver rzv2m_pinctrl_driver = {
1104 .driver = {
1105 .name = DRV_NAME,
1106 .of_match_table = of_match_ptr(rzv2m_pinctrl_of_table),
1107 },
1108 .probe = rzv2m_pinctrl_probe,
1109 };
1110
rzv2m_pinctrl_init(void)1111 static int __init rzv2m_pinctrl_init(void)
1112 {
1113 return platform_driver_register(&rzv2m_pinctrl_driver);
1114 }
1115 core_initcall(rzv2m_pinctrl_init);
1116
1117 MODULE_AUTHOR("Phil Edworthy <phil.edworthy@renesas.com>");
1118 MODULE_DESCRIPTION("Pin and gpio controller driver for RZ/V2M");
1119 MODULE_LICENSE("GPL");
1120
