1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2018-19, Linaro Limited
3
4 #include <linux/module.h>
5 #include <linux/of.h>
6 #include <linux/of_device.h>
7 #include <linux/platform_device.h>
8 #include <linux/phy.h>
9 #include "stmmac.h"
10 #include "stmmac_platform.h"
11
12 #define RGMII_IO_MACRO_CONFIG 0x0
13 #define SDCC_HC_REG_DLL_CONFIG 0x4
14 #define SDCC_HC_REG_DDR_CONFIG 0xC
15 #define SDCC_HC_REG_DLL_CONFIG2 0x10
16 #define SDC4_STATUS 0x14
17 #define SDCC_USR_CTL 0x18
18 #define RGMII_IO_MACRO_CONFIG2 0x1C
19 #define RGMII_IO_MACRO_DEBUG1 0x20
20 #define EMAC_SYSTEM_LOW_POWER_DEBUG 0x28
21
22 /* RGMII_IO_MACRO_CONFIG fields */
23 #define RGMII_CONFIG_FUNC_CLK_EN BIT(30)
24 #define RGMII_CONFIG_POS_NEG_DATA_SEL BIT(23)
25 #define RGMII_CONFIG_GPIO_CFG_RX_INT GENMASK(21, 20)
26 #define RGMII_CONFIG_GPIO_CFG_TX_INT GENMASK(19, 17)
27 #define RGMII_CONFIG_MAX_SPD_PRG_9 GENMASK(16, 8)
28 #define RGMII_CONFIG_MAX_SPD_PRG_2 GENMASK(7, 6)
29 #define RGMII_CONFIG_INTF_SEL GENMASK(5, 4)
30 #define RGMII_CONFIG_BYPASS_TX_ID_EN BIT(3)
31 #define RGMII_CONFIG_LOOPBACK_EN BIT(2)
32 #define RGMII_CONFIG_PROG_SWAP BIT(1)
33 #define RGMII_CONFIG_DDR_MODE BIT(0)
34
35 /* SDCC_HC_REG_DLL_CONFIG fields */
36 #define SDCC_DLL_CONFIG_DLL_RST BIT(30)
37 #define SDCC_DLL_CONFIG_PDN BIT(29)
38 #define SDCC_DLL_CONFIG_MCLK_FREQ GENMASK(26, 24)
39 #define SDCC_DLL_CONFIG_CDR_SELEXT GENMASK(23, 20)
40 #define SDCC_DLL_CONFIG_CDR_EXT_EN BIT(19)
41 #define SDCC_DLL_CONFIG_CK_OUT_EN BIT(18)
42 #define SDCC_DLL_CONFIG_CDR_EN BIT(17)
43 #define SDCC_DLL_CONFIG_DLL_EN BIT(16)
44 #define SDCC_DLL_MCLK_GATING_EN BIT(5)
45 #define SDCC_DLL_CDR_FINE_PHASE GENMASK(3, 2)
46
47 /* SDCC_HC_REG_DDR_CONFIG fields */
48 #define SDCC_DDR_CONFIG_PRG_DLY_EN BIT(31)
49 #define SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY GENMASK(26, 21)
50 #define SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_CODE GENMASK(29, 27)
51 #define SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN BIT(30)
52 #define SDCC_DDR_CONFIG_PRG_RCLK_DLY GENMASK(8, 0)
53
54 /* SDCC_HC_REG_DLL_CONFIG2 fields */
55 #define SDCC_DLL_CONFIG2_DLL_CLOCK_DIS BIT(21)
56 #define SDCC_DLL_CONFIG2_MCLK_FREQ_CALC GENMASK(17, 10)
57 #define SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SEL GENMASK(3, 2)
58 #define SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SW BIT(1)
59 #define SDCC_DLL_CONFIG2_DDR_CAL_EN BIT(0)
60
61 /* SDC4_STATUS bits */
62 #define SDC4_STATUS_DLL_LOCK BIT(7)
63
64 /* RGMII_IO_MACRO_CONFIG2 fields */
65 #define RGMII_CONFIG2_RSVD_CONFIG15 GENMASK(31, 17)
66 #define RGMII_CONFIG2_RGMII_CLK_SEL_CFG BIT(16)
67 #define RGMII_CONFIG2_TX_TO_RX_LOOPBACK_EN BIT(13)
68 #define RGMII_CONFIG2_CLK_DIVIDE_SEL BIT(12)
69 #define RGMII_CONFIG2_RX_PROG_SWAP BIT(7)
70 #define RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL BIT(6)
71 #define RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN BIT(5)
72
73 struct ethqos_emac_por {
74 unsigned int offset;
75 unsigned int value;
76 };
77
78 struct ethqos_emac_driver_data {
79 const struct ethqos_emac_por *por;
80 unsigned int num_por;
81 bool rgmii_config_looback_en;
82 };
83
84 struct qcom_ethqos {
85 struct platform_device *pdev;
86 void __iomem *rgmii_base;
87
88 unsigned int rgmii_clk_rate;
89 struct clk *rgmii_clk;
90 unsigned int speed;
91
92 const struct ethqos_emac_por *por;
93 unsigned int num_por;
94 bool rgmii_config_looback_en;
95 };
96
rgmii_readl(struct qcom_ethqos * ethqos,unsigned int offset)97 static int rgmii_readl(struct qcom_ethqos *ethqos, unsigned int offset)
98 {
99 return readl(ethqos->rgmii_base + offset);
100 }
101
rgmii_writel(struct qcom_ethqos * ethqos,int value,unsigned int offset)102 static void rgmii_writel(struct qcom_ethqos *ethqos,
103 int value, unsigned int offset)
104 {
105 writel(value, ethqos->rgmii_base + offset);
106 }
107
rgmii_updatel(struct qcom_ethqos * ethqos,int mask,int val,unsigned int offset)108 static void rgmii_updatel(struct qcom_ethqos *ethqos,
109 int mask, int val, unsigned int offset)
110 {
111 unsigned int temp;
112
113 temp = rgmii_readl(ethqos, offset);
114 temp = (temp & ~(mask)) | val;
115 rgmii_writel(ethqos, temp, offset);
116 }
117
rgmii_dump(void * priv)118 static void rgmii_dump(void *priv)
119 {
120 struct qcom_ethqos *ethqos = priv;
121
122 dev_dbg(ðqos->pdev->dev, "Rgmii register dump\n");
123 dev_dbg(ðqos->pdev->dev, "RGMII_IO_MACRO_CONFIG: %x\n",
124 rgmii_readl(ethqos, RGMII_IO_MACRO_CONFIG));
125 dev_dbg(ðqos->pdev->dev, "SDCC_HC_REG_DLL_CONFIG: %x\n",
126 rgmii_readl(ethqos, SDCC_HC_REG_DLL_CONFIG));
127 dev_dbg(ðqos->pdev->dev, "SDCC_HC_REG_DDR_CONFIG: %x\n",
128 rgmii_readl(ethqos, SDCC_HC_REG_DDR_CONFIG));
129 dev_dbg(ðqos->pdev->dev, "SDCC_HC_REG_DLL_CONFIG2: %x\n",
130 rgmii_readl(ethqos, SDCC_HC_REG_DLL_CONFIG2));
131 dev_dbg(ðqos->pdev->dev, "SDC4_STATUS: %x\n",
132 rgmii_readl(ethqos, SDC4_STATUS));
133 dev_dbg(ðqos->pdev->dev, "SDCC_USR_CTL: %x\n",
134 rgmii_readl(ethqos, SDCC_USR_CTL));
135 dev_dbg(ðqos->pdev->dev, "RGMII_IO_MACRO_CONFIG2: %x\n",
136 rgmii_readl(ethqos, RGMII_IO_MACRO_CONFIG2));
137 dev_dbg(ðqos->pdev->dev, "RGMII_IO_MACRO_DEBUG1: %x\n",
138 rgmii_readl(ethqos, RGMII_IO_MACRO_DEBUG1));
139 dev_dbg(ðqos->pdev->dev, "EMAC_SYSTEM_LOW_POWER_DEBUG: %x\n",
140 rgmii_readl(ethqos, EMAC_SYSTEM_LOW_POWER_DEBUG));
141 }
142
143 /* Clock rates */
144 #define RGMII_1000_NOM_CLK_FREQ (250 * 1000 * 1000UL)
145 #define RGMII_ID_MODE_100_LOW_SVS_CLK_FREQ (50 * 1000 * 1000UL)
146 #define RGMII_ID_MODE_10_LOW_SVS_CLK_FREQ (5 * 1000 * 1000UL)
147
148 static void
ethqos_update_rgmii_clk(struct qcom_ethqos * ethqos,unsigned int speed)149 ethqos_update_rgmii_clk(struct qcom_ethqos *ethqos, unsigned int speed)
150 {
151 switch (speed) {
152 case SPEED_1000:
153 ethqos->rgmii_clk_rate = RGMII_1000_NOM_CLK_FREQ;
154 break;
155
156 case SPEED_100:
157 ethqos->rgmii_clk_rate = RGMII_ID_MODE_100_LOW_SVS_CLK_FREQ;
158 break;
159
160 case SPEED_10:
161 ethqos->rgmii_clk_rate = RGMII_ID_MODE_10_LOW_SVS_CLK_FREQ;
162 break;
163 }
164
165 clk_set_rate(ethqos->rgmii_clk, ethqos->rgmii_clk_rate);
166 }
167
ethqos_set_func_clk_en(struct qcom_ethqos * ethqos)168 static void ethqos_set_func_clk_en(struct qcom_ethqos *ethqos)
169 {
170 rgmii_updatel(ethqos, RGMII_CONFIG_FUNC_CLK_EN,
171 RGMII_CONFIG_FUNC_CLK_EN, RGMII_IO_MACRO_CONFIG);
172 }
173
174 static const struct ethqos_emac_por emac_v2_3_0_por[] = {
175 { .offset = RGMII_IO_MACRO_CONFIG, .value = 0x00C01343 },
176 { .offset = SDCC_HC_REG_DLL_CONFIG, .value = 0x2004642C },
177 { .offset = SDCC_HC_REG_DDR_CONFIG, .value = 0x00000000 },
178 { .offset = SDCC_HC_REG_DLL_CONFIG2, .value = 0x00200000 },
179 { .offset = SDCC_USR_CTL, .value = 0x00010800 },
180 { .offset = RGMII_IO_MACRO_CONFIG2, .value = 0x00002060 },
181 };
182
183 static const struct ethqos_emac_driver_data emac_v2_3_0_data = {
184 .por = emac_v2_3_0_por,
185 .num_por = ARRAY_SIZE(emac_v2_3_0_por),
186 .rgmii_config_looback_en = true,
187 };
188
189 static const struct ethqos_emac_por emac_v2_1_0_por[] = {
190 { .offset = RGMII_IO_MACRO_CONFIG, .value = 0x40C01343 },
191 { .offset = SDCC_HC_REG_DLL_CONFIG, .value = 0x2004642C },
192 { .offset = SDCC_HC_REG_DDR_CONFIG, .value = 0x00000000 },
193 { .offset = SDCC_HC_REG_DLL_CONFIG2, .value = 0x00200000 },
194 { .offset = SDCC_USR_CTL, .value = 0x00010800 },
195 { .offset = RGMII_IO_MACRO_CONFIG2, .value = 0x00002060 },
196 };
197
198 static const struct ethqos_emac_driver_data emac_v2_1_0_data = {
199 .por = emac_v2_1_0_por,
200 .num_por = ARRAY_SIZE(emac_v2_1_0_por),
201 .rgmii_config_looback_en = false,
202 };
203
ethqos_dll_configure(struct qcom_ethqos * ethqos)204 static int ethqos_dll_configure(struct qcom_ethqos *ethqos)
205 {
206 unsigned int val;
207 int retry = 1000;
208
209 /* Set CDR_EN */
210 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CDR_EN,
211 SDCC_DLL_CONFIG_CDR_EN, SDCC_HC_REG_DLL_CONFIG);
212
213 /* Set CDR_EXT_EN */
214 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CDR_EXT_EN,
215 SDCC_DLL_CONFIG_CDR_EXT_EN, SDCC_HC_REG_DLL_CONFIG);
216
217 /* Clear CK_OUT_EN */
218 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CK_OUT_EN,
219 0, SDCC_HC_REG_DLL_CONFIG);
220
221 /* Set DLL_EN */
222 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_DLL_EN,
223 SDCC_DLL_CONFIG_DLL_EN, SDCC_HC_REG_DLL_CONFIG);
224
225 rgmii_updatel(ethqos, SDCC_DLL_MCLK_GATING_EN,
226 0, SDCC_HC_REG_DLL_CONFIG);
227
228 rgmii_updatel(ethqos, SDCC_DLL_CDR_FINE_PHASE,
229 0, SDCC_HC_REG_DLL_CONFIG);
230
231 /* Wait for CK_OUT_EN clear */
232 do {
233 val = rgmii_readl(ethqos, SDCC_HC_REG_DLL_CONFIG);
234 val &= SDCC_DLL_CONFIG_CK_OUT_EN;
235 if (!val)
236 break;
237 mdelay(1);
238 retry--;
239 } while (retry > 0);
240 if (!retry)
241 dev_err(ðqos->pdev->dev, "Clear CK_OUT_EN timedout\n");
242
243 /* Set CK_OUT_EN */
244 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CK_OUT_EN,
245 SDCC_DLL_CONFIG_CK_OUT_EN, SDCC_HC_REG_DLL_CONFIG);
246
247 /* Wait for CK_OUT_EN set */
248 retry = 1000;
249 do {
250 val = rgmii_readl(ethqos, SDCC_HC_REG_DLL_CONFIG);
251 val &= SDCC_DLL_CONFIG_CK_OUT_EN;
252 if (val)
253 break;
254 mdelay(1);
255 retry--;
256 } while (retry > 0);
257 if (!retry)
258 dev_err(ðqos->pdev->dev, "Set CK_OUT_EN timedout\n");
259
260 /* Set DDR_CAL_EN */
261 rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DDR_CAL_EN,
262 SDCC_DLL_CONFIG2_DDR_CAL_EN, SDCC_HC_REG_DLL_CONFIG2);
263
264 rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DLL_CLOCK_DIS,
265 0, SDCC_HC_REG_DLL_CONFIG2);
266
267 rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_MCLK_FREQ_CALC,
268 0x1A << 10, SDCC_HC_REG_DLL_CONFIG2);
269
270 rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SEL,
271 BIT(2), SDCC_HC_REG_DLL_CONFIG2);
272
273 rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SW,
274 SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SW,
275 SDCC_HC_REG_DLL_CONFIG2);
276
277 return 0;
278 }
279
ethqos_rgmii_macro_init(struct qcom_ethqos * ethqos)280 static int ethqos_rgmii_macro_init(struct qcom_ethqos *ethqos)
281 {
282 /* Disable loopback mode */
283 rgmii_updatel(ethqos, RGMII_CONFIG2_TX_TO_RX_LOOPBACK_EN,
284 0, RGMII_IO_MACRO_CONFIG2);
285
286 /* Select RGMII, write 0 to interface select */
287 rgmii_updatel(ethqos, RGMII_CONFIG_INTF_SEL,
288 0, RGMII_IO_MACRO_CONFIG);
289
290 switch (ethqos->speed) {
291 case SPEED_1000:
292 rgmii_updatel(ethqos, RGMII_CONFIG_DDR_MODE,
293 RGMII_CONFIG_DDR_MODE, RGMII_IO_MACRO_CONFIG);
294 rgmii_updatel(ethqos, RGMII_CONFIG_BYPASS_TX_ID_EN,
295 0, RGMII_IO_MACRO_CONFIG);
296 rgmii_updatel(ethqos, RGMII_CONFIG_POS_NEG_DATA_SEL,
297 RGMII_CONFIG_POS_NEG_DATA_SEL,
298 RGMII_IO_MACRO_CONFIG);
299 rgmii_updatel(ethqos, RGMII_CONFIG_PROG_SWAP,
300 RGMII_CONFIG_PROG_SWAP, RGMII_IO_MACRO_CONFIG);
301 rgmii_updatel(ethqos, RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL,
302 0, RGMII_IO_MACRO_CONFIG2);
303 rgmii_updatel(ethqos, RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN,
304 RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN,
305 RGMII_IO_MACRO_CONFIG2);
306 rgmii_updatel(ethqos, RGMII_CONFIG2_RSVD_CONFIG15,
307 0, RGMII_IO_MACRO_CONFIG2);
308 rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP,
309 RGMII_CONFIG2_RX_PROG_SWAP,
310 RGMII_IO_MACRO_CONFIG2);
311
312 /* Set PRG_RCLK_DLY to 57 for 1.8 ns delay */
313 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_PRG_RCLK_DLY,
314 57, SDCC_HC_REG_DDR_CONFIG);
315 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_PRG_DLY_EN,
316 SDCC_DDR_CONFIG_PRG_DLY_EN,
317 SDCC_HC_REG_DDR_CONFIG);
318 if (ethqos->rgmii_config_looback_en)
319 rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN,
320 RGMII_CONFIG_LOOPBACK_EN, RGMII_IO_MACRO_CONFIG);
321 else
322 rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN,
323 0, RGMII_IO_MACRO_CONFIG);
324 break;
325
326 case SPEED_100:
327 rgmii_updatel(ethqos, RGMII_CONFIG_DDR_MODE,
328 RGMII_CONFIG_DDR_MODE, RGMII_IO_MACRO_CONFIG);
329 rgmii_updatel(ethqos, RGMII_CONFIG_BYPASS_TX_ID_EN,
330 RGMII_CONFIG_BYPASS_TX_ID_EN,
331 RGMII_IO_MACRO_CONFIG);
332 rgmii_updatel(ethqos, RGMII_CONFIG_POS_NEG_DATA_SEL,
333 0, RGMII_IO_MACRO_CONFIG);
334 rgmii_updatel(ethqos, RGMII_CONFIG_PROG_SWAP,
335 0, RGMII_IO_MACRO_CONFIG);
336 rgmii_updatel(ethqos, RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL,
337 0, RGMII_IO_MACRO_CONFIG2);
338 rgmii_updatel(ethqos, RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN,
339 RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN,
340 RGMII_IO_MACRO_CONFIG2);
341 rgmii_updatel(ethqos, RGMII_CONFIG_MAX_SPD_PRG_2,
342 BIT(6), RGMII_IO_MACRO_CONFIG);
343 rgmii_updatel(ethqos, RGMII_CONFIG2_RSVD_CONFIG15,
344 0, RGMII_IO_MACRO_CONFIG2);
345 rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP,
346 0, RGMII_IO_MACRO_CONFIG2);
347 /* Write 0x5 to PRG_RCLK_DLY_CODE */
348 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_CODE,
349 (BIT(29) | BIT(27)), SDCC_HC_REG_DDR_CONFIG);
350 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY,
351 SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY,
352 SDCC_HC_REG_DDR_CONFIG);
353 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN,
354 SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN,
355 SDCC_HC_REG_DDR_CONFIG);
356 if (ethqos->rgmii_config_looback_en)
357 rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN,
358 RGMII_CONFIG_LOOPBACK_EN, RGMII_IO_MACRO_CONFIG);
359 else
360 rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN,
361 0, RGMII_IO_MACRO_CONFIG);
362
363 break;
364
365 case SPEED_10:
366 rgmii_updatel(ethqos, RGMII_CONFIG_DDR_MODE,
367 RGMII_CONFIG_DDR_MODE, RGMII_IO_MACRO_CONFIG);
368 rgmii_updatel(ethqos, RGMII_CONFIG_BYPASS_TX_ID_EN,
369 RGMII_CONFIG_BYPASS_TX_ID_EN,
370 RGMII_IO_MACRO_CONFIG);
371 rgmii_updatel(ethqos, RGMII_CONFIG_POS_NEG_DATA_SEL,
372 0, RGMII_IO_MACRO_CONFIG);
373 rgmii_updatel(ethqos, RGMII_CONFIG_PROG_SWAP,
374 0, RGMII_IO_MACRO_CONFIG);
375 rgmii_updatel(ethqos, RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL,
376 0, RGMII_IO_MACRO_CONFIG2);
377 rgmii_updatel(ethqos, RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN,
378 0, RGMII_IO_MACRO_CONFIG2);
379 rgmii_updatel(ethqos, RGMII_CONFIG_MAX_SPD_PRG_9,
380 BIT(12) | GENMASK(9, 8),
381 RGMII_IO_MACRO_CONFIG);
382 rgmii_updatel(ethqos, RGMII_CONFIG2_RSVD_CONFIG15,
383 0, RGMII_IO_MACRO_CONFIG2);
384 rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP,
385 0, RGMII_IO_MACRO_CONFIG2);
386 /* Write 0x5 to PRG_RCLK_DLY_CODE */
387 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_CODE,
388 (BIT(29) | BIT(27)), SDCC_HC_REG_DDR_CONFIG);
389 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY,
390 SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY,
391 SDCC_HC_REG_DDR_CONFIG);
392 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN,
393 SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN,
394 SDCC_HC_REG_DDR_CONFIG);
395 rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN,
396 RGMII_CONFIG_LOOPBACK_EN, RGMII_IO_MACRO_CONFIG);
397 break;
398 default:
399 dev_err(ðqos->pdev->dev,
400 "Invalid speed %d\n", ethqos->speed);
401 return -EINVAL;
402 }
403
404 return 0;
405 }
406
ethqos_configure(struct qcom_ethqos * ethqos)407 static int ethqos_configure(struct qcom_ethqos *ethqos)
408 {
409 volatile unsigned int dll_lock;
410 unsigned int i, retry = 1000;
411
412 /* Reset to POR values and enable clk */
413 for (i = 0; i < ethqos->num_por; i++)
414 rgmii_writel(ethqos, ethqos->por[i].value,
415 ethqos->por[i].offset);
416 ethqos_set_func_clk_en(ethqos);
417
418 /* Initialize the DLL first */
419
420 /* Set DLL_RST */
421 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_DLL_RST,
422 SDCC_DLL_CONFIG_DLL_RST, SDCC_HC_REG_DLL_CONFIG);
423
424 /* Set PDN */
425 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_PDN,
426 SDCC_DLL_CONFIG_PDN, SDCC_HC_REG_DLL_CONFIG);
427
428 /* Clear DLL_RST */
429 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_DLL_RST, 0,
430 SDCC_HC_REG_DLL_CONFIG);
431
432 /* Clear PDN */
433 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_PDN, 0,
434 SDCC_HC_REG_DLL_CONFIG);
435
436 if (ethqos->speed != SPEED_100 && ethqos->speed != SPEED_10) {
437 /* Set DLL_EN */
438 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_DLL_EN,
439 SDCC_DLL_CONFIG_DLL_EN, SDCC_HC_REG_DLL_CONFIG);
440
441 /* Set CK_OUT_EN */
442 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CK_OUT_EN,
443 SDCC_DLL_CONFIG_CK_OUT_EN,
444 SDCC_HC_REG_DLL_CONFIG);
445
446 /* Set USR_CTL bit 26 with mask of 3 bits */
447 rgmii_updatel(ethqos, GENMASK(26, 24), BIT(26), SDCC_USR_CTL);
448
449 /* wait for DLL LOCK */
450 do {
451 mdelay(1);
452 dll_lock = rgmii_readl(ethqos, SDC4_STATUS);
453 if (dll_lock & SDC4_STATUS_DLL_LOCK)
454 break;
455 retry--;
456 } while (retry > 0);
457 if (!retry)
458 dev_err(ðqos->pdev->dev,
459 "Timeout while waiting for DLL lock\n");
460 }
461
462 if (ethqos->speed == SPEED_1000)
463 ethqos_dll_configure(ethqos);
464
465 ethqos_rgmii_macro_init(ethqos);
466
467 return 0;
468 }
469
ethqos_fix_mac_speed(void * priv,unsigned int speed)470 static void ethqos_fix_mac_speed(void *priv, unsigned int speed)
471 {
472 struct qcom_ethqos *ethqos = priv;
473
474 ethqos->speed = speed;
475 ethqos_update_rgmii_clk(ethqos, speed);
476 ethqos_configure(ethqos);
477 }
478
ethqos_clks_config(void * priv,bool enabled)479 static int ethqos_clks_config(void *priv, bool enabled)
480 {
481 struct qcom_ethqos *ethqos = priv;
482 int ret = 0;
483
484 if (enabled) {
485 ret = clk_prepare_enable(ethqos->rgmii_clk);
486 if (ret) {
487 dev_err(ðqos->pdev->dev, "rgmii_clk enable failed\n");
488 return ret;
489 }
490
491 /* Enable functional clock to prevent DMA reset to timeout due
492 * to lacking PHY clock after the hardware block has been power
493 * cycled. The actual configuration will be adjusted once
494 * ethqos_fix_mac_speed() is invoked.
495 */
496 ethqos_set_func_clk_en(ethqos);
497 } else {
498 clk_disable_unprepare(ethqos->rgmii_clk);
499 }
500
501 return ret;
502 }
503
qcom_ethqos_probe(struct platform_device * pdev)504 static int qcom_ethqos_probe(struct platform_device *pdev)
505 {
506 struct device_node *np = pdev->dev.of_node;
507 struct plat_stmmacenet_data *plat_dat;
508 struct stmmac_resources stmmac_res;
509 const struct ethqos_emac_driver_data *data;
510 struct qcom_ethqos *ethqos;
511 int ret;
512
513 ret = stmmac_get_platform_resources(pdev, &stmmac_res);
514 if (ret)
515 return ret;
516
517 plat_dat = stmmac_probe_config_dt(pdev, stmmac_res.mac);
518 if (IS_ERR(plat_dat)) {
519 dev_err(&pdev->dev, "dt configuration failed\n");
520 return PTR_ERR(plat_dat);
521 }
522
523 plat_dat->clks_config = ethqos_clks_config;
524
525 ethqos = devm_kzalloc(&pdev->dev, sizeof(*ethqos), GFP_KERNEL);
526 if (!ethqos) {
527 ret = -ENOMEM;
528 goto err_mem;
529 }
530
531 ethqos->pdev = pdev;
532 ethqos->rgmii_base = devm_platform_ioremap_resource_byname(pdev, "rgmii");
533 if (IS_ERR(ethqos->rgmii_base)) {
534 ret = PTR_ERR(ethqos->rgmii_base);
535 goto err_mem;
536 }
537
538 data = of_device_get_match_data(&pdev->dev);
539 ethqos->por = data->por;
540 ethqos->num_por = data->num_por;
541 ethqos->rgmii_config_looback_en = data->rgmii_config_looback_en;
542
543 ethqos->rgmii_clk = devm_clk_get(&pdev->dev, "rgmii");
544 if (IS_ERR(ethqos->rgmii_clk)) {
545 ret = PTR_ERR(ethqos->rgmii_clk);
546 goto err_mem;
547 }
548
549 ret = ethqos_clks_config(ethqos, true);
550 if (ret)
551 goto err_mem;
552
553 ethqos->speed = SPEED_1000;
554 ethqos_update_rgmii_clk(ethqos, SPEED_1000);
555 ethqos_set_func_clk_en(ethqos);
556
557 plat_dat->bsp_priv = ethqos;
558 plat_dat->fix_mac_speed = ethqos_fix_mac_speed;
559 plat_dat->dump_debug_regs = rgmii_dump;
560 plat_dat->has_gmac4 = 1;
561 plat_dat->pmt = 1;
562 plat_dat->tso_en = of_property_read_bool(np, "snps,tso");
563
564 ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res);
565 if (ret)
566 goto err_clk;
567
568 return ret;
569
570 err_clk:
571 ethqos_clks_config(ethqos, false);
572
573 err_mem:
574 stmmac_remove_config_dt(pdev, plat_dat);
575
576 return ret;
577 }
578
qcom_ethqos_remove(struct platform_device * pdev)579 static int qcom_ethqos_remove(struct platform_device *pdev)
580 {
581 struct qcom_ethqos *ethqos;
582 int ret;
583
584 ethqos = get_stmmac_bsp_priv(&pdev->dev);
585 if (!ethqos)
586 return -ENODEV;
587
588 ret = stmmac_pltfr_remove(pdev);
589 ethqos_clks_config(ethqos, false);
590
591 return ret;
592 }
593
594 static const struct of_device_id qcom_ethqos_match[] = {
595 { .compatible = "qcom,qcs404-ethqos", .data = &emac_v2_3_0_data},
596 { .compatible = "qcom,sm8150-ethqos", .data = &emac_v2_1_0_data},
597 { }
598 };
599 MODULE_DEVICE_TABLE(of, qcom_ethqos_match);
600
601 static struct platform_driver qcom_ethqos_driver = {
602 .probe = qcom_ethqos_probe,
603 .remove = qcom_ethqos_remove,
604 .driver = {
605 .name = "qcom-ethqos",
606 .pm = &stmmac_pltfr_pm_ops,
607 .of_match_table = of_match_ptr(qcom_ethqos_match),
608 },
609 };
610 module_platform_driver(qcom_ethqos_driver);
611
612 MODULE_DESCRIPTION("Qualcomm ETHQOS driver");
613 MODULE_LICENSE("GPL v2");
614
