1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * R-Car MIPI DSI Encoder
4 *
5 * Copyright (C) 2020 Renesas Electronics Corporation
6 */
7
8 #include <linux/clk.h>
9 #include <linux/delay.h>
10 #include <linux/io.h>
11 #include <linux/iopoll.h>
12 #include <linux/module.h>
13 #include <linux/of.h>
14 #include <linux/of_device.h>
15 #include <linux/of_graph.h>
16 #include <linux/platform_device.h>
17 #include <linux/reset.h>
18 #include <linux/slab.h>
19
20 #include <drm/drm_atomic.h>
21 #include <drm/drm_atomic_helper.h>
22 #include <drm/drm_bridge.h>
23 #include <drm/drm_mipi_dsi.h>
24 #include <drm/drm_of.h>
25 #include <drm/drm_panel.h>
26 #include <drm/drm_probe_helper.h>
27
28 #include "rcar_mipi_dsi.h"
29 #include "rcar_mipi_dsi_regs.h"
30
31 struct rcar_mipi_dsi {
32 struct device *dev;
33 const struct rcar_mipi_dsi_device_info *info;
34 struct reset_control *rstc;
35
36 struct mipi_dsi_host host;
37 struct drm_bridge bridge;
38 struct drm_bridge *next_bridge;
39 struct drm_connector connector;
40
41 void __iomem *mmio;
42 struct {
43 struct clk *mod;
44 struct clk *pll;
45 struct clk *dsi;
46 } clocks;
47
48 enum mipi_dsi_pixel_format format;
49 unsigned int num_data_lanes;
50 unsigned int lanes;
51 };
52
53 static inline struct rcar_mipi_dsi *
bridge_to_rcar_mipi_dsi(struct drm_bridge * bridge)54 bridge_to_rcar_mipi_dsi(struct drm_bridge *bridge)
55 {
56 return container_of(bridge, struct rcar_mipi_dsi, bridge);
57 }
58
59 static inline struct rcar_mipi_dsi *
host_to_rcar_mipi_dsi(struct mipi_dsi_host * host)60 host_to_rcar_mipi_dsi(struct mipi_dsi_host *host)
61 {
62 return container_of(host, struct rcar_mipi_dsi, host);
63 }
64
65 static const u32 phtw[] = {
66 0x01020114, 0x01600115, /* General testing */
67 0x01030116, 0x0102011d, /* General testing */
68 0x011101a4, 0x018601a4, /* 1Gbps testing */
69 0x014201a0, 0x010001a3, /* 1Gbps testing */
70 0x0101011f, /* 1Gbps testing */
71 };
72
73 static const u32 phtw2[] = {
74 0x010c0130, 0x010c0140, /* General testing */
75 0x010c0150, 0x010c0180, /* General testing */
76 0x010c0190,
77 0x010a0160, 0x010a0170,
78 0x01800164, 0x01800174, /* 1Gbps testing */
79 };
80
81 static const u32 hsfreqrange_table[][2] = {
82 { 80000000U, 0x00 }, { 90000000U, 0x10 }, { 100000000U, 0x20 },
83 { 110000000U, 0x30 }, { 120000000U, 0x01 }, { 130000000U, 0x11 },
84 { 140000000U, 0x21 }, { 150000000U, 0x31 }, { 160000000U, 0x02 },
85 { 170000000U, 0x12 }, { 180000000U, 0x22 }, { 190000000U, 0x32 },
86 { 205000000U, 0x03 }, { 220000000U, 0x13 }, { 235000000U, 0x23 },
87 { 250000000U, 0x33 }, { 275000000U, 0x04 }, { 300000000U, 0x14 },
88 { 325000000U, 0x25 }, { 350000000U, 0x35 }, { 400000000U, 0x05 },
89 { 450000000U, 0x16 }, { 500000000U, 0x26 }, { 550000000U, 0x37 },
90 { 600000000U, 0x07 }, { 650000000U, 0x18 }, { 700000000U, 0x28 },
91 { 750000000U, 0x39 }, { 800000000U, 0x09 }, { 850000000U, 0x19 },
92 { 900000000U, 0x29 }, { 950000000U, 0x3a }, { 1000000000U, 0x0a },
93 { 1050000000U, 0x1a }, { 1100000000U, 0x2a }, { 1150000000U, 0x3b },
94 { 1200000000U, 0x0b }, { 1250000000U, 0x1b }, { 1300000000U, 0x2b },
95 { 1350000000U, 0x3c }, { 1400000000U, 0x0c }, { 1450000000U, 0x1c },
96 { 1500000000U, 0x2c }, { 1550000000U, 0x3d }, { 1600000000U, 0x0d },
97 { 1650000000U, 0x1d }, { 1700000000U, 0x2e }, { 1750000000U, 0x3e },
98 { 1800000000U, 0x0e }, { 1850000000U, 0x1e }, { 1900000000U, 0x2f },
99 { 1950000000U, 0x3f }, { 2000000000U, 0x0f }, { 2050000000U, 0x40 },
100 { 2100000000U, 0x41 }, { 2150000000U, 0x42 }, { 2200000000U, 0x43 },
101 { 2250000000U, 0x44 }, { 2300000000U, 0x45 }, { 2350000000U, 0x46 },
102 { 2400000000U, 0x47 }, { 2450000000U, 0x48 }, { 2500000000U, 0x49 },
103 { /* sentinel */ },
104 };
105
106 struct vco_cntrl_value {
107 u32 min_freq;
108 u32 max_freq;
109 u16 value;
110 };
111
112 static const struct vco_cntrl_value vco_cntrl_table[] = {
113 { .min_freq = 40000000U, .max_freq = 55000000U, .value = 0x3f },
114 { .min_freq = 52500000U, .max_freq = 80000000U, .value = 0x39 },
115 { .min_freq = 80000000U, .max_freq = 110000000U, .value = 0x2f },
116 { .min_freq = 105000000U, .max_freq = 160000000U, .value = 0x29 },
117 { .min_freq = 160000000U, .max_freq = 220000000U, .value = 0x1f },
118 { .min_freq = 210000000U, .max_freq = 320000000U, .value = 0x19 },
119 { .min_freq = 320000000U, .max_freq = 440000000U, .value = 0x0f },
120 { .min_freq = 420000000U, .max_freq = 660000000U, .value = 0x09 },
121 { .min_freq = 630000000U, .max_freq = 1149000000U, .value = 0x03 },
122 { .min_freq = 1100000000U, .max_freq = 1152000000U, .value = 0x01 },
123 { .min_freq = 1150000000U, .max_freq = 1250000000U, .value = 0x01 },
124 { /* sentinel */ },
125 };
126
rcar_mipi_dsi_write(struct rcar_mipi_dsi * dsi,u32 reg,u32 data)127 static void rcar_mipi_dsi_write(struct rcar_mipi_dsi *dsi, u32 reg, u32 data)
128 {
129 iowrite32(data, dsi->mmio + reg);
130 }
131
rcar_mipi_dsi_read(struct rcar_mipi_dsi * dsi,u32 reg)132 static u32 rcar_mipi_dsi_read(struct rcar_mipi_dsi *dsi, u32 reg)
133 {
134 return ioread32(dsi->mmio + reg);
135 }
136
rcar_mipi_dsi_clr(struct rcar_mipi_dsi * dsi,u32 reg,u32 clr)137 static void rcar_mipi_dsi_clr(struct rcar_mipi_dsi *dsi, u32 reg, u32 clr)
138 {
139 rcar_mipi_dsi_write(dsi, reg, rcar_mipi_dsi_read(dsi, reg) & ~clr);
140 }
141
rcar_mipi_dsi_set(struct rcar_mipi_dsi * dsi,u32 reg,u32 set)142 static void rcar_mipi_dsi_set(struct rcar_mipi_dsi *dsi, u32 reg, u32 set)
143 {
144 rcar_mipi_dsi_write(dsi, reg, rcar_mipi_dsi_read(dsi, reg) | set);
145 }
146
rcar_mipi_dsi_phtw_test(struct rcar_mipi_dsi * dsi,u32 phtw)147 static int rcar_mipi_dsi_phtw_test(struct rcar_mipi_dsi *dsi, u32 phtw)
148 {
149 u32 status;
150 int ret;
151
152 rcar_mipi_dsi_write(dsi, PHTW, phtw);
153
154 ret = read_poll_timeout(rcar_mipi_dsi_read, status,
155 !(status & (PHTW_DWEN | PHTW_CWEN)),
156 2000, 10000, false, dsi, PHTW);
157 if (ret < 0) {
158 dev_err(dsi->dev, "PHY test interface write timeout (0x%08x)\n",
159 phtw);
160 return ret;
161 }
162
163 return ret;
164 }
165
166 /* -----------------------------------------------------------------------------
167 * Hardware Setup
168 */
169
170 struct dsi_setup_info {
171 unsigned long fout;
172 u16 vco_cntrl;
173 u16 prop_cntrl;
174 u16 hsfreqrange;
175 u16 div;
176 unsigned int m;
177 unsigned int n;
178 };
179
rcar_mipi_dsi_parameters_calc(struct rcar_mipi_dsi * dsi,struct clk * clk,unsigned long target,struct dsi_setup_info * setup_info)180 static void rcar_mipi_dsi_parameters_calc(struct rcar_mipi_dsi *dsi,
181 struct clk *clk, unsigned long target,
182 struct dsi_setup_info *setup_info)
183 {
184
185 const struct vco_cntrl_value *vco_cntrl;
186 unsigned long fout_target;
187 unsigned long fin, fout;
188 unsigned long hsfreq;
189 unsigned int best_err = -1;
190 unsigned int divider;
191 unsigned int n;
192 unsigned int i;
193 unsigned int err;
194
195 /*
196 * Calculate Fout = dot clock * ColorDepth / (2 * Lane Count)
197 * The range out Fout is [40 - 1250] Mhz
198 */
199 fout_target = target * mipi_dsi_pixel_format_to_bpp(dsi->format)
200 / (2 * dsi->lanes);
201 if (fout_target < 40000000 || fout_target > 1250000000)
202 return;
203
204 /* Find vco_cntrl */
205 for (vco_cntrl = vco_cntrl_table; vco_cntrl->min_freq != 0; vco_cntrl++) {
206 if (fout_target > vco_cntrl->min_freq &&
207 fout_target <= vco_cntrl->max_freq) {
208 setup_info->vco_cntrl = vco_cntrl->value;
209 if (fout_target >= 1150000000)
210 setup_info->prop_cntrl = 0x0c;
211 else
212 setup_info->prop_cntrl = 0x0b;
213 break;
214 }
215 }
216
217 /* Add divider */
218 setup_info->div = (setup_info->vco_cntrl & 0x30) >> 4;
219
220 /* Find hsfreqrange */
221 hsfreq = fout_target * 2;
222 for (i = 0; i < ARRAY_SIZE(hsfreqrange_table); i++) {
223 if (hsfreqrange_table[i][0] >= hsfreq) {
224 setup_info->hsfreqrange = hsfreqrange_table[i][1];
225 break;
226 }
227 }
228
229 /*
230 * Calculate n and m for PLL clock
231 * Following the HW manual the ranges of n and m are
232 * n = [3-8] and m = [64-625]
233 */
234 fin = clk_get_rate(clk);
235 divider = 1 << setup_info->div;
236 for (n = 3; n < 9; n++) {
237 unsigned long fpfd;
238 unsigned int m;
239
240 fpfd = fin / n;
241
242 for (m = 64; m < 626; m++) {
243 fout = fpfd * m / divider;
244 err = abs((long)(fout - fout_target) * 10000 /
245 (long)fout_target);
246 if (err < best_err) {
247 setup_info->m = m - 2;
248 setup_info->n = n - 1;
249 setup_info->fout = fout;
250 best_err = err;
251 if (err == 0)
252 goto done;
253 }
254 }
255 }
256
257 done:
258 dev_dbg(dsi->dev,
259 "%pC %lu Hz -> Fout %lu Hz (target %lu Hz, error %d.%02u%%), PLL M/N/DIV %u/%u/%u\n",
260 clk, fin, setup_info->fout, fout_target, best_err / 100,
261 best_err % 100, setup_info->m, setup_info->n, setup_info->div);
262 dev_dbg(dsi->dev,
263 "vco_cntrl = 0x%x\tprop_cntrl = 0x%x\thsfreqrange = 0x%x\n",
264 setup_info->vco_cntrl, setup_info->prop_cntrl,
265 setup_info->hsfreqrange);
266 }
267
rcar_mipi_dsi_set_display_timing(struct rcar_mipi_dsi * dsi,const struct drm_display_mode * mode)268 static void rcar_mipi_dsi_set_display_timing(struct rcar_mipi_dsi *dsi,
269 const struct drm_display_mode *mode)
270 {
271 u32 setr;
272 u32 vprmset0r;
273 u32 vprmset1r;
274 u32 vprmset2r;
275 u32 vprmset3r;
276 u32 vprmset4r;
277
278 /* Configuration for Pixel Stream and Packet Header */
279 if (mipi_dsi_pixel_format_to_bpp(dsi->format) == 24)
280 rcar_mipi_dsi_write(dsi, TXVMPSPHSETR, TXVMPSPHSETR_DT_RGB24);
281 else if (mipi_dsi_pixel_format_to_bpp(dsi->format) == 18)
282 rcar_mipi_dsi_write(dsi, TXVMPSPHSETR, TXVMPSPHSETR_DT_RGB18);
283 else if (mipi_dsi_pixel_format_to_bpp(dsi->format) == 16)
284 rcar_mipi_dsi_write(dsi, TXVMPSPHSETR, TXVMPSPHSETR_DT_RGB16);
285 else {
286 dev_warn(dsi->dev, "unsupported format");
287 return;
288 }
289
290 /* Configuration for Blanking sequence and Input Pixel */
291 setr = TXVMSETR_HSABPEN_EN | TXVMSETR_HBPBPEN_EN
292 | TXVMSETR_HFPBPEN_EN | TXVMSETR_SYNSEQ_PULSES
293 | TXVMSETR_PIXWDTH | TXVMSETR_VSTPM;
294 rcar_mipi_dsi_write(dsi, TXVMSETR, setr);
295
296 /* Configuration for Video Parameters */
297 vprmset0r = (mode->flags & DRM_MODE_FLAG_PVSYNC ?
298 TXVMVPRMSET0R_VSPOL_HIG : TXVMVPRMSET0R_VSPOL_LOW)
299 | (mode->flags & DRM_MODE_FLAG_PHSYNC ?
300 TXVMVPRMSET0R_HSPOL_HIG : TXVMVPRMSET0R_HSPOL_LOW)
301 | TXVMVPRMSET0R_CSPC_RGB | TXVMVPRMSET0R_BPP_24;
302
303 vprmset1r = TXVMVPRMSET1R_VACTIVE(mode->vdisplay)
304 | TXVMVPRMSET1R_VSA(mode->vsync_end - mode->vsync_start);
305
306 vprmset2r = TXVMVPRMSET2R_VFP(mode->vsync_start - mode->vdisplay)
307 | TXVMVPRMSET2R_VBP(mode->vtotal - mode->vsync_end);
308
309 vprmset3r = TXVMVPRMSET3R_HACTIVE(mode->hdisplay)
310 | TXVMVPRMSET3R_HSA(mode->hsync_end - mode->hsync_start);
311
312 vprmset4r = TXVMVPRMSET4R_HFP(mode->hsync_start - mode->hdisplay)
313 | TXVMVPRMSET4R_HBP(mode->htotal - mode->hsync_end);
314
315 rcar_mipi_dsi_write(dsi, TXVMVPRMSET0R, vprmset0r);
316 rcar_mipi_dsi_write(dsi, TXVMVPRMSET1R, vprmset1r);
317 rcar_mipi_dsi_write(dsi, TXVMVPRMSET2R, vprmset2r);
318 rcar_mipi_dsi_write(dsi, TXVMVPRMSET3R, vprmset3r);
319 rcar_mipi_dsi_write(dsi, TXVMVPRMSET4R, vprmset4r);
320 }
321
rcar_mipi_dsi_startup(struct rcar_mipi_dsi * dsi,const struct drm_display_mode * mode)322 static int rcar_mipi_dsi_startup(struct rcar_mipi_dsi *dsi,
323 const struct drm_display_mode *mode)
324 {
325 struct dsi_setup_info setup_info = {};
326 unsigned int timeout;
327 int ret, i;
328 int dsi_format;
329 u32 phy_setup;
330 u32 clockset2, clockset3;
331 u32 ppisetr;
332 u32 vclkset;
333
334 /* Checking valid format */
335 dsi_format = mipi_dsi_pixel_format_to_bpp(dsi->format);
336 if (dsi_format < 0) {
337 dev_warn(dsi->dev, "invalid format");
338 return -EINVAL;
339 }
340
341 /* Parameters Calculation */
342 rcar_mipi_dsi_parameters_calc(dsi, dsi->clocks.pll,
343 mode->clock * 1000, &setup_info);
344
345 /* LPCLK enable */
346 rcar_mipi_dsi_set(dsi, LPCLKSET, LPCLKSET_CKEN);
347
348 /* CFGCLK enabled */
349 rcar_mipi_dsi_set(dsi, CFGCLKSET, CFGCLKSET_CKEN);
350
351 rcar_mipi_dsi_clr(dsi, PHYSETUP, PHYSETUP_RSTZ);
352 rcar_mipi_dsi_clr(dsi, PHYSETUP, PHYSETUP_SHUTDOWNZ);
353
354 rcar_mipi_dsi_set(dsi, PHTC, PHTC_TESTCLR);
355 rcar_mipi_dsi_clr(dsi, PHTC, PHTC_TESTCLR);
356
357 /* PHY setting */
358 phy_setup = rcar_mipi_dsi_read(dsi, PHYSETUP);
359 phy_setup &= ~PHYSETUP_HSFREQRANGE_MASK;
360 phy_setup |= PHYSETUP_HSFREQRANGE(setup_info.hsfreqrange);
361 rcar_mipi_dsi_write(dsi, PHYSETUP, phy_setup);
362
363 for (i = 0; i < ARRAY_SIZE(phtw); i++) {
364 ret = rcar_mipi_dsi_phtw_test(dsi, phtw[i]);
365 if (ret < 0)
366 return ret;
367 }
368
369 /* PLL Clock Setting */
370 rcar_mipi_dsi_clr(dsi, CLOCKSET1, CLOCKSET1_SHADOW_CLEAR);
371 rcar_mipi_dsi_set(dsi, CLOCKSET1, CLOCKSET1_SHADOW_CLEAR);
372 rcar_mipi_dsi_clr(dsi, CLOCKSET1, CLOCKSET1_SHADOW_CLEAR);
373
374 clockset2 = CLOCKSET2_M(setup_info.m) | CLOCKSET2_N(setup_info.n)
375 | CLOCKSET2_VCO_CNTRL(setup_info.vco_cntrl);
376 clockset3 = CLOCKSET3_PROP_CNTRL(setup_info.prop_cntrl)
377 | CLOCKSET3_INT_CNTRL(0)
378 | CLOCKSET3_CPBIAS_CNTRL(0x10)
379 | CLOCKSET3_GMP_CNTRL(1);
380 rcar_mipi_dsi_write(dsi, CLOCKSET2, clockset2);
381 rcar_mipi_dsi_write(dsi, CLOCKSET3, clockset3);
382
383 rcar_mipi_dsi_clr(dsi, CLOCKSET1, CLOCKSET1_UPDATEPLL);
384 rcar_mipi_dsi_set(dsi, CLOCKSET1, CLOCKSET1_UPDATEPLL);
385 udelay(10);
386 rcar_mipi_dsi_clr(dsi, CLOCKSET1, CLOCKSET1_UPDATEPLL);
387
388 ppisetr = PPISETR_DLEN_3 | PPISETR_CLEN;
389 rcar_mipi_dsi_write(dsi, PPISETR, ppisetr);
390
391 rcar_mipi_dsi_set(dsi, PHYSETUP, PHYSETUP_SHUTDOWNZ);
392 rcar_mipi_dsi_set(dsi, PHYSETUP, PHYSETUP_RSTZ);
393 usleep_range(400, 500);
394
395 /* Checking PPI clock status register */
396 for (timeout = 10; timeout > 0; --timeout) {
397 if ((rcar_mipi_dsi_read(dsi, PPICLSR) & PPICLSR_STPST) &&
398 (rcar_mipi_dsi_read(dsi, PPIDLSR) & PPIDLSR_STPST) &&
399 (rcar_mipi_dsi_read(dsi, CLOCKSET1) & CLOCKSET1_LOCK))
400 break;
401
402 usleep_range(1000, 2000);
403 }
404
405 if (!timeout) {
406 dev_err(dsi->dev, "failed to enable PPI clock\n");
407 return -ETIMEDOUT;
408 }
409
410 for (i = 0; i < ARRAY_SIZE(phtw2); i++) {
411 ret = rcar_mipi_dsi_phtw_test(dsi, phtw2[i]);
412 if (ret < 0)
413 return ret;
414 }
415
416 /* Enable DOT clock */
417 vclkset = VCLKSET_CKEN;
418 rcar_mipi_dsi_write(dsi, VCLKSET, vclkset);
419
420 if (dsi_format == 24)
421 vclkset |= VCLKSET_BPP_24;
422 else if (dsi_format == 18)
423 vclkset |= VCLKSET_BPP_18;
424 else if (dsi_format == 16)
425 vclkset |= VCLKSET_BPP_16;
426 else {
427 dev_warn(dsi->dev, "unsupported format");
428 return -EINVAL;
429 }
430 vclkset |= VCLKSET_COLOR_RGB | VCLKSET_DIV(setup_info.div)
431 | VCLKSET_LANE(dsi->lanes - 1);
432
433 rcar_mipi_dsi_write(dsi, VCLKSET, vclkset);
434
435 /* After setting VCLKSET register, enable VCLKEN */
436 rcar_mipi_dsi_set(dsi, VCLKEN, VCLKEN_CKEN);
437
438 dev_dbg(dsi->dev, "DSI device is started\n");
439
440 return 0;
441 }
442
rcar_mipi_dsi_shutdown(struct rcar_mipi_dsi * dsi)443 static void rcar_mipi_dsi_shutdown(struct rcar_mipi_dsi *dsi)
444 {
445 /* Disable VCLKEN */
446 rcar_mipi_dsi_write(dsi, VCLKSET, 0);
447
448 /* Disable DOT clock */
449 rcar_mipi_dsi_write(dsi, VCLKSET, 0);
450
451 rcar_mipi_dsi_clr(dsi, PHYSETUP, PHYSETUP_RSTZ);
452 rcar_mipi_dsi_clr(dsi, PHYSETUP, PHYSETUP_SHUTDOWNZ);
453
454 /* CFGCLK disable */
455 rcar_mipi_dsi_clr(dsi, CFGCLKSET, CFGCLKSET_CKEN);
456
457 /* LPCLK disable */
458 rcar_mipi_dsi_clr(dsi, LPCLKSET, LPCLKSET_CKEN);
459
460 dev_dbg(dsi->dev, "DSI device is shutdown\n");
461 }
462
rcar_mipi_dsi_clk_enable(struct rcar_mipi_dsi * dsi)463 static int rcar_mipi_dsi_clk_enable(struct rcar_mipi_dsi *dsi)
464 {
465 int ret;
466
467 reset_control_deassert(dsi->rstc);
468
469 ret = clk_prepare_enable(dsi->clocks.mod);
470 if (ret < 0)
471 goto err_reset;
472
473 ret = clk_prepare_enable(dsi->clocks.dsi);
474 if (ret < 0)
475 goto err_clock;
476
477 return 0;
478
479 err_clock:
480 clk_disable_unprepare(dsi->clocks.mod);
481 err_reset:
482 reset_control_assert(dsi->rstc);
483 return ret;
484 }
485
rcar_mipi_dsi_clk_disable(struct rcar_mipi_dsi * dsi)486 static void rcar_mipi_dsi_clk_disable(struct rcar_mipi_dsi *dsi)
487 {
488 clk_disable_unprepare(dsi->clocks.dsi);
489 clk_disable_unprepare(dsi->clocks.mod);
490
491 reset_control_assert(dsi->rstc);
492 }
493
rcar_mipi_dsi_start_hs_clock(struct rcar_mipi_dsi * dsi)494 static int rcar_mipi_dsi_start_hs_clock(struct rcar_mipi_dsi *dsi)
495 {
496 /*
497 * In HW manual, we need to check TxDDRClkHS-Q Stable? but it dont
498 * write how to check. So we skip this check in this patch
499 */
500 u32 status;
501 int ret;
502
503 /* Start HS clock. */
504 rcar_mipi_dsi_set(dsi, PPICLCR, PPICLCR_TXREQHS);
505
506 ret = read_poll_timeout(rcar_mipi_dsi_read, status,
507 status & PPICLSR_TOHS,
508 2000, 10000, false, dsi, PPICLSR);
509 if (ret < 0) {
510 dev_err(dsi->dev, "failed to enable HS clock\n");
511 return ret;
512 }
513
514 rcar_mipi_dsi_set(dsi, PPICLSCR, PPICLSCR_TOHS);
515
516 return 0;
517 }
518
rcar_mipi_dsi_start_video(struct rcar_mipi_dsi * dsi)519 static int rcar_mipi_dsi_start_video(struct rcar_mipi_dsi *dsi)
520 {
521 u32 status;
522 int ret;
523
524 /* Wait for the link to be ready. */
525 ret = read_poll_timeout(rcar_mipi_dsi_read, status,
526 !(status & (LINKSR_LPBUSY | LINKSR_HSBUSY)),
527 2000, 10000, false, dsi, LINKSR);
528 if (ret < 0) {
529 dev_err(dsi->dev, "Link failed to become ready\n");
530 return ret;
531 }
532
533 /* De-assert video FIFO clear. */
534 rcar_mipi_dsi_clr(dsi, TXVMCR, TXVMCR_VFCLR);
535
536 ret = read_poll_timeout(rcar_mipi_dsi_read, status,
537 status & TXVMSR_VFRDY,
538 2000, 10000, false, dsi, TXVMSR);
539 if (ret < 0) {
540 dev_err(dsi->dev, "Failed to de-assert video FIFO clear\n");
541 return ret;
542 }
543
544 /* Enable transmission in video mode. */
545 rcar_mipi_dsi_set(dsi, TXVMCR, TXVMCR_EN_VIDEO);
546
547 ret = read_poll_timeout(rcar_mipi_dsi_read, status,
548 status & TXVMSR_RDY,
549 2000, 10000, false, dsi, TXVMSR);
550 if (ret < 0) {
551 dev_err(dsi->dev, "Failed to enable video transmission\n");
552 return ret;
553 }
554
555 return 0;
556 }
557
rcar_mipi_dsi_stop_video(struct rcar_mipi_dsi * dsi)558 static void rcar_mipi_dsi_stop_video(struct rcar_mipi_dsi *dsi)
559 {
560 u32 status;
561 int ret;
562
563 /* Disable transmission in video mode. */
564 rcar_mipi_dsi_clr(dsi, TXVMCR, TXVMCR_EN_VIDEO);
565
566 ret = read_poll_timeout(rcar_mipi_dsi_read, status,
567 !(status & TXVMSR_ACT),
568 2000, 100000, false, dsi, TXVMSR);
569 if (ret < 0) {
570 dev_err(dsi->dev, "Failed to disable video transmission\n");
571 return;
572 }
573
574 /* Assert video FIFO clear. */
575 rcar_mipi_dsi_set(dsi, TXVMCR, TXVMCR_VFCLR);
576
577 ret = read_poll_timeout(rcar_mipi_dsi_read, status,
578 !(status & TXVMSR_VFRDY),
579 2000, 100000, false, dsi, TXVMSR);
580 if (ret < 0) {
581 dev_err(dsi->dev, "Failed to assert video FIFO clear\n");
582 return;
583 }
584 }
585
586 /* -----------------------------------------------------------------------------
587 * Bridge
588 */
589
rcar_mipi_dsi_attach(struct drm_bridge * bridge,enum drm_bridge_attach_flags flags)590 static int rcar_mipi_dsi_attach(struct drm_bridge *bridge,
591 enum drm_bridge_attach_flags flags)
592 {
593 struct rcar_mipi_dsi *dsi = bridge_to_rcar_mipi_dsi(bridge);
594
595 return drm_bridge_attach(bridge->encoder, dsi->next_bridge, bridge,
596 flags);
597 }
598
rcar_mipi_dsi_atomic_enable(struct drm_bridge * bridge,struct drm_bridge_state * old_bridge_state)599 static void rcar_mipi_dsi_atomic_enable(struct drm_bridge *bridge,
600 struct drm_bridge_state *old_bridge_state)
601 {
602 struct rcar_mipi_dsi *dsi = bridge_to_rcar_mipi_dsi(bridge);
603
604 rcar_mipi_dsi_start_video(dsi);
605 }
606
rcar_mipi_dsi_atomic_disable(struct drm_bridge * bridge,struct drm_bridge_state * old_bridge_state)607 static void rcar_mipi_dsi_atomic_disable(struct drm_bridge *bridge,
608 struct drm_bridge_state *old_bridge_state)
609 {
610 struct rcar_mipi_dsi *dsi = bridge_to_rcar_mipi_dsi(bridge);
611
612 rcar_mipi_dsi_stop_video(dsi);
613 }
614
rcar_mipi_dsi_pclk_enable(struct drm_bridge * bridge,struct drm_atomic_state * state)615 void rcar_mipi_dsi_pclk_enable(struct drm_bridge *bridge,
616 struct drm_atomic_state *state)
617 {
618 struct rcar_mipi_dsi *dsi = bridge_to_rcar_mipi_dsi(bridge);
619 const struct drm_display_mode *mode;
620 struct drm_connector *connector;
621 struct drm_crtc *crtc;
622 int ret;
623
624 connector = drm_atomic_get_new_connector_for_encoder(state,
625 bridge->encoder);
626 crtc = drm_atomic_get_new_connector_state(state, connector)->crtc;
627 mode = &drm_atomic_get_new_crtc_state(state, crtc)->adjusted_mode;
628
629 ret = rcar_mipi_dsi_clk_enable(dsi);
630 if (ret < 0) {
631 dev_err(dsi->dev, "failed to enable DSI clocks\n");
632 return;
633 }
634
635 ret = rcar_mipi_dsi_startup(dsi, mode);
636 if (ret < 0)
637 goto err_dsi_startup;
638
639 rcar_mipi_dsi_set_display_timing(dsi, mode);
640
641 ret = rcar_mipi_dsi_start_hs_clock(dsi);
642 if (ret < 0)
643 goto err_dsi_start_hs;
644
645 return;
646
647 err_dsi_start_hs:
648 rcar_mipi_dsi_shutdown(dsi);
649 err_dsi_startup:
650 rcar_mipi_dsi_clk_disable(dsi);
651 }
652 EXPORT_SYMBOL_GPL(rcar_mipi_dsi_pclk_enable);
653
rcar_mipi_dsi_pclk_disable(struct drm_bridge * bridge)654 void rcar_mipi_dsi_pclk_disable(struct drm_bridge *bridge)
655 {
656 struct rcar_mipi_dsi *dsi = bridge_to_rcar_mipi_dsi(bridge);
657
658 rcar_mipi_dsi_shutdown(dsi);
659 rcar_mipi_dsi_clk_disable(dsi);
660 }
661 EXPORT_SYMBOL_GPL(rcar_mipi_dsi_pclk_disable);
662
663 static enum drm_mode_status
rcar_mipi_dsi_bridge_mode_valid(struct drm_bridge * bridge,const struct drm_display_info * info,const struct drm_display_mode * mode)664 rcar_mipi_dsi_bridge_mode_valid(struct drm_bridge *bridge,
665 const struct drm_display_info *info,
666 const struct drm_display_mode *mode)
667 {
668 if (mode->clock > 297000)
669 return MODE_CLOCK_HIGH;
670
671 return MODE_OK;
672 }
673
674 static const struct drm_bridge_funcs rcar_mipi_dsi_bridge_ops = {
675 .attach = rcar_mipi_dsi_attach,
676 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
677 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
678 .atomic_reset = drm_atomic_helper_bridge_reset,
679 .atomic_enable = rcar_mipi_dsi_atomic_enable,
680 .atomic_disable = rcar_mipi_dsi_atomic_disable,
681 .mode_valid = rcar_mipi_dsi_bridge_mode_valid,
682 };
683
684 /* -----------------------------------------------------------------------------
685 * Host setting
686 */
687
rcar_mipi_dsi_host_attach(struct mipi_dsi_host * host,struct mipi_dsi_device * device)688 static int rcar_mipi_dsi_host_attach(struct mipi_dsi_host *host,
689 struct mipi_dsi_device *device)
690 {
691 struct rcar_mipi_dsi *dsi = host_to_rcar_mipi_dsi(host);
692 int ret;
693
694 if (device->lanes > dsi->num_data_lanes)
695 return -EINVAL;
696
697 dsi->lanes = device->lanes;
698 dsi->format = device->format;
699
700 dsi->next_bridge = devm_drm_of_get_bridge(dsi->dev, dsi->dev->of_node,
701 1, 0);
702 if (IS_ERR(dsi->next_bridge)) {
703 ret = PTR_ERR(dsi->next_bridge);
704 dev_err(dsi->dev, "failed to get next bridge: %d\n", ret);
705 return ret;
706 }
707
708 /* Initialize the DRM bridge. */
709 dsi->bridge.funcs = &rcar_mipi_dsi_bridge_ops;
710 dsi->bridge.of_node = dsi->dev->of_node;
711 drm_bridge_add(&dsi->bridge);
712
713 return 0;
714 }
715
rcar_mipi_dsi_host_detach(struct mipi_dsi_host * host,struct mipi_dsi_device * device)716 static int rcar_mipi_dsi_host_detach(struct mipi_dsi_host *host,
717 struct mipi_dsi_device *device)
718 {
719 struct rcar_mipi_dsi *dsi = host_to_rcar_mipi_dsi(host);
720
721 drm_bridge_remove(&dsi->bridge);
722
723 return 0;
724 }
725
726 static const struct mipi_dsi_host_ops rcar_mipi_dsi_host_ops = {
727 .attach = rcar_mipi_dsi_host_attach,
728 .detach = rcar_mipi_dsi_host_detach,
729 };
730
731 /* -----------------------------------------------------------------------------
732 * Probe & Remove
733 */
734
rcar_mipi_dsi_parse_dt(struct rcar_mipi_dsi * dsi)735 static int rcar_mipi_dsi_parse_dt(struct rcar_mipi_dsi *dsi)
736 {
737 int ret;
738
739 ret = drm_of_get_data_lanes_count_ep(dsi->dev->of_node, 1, 0, 1, 4);
740 if (ret < 0) {
741 dev_err(dsi->dev, "missing or invalid data-lanes property\n");
742 return ret;
743 }
744
745 dsi->num_data_lanes = ret;
746 return 0;
747 }
748
rcar_mipi_dsi_get_clock(struct rcar_mipi_dsi * dsi,const char * name,bool optional)749 static struct clk *rcar_mipi_dsi_get_clock(struct rcar_mipi_dsi *dsi,
750 const char *name,
751 bool optional)
752 {
753 struct clk *clk;
754
755 clk = devm_clk_get(dsi->dev, name);
756 if (!IS_ERR(clk))
757 return clk;
758
759 if (PTR_ERR(clk) == -ENOENT && optional)
760 return NULL;
761
762 dev_err_probe(dsi->dev, PTR_ERR(clk), "failed to get %s clock\n",
763 name ? name : "module");
764
765 return clk;
766 }
767
rcar_mipi_dsi_get_clocks(struct rcar_mipi_dsi * dsi)768 static int rcar_mipi_dsi_get_clocks(struct rcar_mipi_dsi *dsi)
769 {
770 dsi->clocks.mod = rcar_mipi_dsi_get_clock(dsi, NULL, false);
771 if (IS_ERR(dsi->clocks.mod))
772 return PTR_ERR(dsi->clocks.mod);
773
774 dsi->clocks.pll = rcar_mipi_dsi_get_clock(dsi, "pll", true);
775 if (IS_ERR(dsi->clocks.pll))
776 return PTR_ERR(dsi->clocks.pll);
777
778 dsi->clocks.dsi = rcar_mipi_dsi_get_clock(dsi, "dsi", true);
779 if (IS_ERR(dsi->clocks.dsi))
780 return PTR_ERR(dsi->clocks.dsi);
781
782 if (!dsi->clocks.pll && !dsi->clocks.dsi) {
783 dev_err(dsi->dev, "no input clock (pll, dsi)\n");
784 return -EINVAL;
785 }
786
787 return 0;
788 }
789
rcar_mipi_dsi_probe(struct platform_device * pdev)790 static int rcar_mipi_dsi_probe(struct platform_device *pdev)
791 {
792 struct rcar_mipi_dsi *dsi;
793 struct resource *mem;
794 int ret;
795
796 dsi = devm_kzalloc(&pdev->dev, sizeof(*dsi), GFP_KERNEL);
797 if (dsi == NULL)
798 return -ENOMEM;
799
800 platform_set_drvdata(pdev, dsi);
801
802 dsi->dev = &pdev->dev;
803 dsi->info = of_device_get_match_data(&pdev->dev);
804
805 ret = rcar_mipi_dsi_parse_dt(dsi);
806 if (ret < 0)
807 return ret;
808
809 /* Acquire resources. */
810 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
811 dsi->mmio = devm_ioremap_resource(dsi->dev, mem);
812 if (IS_ERR(dsi->mmio))
813 return PTR_ERR(dsi->mmio);
814
815 ret = rcar_mipi_dsi_get_clocks(dsi);
816 if (ret < 0)
817 return ret;
818
819 dsi->rstc = devm_reset_control_get(dsi->dev, NULL);
820 if (IS_ERR(dsi->rstc)) {
821 dev_err(dsi->dev, "failed to get cpg reset\n");
822 return PTR_ERR(dsi->rstc);
823 }
824
825 /* Initialize the DSI host. */
826 dsi->host.dev = dsi->dev;
827 dsi->host.ops = &rcar_mipi_dsi_host_ops;
828 ret = mipi_dsi_host_register(&dsi->host);
829 if (ret < 0)
830 return ret;
831
832 return 0;
833 }
834
rcar_mipi_dsi_remove(struct platform_device * pdev)835 static int rcar_mipi_dsi_remove(struct platform_device *pdev)
836 {
837 struct rcar_mipi_dsi *dsi = platform_get_drvdata(pdev);
838
839 mipi_dsi_host_unregister(&dsi->host);
840
841 return 0;
842 }
843
844 static const struct of_device_id rcar_mipi_dsi_of_table[] = {
845 { .compatible = "renesas,r8a779a0-dsi-csi2-tx" },
846 { }
847 };
848
849 MODULE_DEVICE_TABLE(of, rcar_mipi_dsi_of_table);
850
851 static struct platform_driver rcar_mipi_dsi_platform_driver = {
852 .probe = rcar_mipi_dsi_probe,
853 .remove = rcar_mipi_dsi_remove,
854 .driver = {
855 .name = "rcar-mipi-dsi",
856 .of_match_table = rcar_mipi_dsi_of_table,
857 },
858 };
859
860 module_platform_driver(rcar_mipi_dsi_platform_driver);
861
862 MODULE_DESCRIPTION("Renesas R-Car MIPI DSI Encoder Driver");
863 MODULE_LICENSE("GPL");
864
