1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2 # Copyright (C) 2020 SiFive, Inc.
3 %YAML 1.2
4 ---
5 $id: http://devicetree.org/schemas/interrupt-controller/sifive,plic-1.0.0.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 
8 title: SiFive Platform-Level Interrupt Controller (PLIC)
9 
10 description:
11   SiFive SoCs and other RISC-V SoCs include an implementation of the
12   Platform-Level Interrupt Controller (PLIC) high-level specification in
13   the RISC-V Privileged Architecture specification. The PLIC connects all
14   external interrupts in the system to all hart contexts in the system, via
15   the external interrupt source in each hart.
16 
17   A hart context is a privilege mode in a hardware execution thread. For example,
18   in an 4 core system with 2-way SMT, you have 8 harts and probably at least two
19   privilege modes per hart; machine mode and supervisor mode.
20 
21   Each interrupt can be enabled on per-context basis. Any context can claim
22   a pending enabled interrupt and then release it once it has been handled.
23 
24   Each interrupt has a configurable priority. Higher priority interrupts are
25   serviced first.  Each context can specify a priority threshold. Interrupts
26   with priority below this threshold will not cause the PLIC to raise its
27   interrupt line leading to the context.
28 
29   The PLIC supports both edge-triggered and level-triggered interrupts. For
30   edge-triggered interrupts, the RISC-V PLIC spec allows two responses to edges
31   seen while an interrupt handler is active; the PLIC may either queue them or
32   ignore them. In the first case, handlers are oblivious to the trigger type, so
33   it is not included in the interrupt specifier. In the second case, software
34   needs to know the trigger type, so it can reorder the interrupt flow to avoid
35   missing interrupts. This special handling is needed by at least the Renesas
36   RZ/Five SoC (AX45MP AndesCore with a NCEPLIC100) and the T-HEAD C900 PLIC.
37 
38   While the RISC-V ISA doesn't specify a memory layout for the PLIC, the
39   "sifive,plic-1.0.0" device is a concrete implementation of the PLIC that
40   contains a specific memory layout, which is documented in chapter 8 of the
41   SiFive U5 Coreplex Series Manual <https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf>.
42 
43   The thead,c900-plic is different from sifive,plic-1.0.0 in opensbi, the
44   T-HEAD PLIC implementation requires setting a delegation bit to allow access
45   from S-mode. So add thead,c900-plic to distinguish them.
46 
47 maintainers:
48   - Sagar Kadam <sagar.kadam@sifive.com>
49   - Paul Walmsley  <paul.walmsley@sifive.com>
50   - Palmer Dabbelt <palmer@dabbelt.com>
51 
52 properties:
53   compatible:
54     oneOf:
55       - items:
56           - enum:
57               - renesas,r9a07g043-plic
58           - const: andestech,nceplic100
59       - items:
60           - enum:
61               - sifive,fu540-c000-plic
62               - starfive,jh7100-plic
63               - canaan,k210-plic
64           - const: sifive,plic-1.0.0
65       - items:
66           - enum:
67               - allwinner,sun20i-d1-plic
68           - const: thead,c900-plic
69       - items:
70           - const: sifive,plic-1.0.0
71           - const: riscv,plic0
72         deprecated: true
73         description: For the QEMU virt machine only
74 
75   reg:
76     maxItems: 1
77 
78   '#address-cells':
79     const: 0
80 
81   '#interrupt-cells': true
82 
83   interrupt-controller: true
84 
85   interrupts-extended:
86     minItems: 1
87     maxItems: 15872
88     description:
89       Specifies which contexts are connected to the PLIC, with "-1" specifying
90       that a context is not present. Each node pointed to should be a
91       riscv,cpu-intc node, which has a riscv node as parent.
92 
93   riscv,ndev:
94     $ref: "/schemas/types.yaml#/definitions/uint32"
95     description:
96       Specifies how many external interrupts are supported by this controller.
97 
98   clocks: true
99 
100   power-domains: true
101 
102   resets: true
103 
104 required:
105   - compatible
106   - '#address-cells'
107   - '#interrupt-cells'
108   - interrupt-controller
109   - reg
110   - interrupts-extended
111   - riscv,ndev
112 
113 allOf:
114   - if:
115       properties:
116         compatible:
117           contains:
118             enum:
119               - andestech,nceplic100
120               - thead,c900-plic
121 
122     then:
123       properties:
124         '#interrupt-cells':
125           const: 2
126 
127     else:
128       properties:
129         '#interrupt-cells':
130           const: 1
131 
132   - if:
133       properties:
134         compatible:
135           contains:
136             const: renesas,r9a07g043-plic
137 
138     then:
139       properties:
140         clocks:
141           maxItems: 1
142 
143         power-domains:
144           maxItems: 1
145 
146         resets:
147           maxItems: 1
148 
149       required:
150         - clocks
151         - power-domains
152         - resets
153 
154 additionalProperties: false
155 
156 examples:
157   - |
158     plic: interrupt-controller@c000000 {
159       #address-cells = <0>;
160       #interrupt-cells = <1>;
161       compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
162       interrupt-controller;
163       interrupts-extended = <&cpu0_intc 11>,
164                             <&cpu1_intc 11>, <&cpu1_intc 9>,
165                             <&cpu2_intc 11>, <&cpu2_intc 9>,
166                             <&cpu3_intc 11>, <&cpu3_intc 9>,
167                             <&cpu4_intc 11>, <&cpu4_intc 9>;
168       reg = <0xc000000 0x4000000>;
169       riscv,ndev = <10>;
170     };
171