1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
2 //
3 // This file is provided under a dual BSD/GPLv2 license. When using or
4 // redistributing this file, you may do so under either license.
5 //
6 // Copyright(c) 2018 Intel Corporation. All rights reserved.
7 //
8 // Authors: Liam Girdwood <liam.r.girdwood@linux.intel.com>
9 // Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
10 // Rander Wang <rander.wang@intel.com>
11 // Keyon Jie <yang.jie@linux.intel.com>
12 //
13
14 /*
15 * Hardware interface for HDA DSP code loader
16 */
17
18 #include <linux/firmware.h>
19 #include <sound/hdaudio_ext.h>
20 #include <sound/sof.h>
21 #include "../ops.h"
22 #include "hda.h"
23
24 #define HDA_FW_BOOT_ATTEMPTS 3
25
cl_stream_prepare(struct snd_sof_dev * sdev,unsigned int format,unsigned int size,struct snd_dma_buffer * dmab,int direction)26 static int cl_stream_prepare(struct snd_sof_dev *sdev, unsigned int format,
27 unsigned int size, struct snd_dma_buffer *dmab,
28 int direction)
29 {
30 struct hdac_ext_stream *dsp_stream;
31 struct hdac_stream *hstream;
32 struct pci_dev *pci = to_pci_dev(sdev->dev);
33 int ret;
34
35 if (direction != SNDRV_PCM_STREAM_PLAYBACK) {
36 dev_err(sdev->dev, "error: code loading DMA is playback only\n");
37 return -EINVAL;
38 }
39
40 dsp_stream = hda_dsp_stream_get(sdev, direction);
41
42 if (!dsp_stream) {
43 dev_err(sdev->dev, "error: no stream available\n");
44 return -ENODEV;
45 }
46 hstream = &dsp_stream->hstream;
47 hstream->substream = NULL;
48
49 /* allocate DMA buffer */
50 ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV_SG, &pci->dev, size, dmab);
51 if (ret < 0) {
52 dev_err(sdev->dev, "error: memory alloc failed: %x\n", ret);
53 goto error;
54 }
55
56 hstream->period_bytes = 0;/* initialize period_bytes */
57 hstream->format_val = format;
58 hstream->bufsize = size;
59
60 ret = hda_dsp_stream_hw_params(sdev, dsp_stream, dmab, NULL);
61 if (ret < 0) {
62 dev_err(sdev->dev, "error: hdac prepare failed: %x\n", ret);
63 goto error;
64 }
65
66 hda_dsp_stream_spib_config(sdev, dsp_stream, HDA_DSP_SPIB_ENABLE, size);
67
68 return hstream->stream_tag;
69
70 error:
71 hda_dsp_stream_put(sdev, direction, hstream->stream_tag);
72 snd_dma_free_pages(dmab);
73 return ret;
74 }
75
76 /*
77 * first boot sequence has some extra steps. core 0 waits for power
78 * status on core 1, so power up core 1 also momentarily, keep it in
79 * reset/stall and then turn it off
80 */
cl_dsp_init(struct snd_sof_dev * sdev,const void * fwdata,u32 fwsize,int stream_tag)81 static int cl_dsp_init(struct snd_sof_dev *sdev, const void *fwdata,
82 u32 fwsize, int stream_tag)
83 {
84 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
85 const struct sof_intel_dsp_desc *chip = hda->desc;
86 unsigned int status;
87 int ret;
88 int i;
89
90 /* step 1: power up corex */
91 ret = hda_dsp_core_power_up(sdev, chip->cores_mask);
92 if (ret < 0) {
93 dev_err(sdev->dev, "error: dsp core 0/1 power up failed\n");
94 goto err;
95 }
96
97 /* DSP is powered up, set all SSPs to slave mode */
98 for (i = 0; i < chip->ssp_count; i++) {
99 snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR,
100 chip->ssp_base_offset
101 + i * SSP_DEV_MEM_SIZE
102 + SSP_SSC1_OFFSET,
103 SSP_SET_SLAVE,
104 SSP_SET_SLAVE);
105 }
106
107 /* step 2: purge FW request */
108 snd_sof_dsp_write(sdev, HDA_DSP_BAR, chip->ipc_req,
109 chip->ipc_req_mask | (HDA_DSP_IPC_PURGE_FW |
110 ((stream_tag - 1) << 9)));
111
112 /* step 3: unset core 0 reset state & unstall/run core 0 */
113 ret = hda_dsp_core_run(sdev, HDA_DSP_CORE_MASK(0));
114 if (ret < 0) {
115 dev_err(sdev->dev, "error: dsp core start failed %d\n", ret);
116 ret = -EIO;
117 goto err;
118 }
119
120 /* step 4: wait for IPC DONE bit from ROM */
121 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR,
122 chip->ipc_ack, status,
123 ((status & chip->ipc_ack_mask)
124 == chip->ipc_ack_mask),
125 HDA_DSP_REG_POLL_INTERVAL_US,
126 HDA_DSP_INIT_TIMEOUT_US);
127
128 if (ret < 0) {
129 dev_err(sdev->dev, "error: waiting for HIPCIE done\n");
130 goto err;
131 }
132
133 /* step 5: power down corex */
134 ret = hda_dsp_core_power_down(sdev,
135 chip->cores_mask & ~(HDA_DSP_CORE_MASK(0)));
136 if (ret < 0) {
137 dev_err(sdev->dev, "error: dsp core x power down failed\n");
138 goto err;
139 }
140
141 /* step 6: enable IPC interrupts */
142 hda_dsp_ipc_int_enable(sdev);
143
144 /* step 7: wait for ROM init */
145 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR,
146 HDA_DSP_SRAM_REG_ROM_STATUS, status,
147 ((status & HDA_DSP_ROM_STS_MASK)
148 == HDA_DSP_ROM_INIT),
149 HDA_DSP_REG_POLL_INTERVAL_US,
150 chip->rom_init_timeout *
151 USEC_PER_MSEC);
152 if (!ret)
153 return 0;
154
155 err:
156 hda_dsp_dump(sdev, SOF_DBG_REGS | SOF_DBG_PCI | SOF_DBG_MBOX);
157 hda_dsp_core_reset_power_down(sdev, chip->cores_mask);
158
159 return ret;
160 }
161
cl_trigger(struct snd_sof_dev * sdev,struct hdac_ext_stream * stream,int cmd)162 static int cl_trigger(struct snd_sof_dev *sdev,
163 struct hdac_ext_stream *stream, int cmd)
164 {
165 struct hdac_stream *hstream = &stream->hstream;
166 int sd_offset = SOF_STREAM_SD_OFFSET(hstream);
167
168 /* code loader is special case that reuses stream ops */
169 switch (cmd) {
170 case SNDRV_PCM_TRIGGER_START:
171 wait_event_timeout(sdev->waitq, !sdev->code_loading,
172 HDA_DSP_CL_TRIGGER_TIMEOUT);
173
174 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL,
175 1 << hstream->index,
176 1 << hstream->index);
177
178 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
179 sd_offset,
180 SOF_HDA_SD_CTL_DMA_START |
181 SOF_HDA_CL_DMA_SD_INT_MASK,
182 SOF_HDA_SD_CTL_DMA_START |
183 SOF_HDA_CL_DMA_SD_INT_MASK);
184
185 hstream->running = true;
186 return 0;
187 default:
188 return hda_dsp_stream_trigger(sdev, stream, cmd);
189 }
190 }
191
get_stream_with_tag(struct snd_sof_dev * sdev,int tag)192 static struct hdac_ext_stream *get_stream_with_tag(struct snd_sof_dev *sdev,
193 int tag)
194 {
195 struct hdac_bus *bus = sof_to_bus(sdev);
196 struct hdac_stream *s;
197
198 /* get stream with tag */
199 list_for_each_entry(s, &bus->stream_list, list) {
200 if (s->direction == SNDRV_PCM_STREAM_PLAYBACK &&
201 s->stream_tag == tag) {
202 return stream_to_hdac_ext_stream(s);
203 }
204 }
205
206 return NULL;
207 }
208
cl_cleanup(struct snd_sof_dev * sdev,struct snd_dma_buffer * dmab,struct hdac_ext_stream * stream)209 static int cl_cleanup(struct snd_sof_dev *sdev, struct snd_dma_buffer *dmab,
210 struct hdac_ext_stream *stream)
211 {
212 struct hdac_stream *hstream = &stream->hstream;
213 int sd_offset = SOF_STREAM_SD_OFFSET(hstream);
214 int ret;
215
216 ret = hda_dsp_stream_spib_config(sdev, stream, HDA_DSP_SPIB_DISABLE, 0);
217
218 hda_dsp_stream_put(sdev, SNDRV_PCM_STREAM_PLAYBACK,
219 hstream->stream_tag);
220 hstream->running = 0;
221 hstream->substream = NULL;
222
223 /* reset BDL address */
224 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
225 sd_offset + SOF_HDA_ADSP_REG_CL_SD_BDLPL, 0);
226 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
227 sd_offset + SOF_HDA_ADSP_REG_CL_SD_BDLPU, 0);
228
229 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, sd_offset, 0);
230 snd_dma_free_pages(dmab);
231 dmab->area = NULL;
232 hstream->bufsize = 0;
233 hstream->format_val = 0;
234
235 return ret;
236 }
237
cl_copy_fw(struct snd_sof_dev * sdev,struct hdac_ext_stream * stream)238 static int cl_copy_fw(struct snd_sof_dev *sdev, struct hdac_ext_stream *stream)
239 {
240 unsigned int reg;
241 int ret, status;
242
243 ret = cl_trigger(sdev, stream, SNDRV_PCM_TRIGGER_START);
244 if (ret < 0) {
245 dev_err(sdev->dev, "error: DMA trigger start failed\n");
246 return ret;
247 }
248
249 status = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR,
250 HDA_DSP_SRAM_REG_ROM_STATUS, reg,
251 ((reg & HDA_DSP_ROM_STS_MASK)
252 == HDA_DSP_ROM_FW_ENTERED),
253 HDA_DSP_REG_POLL_INTERVAL_US,
254 HDA_DSP_BASEFW_TIMEOUT_US);
255
256 ret = cl_trigger(sdev, stream, SNDRV_PCM_TRIGGER_STOP);
257 if (ret < 0) {
258 dev_err(sdev->dev, "error: DMA trigger stop failed\n");
259 return ret;
260 }
261
262 return status;
263 }
264
hda_dsp_cl_boot_firmware(struct snd_sof_dev * sdev)265 int hda_dsp_cl_boot_firmware(struct snd_sof_dev *sdev)
266 {
267 struct snd_sof_pdata *plat_data = sdev->pdata;
268 const struct sof_dev_desc *desc = plat_data->desc;
269 const struct sof_intel_dsp_desc *chip_info;
270 struct hdac_ext_stream *stream;
271 struct firmware stripped_firmware;
272 int ret, ret1, tag, i;
273
274 chip_info = desc->chip_info;
275
276 stripped_firmware.data = plat_data->fw->data;
277 stripped_firmware.size = plat_data->fw->size;
278
279 /* init for booting wait */
280 init_waitqueue_head(&sdev->boot_wait);
281 sdev->boot_complete = false;
282
283 /* prepare DMA for code loader stream */
284 tag = cl_stream_prepare(sdev, 0x40, stripped_firmware.size,
285 &sdev->dmab, SNDRV_PCM_STREAM_PLAYBACK);
286
287 if (tag < 0) {
288 dev_err(sdev->dev, "error: dma prepare for fw loading err: %x\n",
289 tag);
290 return tag;
291 }
292
293 /* get stream with tag */
294 stream = get_stream_with_tag(sdev, tag);
295 if (!stream) {
296 dev_err(sdev->dev,
297 "error: could not get stream with stream tag %d\n",
298 tag);
299 ret = -ENODEV;
300 goto err;
301 }
302
303 memcpy(sdev->dmab.area, stripped_firmware.data,
304 stripped_firmware.size);
305
306 /* try ROM init a few times before giving up */
307 for (i = 0; i < HDA_FW_BOOT_ATTEMPTS; i++) {
308 ret = cl_dsp_init(sdev, stripped_firmware.data,
309 stripped_firmware.size, tag);
310
311 /* don't retry anymore if successful */
312 if (!ret)
313 break;
314
315 dev_err(sdev->dev, "error: Error code=0x%x: FW status=0x%x\n",
316 snd_sof_dsp_read(sdev, HDA_DSP_BAR,
317 HDA_DSP_SRAM_REG_ROM_ERROR),
318 snd_sof_dsp_read(sdev, HDA_DSP_BAR,
319 HDA_DSP_SRAM_REG_ROM_STATUS));
320 dev_err(sdev->dev, "error: iteration %d of Core En/ROM load failed: %d\n",
321 i, ret);
322 }
323
324 if (i == HDA_FW_BOOT_ATTEMPTS) {
325 dev_err(sdev->dev, "error: dsp init failed after %d attempts with err: %d\n",
326 i, ret);
327 goto cleanup;
328 }
329
330 /*
331 * at this point DSP ROM has been initialized and
332 * should be ready for code loading and firmware boot
333 */
334 ret = cl_copy_fw(sdev, stream);
335 if (!ret)
336 dev_dbg(sdev->dev, "Firmware download successful, booting...\n");
337 else
338 dev_err(sdev->dev, "error: load fw failed ret: %d\n", ret);
339
340 cleanup:
341 /*
342 * Perform codeloader stream cleanup.
343 * This should be done even if firmware loading fails.
344 */
345 ret1 = cl_cleanup(sdev, &sdev->dmab, stream);
346 if (ret1 < 0) {
347 dev_err(sdev->dev, "error: Code loader DSP cleanup failed\n");
348
349 /* set return value to indicate cleanup failure */
350 ret = ret1;
351 }
352
353 /*
354 * return master core id if both fw copy
355 * and stream clean up are successful
356 */
357 if (!ret)
358 return chip_info->init_core_mask;
359
360 /* dump dsp registers and disable DSP upon error */
361 err:
362 hda_dsp_dump(sdev, SOF_DBG_REGS | SOF_DBG_PCI | SOF_DBG_MBOX);
363
364 /* disable DSP */
365 snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR,
366 SOF_HDA_REG_PP_PPCTL,
367 SOF_HDA_PPCTL_GPROCEN, 0);
368 return ret;
369 }
370
371 /* pre fw run operations */
hda_dsp_pre_fw_run(struct snd_sof_dev * sdev)372 int hda_dsp_pre_fw_run(struct snd_sof_dev *sdev)
373 {
374 /* disable clock gating and power gating */
375 return hda_dsp_ctrl_clock_power_gating(sdev, false);
376 }
377
378 /* post fw run operations */
hda_dsp_post_fw_run(struct snd_sof_dev * sdev)379 int hda_dsp_post_fw_run(struct snd_sof_dev *sdev)
380 {
381 /* re-enable clock gating and power gating */
382 return hda_dsp_ctrl_clock_power_gating(sdev, true);
383 }
384
