1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * 10G controller driver for Samsung EXYNOS SoCs
4  *
5  * Copyright (C) 2013 Samsung Electronics Co., Ltd.
6  *		http://www.samsung.com
7  *
8  * Author: Siva Reddy Kallam <siva.kallam@samsung.com>
9  */
10 #ifndef __SXGBE_PLATFORM_H__
11 #define __SXGBE_PLATFORM_H__
12 
13 /* MDC Clock Selection define*/
14 #define SXGBE_CSR_100_150M	0x0	/* MDC = clk_scr_i/62 */
15 #define SXGBE_CSR_150_250M	0x1	/* MDC = clk_scr_i/102 */
16 #define SXGBE_CSR_250_300M	0x2	/* MDC = clk_scr_i/122 */
17 #define SXGBE_CSR_300_350M	0x3	/* MDC = clk_scr_i/142 */
18 #define SXGBE_CSR_350_400M	0x4	/* MDC = clk_scr_i/162 */
19 #define SXGBE_CSR_400_500M	0x5	/* MDC = clk_scr_i/202 */
20 
21 /* Platfrom data for platform device structure's
22  * platform_data field
23  */
24 struct sxgbe_mdio_bus_data {
25 	unsigned int phy_mask;
26 	int *irqs;
27 	int probed_phy_irq;
28 };
29 
30 struct sxgbe_dma_cfg {
31 	int pbl;
32 	int fixed_burst;
33 	int burst_map;
34 	int adv_addr_mode;
35 };
36 
37 struct sxgbe_plat_data {
38 	char *phy_bus_name;
39 	int bus_id;
40 	int phy_addr;
41 	int interface;
42 	struct sxgbe_mdio_bus_data *mdio_bus_data;
43 	struct sxgbe_dma_cfg *dma_cfg;
44 	int clk_csr;
45 	int pmt;
46 	int force_sf_dma_mode;
47 	int force_thresh_dma_mode;
48 	int riwt_off;
49 };
50 
51 #endif /* __SXGBE_PLATFORM_H__ */
52