1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef MLX5_DRIVER_H 34 #define MLX5_DRIVER_H 35 36 #include <linux/kernel.h> 37 #include <linux/completion.h> 38 #include <linux/pci.h> 39 #include <linux/irq.h> 40 #include <linux/spinlock_types.h> 41 #include <linux/semaphore.h> 42 #include <linux/slab.h> 43 #include <linux/vmalloc.h> 44 #include <linux/xarray.h> 45 #include <linux/workqueue.h> 46 #include <linux/mempool.h> 47 #include <linux/interrupt.h> 48 #include <linux/idr.h> 49 #include <linux/notifier.h> 50 #include <linux/refcount.h> 51 52 #include <linux/mlx5/device.h> 53 #include <linux/mlx5/doorbell.h> 54 #include <linux/mlx5/eq.h> 55 #include <linux/timecounter.h> 56 #include <linux/ptp_clock_kernel.h> 57 #include <net/devlink.h> 58 59 enum { 60 MLX5_BOARD_ID_LEN = 64, 61 }; 62 63 enum { 64 /* one minute for the sake of bringup. Generally, commands must always 65 * complete and we may need to increase this timeout value 66 */ 67 MLX5_CMD_TIMEOUT_MSEC = 60 * 1000, 68 MLX5_CMD_WQ_MAX_NAME = 32, 69 }; 70 71 enum { 72 CMD_OWNER_SW = 0x0, 73 CMD_OWNER_HW = 0x1, 74 CMD_STATUS_SUCCESS = 0, 75 }; 76 77 enum mlx5_sqp_t { 78 MLX5_SQP_SMI = 0, 79 MLX5_SQP_GSI = 1, 80 MLX5_SQP_IEEE_1588 = 2, 81 MLX5_SQP_SNIFFER = 3, 82 MLX5_SQP_SYNC_UMR = 4, 83 }; 84 85 enum { 86 MLX5_MAX_PORTS = 2, 87 }; 88 89 enum { 90 MLX5_ATOMIC_MODE_OFFSET = 16, 91 MLX5_ATOMIC_MODE_IB_COMP = 1, 92 MLX5_ATOMIC_MODE_CX = 2, 93 MLX5_ATOMIC_MODE_8B = 3, 94 MLX5_ATOMIC_MODE_16B = 4, 95 MLX5_ATOMIC_MODE_32B = 5, 96 MLX5_ATOMIC_MODE_64B = 6, 97 MLX5_ATOMIC_MODE_128B = 7, 98 MLX5_ATOMIC_MODE_256B = 8, 99 }; 100 101 enum { 102 MLX5_REG_QPTS = 0x4002, 103 MLX5_REG_QETCR = 0x4005, 104 MLX5_REG_QTCT = 0x400a, 105 MLX5_REG_QPDPM = 0x4013, 106 MLX5_REG_QCAM = 0x4019, 107 MLX5_REG_DCBX_PARAM = 0x4020, 108 MLX5_REG_DCBX_APP = 0x4021, 109 MLX5_REG_FPGA_CAP = 0x4022, 110 MLX5_REG_FPGA_CTRL = 0x4023, 111 MLX5_REG_FPGA_ACCESS_REG = 0x4024, 112 MLX5_REG_CORE_DUMP = 0x402e, 113 MLX5_REG_PCAP = 0x5001, 114 MLX5_REG_PMTU = 0x5003, 115 MLX5_REG_PTYS = 0x5004, 116 MLX5_REG_PAOS = 0x5006, 117 MLX5_REG_PFCC = 0x5007, 118 MLX5_REG_PPCNT = 0x5008, 119 MLX5_REG_PPTB = 0x500b, 120 MLX5_REG_PBMC = 0x500c, 121 MLX5_REG_PMAOS = 0x5012, 122 MLX5_REG_PUDE = 0x5009, 123 MLX5_REG_PMPE = 0x5010, 124 MLX5_REG_PELC = 0x500e, 125 MLX5_REG_PVLC = 0x500f, 126 MLX5_REG_PCMR = 0x5041, 127 MLX5_REG_PMLP = 0x5002, 128 MLX5_REG_PPLM = 0x5023, 129 MLX5_REG_PCAM = 0x507f, 130 MLX5_REG_NODE_DESC = 0x6001, 131 MLX5_REG_HOST_ENDIANNESS = 0x7004, 132 MLX5_REG_MCIA = 0x9014, 133 MLX5_REG_MLCR = 0x902b, 134 MLX5_REG_MTRC_CAP = 0x9040, 135 MLX5_REG_MTRC_CONF = 0x9041, 136 MLX5_REG_MTRC_STDB = 0x9042, 137 MLX5_REG_MTRC_CTRL = 0x9043, 138 MLX5_REG_MPEIN = 0x9050, 139 MLX5_REG_MPCNT = 0x9051, 140 MLX5_REG_MTPPS = 0x9053, 141 MLX5_REG_MTPPSE = 0x9054, 142 MLX5_REG_MPEGC = 0x9056, 143 MLX5_REG_MCQS = 0x9060, 144 MLX5_REG_MCQI = 0x9061, 145 MLX5_REG_MCC = 0x9062, 146 MLX5_REG_MCDA = 0x9063, 147 MLX5_REG_MCAM = 0x907f, 148 }; 149 150 enum mlx5_qpts_trust_state { 151 MLX5_QPTS_TRUST_PCP = 1, 152 MLX5_QPTS_TRUST_DSCP = 2, 153 }; 154 155 enum mlx5_dcbx_oper_mode { 156 MLX5E_DCBX_PARAM_VER_OPER_HOST = 0x0, 157 MLX5E_DCBX_PARAM_VER_OPER_AUTO = 0x3, 158 }; 159 160 enum { 161 MLX5_ATOMIC_OPS_CMP_SWAP = 1 << 0, 162 MLX5_ATOMIC_OPS_FETCH_ADD = 1 << 1, 163 MLX5_ATOMIC_OPS_EXTENDED_CMP_SWAP = 1 << 2, 164 MLX5_ATOMIC_OPS_EXTENDED_FETCH_ADD = 1 << 3, 165 }; 166 167 enum mlx5_page_fault_resume_flags { 168 MLX5_PAGE_FAULT_RESUME_REQUESTOR = 1 << 0, 169 MLX5_PAGE_FAULT_RESUME_WRITE = 1 << 1, 170 MLX5_PAGE_FAULT_RESUME_RDMA = 1 << 2, 171 MLX5_PAGE_FAULT_RESUME_ERROR = 1 << 7, 172 }; 173 174 enum dbg_rsc_type { 175 MLX5_DBG_RSC_QP, 176 MLX5_DBG_RSC_EQ, 177 MLX5_DBG_RSC_CQ, 178 }; 179 180 enum port_state_policy { 181 MLX5_POLICY_DOWN = 0, 182 MLX5_POLICY_UP = 1, 183 MLX5_POLICY_FOLLOW = 2, 184 MLX5_POLICY_INVALID = 0xffffffff 185 }; 186 187 enum mlx5_coredev_type { 188 MLX5_COREDEV_PF, 189 MLX5_COREDEV_VF 190 }; 191 192 struct mlx5_field_desc { 193 int i; 194 }; 195 196 struct mlx5_rsc_debug { 197 struct mlx5_core_dev *dev; 198 void *object; 199 enum dbg_rsc_type type; 200 struct dentry *root; 201 struct mlx5_field_desc fields[0]; 202 }; 203 204 enum mlx5_dev_event { 205 MLX5_DEV_EVENT_SYS_ERROR = 128, /* 0 - 127 are FW events */ 206 MLX5_DEV_EVENT_PORT_AFFINITY = 129, 207 }; 208 209 enum mlx5_port_status { 210 MLX5_PORT_UP = 1, 211 MLX5_PORT_DOWN = 2, 212 }; 213 214 struct mlx5_bfreg_info { 215 u32 *sys_pages; 216 int num_low_latency_bfregs; 217 unsigned int *count; 218 219 /* 220 * protect bfreg allocation data structs 221 */ 222 struct mutex lock; 223 u32 ver; 224 bool lib_uar_4k; 225 u32 num_sys_pages; 226 u32 num_static_sys_pages; 227 u32 total_num_bfregs; 228 u32 num_dyn_bfregs; 229 }; 230 231 struct mlx5_cmd_first { 232 __be32 data[4]; 233 }; 234 235 struct mlx5_cmd_msg { 236 struct list_head list; 237 struct cmd_msg_cache *parent; 238 u32 len; 239 struct mlx5_cmd_first first; 240 struct mlx5_cmd_mailbox *next; 241 }; 242 243 struct mlx5_cmd_debug { 244 struct dentry *dbg_root; 245 void *in_msg; 246 void *out_msg; 247 u8 status; 248 u16 inlen; 249 u16 outlen; 250 }; 251 252 struct cmd_msg_cache { 253 /* protect block chain allocations 254 */ 255 spinlock_t lock; 256 struct list_head head; 257 unsigned int max_inbox_size; 258 unsigned int num_ent; 259 }; 260 261 enum { 262 MLX5_NUM_COMMAND_CACHES = 5, 263 }; 264 265 struct mlx5_cmd_stats { 266 u64 sum; 267 u64 n; 268 struct dentry *root; 269 /* protect command average calculations */ 270 spinlock_t lock; 271 }; 272 273 struct mlx5_cmd { 274 struct mlx5_nb nb; 275 276 void *cmd_alloc_buf; 277 dma_addr_t alloc_dma; 278 int alloc_size; 279 void *cmd_buf; 280 dma_addr_t dma; 281 u16 cmdif_rev; 282 u8 log_sz; 283 u8 log_stride; 284 int max_reg_cmds; 285 int events; 286 u32 __iomem *vector; 287 288 /* protect command queue allocations 289 */ 290 spinlock_t alloc_lock; 291 292 /* protect token allocations 293 */ 294 spinlock_t token_lock; 295 u8 token; 296 unsigned long bitmask; 297 char wq_name[MLX5_CMD_WQ_MAX_NAME]; 298 struct workqueue_struct *wq; 299 struct semaphore sem; 300 struct semaphore pages_sem; 301 int mode; 302 struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS]; 303 struct dma_pool *pool; 304 struct mlx5_cmd_debug dbg; 305 struct cmd_msg_cache cache[MLX5_NUM_COMMAND_CACHES]; 306 int checksum_disabled; 307 struct mlx5_cmd_stats stats[MLX5_CMD_OP_MAX]; 308 }; 309 310 struct mlx5_port_caps { 311 int gid_table_len; 312 int pkey_table_len; 313 u8 ext_port_cap; 314 bool has_smi; 315 }; 316 317 struct mlx5_cmd_mailbox { 318 void *buf; 319 dma_addr_t dma; 320 struct mlx5_cmd_mailbox *next; 321 }; 322 323 struct mlx5_buf_list { 324 void *buf; 325 dma_addr_t map; 326 }; 327 328 struct mlx5_frag_buf { 329 struct mlx5_buf_list *frags; 330 int npages; 331 int size; 332 u8 page_shift; 333 }; 334 335 struct mlx5_frag_buf_ctrl { 336 struct mlx5_buf_list *frags; 337 u32 sz_m1; 338 u16 frag_sz_m1; 339 u16 strides_offset; 340 u8 log_sz; 341 u8 log_stride; 342 u8 log_frag_strides; 343 }; 344 345 struct mlx5_core_psv { 346 u32 psv_idx; 347 struct psv_layout { 348 u32 pd; 349 u16 syndrome; 350 u16 reserved; 351 u16 bg; 352 u16 app_tag; 353 u32 ref_tag; 354 } psv; 355 }; 356 357 struct mlx5_core_sig_ctx { 358 struct mlx5_core_psv psv_memory; 359 struct mlx5_core_psv psv_wire; 360 struct ib_sig_err err_item; 361 bool sig_status_checked; 362 bool sig_err_exists; 363 u32 sigerr_count; 364 }; 365 366 enum { 367 MLX5_MKEY_MR = 1, 368 MLX5_MKEY_MW, 369 MLX5_MKEY_INDIRECT_DEVX, 370 }; 371 372 struct mlx5_core_mkey { 373 u64 iova; 374 u64 size; 375 u32 key; 376 u32 pd; 377 u32 type; 378 }; 379 380 #define MLX5_24BIT_MASK ((1 << 24) - 1) 381 382 enum mlx5_res_type { 383 MLX5_RES_QP = MLX5_EVENT_QUEUE_TYPE_QP, 384 MLX5_RES_RQ = MLX5_EVENT_QUEUE_TYPE_RQ, 385 MLX5_RES_SQ = MLX5_EVENT_QUEUE_TYPE_SQ, 386 MLX5_RES_SRQ = 3, 387 MLX5_RES_XSRQ = 4, 388 MLX5_RES_XRQ = 5, 389 MLX5_RES_DCT = MLX5_EVENT_QUEUE_TYPE_DCT, 390 }; 391 392 struct mlx5_core_rsc_common { 393 enum mlx5_res_type res; 394 refcount_t refcount; 395 struct completion free; 396 }; 397 398 struct mlx5_uars_page { 399 void __iomem *map; 400 bool wc; 401 u32 index; 402 struct list_head list; 403 unsigned int bfregs; 404 unsigned long *reg_bitmap; /* for non fast path bf regs */ 405 unsigned long *fp_bitmap; 406 unsigned int reg_avail; 407 unsigned int fp_avail; 408 struct kref ref_count; 409 struct mlx5_core_dev *mdev; 410 }; 411 412 struct mlx5_bfreg_head { 413 /* protect blue flame registers allocations */ 414 struct mutex lock; 415 struct list_head list; 416 }; 417 418 struct mlx5_bfreg_data { 419 struct mlx5_bfreg_head reg_head; 420 struct mlx5_bfreg_head wc_head; 421 }; 422 423 struct mlx5_sq_bfreg { 424 void __iomem *map; 425 struct mlx5_uars_page *up; 426 bool wc; 427 u32 index; 428 unsigned int offset; 429 }; 430 431 struct mlx5_core_health { 432 struct health_buffer __iomem *health; 433 __be32 __iomem *health_counter; 434 struct timer_list timer; 435 u32 prev; 436 int miss_counter; 437 u8 synd; 438 u32 fatal_error; 439 u32 crdump_size; 440 /* wq spinlock to synchronize draining */ 441 spinlock_t wq_lock; 442 struct workqueue_struct *wq; 443 unsigned long flags; 444 struct work_struct fatal_report_work; 445 struct work_struct report_work; 446 struct delayed_work recover_work; 447 struct devlink_health_reporter *fw_reporter; 448 struct devlink_health_reporter *fw_fatal_reporter; 449 }; 450 451 struct mlx5_qp_table { 452 struct notifier_block nb; 453 454 /* protect radix tree 455 */ 456 spinlock_t lock; 457 struct radix_tree_root tree; 458 }; 459 460 struct mlx5_vf_context { 461 int enabled; 462 u64 port_guid; 463 u64 node_guid; 464 enum port_state_policy policy; 465 }; 466 467 struct mlx5_core_sriov { 468 struct mlx5_vf_context *vfs_ctx; 469 int num_vfs; 470 u16 max_vfs; 471 }; 472 473 struct mlx5_fc_pool { 474 struct mlx5_core_dev *dev; 475 struct mutex pool_lock; /* protects pool lists */ 476 struct list_head fully_used; 477 struct list_head partially_used; 478 struct list_head unused; 479 int available_fcs; 480 int used_fcs; 481 int threshold; 482 }; 483 484 struct mlx5_fc_stats { 485 spinlock_t counters_idr_lock; /* protects counters_idr */ 486 struct idr counters_idr; 487 struct list_head counters; 488 struct llist_head addlist; 489 struct llist_head dellist; 490 491 struct workqueue_struct *wq; 492 struct delayed_work work; 493 unsigned long next_query; 494 unsigned long sampling_interval; /* jiffies */ 495 u32 *bulk_query_out; 496 struct mlx5_fc_pool fc_pool; 497 }; 498 499 struct mlx5_events; 500 struct mlx5_mpfs; 501 struct mlx5_eswitch; 502 struct mlx5_lag; 503 struct mlx5_devcom; 504 struct mlx5_eq_table; 505 struct mlx5_irq_table; 506 507 struct mlx5_rate_limit { 508 u32 rate; 509 u32 max_burst_sz; 510 u16 typical_pkt_sz; 511 }; 512 513 struct mlx5_rl_entry { 514 struct mlx5_rate_limit rl; 515 u16 index; 516 u16 refcount; 517 }; 518 519 struct mlx5_rl_table { 520 /* protect rate limit table */ 521 struct mutex rl_lock; 522 u16 max_size; 523 u32 max_rate; 524 u32 min_rate; 525 struct mlx5_rl_entry *rl_entry; 526 }; 527 528 struct mlx5_core_roce { 529 struct mlx5_flow_table *ft; 530 struct mlx5_flow_group *fg; 531 struct mlx5_flow_handle *allow_rule; 532 }; 533 534 struct mlx5_priv { 535 /* IRQ table valid only for real pci devices PF or VF */ 536 struct mlx5_irq_table *irq_table; 537 struct mlx5_eq_table *eq_table; 538 539 /* pages stuff */ 540 struct mlx5_nb pg_nb; 541 struct workqueue_struct *pg_wq; 542 struct rb_root page_root; 543 int fw_pages; 544 atomic_t reg_pages; 545 struct list_head free_list; 546 int vfs_pages; 547 int peer_pf_pages; 548 549 struct mlx5_core_health health; 550 551 /* start: qp staff */ 552 struct mlx5_qp_table qp_table; 553 struct dentry *qp_debugfs; 554 struct dentry *eq_debugfs; 555 struct dentry *cq_debugfs; 556 struct dentry *cmdif_debugfs; 557 /* end: qp staff */ 558 559 struct xarray mkey_table; 560 561 /* start: alloc staff */ 562 /* protect buffer alocation according to numa node */ 563 struct mutex alloc_mutex; 564 int numa_node; 565 566 struct mutex pgdir_mutex; 567 struct list_head pgdir_list; 568 /* end: alloc staff */ 569 struct dentry *dbg_root; 570 571 /* protect mkey key part */ 572 spinlock_t mkey_lock; 573 u8 mkey_key; 574 575 struct list_head dev_list; 576 struct list_head ctx_list; 577 spinlock_t ctx_lock; 578 struct mlx5_events *events; 579 580 struct mlx5_flow_steering *steering; 581 struct mlx5_mpfs *mpfs; 582 struct mlx5_eswitch *eswitch; 583 struct mlx5_core_sriov sriov; 584 struct mlx5_lag *lag; 585 struct mlx5_devcom *devcom; 586 struct mlx5_core_roce roce; 587 struct mlx5_fc_stats fc_stats; 588 struct mlx5_rl_table rl_table; 589 590 struct mlx5_bfreg_data bfregs; 591 struct mlx5_uars_page *uar; 592 }; 593 594 enum mlx5_device_state { 595 MLX5_DEVICE_STATE_UNINITIALIZED, 596 MLX5_DEVICE_STATE_UP, 597 MLX5_DEVICE_STATE_INTERNAL_ERROR, 598 }; 599 600 enum mlx5_interface_state { 601 MLX5_INTERFACE_STATE_UP = BIT(0), 602 }; 603 604 enum mlx5_pci_status { 605 MLX5_PCI_STATUS_DISABLED, 606 MLX5_PCI_STATUS_ENABLED, 607 }; 608 609 enum mlx5_pagefault_type_flags { 610 MLX5_PFAULT_REQUESTOR = 1 << 0, 611 MLX5_PFAULT_WRITE = 1 << 1, 612 MLX5_PFAULT_RDMA = 1 << 2, 613 }; 614 615 struct mlx5_td { 616 /* protects tirs list changes while tirs refresh */ 617 struct mutex list_lock; 618 struct list_head tirs_list; 619 u32 tdn; 620 }; 621 622 struct mlx5e_resources { 623 u32 pdn; 624 struct mlx5_td td; 625 struct mlx5_core_mkey mkey; 626 struct mlx5_sq_bfreg bfreg; 627 }; 628 629 enum mlx5_sw_icm_type { 630 MLX5_SW_ICM_TYPE_STEERING, 631 MLX5_SW_ICM_TYPE_HEADER_MODIFY, 632 }; 633 634 #define MLX5_MAX_RESERVED_GIDS 8 635 636 struct mlx5_rsvd_gids { 637 unsigned int start; 638 unsigned int count; 639 struct ida ida; 640 }; 641 642 #define MAX_PIN_NUM 8 643 struct mlx5_pps { 644 u8 pin_caps[MAX_PIN_NUM]; 645 struct work_struct out_work; 646 u64 start[MAX_PIN_NUM]; 647 u8 enabled; 648 }; 649 650 struct mlx5_clock { 651 struct mlx5_core_dev *mdev; 652 struct mlx5_nb pps_nb; 653 seqlock_t lock; 654 struct cyclecounter cycles; 655 struct timecounter tc; 656 struct hwtstamp_config hwtstamp_config; 657 u32 nominal_c_mult; 658 unsigned long overflow_period; 659 struct delayed_work overflow_work; 660 struct ptp_clock *ptp; 661 struct ptp_clock_info ptp_info; 662 struct mlx5_pps pps_info; 663 }; 664 665 struct mlx5_dm; 666 struct mlx5_fw_tracer; 667 struct mlx5_vxlan; 668 struct mlx5_geneve; 669 struct mlx5_hv_vhca; 670 671 #define MLX5_LOG_SW_ICM_BLOCK_SIZE(dev) (MLX5_CAP_DEV_MEM(dev, log_sw_icm_alloc_granularity)) 672 #define MLX5_SW_ICM_BLOCK_SIZE(dev) (1 << MLX5_LOG_SW_ICM_BLOCK_SIZE(dev)) 673 674 struct mlx5_core_dev { 675 struct device *device; 676 enum mlx5_coredev_type coredev_type; 677 struct pci_dev *pdev; 678 /* sync pci state */ 679 struct mutex pci_status_mutex; 680 enum mlx5_pci_status pci_status; 681 u8 rev_id; 682 char board_id[MLX5_BOARD_ID_LEN]; 683 struct mlx5_cmd cmd; 684 struct mlx5_port_caps port_caps[MLX5_MAX_PORTS]; 685 struct { 686 u32 hca_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)]; 687 u32 hca_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)]; 688 u32 pcam[MLX5_ST_SZ_DW(pcam_reg)]; 689 u32 mcam[MLX5_ST_SZ_DW(mcam_reg)]; 690 u32 fpga[MLX5_ST_SZ_DW(fpga_cap)]; 691 u32 qcam[MLX5_ST_SZ_DW(qcam_reg)]; 692 u8 embedded_cpu; 693 } caps; 694 u64 sys_image_guid; 695 phys_addr_t iseg_base; 696 struct mlx5_init_seg __iomem *iseg; 697 phys_addr_t bar_addr; 698 enum mlx5_device_state state; 699 /* sync interface state */ 700 struct mutex intf_state_mutex; 701 unsigned long intf_state; 702 struct mlx5_priv priv; 703 struct mlx5_profile *profile; 704 atomic_t num_qps; 705 u32 issi; 706 struct mlx5e_resources mlx5e_res; 707 struct mlx5_dm *dm; 708 struct mlx5_vxlan *vxlan; 709 struct mlx5_geneve *geneve; 710 struct { 711 struct mlx5_rsvd_gids reserved_gids; 712 u32 roce_en; 713 } roce; 714 #ifdef CONFIG_MLX5_FPGA 715 struct mlx5_fpga_device *fpga; 716 #endif 717 struct mlx5_clock clock; 718 struct mlx5_ib_clock_info *clock_info; 719 struct mlx5_fw_tracer *tracer; 720 u32 vsc_addr; 721 struct mlx5_hv_vhca *hv_vhca; 722 }; 723 724 struct mlx5_db { 725 __be32 *db; 726 union { 727 struct mlx5_db_pgdir *pgdir; 728 struct mlx5_ib_user_db_page *user_page; 729 } u; 730 dma_addr_t dma; 731 int index; 732 }; 733 734 enum { 735 MLX5_COMP_EQ_SIZE = 1024, 736 }; 737 738 enum { 739 MLX5_PTYS_IB = 1 << 0, 740 MLX5_PTYS_EN = 1 << 2, 741 }; 742 743 typedef void (*mlx5_cmd_cbk_t)(int status, void *context); 744 745 enum { 746 MLX5_CMD_ENT_STATE_PENDING_COMP, 747 }; 748 749 struct mlx5_cmd_work_ent { 750 unsigned long state; 751 struct mlx5_cmd_msg *in; 752 struct mlx5_cmd_msg *out; 753 void *uout; 754 int uout_size; 755 mlx5_cmd_cbk_t callback; 756 struct delayed_work cb_timeout_work; 757 void *context; 758 int idx; 759 struct completion done; 760 struct mlx5_cmd *cmd; 761 struct work_struct work; 762 struct mlx5_cmd_layout *lay; 763 int ret; 764 int page_queue; 765 u8 status; 766 u8 token; 767 u64 ts1; 768 u64 ts2; 769 u16 op; 770 bool polling; 771 }; 772 773 struct mlx5_pas { 774 u64 pa; 775 u8 log_sz; 776 }; 777 778 enum phy_port_state { 779 MLX5_AAA_111 780 }; 781 782 struct mlx5_hca_vport_context { 783 u32 field_select; 784 bool sm_virt_aware; 785 bool has_smi; 786 bool has_raw; 787 enum port_state_policy policy; 788 enum phy_port_state phys_state; 789 enum ib_port_state vport_state; 790 u8 port_physical_state; 791 u64 sys_image_guid; 792 u64 port_guid; 793 u64 node_guid; 794 u32 cap_mask1; 795 u32 cap_mask1_perm; 796 u16 cap_mask2; 797 u16 cap_mask2_perm; 798 u16 lid; 799 u8 init_type_reply; /* bitmask: see ib spec 14.2.5.6 InitTypeReply */ 800 u8 lmc; 801 u8 subnet_timeout; 802 u16 sm_lid; 803 u8 sm_sl; 804 u16 qkey_violation_counter; 805 u16 pkey_violation_counter; 806 bool grh_required; 807 }; 808 mlx5_buf_offset(struct mlx5_frag_buf * buf,int offset)809 static inline void *mlx5_buf_offset(struct mlx5_frag_buf *buf, int offset) 810 { 811 return buf->frags->buf + offset; 812 } 813 814 #define STRUCT_FIELD(header, field) \ 815 .struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field), \ 816 .struct_size_bytes = sizeof((struct ib_unpacked_ ## header *)0)->field 817 pci2mlx5_core_dev(struct pci_dev * pdev)818 static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev) 819 { 820 return pci_get_drvdata(pdev); 821 } 822 823 extern struct dentry *mlx5_debugfs_root; 824 fw_rev_maj(struct mlx5_core_dev * dev)825 static inline u16 fw_rev_maj(struct mlx5_core_dev *dev) 826 { 827 return ioread32be(&dev->iseg->fw_rev) & 0xffff; 828 } 829 fw_rev_min(struct mlx5_core_dev * dev)830 static inline u16 fw_rev_min(struct mlx5_core_dev *dev) 831 { 832 return ioread32be(&dev->iseg->fw_rev) >> 16; 833 } 834 fw_rev_sub(struct mlx5_core_dev * dev)835 static inline u16 fw_rev_sub(struct mlx5_core_dev *dev) 836 { 837 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff; 838 } 839 cmdif_rev(struct mlx5_core_dev * dev)840 static inline u16 cmdif_rev(struct mlx5_core_dev *dev) 841 { 842 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16; 843 } 844 mlx5_base_mkey(const u32 key)845 static inline u32 mlx5_base_mkey(const u32 key) 846 { 847 return key & 0xffffff00u; 848 } 849 mlx5_init_fbc_offset(struct mlx5_buf_list * frags,u8 log_stride,u8 log_sz,u16 strides_offset,struct mlx5_frag_buf_ctrl * fbc)850 static inline void mlx5_init_fbc_offset(struct mlx5_buf_list *frags, 851 u8 log_stride, u8 log_sz, 852 u16 strides_offset, 853 struct mlx5_frag_buf_ctrl *fbc) 854 { 855 fbc->frags = frags; 856 fbc->log_stride = log_stride; 857 fbc->log_sz = log_sz; 858 fbc->sz_m1 = (1 << fbc->log_sz) - 1; 859 fbc->log_frag_strides = PAGE_SHIFT - fbc->log_stride; 860 fbc->frag_sz_m1 = (1 << fbc->log_frag_strides) - 1; 861 fbc->strides_offset = strides_offset; 862 } 863 mlx5_init_fbc(struct mlx5_buf_list * frags,u8 log_stride,u8 log_sz,struct mlx5_frag_buf_ctrl * fbc)864 static inline void mlx5_init_fbc(struct mlx5_buf_list *frags, 865 u8 log_stride, u8 log_sz, 866 struct mlx5_frag_buf_ctrl *fbc) 867 { 868 mlx5_init_fbc_offset(frags, log_stride, log_sz, 0, fbc); 869 } 870 mlx5_frag_buf_get_wqe(struct mlx5_frag_buf_ctrl * fbc,u32 ix)871 static inline void *mlx5_frag_buf_get_wqe(struct mlx5_frag_buf_ctrl *fbc, 872 u32 ix) 873 { 874 unsigned int frag; 875 876 ix += fbc->strides_offset; 877 frag = ix >> fbc->log_frag_strides; 878 879 return fbc->frags[frag].buf + ((fbc->frag_sz_m1 & ix) << fbc->log_stride); 880 } 881 882 static inline u32 mlx5_frag_buf_get_idx_last_contig_stride(struct mlx5_frag_buf_ctrl * fbc,u32 ix)883 mlx5_frag_buf_get_idx_last_contig_stride(struct mlx5_frag_buf_ctrl *fbc, u32 ix) 884 { 885 u32 last_frag_stride_idx = (ix + fbc->strides_offset) | fbc->frag_sz_m1; 886 887 return min_t(u32, last_frag_stride_idx - fbc->strides_offset, fbc->sz_m1); 888 } 889 890 int mlx5_cmd_init(struct mlx5_core_dev *dev); 891 void mlx5_cmd_cleanup(struct mlx5_core_dev *dev); 892 void mlx5_cmd_use_events(struct mlx5_core_dev *dev); 893 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev); 894 895 struct mlx5_async_ctx { 896 struct mlx5_core_dev *dev; 897 atomic_t num_inflight; 898 struct wait_queue_head wait; 899 }; 900 901 struct mlx5_async_work; 902 903 typedef void (*mlx5_async_cbk_t)(int status, struct mlx5_async_work *context); 904 905 struct mlx5_async_work { 906 struct mlx5_async_ctx *ctx; 907 mlx5_async_cbk_t user_callback; 908 }; 909 910 void mlx5_cmd_init_async_ctx(struct mlx5_core_dev *dev, 911 struct mlx5_async_ctx *ctx); 912 void mlx5_cmd_cleanup_async_ctx(struct mlx5_async_ctx *ctx); 913 int mlx5_cmd_exec_cb(struct mlx5_async_ctx *ctx, void *in, int in_size, 914 void *out, int out_size, mlx5_async_cbk_t callback, 915 struct mlx5_async_work *work); 916 917 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out, 918 int out_size); 919 int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size, 920 void *out, int out_size); 921 void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome); 922 923 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type); 924 int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn); 925 int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn); 926 void mlx5_health_flush(struct mlx5_core_dev *dev); 927 void mlx5_health_cleanup(struct mlx5_core_dev *dev); 928 int mlx5_health_init(struct mlx5_core_dev *dev); 929 void mlx5_start_health_poll(struct mlx5_core_dev *dev); 930 void mlx5_stop_health_poll(struct mlx5_core_dev *dev, bool disable_health); 931 void mlx5_drain_health_wq(struct mlx5_core_dev *dev); 932 void mlx5_trigger_health_work(struct mlx5_core_dev *dev); 933 int mlx5_buf_alloc_node(struct mlx5_core_dev *dev, int size, 934 struct mlx5_frag_buf *buf, int node); 935 int mlx5_buf_alloc(struct mlx5_core_dev *dev, 936 int size, struct mlx5_frag_buf *buf); 937 void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf); 938 int mlx5_frag_buf_alloc_node(struct mlx5_core_dev *dev, int size, 939 struct mlx5_frag_buf *buf, int node); 940 void mlx5_frag_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf); 941 struct mlx5_cmd_mailbox *mlx5_alloc_cmd_mailbox_chain(struct mlx5_core_dev *dev, 942 gfp_t flags, int npages); 943 void mlx5_free_cmd_mailbox_chain(struct mlx5_core_dev *dev, 944 struct mlx5_cmd_mailbox *head); 945 void mlx5_init_mkey_table(struct mlx5_core_dev *dev); 946 void mlx5_cleanup_mkey_table(struct mlx5_core_dev *dev); 947 int mlx5_core_create_mkey_cb(struct mlx5_core_dev *dev, 948 struct mlx5_core_mkey *mkey, 949 struct mlx5_async_ctx *async_ctx, u32 *in, 950 int inlen, u32 *out, int outlen, 951 mlx5_async_cbk_t callback, 952 struct mlx5_async_work *context); 953 int mlx5_core_create_mkey(struct mlx5_core_dev *dev, 954 struct mlx5_core_mkey *mkey, 955 u32 *in, int inlen); 956 int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev, 957 struct mlx5_core_mkey *mkey); 958 int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mkey *mkey, 959 u32 *out, int outlen); 960 int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn); 961 int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn); 962 int mlx5_pagealloc_init(struct mlx5_core_dev *dev); 963 void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev); 964 void mlx5_pagealloc_start(struct mlx5_core_dev *dev); 965 void mlx5_pagealloc_stop(struct mlx5_core_dev *dev); 966 void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id, 967 s32 npages, bool ec_function); 968 int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot); 969 int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev); 970 void mlx5_register_debugfs(void); 971 void mlx5_unregister_debugfs(void); 972 973 void mlx5_fill_page_array(struct mlx5_frag_buf *buf, __be64 *pas); 974 void mlx5_fill_page_frag_array(struct mlx5_frag_buf *frag_buf, __be64 *pas); 975 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, 976 unsigned int *irqn); 977 int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn); 978 int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn); 979 980 void mlx5_qp_debugfs_init(struct mlx5_core_dev *dev); 981 void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev); 982 int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in, 983 int size_in, void *data_out, int size_out, 984 u16 reg_num, int arg, int write); 985 986 int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db); 987 int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db, 988 int node); 989 void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db); 990 991 const char *mlx5_command_str(int command); 992 void mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev); 993 void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev); 994 int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn, 995 int npsvs, u32 *sig_index); 996 int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num); 997 void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common); 998 int mlx5_query_odp_caps(struct mlx5_core_dev *dev, 999 struct mlx5_odp_caps *odp_caps); 1000 int mlx5_core_query_ib_ppcnt(struct mlx5_core_dev *dev, 1001 u8 port_num, void *out, size_t sz); 1002 1003 int mlx5_init_rl_table(struct mlx5_core_dev *dev); 1004 void mlx5_cleanup_rl_table(struct mlx5_core_dev *dev); 1005 int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u16 *index, 1006 struct mlx5_rate_limit *rl); 1007 void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, struct mlx5_rate_limit *rl); 1008 bool mlx5_rl_is_in_range(struct mlx5_core_dev *dev, u32 rate); 1009 bool mlx5_rl_are_equal(struct mlx5_rate_limit *rl_0, 1010 struct mlx5_rate_limit *rl_1); 1011 int mlx5_alloc_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg, 1012 bool map_wc, bool fast_path); 1013 void mlx5_free_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg); 1014 1015 unsigned int mlx5_comp_vectors_count(struct mlx5_core_dev *dev); 1016 struct cpumask * 1017 mlx5_comp_irq_get_affinity_mask(struct mlx5_core_dev *dev, int vector); 1018 unsigned int mlx5_core_reserved_gids_count(struct mlx5_core_dev *dev); 1019 int mlx5_core_roce_gid_set(struct mlx5_core_dev *dev, unsigned int index, 1020 u8 roce_version, u8 roce_l3_type, const u8 *gid, 1021 const u8 *mac, bool vlan, u16 vlan_id, u8 port_num); 1022 fw_initializing(struct mlx5_core_dev * dev)1023 static inline int fw_initializing(struct mlx5_core_dev *dev) 1024 { 1025 return ioread32be(&dev->iseg->initializing) >> 31; 1026 } 1027 mlx5_mkey_to_idx(u32 mkey)1028 static inline u32 mlx5_mkey_to_idx(u32 mkey) 1029 { 1030 return mkey >> 8; 1031 } 1032 mlx5_idx_to_mkey(u32 mkey_idx)1033 static inline u32 mlx5_idx_to_mkey(u32 mkey_idx) 1034 { 1035 return mkey_idx << 8; 1036 } 1037 mlx5_mkey_variant(u32 mkey)1038 static inline u8 mlx5_mkey_variant(u32 mkey) 1039 { 1040 return mkey & 0xff; 1041 } 1042 1043 enum { 1044 MLX5_PROF_MASK_QP_SIZE = (u64)1 << 0, 1045 MLX5_PROF_MASK_MR_CACHE = (u64)1 << 1, 1046 }; 1047 1048 enum { 1049 MR_CACHE_LAST_STD_ENTRY = 20, 1050 MLX5_IMR_MTT_CACHE_ENTRY, 1051 MLX5_IMR_KSM_CACHE_ENTRY, 1052 MAX_MR_CACHE_ENTRIES 1053 }; 1054 1055 enum { 1056 MLX5_INTERFACE_PROTOCOL_IB = 0, 1057 MLX5_INTERFACE_PROTOCOL_ETH = 1, 1058 }; 1059 1060 struct mlx5_interface { 1061 void * (*add)(struct mlx5_core_dev *dev); 1062 void (*remove)(struct mlx5_core_dev *dev, void *context); 1063 int (*attach)(struct mlx5_core_dev *dev, void *context); 1064 void (*detach)(struct mlx5_core_dev *dev, void *context); 1065 int protocol; 1066 struct list_head list; 1067 }; 1068 1069 int mlx5_register_interface(struct mlx5_interface *intf); 1070 void mlx5_unregister_interface(struct mlx5_interface *intf); 1071 int mlx5_notifier_register(struct mlx5_core_dev *dev, struct notifier_block *nb); 1072 int mlx5_notifier_unregister(struct mlx5_core_dev *dev, struct notifier_block *nb); 1073 int mlx5_eq_notifier_register(struct mlx5_core_dev *dev, struct mlx5_nb *nb); 1074 int mlx5_eq_notifier_unregister(struct mlx5_core_dev *dev, struct mlx5_nb *nb); 1075 1076 int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id); 1077 1078 int mlx5_cmd_create_vport_lag(struct mlx5_core_dev *dev); 1079 int mlx5_cmd_destroy_vport_lag(struct mlx5_core_dev *dev); 1080 bool mlx5_lag_is_roce(struct mlx5_core_dev *dev); 1081 bool mlx5_lag_is_sriov(struct mlx5_core_dev *dev); 1082 bool mlx5_lag_is_multipath(struct mlx5_core_dev *dev); 1083 bool mlx5_lag_is_active(struct mlx5_core_dev *dev); 1084 struct net_device *mlx5_lag_get_roce_netdev(struct mlx5_core_dev *dev); 1085 int mlx5_lag_query_cong_counters(struct mlx5_core_dev *dev, 1086 u64 *values, 1087 int num_counters, 1088 size_t *offsets); 1089 struct mlx5_uars_page *mlx5_get_uars_page(struct mlx5_core_dev *mdev); 1090 void mlx5_put_uars_page(struct mlx5_core_dev *mdev, struct mlx5_uars_page *up); 1091 int mlx5_dm_sw_icm_alloc(struct mlx5_core_dev *dev, enum mlx5_sw_icm_type type, 1092 u64 length, u16 uid, phys_addr_t *addr, u32 *obj_id); 1093 int mlx5_dm_sw_icm_dealloc(struct mlx5_core_dev *dev, enum mlx5_sw_icm_type type, 1094 u64 length, u16 uid, phys_addr_t addr, u32 obj_id); 1095 1096 #ifdef CONFIG_MLX5_CORE_IPOIB 1097 struct net_device *mlx5_rdma_netdev_alloc(struct mlx5_core_dev *mdev, 1098 struct ib_device *ibdev, 1099 const char *name, 1100 void (*setup)(struct net_device *)); 1101 #endif /* CONFIG_MLX5_CORE_IPOIB */ 1102 int mlx5_rdma_rn_get_params(struct mlx5_core_dev *mdev, 1103 struct ib_device *device, 1104 struct rdma_netdev_alloc_params *params); 1105 1106 struct mlx5_profile { 1107 u64 mask; 1108 u8 log_max_qp; 1109 struct { 1110 int size; 1111 int limit; 1112 } mr_cache[MAX_MR_CACHE_ENTRIES]; 1113 }; 1114 1115 enum { 1116 MLX5_PCI_DEV_IS_VF = 1 << 0, 1117 }; 1118 mlx5_core_is_pf(const struct mlx5_core_dev * dev)1119 static inline bool mlx5_core_is_pf(const struct mlx5_core_dev *dev) 1120 { 1121 return dev->coredev_type == MLX5_COREDEV_PF; 1122 } 1123 mlx5_core_is_ecpf(struct mlx5_core_dev * dev)1124 static inline bool mlx5_core_is_ecpf(struct mlx5_core_dev *dev) 1125 { 1126 return dev->caps.embedded_cpu; 1127 } 1128 1129 static inline bool mlx5_core_is_ecpf_esw_manager(const struct mlx5_core_dev * dev)1130 mlx5_core_is_ecpf_esw_manager(const struct mlx5_core_dev *dev) 1131 { 1132 return dev->caps.embedded_cpu && MLX5_CAP_GEN(dev, eswitch_manager); 1133 } 1134 mlx5_ecpf_vport_exists(const struct mlx5_core_dev * dev)1135 static inline bool mlx5_ecpf_vport_exists(const struct mlx5_core_dev *dev) 1136 { 1137 return mlx5_core_is_pf(dev) && MLX5_CAP_ESW(dev, ecpf_vport_exists); 1138 } 1139 mlx5_core_max_vfs(const struct mlx5_core_dev * dev)1140 static inline u16 mlx5_core_max_vfs(const struct mlx5_core_dev *dev) 1141 { 1142 return dev->priv.sriov.max_vfs; 1143 } 1144 mlx5_get_gid_table_len(u16 param)1145 static inline int mlx5_get_gid_table_len(u16 param) 1146 { 1147 if (param > 4) { 1148 pr_warn("gid table length is zero\n"); 1149 return 0; 1150 } 1151 1152 return 8 * (1 << param); 1153 } 1154 mlx5_rl_is_supported(struct mlx5_core_dev * dev)1155 static inline bool mlx5_rl_is_supported(struct mlx5_core_dev *dev) 1156 { 1157 return !!(dev->priv.rl_table.max_size); 1158 } 1159 mlx5_core_is_mp_slave(struct mlx5_core_dev * dev)1160 static inline int mlx5_core_is_mp_slave(struct mlx5_core_dev *dev) 1161 { 1162 return MLX5_CAP_GEN(dev, affiliate_nic_vport_criteria) && 1163 MLX5_CAP_GEN(dev, num_vhca_ports) <= 1; 1164 } 1165 mlx5_core_is_mp_master(struct mlx5_core_dev * dev)1166 static inline int mlx5_core_is_mp_master(struct mlx5_core_dev *dev) 1167 { 1168 return MLX5_CAP_GEN(dev, num_vhca_ports) > 1; 1169 } 1170 mlx5_core_mp_enabled(struct mlx5_core_dev * dev)1171 static inline int mlx5_core_mp_enabled(struct mlx5_core_dev *dev) 1172 { 1173 return mlx5_core_is_mp_slave(dev) || 1174 mlx5_core_is_mp_master(dev); 1175 } 1176 mlx5_core_native_port_num(struct mlx5_core_dev * dev)1177 static inline int mlx5_core_native_port_num(struct mlx5_core_dev *dev) 1178 { 1179 if (!mlx5_core_mp_enabled(dev)) 1180 return 1; 1181 1182 return MLX5_CAP_GEN(dev, native_port_num); 1183 } 1184 1185 enum { 1186 MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32, 1187 }; 1188 1189 #endif /* MLX5_DRIVER_H */ 1190