1  /* SPDX-License-Identifier: ISC */
2  /* Copyright (C) 2019 MediaTek Inc. */
3  
4  #ifndef __MT7615_MCU_H
5  #define __MT7615_MCU_H
6  
7  struct mt7615_mcu_txd {
8  	__le32 txd[8];
9  
10  	__le16 len;
11  	__le16 pq_id;
12  
13  	u8 cid;
14  	u8 pkt_type;
15  	u8 set_query; /* FW don't care */
16  	u8 seq;
17  
18  	u8 uc_d2b0_rev;
19  	u8 ext_cid;
20  	u8 s2d_index;
21  	u8 ext_cid_ack;
22  
23  	u32 reserved[5];
24  } __packed __aligned(4);
25  
26  /* event table */
27  enum {
28  	MCU_EVENT_TARGET_ADDRESS_LEN = 0x01,
29  	MCU_EVENT_FW_START = 0x01,
30  	MCU_EVENT_GENERIC = 0x01,
31  	MCU_EVENT_ACCESS_REG = 0x02,
32  	MCU_EVENT_MT_PATCH_SEM = 0x04,
33  	MCU_EVENT_CH_PRIVILEGE = 0x18,
34  	MCU_EVENT_EXT = 0xed,
35  	MCU_EVENT_RESTART_DL = 0xef,
36  };
37  
38  /* ext event table */
39  enum {
40  	MCU_EXT_EVENT_PS_SYNC = 0x5,
41  	MCU_EXT_EVENT_FW_LOG_2_HOST = 0x13,
42  	MCU_EXT_EVENT_THERMAL_PROTECT = 0x22,
43  	MCU_EXT_EVENT_ASSERT_DUMP = 0x23,
44  	MCU_EXT_EVENT_RDD_REPORT = 0x3a,
45  	MCU_EXT_EVENT_CSA_NOTIFY = 0x4f,
46  };
47  
48  struct mt7615_mcu_rxd {
49  	__le32 rxd[4];
50  
51  	__le16 len;
52  	__le16 pkt_type_id;
53  
54  	u8 eid;
55  	u8 seq;
56  	__le16 __rsv;
57  
58  	u8 ext_eid;
59  	u8 __rsv1[2];
60  	u8 s2d_index;
61  };
62  
63  #define MCU_PQ_ID(p, q)		(((p) << 15) | ((q) << 10))
64  #define MCU_PKT_ID		0xa0
65  
66  enum {
67  	MCU_Q_QUERY,
68  	MCU_Q_SET,
69  	MCU_Q_RESERVED,
70  	MCU_Q_NA
71  };
72  
73  enum {
74  	MCU_S2D_H2N,
75  	MCU_S2D_C2N,
76  	MCU_S2D_H2C,
77  	MCU_S2D_H2CN
78  };
79  
80  enum {
81  	MCU_CMD_TARGET_ADDRESS_LEN_REQ = 0x01,
82  	MCU_CMD_FW_START_REQ = 0x02,
83  	MCU_CMD_INIT_ACCESS_REG = 0x3,
84  	MCU_CMD_PATCH_START_REQ = 0x05,
85  	MCU_CMD_PATCH_FINISH_REQ = 0x07,
86  	MCU_CMD_PATCH_SEM_CONTROL = 0x10,
87  	MCU_CMD_EXT_CID = 0xED,
88  	MCU_CMD_FW_SCATTER = 0xEE,
89  	MCU_CMD_RESTART_DL_REQ = 0xEF,
90  };
91  
92  enum {
93  	MCU_EXT_CMD_PM_STATE_CTRL = 0x07,
94  	MCU_EXT_CMD_CHANNEL_SWITCH = 0x08,
95  	MCU_EXT_CMD_SET_TX_POWER_CTRL = 0x11,
96  	MCU_EXT_CMD_EFUSE_BUFFER_MODE = 0x21,
97  	MCU_EXT_CMD_STA_REC_UPDATE = 0x25,
98  	MCU_EXT_CMD_BSS_INFO_UPDATE = 0x26,
99  	MCU_EXT_CMD_EDCA_UPDATE = 0x27,
100  	MCU_EXT_CMD_DEV_INFO_UPDATE = 0x2A,
101  	MCU_EXT_CMD_GET_TEMP = 0x2c,
102  	MCU_EXT_CMD_WTBL_UPDATE = 0x32,
103  	MCU_EXT_CMD_SET_RDD_CTRL = 0x3a,
104  	MCU_EXT_CMD_PROTECT_CTRL = 0x3e,
105  	MCU_EXT_CMD_MAC_INIT_CTRL = 0x46,
106  	MCU_EXT_CMD_BCN_OFFLOAD = 0x49,
107  	MCU_EXT_CMD_SET_RX_PATH = 0x4e,
108  	MCU_EXT_CMD_SET_RDD_PATTERN = 0x7d,
109  };
110  
111  enum {
112  	PATCH_SEM_RELEASE = 0x0,
113  	PATCH_SEM_GET	  = 0x1
114  };
115  
116  enum {
117  	PATCH_NOT_DL_SEM_FAIL	 = 0x0,
118  	PATCH_IS_DL		 = 0x1,
119  	PATCH_NOT_DL_SEM_SUCCESS = 0x2,
120  	PATCH_REL_SEM_SUCCESS	 = 0x3
121  };
122  
123  enum {
124  	FW_STATE_INITIAL          = 0,
125  	FW_STATE_FW_DOWNLOAD      = 1,
126  	FW_STATE_NORMAL_OPERATION = 2,
127  	FW_STATE_NORMAL_TRX       = 3,
128  	FW_STATE_CR4_RDY          = 7
129  };
130  
131  #define STA_TYPE_STA		BIT(0)
132  #define STA_TYPE_AP		BIT(1)
133  #define STA_TYPE_ADHOC		BIT(2)
134  #define STA_TYPE_WDS		BIT(4)
135  #define STA_TYPE_BC		BIT(5)
136  
137  #define NETWORK_INFRA		BIT(16)
138  #define NETWORK_P2P		BIT(17)
139  #define NETWORK_IBSS		BIT(18)
140  #define NETWORK_WDS		BIT(21)
141  
142  #define CONNECTION_INFRA_STA	(STA_TYPE_STA | NETWORK_INFRA)
143  #define CONNECTION_INFRA_AP	(STA_TYPE_AP | NETWORK_INFRA)
144  #define CONNECTION_P2P_GC	(STA_TYPE_STA | NETWORK_P2P)
145  #define CONNECTION_P2P_GO	(STA_TYPE_AP | NETWORK_P2P)
146  #define CONNECTION_IBSS_ADHOC	(STA_TYPE_ADHOC | NETWORK_IBSS)
147  #define CONNECTION_WDS		(STA_TYPE_WDS | NETWORK_WDS)
148  #define CONNECTION_INFRA_BC	(STA_TYPE_BC | NETWORK_INFRA)
149  
150  #define CONN_STATE_DISCONNECT	0
151  #define CONN_STATE_CONNECT	1
152  #define CONN_STATE_PORT_SECURE	2
153  
154  enum {
155  	DEV_INFO_ACTIVE,
156  	DEV_INFO_MAX_NUM
157  };
158  
159  struct bss_info_omac {
160  	__le16 tag;
161  	__le16 len;
162  	u8 hw_bss_idx;
163  	u8 omac_idx;
164  	u8 band_idx;
165  	u8 rsv0;
166  	__le32 conn_type;
167  	u32 rsv1;
168  } __packed;
169  
170  struct bss_info_basic {
171  	__le16 tag;
172  	__le16 len;
173  	__le32 network_type;
174  	u8 active;
175  	u8 rsv0;
176  	__le16 bcn_interval;
177  	u8 bssid[ETH_ALEN];
178  	u8 wmm_idx;
179  	u8 dtim_period;
180  	u8 bmc_tx_wlan_idx;
181  	u8 cipher; /* not used */
182  	u8 phymode; /* not used */
183  	u8 rsv1[5];
184  } __packed;
185  
186  struct bss_info_rf_ch {
187  	__le16 tag;
188  	__le16 len;
189  	u8 pri_ch;
190  	u8 central_ch0;
191  	u8 central_ch1;
192  	u8 bw;
193  } __packed;
194  
195  struct bss_info_ext_bss {
196  	__le16 tag;
197  	__le16 len;
198  	__le32 mbss_tsf_offset; /* in unit of us */
199  	u8 rsv[8];
200  } __packed;
201  
202  enum {
203  	BSS_INFO_OMAC,
204  	BSS_INFO_BASIC,
205  	BSS_INFO_RF_CH, /* optional, for BT/LTE coex */
206  	BSS_INFO_PM, /* sta only */
207  	BSS_INFO_UAPSD, /* sta only */
208  	BSS_INFO_ROAM_DETECTION, /* obsoleted */
209  	BSS_INFO_LQ_RM, /* obsoleted */
210  	BSS_INFO_EXT_BSS,
211  	BSS_INFO_BMC_INFO, /* for bmc rate control in CR4 */
212  	BSS_INFO_SYNC_MODE, /* obsoleted */
213  	BSS_INFO_RA,
214  	BSS_INFO_MAX_NUM
215  };
216  
217  enum {
218  	WTBL_RESET_AND_SET = 1,
219  	WTBL_SET,
220  	WTBL_QUERY,
221  	WTBL_RESET_ALL
222  };
223  
224  struct wtbl_req_hdr {
225  	u8 wlan_idx;
226  	u8 operation;
227  	__le16 tlv_num;
228  	u8 rsv[4];
229  } __packed;
230  
231  struct wtbl_generic {
232  	__le16 tag;
233  	__le16 len;
234  	u8 peer_addr[ETH_ALEN];
235  	u8 muar_idx;
236  	u8 skip_tx;
237  	u8 cf_ack;
238  	u8 qos;
239  	u8 mesh;
240  	u8 adm;
241  	__le16 partial_aid;
242  	u8 baf_en;
243  	u8 aad_om;
244  } __packed;
245  
246  struct wtbl_rx {
247  	__le16 tag;
248  	__le16 len;
249  	u8 rcid;
250  	u8 rca1;
251  	u8 rca2;
252  	u8 rv;
253  	u8 rsv[4];
254  } __packed;
255  
256  struct wtbl_ht {
257  	__le16 tag;
258  	__le16 len;
259  	u8 ht;
260  	u8 ldpc;
261  	u8 af;
262  	u8 mm;
263  	u8 rsv[4];
264  } __packed;
265  
266  struct wtbl_vht {
267  	__le16 tag;
268  	__le16 len;
269  	u8 ldpc;
270  	u8 dyn_bw;
271  	u8 vht;
272  	u8 txop_ps;
273  	u8 rsv[4];
274  } __packed;
275  
276  struct wtbl_tx_ps {
277  	__le16 tag;
278  	__le16 len;
279  	u8 txps;
280  	u8 rsv[3];
281  } __packed;
282  
283  struct wtbl_hdr_trans {
284  	__le16 tag;
285  	__le16 len;
286  	u8 to_ds;
287  	u8 from_ds;
288  	u8 disable_rx_trans;
289  	u8 rsv;
290  } __packed;
291  
292  enum {
293  	MT_BA_TYPE_INVALID,
294  	MT_BA_TYPE_ORIGINATOR,
295  	MT_BA_TYPE_RECIPIENT
296  };
297  
298  enum {
299  	RST_BA_MAC_TID_MATCH,
300  	RST_BA_MAC_MATCH,
301  	RST_BA_NO_MATCH
302  };
303  
304  struct wtbl_ba {
305  	__le16 tag;
306  	__le16 len;
307  	/* common */
308  	u8 tid;
309  	u8 ba_type;
310  	u8 rsv0[2];
311  	/* originator only */
312  	__le16 sn;
313  	u8 ba_en;
314  	u8 ba_winsize_idx;
315  	__le16 ba_winsize;
316  	/* recipient only */
317  	u8 peer_addr[ETH_ALEN];
318  	u8 rst_ba_tid;
319  	u8 rst_ba_sel;
320  	u8 rst_ba_sb;
321  	u8 band_idx;
322  	u8 rsv1[4];
323  } __packed;
324  
325  struct wtbl_bf {
326  	__le16 tag;
327  	__le16 len;
328  	u8 ibf;
329  	u8 ebf;
330  	u8 ibf_vht;
331  	u8 ebf_vht;
332  	u8 gid;
333  	u8 pfmu_idx;
334  	u8 rsv[2];
335  } __packed;
336  
337  struct wtbl_smps {
338  	__le16 tag;
339  	__le16 len;
340  	u8 smps;
341  	u8 rsv[3];
342  } __packed;
343  
344  struct wtbl_pn {
345  	__le16 tag;
346  	__le16 len;
347  	u8 pn[6];
348  	u8 rsv[2];
349  } __packed;
350  
351  struct wtbl_spe {
352  	__le16 tag;
353  	__le16 len;
354  	u8 spe_idx;
355  	u8 rsv[3];
356  } __packed;
357  
358  struct wtbl_raw {
359  	__le16 tag;
360  	__le16 len;
361  	u8 wtbl_idx;
362  	u8 dw;
363  	u8 rsv[2];
364  	__le32 msk;
365  	__le32 val;
366  } __packed;
367  
368  #define MT7615_WTBL_UPDATE_MAX_SIZE (sizeof(struct wtbl_req_hdr) + \
369  				     sizeof(struct wtbl_generic) + \
370  				     sizeof(struct wtbl_rx) + \
371  				     sizeof(struct wtbl_ht) + \
372  				     sizeof(struct wtbl_vht) + \
373  				     sizeof(struct wtbl_tx_ps) + \
374  				     sizeof(struct wtbl_hdr_trans) + \
375  				     sizeof(struct wtbl_ba) + \
376  				     sizeof(struct wtbl_bf) + \
377  				     sizeof(struct wtbl_smps) + \
378  				     sizeof(struct wtbl_pn) + \
379  				     sizeof(struct wtbl_spe))
380  
381  enum {
382  	WTBL_GENERIC,
383  	WTBL_RX,
384  	WTBL_HT,
385  	WTBL_VHT,
386  	WTBL_PEER_PS, /* not used */
387  	WTBL_TX_PS,
388  	WTBL_HDR_TRANS,
389  	WTBL_SEC_KEY,
390  	WTBL_BA,
391  	WTBL_RDG, /* obsoleted */
392  	WTBL_PROTECT, /* not used */
393  	WTBL_CLEAR, /* not used */
394  	WTBL_BF,
395  	WTBL_SMPS,
396  	WTBL_RAW_DATA, /* debug only */
397  	WTBL_PN,
398  	WTBL_SPE,
399  	WTBL_MAX_NUM
400  };
401  
402  struct sta_req_hdr {
403  	u8 bss_idx;
404  	u8 wlan_idx;
405  	__le16 tlv_num;
406  	u8 is_tlv_append;
407  	u8 muar_idx;
408  	u8 rsv[2];
409  } __packed;
410  
411  struct sta_rec_basic {
412  	__le16 tag;
413  	__le16 len;
414  	__le32 conn_type;
415  	u8 conn_state;
416  	u8 qos;
417  	__le16 aid;
418  	u8 peer_addr[ETH_ALEN];
419  #define EXTRA_INFO_VER	BIT(0)
420  #define EXTRA_INFO_NEW	BIT(1)
421  	__le16 extra_info;
422  } __packed;
423  
424  struct sta_rec_ht {
425  	__le16 tag;
426  	__le16 len;
427  	__le16 ht_cap;
428  	u16 rsv;
429  } __packed;
430  
431  struct sta_rec_vht {
432  	__le16 tag;
433  	__le16 len;
434  	__le32 vht_cap;
435  	__le16 vht_rx_mcs_map;
436  	__le16 vht_tx_mcs_map;
437  } __packed;
438  
439  struct sta_rec_ba {
440  	__le16 tag;
441  	__le16 len;
442  	u8 tid;
443  	u8 ba_type;
444  	u8 amsdu;
445  	u8 ba_en;
446  	__le16 ssn;
447  	__le16 winsize;
448  } __packed;
449  
450  #define MT7615_STA_REC_UPDATE_MAX_SIZE (sizeof(struct sta_rec_basic) + \
451  					sizeof(struct sta_rec_ht) + \
452  					sizeof(struct sta_rec_vht))
453  
454  enum {
455  	STA_REC_BASIC,
456  	STA_REC_RA,
457  	STA_REC_RA_CMM_INFO,
458  	STA_REC_RA_UPDATE,
459  	STA_REC_BF,
460  	STA_REC_AMSDU, /* for CR4 */
461  	STA_REC_BA,
462  	STA_REC_RED, /* not used */
463  	STA_REC_TX_PROC, /* for hdr trans and CSO in CR4 */
464  	STA_REC_HT,
465  	STA_REC_VHT,
466  	STA_REC_APPS,
467  	STA_REC_MAX_NUM
468  };
469  
470  enum {
471  	CMD_CBW_20MHZ,
472  	CMD_CBW_40MHZ,
473  	CMD_CBW_80MHZ,
474  	CMD_CBW_160MHZ,
475  	CMD_CBW_10MHZ,
476  	CMD_CBW_5MHZ,
477  	CMD_CBW_8080MHZ
478  };
479  
480  enum {
481  	CH_SWITCH_NORMAL = 0,
482  	CH_SWITCH_SCAN = 3,
483  	CH_SWITCH_MCC = 4,
484  	CH_SWITCH_DFS = 5,
485  	CH_SWITCH_BACKGROUND_SCAN_START = 6,
486  	CH_SWITCH_BACKGROUND_SCAN_RUNNING = 7,
487  	CH_SWITCH_BACKGROUND_SCAN_STOP = 8,
488  	CH_SWITCH_SCAN_BYPASS_DPD = 9
489  };
490  
491  static inline struct sk_buff *
mt7615_mcu_msg_alloc(const void * data,int len)492  mt7615_mcu_msg_alloc(const void *data, int len)
493  {
494  	return mt76_mcu_msg_alloc(data, sizeof(struct mt7615_mcu_txd),
495  				  len, 0);
496  }
497  
498  #endif
499