1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2017 Chelsio Communications. All rights reserved.
4 */
5
6 #include <linux/sort.h>
7
8 #include "t4_regs.h"
9 #include "cxgb4.h"
10 #include "cxgb4_cudbg.h"
11 #include "cudbg_if.h"
12 #include "cudbg_lib_common.h"
13 #include "cudbg_entity.h"
14 #include "cudbg_lib.h"
15 #include "cudbg_zlib.h"
16
cudbg_do_compression(struct cudbg_init * pdbg_init,struct cudbg_buffer * pin_buff,struct cudbg_buffer * dbg_buff)17 static int cudbg_do_compression(struct cudbg_init *pdbg_init,
18 struct cudbg_buffer *pin_buff,
19 struct cudbg_buffer *dbg_buff)
20 {
21 struct cudbg_buffer temp_in_buff = { 0 };
22 int bytes_left, bytes_read, bytes;
23 u32 offset = dbg_buff->offset;
24 int rc;
25
26 temp_in_buff.offset = pin_buff->offset;
27 temp_in_buff.data = pin_buff->data;
28 temp_in_buff.size = pin_buff->size;
29
30 bytes_left = pin_buff->size;
31 bytes_read = 0;
32 while (bytes_left > 0) {
33 /* Do compression in smaller chunks */
34 bytes = min_t(unsigned long, bytes_left,
35 (unsigned long)CUDBG_CHUNK_SIZE);
36 temp_in_buff.data = (char *)pin_buff->data + bytes_read;
37 temp_in_buff.size = bytes;
38 rc = cudbg_compress_buff(pdbg_init, &temp_in_buff, dbg_buff);
39 if (rc)
40 return rc;
41 bytes_left -= bytes;
42 bytes_read += bytes;
43 }
44
45 pin_buff->size = dbg_buff->offset - offset;
46 return 0;
47 }
48
cudbg_write_and_release_buff(struct cudbg_init * pdbg_init,struct cudbg_buffer * pin_buff,struct cudbg_buffer * dbg_buff)49 static int cudbg_write_and_release_buff(struct cudbg_init *pdbg_init,
50 struct cudbg_buffer *pin_buff,
51 struct cudbg_buffer *dbg_buff)
52 {
53 int rc = 0;
54
55 if (pdbg_init->compress_type == CUDBG_COMPRESSION_NONE) {
56 cudbg_update_buff(pin_buff, dbg_buff);
57 } else {
58 rc = cudbg_do_compression(pdbg_init, pin_buff, dbg_buff);
59 if (rc)
60 goto out;
61 }
62
63 out:
64 cudbg_put_buff(pdbg_init, pin_buff);
65 return rc;
66 }
67
is_fw_attached(struct cudbg_init * pdbg_init)68 static int is_fw_attached(struct cudbg_init *pdbg_init)
69 {
70 struct adapter *padap = pdbg_init->adap;
71
72 if (!(padap->flags & CXGB4_FW_OK) || padap->use_bd)
73 return 0;
74
75 return 1;
76 }
77
78 /* This function will add additional padding bytes into debug_buffer to make it
79 * 4 byte aligned.
80 */
cudbg_align_debug_buffer(struct cudbg_buffer * dbg_buff,struct cudbg_entity_hdr * entity_hdr)81 void cudbg_align_debug_buffer(struct cudbg_buffer *dbg_buff,
82 struct cudbg_entity_hdr *entity_hdr)
83 {
84 u8 zero_buf[4] = {0};
85 u8 padding, remain;
86
87 remain = (dbg_buff->offset - entity_hdr->start_offset) % 4;
88 padding = 4 - remain;
89 if (remain) {
90 memcpy(((u8 *)dbg_buff->data) + dbg_buff->offset, &zero_buf,
91 padding);
92 dbg_buff->offset += padding;
93 entity_hdr->num_pad = padding;
94 }
95 entity_hdr->size = dbg_buff->offset - entity_hdr->start_offset;
96 }
97
cudbg_get_entity_hdr(void * outbuf,int i)98 struct cudbg_entity_hdr *cudbg_get_entity_hdr(void *outbuf, int i)
99 {
100 struct cudbg_hdr *cudbg_hdr = (struct cudbg_hdr *)outbuf;
101
102 return (struct cudbg_entity_hdr *)
103 ((char *)outbuf + cudbg_hdr->hdr_len +
104 (sizeof(struct cudbg_entity_hdr) * (i - 1)));
105 }
106
cudbg_read_vpd_reg(struct adapter * padap,u32 addr,u32 len,void * dest)107 static int cudbg_read_vpd_reg(struct adapter *padap, u32 addr, u32 len,
108 void *dest)
109 {
110 int vaddr, rc;
111
112 vaddr = t4_eeprom_ptov(addr, padap->pf, EEPROMPFSIZE);
113 if (vaddr < 0)
114 return vaddr;
115
116 rc = pci_read_vpd(padap->pdev, vaddr, len, dest);
117 if (rc < 0)
118 return rc;
119
120 return 0;
121 }
122
cudbg_mem_desc_cmp(const void * a,const void * b)123 static int cudbg_mem_desc_cmp(const void *a, const void *b)
124 {
125 return ((const struct cudbg_mem_desc *)a)->base -
126 ((const struct cudbg_mem_desc *)b)->base;
127 }
128
cudbg_fill_meminfo(struct adapter * padap,struct cudbg_meminfo * meminfo_buff)129 int cudbg_fill_meminfo(struct adapter *padap,
130 struct cudbg_meminfo *meminfo_buff)
131 {
132 struct cudbg_mem_desc *md;
133 u32 lo, hi, used, alloc;
134 int n, i;
135
136 memset(meminfo_buff->avail, 0,
137 ARRAY_SIZE(meminfo_buff->avail) *
138 sizeof(struct cudbg_mem_desc));
139 memset(meminfo_buff->mem, 0,
140 (ARRAY_SIZE(cudbg_region) + 3) * sizeof(struct cudbg_mem_desc));
141 md = meminfo_buff->mem;
142
143 for (i = 0; i < ARRAY_SIZE(meminfo_buff->mem); i++) {
144 meminfo_buff->mem[i].limit = 0;
145 meminfo_buff->mem[i].idx = i;
146 }
147
148 /* Find and sort the populated memory ranges */
149 i = 0;
150 lo = t4_read_reg(padap, MA_TARGET_MEM_ENABLE_A);
151 if (lo & EDRAM0_ENABLE_F) {
152 hi = t4_read_reg(padap, MA_EDRAM0_BAR_A);
153 meminfo_buff->avail[i].base =
154 cudbg_mbytes_to_bytes(EDRAM0_BASE_G(hi));
155 meminfo_buff->avail[i].limit =
156 meminfo_buff->avail[i].base +
157 cudbg_mbytes_to_bytes(EDRAM0_SIZE_G(hi));
158 meminfo_buff->avail[i].idx = 0;
159 i++;
160 }
161
162 if (lo & EDRAM1_ENABLE_F) {
163 hi = t4_read_reg(padap, MA_EDRAM1_BAR_A);
164 meminfo_buff->avail[i].base =
165 cudbg_mbytes_to_bytes(EDRAM1_BASE_G(hi));
166 meminfo_buff->avail[i].limit =
167 meminfo_buff->avail[i].base +
168 cudbg_mbytes_to_bytes(EDRAM1_SIZE_G(hi));
169 meminfo_buff->avail[i].idx = 1;
170 i++;
171 }
172
173 if (is_t5(padap->params.chip)) {
174 if (lo & EXT_MEM0_ENABLE_F) {
175 hi = t4_read_reg(padap, MA_EXT_MEMORY0_BAR_A);
176 meminfo_buff->avail[i].base =
177 cudbg_mbytes_to_bytes(EXT_MEM_BASE_G(hi));
178 meminfo_buff->avail[i].limit =
179 meminfo_buff->avail[i].base +
180 cudbg_mbytes_to_bytes(EXT_MEM_SIZE_G(hi));
181 meminfo_buff->avail[i].idx = 3;
182 i++;
183 }
184
185 if (lo & EXT_MEM1_ENABLE_F) {
186 hi = t4_read_reg(padap, MA_EXT_MEMORY1_BAR_A);
187 meminfo_buff->avail[i].base =
188 cudbg_mbytes_to_bytes(EXT_MEM1_BASE_G(hi));
189 meminfo_buff->avail[i].limit =
190 meminfo_buff->avail[i].base +
191 cudbg_mbytes_to_bytes(EXT_MEM1_SIZE_G(hi));
192 meminfo_buff->avail[i].idx = 4;
193 i++;
194 }
195 } else {
196 if (lo & EXT_MEM_ENABLE_F) {
197 hi = t4_read_reg(padap, MA_EXT_MEMORY_BAR_A);
198 meminfo_buff->avail[i].base =
199 cudbg_mbytes_to_bytes(EXT_MEM_BASE_G(hi));
200 meminfo_buff->avail[i].limit =
201 meminfo_buff->avail[i].base +
202 cudbg_mbytes_to_bytes(EXT_MEM_SIZE_G(hi));
203 meminfo_buff->avail[i].idx = 2;
204 i++;
205 }
206
207 if (lo & HMA_MUX_F) {
208 hi = t4_read_reg(padap, MA_EXT_MEMORY1_BAR_A);
209 meminfo_buff->avail[i].base =
210 cudbg_mbytes_to_bytes(EXT_MEM1_BASE_G(hi));
211 meminfo_buff->avail[i].limit =
212 meminfo_buff->avail[i].base +
213 cudbg_mbytes_to_bytes(EXT_MEM1_SIZE_G(hi));
214 meminfo_buff->avail[i].idx = 5;
215 i++;
216 }
217 }
218
219 if (!i) /* no memory available */
220 return CUDBG_STATUS_ENTITY_NOT_FOUND;
221
222 meminfo_buff->avail_c = i;
223 sort(meminfo_buff->avail, i, sizeof(struct cudbg_mem_desc),
224 cudbg_mem_desc_cmp, NULL);
225 (md++)->base = t4_read_reg(padap, SGE_DBQ_CTXT_BADDR_A);
226 (md++)->base = t4_read_reg(padap, SGE_IMSG_CTXT_BADDR_A);
227 (md++)->base = t4_read_reg(padap, SGE_FLM_CACHE_BADDR_A);
228 (md++)->base = t4_read_reg(padap, TP_CMM_TCB_BASE_A);
229 (md++)->base = t4_read_reg(padap, TP_CMM_MM_BASE_A);
230 (md++)->base = t4_read_reg(padap, TP_CMM_TIMER_BASE_A);
231 (md++)->base = t4_read_reg(padap, TP_CMM_MM_RX_FLST_BASE_A);
232 (md++)->base = t4_read_reg(padap, TP_CMM_MM_TX_FLST_BASE_A);
233 (md++)->base = t4_read_reg(padap, TP_CMM_MM_PS_FLST_BASE_A);
234
235 /* the next few have explicit upper bounds */
236 md->base = t4_read_reg(padap, TP_PMM_TX_BASE_A);
237 md->limit = md->base - 1 +
238 t4_read_reg(padap, TP_PMM_TX_PAGE_SIZE_A) *
239 PMTXMAXPAGE_G(t4_read_reg(padap, TP_PMM_TX_MAX_PAGE_A));
240 md++;
241
242 md->base = t4_read_reg(padap, TP_PMM_RX_BASE_A);
243 md->limit = md->base - 1 +
244 t4_read_reg(padap, TP_PMM_RX_PAGE_SIZE_A) *
245 PMRXMAXPAGE_G(t4_read_reg(padap, TP_PMM_RX_MAX_PAGE_A));
246 md++;
247
248 if (t4_read_reg(padap, LE_DB_CONFIG_A) & HASHEN_F) {
249 if (CHELSIO_CHIP_VERSION(padap->params.chip) <= CHELSIO_T5) {
250 hi = t4_read_reg(padap, LE_DB_TID_HASHBASE_A) / 4;
251 md->base = t4_read_reg(padap, LE_DB_HASH_TID_BASE_A);
252 } else {
253 hi = t4_read_reg(padap, LE_DB_HASH_TID_BASE_A);
254 md->base = t4_read_reg(padap,
255 LE_DB_HASH_TBL_BASE_ADDR_A);
256 }
257 md->limit = 0;
258 } else {
259 md->base = 0;
260 md->idx = ARRAY_SIZE(cudbg_region); /* hide it */
261 }
262 md++;
263
264 #define ulp_region(reg) do { \
265 md->base = t4_read_reg(padap, ULP_ ## reg ## _LLIMIT_A);\
266 (md++)->limit = t4_read_reg(padap, ULP_ ## reg ## _ULIMIT_A);\
267 } while (0)
268
269 ulp_region(RX_ISCSI);
270 ulp_region(RX_TDDP);
271 ulp_region(TX_TPT);
272 ulp_region(RX_STAG);
273 ulp_region(RX_RQ);
274 ulp_region(RX_RQUDP);
275 ulp_region(RX_PBL);
276 ulp_region(TX_PBL);
277 #undef ulp_region
278 md->base = 0;
279 md->idx = ARRAY_SIZE(cudbg_region);
280 if (!is_t4(padap->params.chip)) {
281 u32 fifo_size = t4_read_reg(padap, SGE_DBVFIFO_SIZE_A);
282 u32 sge_ctrl = t4_read_reg(padap, SGE_CONTROL2_A);
283 u32 size = 0;
284
285 if (is_t5(padap->params.chip)) {
286 if (sge_ctrl & VFIFO_ENABLE_F)
287 size = DBVFIFO_SIZE_G(fifo_size);
288 } else {
289 size = T6_DBVFIFO_SIZE_G(fifo_size);
290 }
291
292 if (size) {
293 md->base = BASEADDR_G(t4_read_reg(padap,
294 SGE_DBVFIFO_BADDR_A));
295 md->limit = md->base + (size << 2) - 1;
296 }
297 }
298
299 md++;
300
301 md->base = t4_read_reg(padap, ULP_RX_CTX_BASE_A);
302 md->limit = 0;
303 md++;
304 md->base = t4_read_reg(padap, ULP_TX_ERR_TABLE_BASE_A);
305 md->limit = 0;
306 md++;
307
308 md->base = padap->vres.ocq.start;
309 if (padap->vres.ocq.size)
310 md->limit = md->base + padap->vres.ocq.size - 1;
311 else
312 md->idx = ARRAY_SIZE(cudbg_region); /* hide it */
313 md++;
314
315 /* add any address-space holes, there can be up to 3 */
316 for (n = 0; n < i - 1; n++)
317 if (meminfo_buff->avail[n].limit <
318 meminfo_buff->avail[n + 1].base)
319 (md++)->base = meminfo_buff->avail[n].limit;
320
321 if (meminfo_buff->avail[n].limit)
322 (md++)->base = meminfo_buff->avail[n].limit;
323
324 n = md - meminfo_buff->mem;
325 meminfo_buff->mem_c = n;
326
327 sort(meminfo_buff->mem, n, sizeof(struct cudbg_mem_desc),
328 cudbg_mem_desc_cmp, NULL);
329
330 lo = t4_read_reg(padap, CIM_SDRAM_BASE_ADDR_A);
331 hi = t4_read_reg(padap, CIM_SDRAM_ADDR_SIZE_A) + lo - 1;
332 meminfo_buff->up_ram_lo = lo;
333 meminfo_buff->up_ram_hi = hi;
334
335 lo = t4_read_reg(padap, CIM_EXTMEM2_BASE_ADDR_A);
336 hi = t4_read_reg(padap, CIM_EXTMEM2_ADDR_SIZE_A) + lo - 1;
337 meminfo_buff->up_extmem2_lo = lo;
338 meminfo_buff->up_extmem2_hi = hi;
339
340 lo = t4_read_reg(padap, TP_PMM_RX_MAX_PAGE_A);
341 for (i = 0, meminfo_buff->free_rx_cnt = 0; i < 2; i++)
342 meminfo_buff->free_rx_cnt +=
343 FREERXPAGECOUNT_G(t4_read_reg(padap,
344 TP_FLM_FREE_RX_CNT_A));
345
346 meminfo_buff->rx_pages_data[0] = PMRXMAXPAGE_G(lo);
347 meminfo_buff->rx_pages_data[1] =
348 t4_read_reg(padap, TP_PMM_RX_PAGE_SIZE_A) >> 10;
349 meminfo_buff->rx_pages_data[2] = (lo & PMRXNUMCHN_F) ? 2 : 1;
350
351 lo = t4_read_reg(padap, TP_PMM_TX_MAX_PAGE_A);
352 hi = t4_read_reg(padap, TP_PMM_TX_PAGE_SIZE_A);
353 for (i = 0, meminfo_buff->free_tx_cnt = 0; i < 4; i++)
354 meminfo_buff->free_tx_cnt +=
355 FREETXPAGECOUNT_G(t4_read_reg(padap,
356 TP_FLM_FREE_TX_CNT_A));
357
358 meminfo_buff->tx_pages_data[0] = PMTXMAXPAGE_G(lo);
359 meminfo_buff->tx_pages_data[1] =
360 hi >= (1 << 20) ? (hi >> 20) : (hi >> 10);
361 meminfo_buff->tx_pages_data[2] =
362 hi >= (1 << 20) ? 'M' : 'K';
363 meminfo_buff->tx_pages_data[3] = 1 << PMTXNUMCHN_G(lo);
364
365 meminfo_buff->p_structs = t4_read_reg(padap, TP_CMM_MM_MAX_PSTRUCT_A);
366 meminfo_buff->p_structs_free_cnt =
367 FREEPSTRUCTCOUNT_G(t4_read_reg(padap, TP_FLM_FREE_PS_CNT_A));
368
369 for (i = 0; i < 4; i++) {
370 if (CHELSIO_CHIP_VERSION(padap->params.chip) > CHELSIO_T5)
371 lo = t4_read_reg(padap,
372 MPS_RX_MAC_BG_PG_CNT0_A + i * 4);
373 else
374 lo = t4_read_reg(padap, MPS_RX_PG_RSV0_A + i * 4);
375 if (is_t5(padap->params.chip)) {
376 used = T5_USED_G(lo);
377 alloc = T5_ALLOC_G(lo);
378 } else {
379 used = USED_G(lo);
380 alloc = ALLOC_G(lo);
381 }
382 meminfo_buff->port_used[i] = used;
383 meminfo_buff->port_alloc[i] = alloc;
384 }
385
386 for (i = 0; i < padap->params.arch.nchan; i++) {
387 if (CHELSIO_CHIP_VERSION(padap->params.chip) > CHELSIO_T5)
388 lo = t4_read_reg(padap,
389 MPS_RX_LPBK_BG_PG_CNT0_A + i * 4);
390 else
391 lo = t4_read_reg(padap, MPS_RX_PG_RSV4_A + i * 4);
392 if (is_t5(padap->params.chip)) {
393 used = T5_USED_G(lo);
394 alloc = T5_ALLOC_G(lo);
395 } else {
396 used = USED_G(lo);
397 alloc = ALLOC_G(lo);
398 }
399 meminfo_buff->loopback_used[i] = used;
400 meminfo_buff->loopback_alloc[i] = alloc;
401 }
402
403 return 0;
404 }
405
cudbg_collect_reg_dump(struct cudbg_init * pdbg_init,struct cudbg_buffer * dbg_buff,struct cudbg_error * cudbg_err)406 int cudbg_collect_reg_dump(struct cudbg_init *pdbg_init,
407 struct cudbg_buffer *dbg_buff,
408 struct cudbg_error *cudbg_err)
409 {
410 struct adapter *padap = pdbg_init->adap;
411 struct cudbg_buffer temp_buff = { 0 };
412 u32 buf_size = 0;
413 int rc = 0;
414
415 if (is_t4(padap->params.chip))
416 buf_size = T4_REGMAP_SIZE;
417 else if (is_t5(padap->params.chip) || is_t6(padap->params.chip))
418 buf_size = T5_REGMAP_SIZE;
419
420 rc = cudbg_get_buff(pdbg_init, dbg_buff, buf_size, &temp_buff);
421 if (rc)
422 return rc;
423 t4_get_regs(padap, (void *)temp_buff.data, temp_buff.size);
424 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
425 }
426
cudbg_collect_fw_devlog(struct cudbg_init * pdbg_init,struct cudbg_buffer * dbg_buff,struct cudbg_error * cudbg_err)427 int cudbg_collect_fw_devlog(struct cudbg_init *pdbg_init,
428 struct cudbg_buffer *dbg_buff,
429 struct cudbg_error *cudbg_err)
430 {
431 struct adapter *padap = pdbg_init->adap;
432 struct cudbg_buffer temp_buff = { 0 };
433 struct devlog_params *dparams;
434 int rc = 0;
435
436 rc = t4_init_devlog_params(padap);
437 if (rc < 0) {
438 cudbg_err->sys_err = rc;
439 return rc;
440 }
441
442 dparams = &padap->params.devlog;
443 rc = cudbg_get_buff(pdbg_init, dbg_buff, dparams->size, &temp_buff);
444 if (rc)
445 return rc;
446
447 /* Collect FW devlog */
448 if (dparams->start != 0) {
449 spin_lock(&padap->win0_lock);
450 rc = t4_memory_rw(padap, padap->params.drv_memwin,
451 dparams->memtype, dparams->start,
452 dparams->size,
453 (__be32 *)(char *)temp_buff.data,
454 1);
455 spin_unlock(&padap->win0_lock);
456 if (rc) {
457 cudbg_err->sys_err = rc;
458 cudbg_put_buff(pdbg_init, &temp_buff);
459 return rc;
460 }
461 }
462 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
463 }
464
cudbg_collect_cim_la(struct cudbg_init * pdbg_init,struct cudbg_buffer * dbg_buff,struct cudbg_error * cudbg_err)465 int cudbg_collect_cim_la(struct cudbg_init *pdbg_init,
466 struct cudbg_buffer *dbg_buff,
467 struct cudbg_error *cudbg_err)
468 {
469 struct adapter *padap = pdbg_init->adap;
470 struct cudbg_buffer temp_buff = { 0 };
471 int size, rc;
472 u32 cfg = 0;
473
474 if (is_t6(padap->params.chip)) {
475 size = padap->params.cim_la_size / 10 + 1;
476 size *= 10 * sizeof(u32);
477 } else {
478 size = padap->params.cim_la_size / 8;
479 size *= 8 * sizeof(u32);
480 }
481
482 size += sizeof(cfg);
483 rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff);
484 if (rc)
485 return rc;
486
487 rc = t4_cim_read(padap, UP_UP_DBG_LA_CFG_A, 1, &cfg);
488 if (rc) {
489 cudbg_err->sys_err = rc;
490 cudbg_put_buff(pdbg_init, &temp_buff);
491 return rc;
492 }
493
494 memcpy((char *)temp_buff.data, &cfg, sizeof(cfg));
495 rc = t4_cim_read_la(padap,
496 (u32 *)((char *)temp_buff.data + sizeof(cfg)),
497 NULL);
498 if (rc < 0) {
499 cudbg_err->sys_err = rc;
500 cudbg_put_buff(pdbg_init, &temp_buff);
501 return rc;
502 }
503 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
504 }
505
cudbg_collect_cim_ma_la(struct cudbg_init * pdbg_init,struct cudbg_buffer * dbg_buff,struct cudbg_error * cudbg_err)506 int cudbg_collect_cim_ma_la(struct cudbg_init *pdbg_init,
507 struct cudbg_buffer *dbg_buff,
508 struct cudbg_error *cudbg_err)
509 {
510 struct adapter *padap = pdbg_init->adap;
511 struct cudbg_buffer temp_buff = { 0 };
512 int size, rc;
513
514 size = 2 * CIM_MALA_SIZE * 5 * sizeof(u32);
515 rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff);
516 if (rc)
517 return rc;
518
519 t4_cim_read_ma_la(padap,
520 (u32 *)temp_buff.data,
521 (u32 *)((char *)temp_buff.data +
522 5 * CIM_MALA_SIZE));
523 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
524 }
525
cudbg_collect_cim_qcfg(struct cudbg_init * pdbg_init,struct cudbg_buffer * dbg_buff,struct cudbg_error * cudbg_err)526 int cudbg_collect_cim_qcfg(struct cudbg_init *pdbg_init,
527 struct cudbg_buffer *dbg_buff,
528 struct cudbg_error *cudbg_err)
529 {
530 struct adapter *padap = pdbg_init->adap;
531 struct cudbg_buffer temp_buff = { 0 };
532 struct cudbg_cim_qcfg *cim_qcfg_data;
533 int rc;
534
535 rc = cudbg_get_buff(pdbg_init, dbg_buff, sizeof(struct cudbg_cim_qcfg),
536 &temp_buff);
537 if (rc)
538 return rc;
539
540 cim_qcfg_data = (struct cudbg_cim_qcfg *)temp_buff.data;
541 cim_qcfg_data->chip = padap->params.chip;
542 rc = t4_cim_read(padap, UP_IBQ_0_RDADDR_A,
543 ARRAY_SIZE(cim_qcfg_data->stat), cim_qcfg_data->stat);
544 if (rc) {
545 cudbg_err->sys_err = rc;
546 cudbg_put_buff(pdbg_init, &temp_buff);
547 return rc;
548 }
549
550 rc = t4_cim_read(padap, UP_OBQ_0_REALADDR_A,
551 ARRAY_SIZE(cim_qcfg_data->obq_wr),
552 cim_qcfg_data->obq_wr);
553 if (rc) {
554 cudbg_err->sys_err = rc;
555 cudbg_put_buff(pdbg_init, &temp_buff);
556 return rc;
557 }
558
559 t4_read_cimq_cfg(padap, cim_qcfg_data->base, cim_qcfg_data->size,
560 cim_qcfg_data->thres);
561 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
562 }
563
cudbg_read_cim_ibq(struct cudbg_init * pdbg_init,struct cudbg_buffer * dbg_buff,struct cudbg_error * cudbg_err,int qid)564 static int cudbg_read_cim_ibq(struct cudbg_init *pdbg_init,
565 struct cudbg_buffer *dbg_buff,
566 struct cudbg_error *cudbg_err, int qid)
567 {
568 struct adapter *padap = pdbg_init->adap;
569 struct cudbg_buffer temp_buff = { 0 };
570 int no_of_read_words, rc = 0;
571 u32 qsize;
572
573 /* collect CIM IBQ */
574 qsize = CIM_IBQ_SIZE * 4 * sizeof(u32);
575 rc = cudbg_get_buff(pdbg_init, dbg_buff, qsize, &temp_buff);
576 if (rc)
577 return rc;
578
579 /* t4_read_cim_ibq will return no. of read words or error */
580 no_of_read_words = t4_read_cim_ibq(padap, qid,
581 (u32 *)temp_buff.data, qsize);
582 /* no_of_read_words is less than or equal to 0 means error */
583 if (no_of_read_words <= 0) {
584 if (!no_of_read_words)
585 rc = CUDBG_SYSTEM_ERROR;
586 else
587 rc = no_of_read_words;
588 cudbg_err->sys_err = rc;
589 cudbg_put_buff(pdbg_init, &temp_buff);
590 return rc;
591 }
592 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
593 }
594
cudbg_collect_cim_ibq_tp0(struct cudbg_init * pdbg_init,struct cudbg_buffer * dbg_buff,struct cudbg_error * cudbg_err)595 int cudbg_collect_cim_ibq_tp0(struct cudbg_init *pdbg_init,
596 struct cudbg_buffer *dbg_buff,
597 struct cudbg_error *cudbg_err)
598 {
599 return cudbg_read_cim_ibq(pdbg_init, dbg_buff, cudbg_err, 0);
600 }
601
cudbg_collect_cim_ibq_tp1(struct cudbg_init * pdbg_init,struct cudbg_buffer * dbg_buff,struct cudbg_error * cudbg_err)602 int cudbg_collect_cim_ibq_tp1(struct cudbg_init *pdbg_init,
603 struct cudbg_buffer *dbg_buff,
604 struct cudbg_error *cudbg_err)
605 {
606 return cudbg_read_cim_ibq(pdbg_init, dbg_buff, cudbg_err, 1);
607 }
608
cudbg_collect_cim_ibq_ulp(struct cudbg_init * pdbg_init,struct cudbg_buffer * dbg_buff,struct cudbg_error * cudbg_err)609 int cudbg_collect_cim_ibq_ulp(struct cudbg_init *pdbg_init,
610 struct cudbg_buffer *dbg_buff,
611 struct cudbg_error *cudbg_err)
612 {
613 return cudbg_read_cim_ibq(pdbg_init, dbg_buff, cudbg_err, 2);
614 }
615
cudbg_collect_cim_ibq_sge0(struct cudbg_init * pdbg_init,struct cudbg_buffer * dbg_buff,struct cudbg_error * cudbg_err)616 int cudbg_collect_cim_ibq_sge0(struct cudbg_init *pdbg_init,
617 struct cudbg_buffer *dbg_buff,
618 struct cudbg_error *cudbg_err)
619 {
620 return cudbg_read_cim_ibq(pdbg_init, dbg_buff, cudbg_err, 3);
621 }
622
cudbg_collect_cim_ibq_sge1(struct cudbg_init * pdbg_init,struct cudbg_buffer * dbg_buff,struct cudbg_error * cudbg_err)623 int cudbg_collect_cim_ibq_sge1(struct cudbg_init *pdbg_init,
624 struct cudbg_buffer *dbg_buff,
625 struct cudbg_error *cudbg_err)
626 {
627 return cudbg_read_cim_ibq(pdbg_init, dbg_buff, cudbg_err, 4);
628 }
629
cudbg_collect_cim_ibq_ncsi(struct cudbg_init * pdbg_init,struct cudbg_buffer * dbg_buff,struct cudbg_error * cudbg_err)630 int cudbg_collect_cim_ibq_ncsi(struct cudbg_init *pdbg_init,
631 struct cudbg_buffer *dbg_buff,
632 struct cudbg_error *cudbg_err)
633 {
634 return cudbg_read_cim_ibq(pdbg_init, dbg_buff, cudbg_err, 5);
635 }
636
cudbg_cim_obq_size(struct adapter * padap,int qid)637 u32 cudbg_cim_obq_size(struct adapter *padap, int qid)
638 {
639 u32 value;
640
641 t4_write_reg(padap, CIM_QUEUE_CONFIG_REF_A, OBQSELECT_F |
642 QUENUMSELECT_V(qid));
643 value = t4_read_reg(padap, CIM_QUEUE_CONFIG_CTRL_A);
644 value = CIMQSIZE_G(value) * 64; /* size in number of words */
645 return value * sizeof(u32);
646 }
647
cudbg_read_cim_obq(struct cudbg_init * pdbg_init,struct cudbg_buffer * dbg_buff,struct cudbg_error * cudbg_err,int qid)648 static int cudbg_read_cim_obq(struct cudbg_init *pdbg_init,
649 struct cudbg_buffer *dbg_buff,
650 struct cudbg_error *cudbg_err, int qid)
651 {
652 struct adapter *padap = pdbg_init->adap;
653 struct cudbg_buffer temp_buff = { 0 };
654 int no_of_read_words, rc = 0;
655 u32 qsize;
656
657 /* collect CIM OBQ */
658 qsize = cudbg_cim_obq_size(padap, qid);
659 rc = cudbg_get_buff(pdbg_init, dbg_buff, qsize, &temp_buff);
660 if (rc)
661 return rc;
662
663 /* t4_read_cim_obq will return no. of read words or error */
664 no_of_read_words = t4_read_cim_obq(padap, qid,
665 (u32 *)temp_buff.data, qsize);
666 /* no_of_read_words is less than or equal to 0 means error */
667 if (no_of_read_words <= 0) {
668 if (!no_of_read_words)
669 rc = CUDBG_SYSTEM_ERROR;
670 else
671 rc = no_of_read_words;
672 cudbg_err->sys_err = rc;
673 cudbg_put_buff(pdbg_init, &temp_buff);
674 return rc;
675 }
676 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
677 }
678
cudbg_collect_cim_obq_ulp0(struct cudbg_init * pdbg_init,struct cudbg_buffer * dbg_buff,struct cudbg_error * cudbg_err)679 int cudbg_collect_cim_obq_ulp0(struct cudbg_init *pdbg_init,
680 struct cudbg_buffer *dbg_buff,
681 struct cudbg_error *cudbg_err)
682 {
683 return cudbg_read_cim_obq(pdbg_init, dbg_buff, cudbg_err, 0);
684 }
685
cudbg_collect_cim_obq_ulp1(struct cudbg_init * pdbg_init,struct cudbg_buffer * dbg_buff,struct cudbg_error * cudbg_err)686 int cudbg_collect_cim_obq_ulp1(struct cudbg_init *pdbg_init,
687 struct cudbg_buffer *dbg_buff,
688 struct cudbg_error *cudbg_err)
689 {
690 return cudbg_read_cim_obq(pdbg_init, dbg_buff, cudbg_err, 1);
691 }
692
cudbg_collect_cim_obq_ulp2(struct cudbg_init * pdbg_init,struct cudbg_buffer * dbg_buff,struct cudbg_error * cudbg_err)693 int cudbg_collect_cim_obq_ulp2(struct cudbg_init *pdbg_init,
694 struct cudbg_buffer *dbg_buff,
695 struct cudbg_error *cudbg_err)
696 {
697 return cudbg_read_cim_obq(pdbg_init, dbg_buff, cudbg_err, 2);
698 }
699
cudbg_collect_cim_obq_ulp3(struct cudbg_init * pdbg_init,struct cudbg_buffer * dbg_buff,struct cudbg_error * cudbg_err)700 int cudbg_collect_cim_obq_ulp3(struct cudbg_init *pdbg_init,
701 struct cudbg_buffer *dbg_buff,
702 struct cudbg_error *cudbg_err)
703 {
704 return cudbg_read_cim_obq(pdbg_init, dbg_buff, cudbg_err, 3);
705 }
706
cudbg_collect_cim_obq_sge(struct cudbg_init * pdbg_init,struct cudbg_buffer * dbg_buff,struct cudbg_error * cudbg_err)707 int cudbg_collect_cim_obq_sge(struct cudbg_init *pdbg_init,
708 struct cudbg_buffer *dbg_buff,
709 struct cudbg_error *cudbg_err)
710 {
711 return cudbg_read_cim_obq(pdbg_init, dbg_buff, cudbg_err, 4);
712 }
713
cudbg_collect_cim_obq_ncsi(struct cudbg_init * pdbg_init,struct cudbg_buffer * dbg_buff,struct cudbg_error * cudbg_err)714 int cudbg_collect_cim_obq_ncsi(struct cudbg_init *pdbg_init,
715 struct cudbg_buffer *dbg_buff,
716 struct cudbg_error *cudbg_err)
717 {
718 return cudbg_read_cim_obq(pdbg_init, dbg_buff, cudbg_err, 5);
719 }
720
cudbg_collect_obq_sge_rx_q0(struct cudbg_init * pdbg_init,struct cudbg_buffer * dbg_buff,struct cudbg_error * cudbg_err)721 int cudbg_collect_obq_sge_rx_q0(struct cudbg_init *pdbg_init,
722 struct cudbg_buffer *dbg_buff,
723 struct cudbg_error *cudbg_err)
724 {
725 return cudbg_read_cim_obq(pdbg_init, dbg_buff, cudbg_err, 6);
726 }
727
cudbg_collect_obq_sge_rx_q1(struct cudbg_init * pdbg_init,struct cudbg_buffer * dbg_buff,struct cudbg_error * cudbg_err)728 int cudbg_collect_obq_sge_rx_q1(struct cudbg_init *pdbg_init,
729 struct cudbg_buffer *dbg_buff,
730 struct cudbg_error *cudbg_err)
731 {
732 return cudbg_read_cim_obq(pdbg_init, dbg_buff, cudbg_err, 7);
733 }
734
cudbg_meminfo_get_mem_index(struct adapter * padap,struct cudbg_meminfo * mem_info,u8 mem_type,u8 * idx)735 static int cudbg_meminfo_get_mem_index(struct adapter *padap,
736 struct cudbg_meminfo *mem_info,
737 u8 mem_type, u8 *idx)
738 {
739 u8 i, flag;
740
741 switch (mem_type) {
742 case MEM_EDC0:
743 flag = EDC0_FLAG;
744 break;
745 case MEM_EDC1:
746 flag = EDC1_FLAG;
747 break;
748 case MEM_MC0:
749 /* Some T5 cards have both MC0 and MC1. */
750 flag = is_t5(padap->params.chip) ? MC0_FLAG : MC_FLAG;
751 break;
752 case MEM_MC1:
753 flag = MC1_FLAG;
754 break;
755 case MEM_HMA:
756 flag = HMA_FLAG;
757 break;
758 default:
759 return CUDBG_STATUS_ENTITY_NOT_FOUND;
760 }
761
762 for (i = 0; i < mem_info->avail_c; i++) {
763 if (mem_info->avail[i].idx == flag) {
764 *idx = i;
765 return 0;
766 }
767 }
768
769 return CUDBG_STATUS_ENTITY_NOT_FOUND;
770 }
771
772 /* Fetch the @region_name's start and end from @meminfo. */
cudbg_get_mem_region(struct adapter * padap,struct cudbg_meminfo * meminfo,u8 mem_type,const char * region_name,struct cudbg_mem_desc * mem_desc)773 static int cudbg_get_mem_region(struct adapter *padap,
774 struct cudbg_meminfo *meminfo,
775 u8 mem_type, const char *region_name,
776 struct cudbg_mem_desc *mem_desc)
777 {
778 u8 mc, found = 0;
779 u32 i, idx = 0;
780 int rc;
781
782 rc = cudbg_meminfo_get_mem_index(padap, meminfo, mem_type, &mc);
783 if (rc)
784 return rc;
785
786 for (i = 0; i < ARRAY_SIZE(cudbg_region); i++) {
787 if (!strcmp(cudbg_region[i], region_name)) {
788 found = 1;
789 idx = i;
790 break;
791 }
792 }
793 if (!found)
794 return -EINVAL;
795
796 found = 0;
797 for (i = 0; i < meminfo->mem_c; i++) {
798 if (meminfo->mem[i].idx >= ARRAY_SIZE(cudbg_region))
799 continue; /* Skip holes */
800
801 if (!(meminfo->mem[i].limit))
802 meminfo->mem[i].limit =
803 i < meminfo->mem_c - 1 ?
804 meminfo->mem[i + 1].base - 1 : ~0;
805
806 if (meminfo->mem[i].idx == idx) {
807 /* Check if the region exists in @mem_type memory */
808 if (meminfo->mem[i].base < meminfo->avail[mc].base &&
809 meminfo->mem[i].limit < meminfo->avail[mc].base)
810 return -EINVAL;
811
812 if (meminfo->mem[i].base > meminfo->avail[mc].limit)
813 return -EINVAL;
814
815 memcpy(mem_desc, &meminfo->mem[i],
816 sizeof(struct cudbg_mem_desc));
817 found = 1;
818 break;
819 }
820 }
821 if (!found)
822 return -EINVAL;
823
824 return 0;
825 }
826
827 /* Fetch and update the start and end of the requested memory region w.r.t 0
828 * in the corresponding EDC/MC/HMA.
829 */
cudbg_get_mem_relative(struct adapter * padap,struct cudbg_meminfo * meminfo,u8 mem_type,u32 * out_base,u32 * out_end)830 static int cudbg_get_mem_relative(struct adapter *padap,
831 struct cudbg_meminfo *meminfo,
832 u8 mem_type, u32 *out_base, u32 *out_end)
833 {
834 u8 mc_idx;
835 int rc;
836
837 rc = cudbg_meminfo_get_mem_index(padap, meminfo, mem_type, &mc_idx);
838 if (rc)
839 return rc;
840
841 if (*out_base < meminfo->avail[mc_idx].base)
842 *out_base = 0;
843 else
844 *out_base -= meminfo->avail[mc_idx].base;
845
846 if (*out_end > meminfo->avail[mc_idx].limit)
847 *out_end = meminfo->avail[mc_idx].limit;
848 else
849 *out_end -= meminfo->avail[mc_idx].base;
850
851 return 0;
852 }
853
854 /* Get TX and RX Payload region */
cudbg_get_payload_range(struct adapter * padap,u8 mem_type,const char * region_name,struct cudbg_region_info * payload)855 static int cudbg_get_payload_range(struct adapter *padap, u8 mem_type,
856 const char *region_name,
857 struct cudbg_region_info *payload)
858 {
859 struct cudbg_mem_desc mem_desc = { 0 };
860 struct cudbg_meminfo meminfo;
861 int rc;
862
863 rc = cudbg_fill_meminfo(padap, &meminfo);
864 if (rc)
865 return rc;
866
867 rc = cudbg_get_mem_region(padap, &meminfo, mem_type, region_name,
868 &mem_desc);
869 if (rc) {
870 payload->exist = false;
871 return 0;
872 }
873
874 payload->exist = true;
875 payload->start = mem_desc.base;
876 payload->end = mem_desc.limit;
877
878 return cudbg_get_mem_relative(padap, &meminfo, mem_type,
879 &payload->start, &payload->end);
880 }
881
cudbg_memory_read(struct cudbg_init * pdbg_init,int win,int mtype,u32 addr,u32 len,void * hbuf)882 static int cudbg_memory_read(struct cudbg_init *pdbg_init, int win,
883 int mtype, u32 addr, u32 len, void *hbuf)
884 {
885 u32 win_pf, memoffset, mem_aperture, mem_base;
886 struct adapter *adap = pdbg_init->adap;
887 u32 pos, offset, resid;
888 u32 *res_buf;
889 u64 *buf;
890 int ret;
891
892 /* Argument sanity checks ...
893 */
894 if (addr & 0x3 || (uintptr_t)hbuf & 0x3)
895 return -EINVAL;
896
897 buf = (u64 *)hbuf;
898
899 /* Try to do 64-bit reads. Residual will be handled later. */
900 resid = len & 0x7;
901 len -= resid;
902
903 ret = t4_memory_rw_init(adap, win, mtype, &memoffset, &mem_base,
904 &mem_aperture);
905 if (ret)
906 return ret;
907
908 addr = addr + memoffset;
909 win_pf = is_t4(adap->params.chip) ? 0 : PFNUM_V(adap->pf);
910
911 pos = addr & ~(mem_aperture - 1);
912 offset = addr - pos;
913
914 /* Set up initial PCI-E Memory Window to cover the start of our
915 * transfer.
916 */
917 t4_memory_update_win(adap, win, pos | win_pf);
918
919 /* Transfer data from the adapter */
920 while (len > 0) {
921 *buf++ = le64_to_cpu((__force __le64)
922 t4_read_reg64(adap, mem_base + offset));
923 offset += sizeof(u64);
924 len -= sizeof(u64);
925
926 /* If we've reached the end of our current window aperture,
927 * move the PCI-E Memory Window on to the next.
928 */
929 if (offset == mem_aperture) {
930 pos += mem_aperture;
931 offset = 0;
932 t4_memory_update_win(adap, win, pos | win_pf);
933 }
934 }
935
936 res_buf = (u32 *)buf;
937 /* Read residual in 32-bit multiples */
938 while (resid > sizeof(u32)) {
939 *res_buf++ = le32_to_cpu((__force __le32)
940 t4_read_reg(adap, mem_base + offset));
941 offset += sizeof(u32);
942 resid -= sizeof(u32);
943
944 /* If we've reached the end of our current window aperture,
945 * move the PCI-E Memory Window on to the next.
946 */
947 if (offset == mem_aperture) {
948 pos += mem_aperture;
949 offset = 0;
950 t4_memory_update_win(adap, win, pos | win_pf);
951 }
952 }
953
954 /* Transfer residual < 32-bits */
955 if (resid)
956 t4_memory_rw_residual(adap, resid, mem_base + offset,
957 (u8 *)res_buf, T4_MEMORY_READ);
958
959 return 0;
960 }
961
962 #define CUDBG_YIELD_ITERATION 256
963
cudbg_read_fw_mem(struct cudbg_init * pdbg_init,struct cudbg_buffer * dbg_buff,u8 mem_type,unsigned long tot_len,struct cudbg_error * cudbg_err)964 static int cudbg_read_fw_mem(struct cudbg_init *pdbg_init,
965 struct cudbg_buffer *dbg_buff, u8 mem_type,
966 unsigned long tot_len,
967 struct cudbg_error *cudbg_err)
968 {
969 static const char * const region_name[] = { "Tx payload:",
970 "Rx payload:" };
971 unsigned long bytes, bytes_left, bytes_read = 0;
972 struct adapter *padap = pdbg_init->adap;
973 struct cudbg_buffer temp_buff = { 0 };
974 struct cudbg_region_info payload[2];
975 u32 yield_count = 0;
976 int rc = 0;
977 u8 i;
978
979 /* Get TX/RX Payload region range if they exist */
980 memset(payload, 0, sizeof(payload));
981 for (i = 0; i < ARRAY_SIZE(region_name); i++) {
982 rc = cudbg_get_payload_range(padap, mem_type, region_name[i],
983 &payload[i]);
984 if (rc)
985 return rc;
986
987 if (payload[i].exist) {
988 /* Align start and end to avoid wrap around */
989 payload[i].start = roundup(payload[i].start,
990 CUDBG_CHUNK_SIZE);
991 payload[i].end = rounddown(payload[i].end,
992 CUDBG_CHUNK_SIZE);
993 }
994 }
995
996 bytes_left = tot_len;
997 while (bytes_left > 0) {
998 /* As MC size is huge and read through PIO access, this
999 * loop will hold cpu for a longer time. OS may think that
1000 * the process is hanged and will generate CPU stall traces.
1001 * So yield the cpu regularly.
1002 */
1003 yield_count++;
1004 if (!(yield_count % CUDBG_YIELD_ITERATION))
1005 schedule();
1006
1007 bytes = min_t(unsigned long, bytes_left,
1008 (unsigned long)CUDBG_CHUNK_SIZE);
1009 rc = cudbg_get_buff(pdbg_init, dbg_buff, bytes, &temp_buff);
1010 if (rc)
1011 return rc;
1012
1013 for (i = 0; i < ARRAY_SIZE(payload); i++)
1014 if (payload[i].exist &&
1015 bytes_read >= payload[i].start &&
1016 bytes_read + bytes <= payload[i].end)
1017 /* TX and RX Payload regions can't overlap */
1018 goto skip_read;
1019
1020 spin_lock(&padap->win0_lock);
1021 rc = cudbg_memory_read(pdbg_init, MEMWIN_NIC, mem_type,
1022 bytes_read, bytes, temp_buff.data);
1023 spin_unlock(&padap->win0_lock);
1024 if (rc) {
1025 cudbg_err->sys_err = rc;
1026 cudbg_put_buff(pdbg_init, &temp_buff);
1027 return rc;
1028 }
1029
1030 skip_read:
1031 bytes_left -= bytes;
1032 bytes_read += bytes;
1033 rc = cudbg_write_and_release_buff(pdbg_init, &temp_buff,
1034 dbg_buff);
1035 if (rc) {
1036 cudbg_put_buff(pdbg_init, &temp_buff);
1037 return rc;
1038 }
1039 }
1040 return rc;
1041 }
1042
cudbg_t4_fwcache(struct cudbg_init * pdbg_init,struct cudbg_error * cudbg_err)1043 static void cudbg_t4_fwcache(struct cudbg_init *pdbg_init,
1044 struct cudbg_error *cudbg_err)
1045 {
1046 struct adapter *padap = pdbg_init->adap;
1047 int rc;
1048
1049 if (is_fw_attached(pdbg_init)) {
1050 /* Flush uP dcache before reading edcX/mcX */
1051 rc = t4_fwcache(padap, FW_PARAM_DEV_FWCACHE_FLUSH);
1052 if (rc)
1053 cudbg_err->sys_warn = rc;
1054 }
1055 }
1056
cudbg_mem_region_size(struct cudbg_init * pdbg_init,struct cudbg_error * cudbg_err,u8 mem_type)1057 static unsigned long cudbg_mem_region_size(struct cudbg_init *pdbg_init,
1058 struct cudbg_error *cudbg_err,
1059 u8 mem_type)
1060 {
1061 struct adapter *padap = pdbg_init->adap;
1062 struct cudbg_meminfo mem_info;
1063 u8 mc_idx;
1064 int rc;
1065
1066 memset(&mem_info, 0, sizeof(struct cudbg_meminfo));
1067 rc = cudbg_fill_meminfo(padap, &mem_info);
1068 if (rc)
1069 return rc;
1070
1071 cudbg_t4_fwcache(pdbg_init, cudbg_err);
1072 rc = cudbg_meminfo_get_mem_index(padap, &mem_info, mem_type, &mc_idx);
1073 if (rc)
1074 return rc;
1075
1076 return mem_info.avail[mc_idx].limit - mem_info.avail[mc_idx].base;
1077 }
1078
cudbg_collect_mem_region(struct cudbg_init * pdbg_init,struct cudbg_buffer * dbg_buff,struct cudbg_error * cudbg_err,u8 mem_type)1079 static int cudbg_collect_mem_region(struct cudbg_init *pdbg_init,
1080 struct cudbg_buffer *dbg_buff,
1081 struct cudbg_error *cudbg_err,
1082 u8 mem_type)
1083 {
1084 unsigned long size = cudbg_mem_region_size(pdbg_init, cudbg_err, mem_type);
1085
1086 return cudbg_read_fw_mem(pdbg_init, dbg_buff, mem_type, size,
1087 cudbg_err);
1088 }
1089
cudbg_collect_edc0_meminfo(struct cudbg_init * pdbg_init,struct cudbg_buffer * dbg_buff,struct cudbg_error * cudbg_err)1090 int cudbg_collect_edc0_meminfo(struct cudbg_init *pdbg_init,
1091 struct cudbg_buffer *dbg_buff,
1092 struct cudbg_error *cudbg_err)
1093 {
1094 return cudbg_collect_mem_region(pdbg_init, dbg_buff, cudbg_err,
1095 MEM_EDC0);
1096 }
1097
cudbg_collect_edc1_meminfo(struct cudbg_init * pdbg_init,struct cudbg_buffer * dbg_buff,struct cudbg_error * cudbg_err)1098 int cudbg_collect_edc1_meminfo(struct cudbg_init *pdbg_init,
1099 struct cudbg_buffer *dbg_buff,
1100 struct cudbg_error *cudbg_err)
1101 {
1102 return cudbg_collect_mem_region(pdbg_init, dbg_buff, cudbg_err,
1103 MEM_EDC1);
1104 }
1105
cudbg_collect_mc0_meminfo(struct cudbg_init * pdbg_init,struct cudbg_buffer * dbg_buff,struct cudbg_error * cudbg_err)1106 int cudbg_collect_mc0_meminfo(struct cudbg_init *pdbg_init,
1107 struct cudbg_buffer *dbg_buff,
1108 struct cudbg_error *cudbg_err)
1109 {
1110 return cudbg_collect_mem_region(pdbg_init, dbg_buff, cudbg_err,
1111 MEM_MC0);
1112 }
1113
cudbg_collect_mc1_meminfo(struct cudbg_init * pdbg_init,struct cudbg_buffer * dbg_buff,struct cudbg_error * cudbg_err)1114 int cudbg_collect_mc1_meminfo(struct cudbg_init *pdbg_init,
1115 struct cudbg_buffer *dbg_buff,
1116 struct cudbg_error *cudbg_err)
1117 {
1118 return cudbg_collect_mem_region(pdbg_init, dbg_buff, cudbg_err,
1119 MEM_MC1);
1120 }
1121
cudbg_collect_hma_meminfo(struct cudbg_init * pdbg_init,struct cudbg_buffer * dbg_buff,struct cudbg_error * cudbg_err)1122 int cudbg_collect_hma_meminfo(struct cudbg_init *pdbg_init,
1123 struct cudbg_buffer *dbg_buff,
1124 struct cudbg_error *cudbg_err)
1125 {
1126 return cudbg_collect_mem_region(pdbg_init, dbg_buff, cudbg_err,
1127 MEM_HMA);
1128 }
1129
cudbg_collect_rss(struct cudbg_init * pdbg_init,struct cudbg_buffer * dbg_buff,struct cudbg_error * cudbg_err)1130 int cudbg_collect_rss(struct cudbg_init *pdbg_init,
1131 struct cudbg_buffer *dbg_buff,
1132 struct cudbg_error *cudbg_err)
1133 {
1134 struct adapter *padap = pdbg_init->adap;
1135 struct cudbg_buffer temp_buff = { 0 };
1136 int rc, nentries;
1137
1138 nentries = t4_chip_rss_size(padap);
1139 rc = cudbg_get_buff(pdbg_init, dbg_buff, nentries * sizeof(u16),
1140 &temp_buff);
1141 if (rc)
1142 return rc;
1143
1144 rc = t4_read_rss(padap, (u16 *)temp_buff.data);
1145 if (rc) {
1146 cudbg_err->sys_err = rc;
1147 cudbg_put_buff(pdbg_init, &temp_buff);
1148 return rc;
1149 }
1150 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
1151 }
1152
cudbg_collect_rss_vf_config(struct cudbg_init * pdbg_init,struct cudbg_buffer * dbg_buff,struct cudbg_error * cudbg_err)1153 int cudbg_collect_rss_vf_config(struct cudbg_init *pdbg_init,
1154 struct cudbg_buffer *dbg_buff,
1155 struct cudbg_error *cudbg_err)
1156 {
1157 struct adapter *padap = pdbg_init->adap;
1158 struct cudbg_buffer temp_buff = { 0 };
1159 struct cudbg_rss_vf_conf *vfconf;
1160 int vf, rc, vf_count;
1161
1162 vf_count = padap->params.arch.vfcount;
1163 rc = cudbg_get_buff(pdbg_init, dbg_buff,
1164 vf_count * sizeof(struct cudbg_rss_vf_conf),
1165 &temp_buff);
1166 if (rc)
1167 return rc;
1168
1169 vfconf = (struct cudbg_rss_vf_conf *)temp_buff.data;
1170 for (vf = 0; vf < vf_count; vf++)
1171 t4_read_rss_vf_config(padap, vf, &vfconf[vf].rss_vf_vfl,
1172 &vfconf[vf].rss_vf_vfh, true);
1173 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
1174 }
1175
cudbg_collect_path_mtu(struct cudbg_init * pdbg_init,struct cudbg_buffer * dbg_buff,struct cudbg_error * cudbg_err)1176 int cudbg_collect_path_mtu(struct cudbg_init *pdbg_init,
1177 struct cudbg_buffer *dbg_buff,
1178 struct cudbg_error *cudbg_err)
1179 {
1180 struct adapter *padap = pdbg_init->adap;
1181 struct cudbg_buffer temp_buff = { 0 };
1182 int rc;
1183
1184 rc = cudbg_get_buff(pdbg_init, dbg_buff, NMTUS * sizeof(u16),
1185 &temp_buff);
1186 if (rc)
1187 return rc;
1188
1189 t4_read_mtu_tbl(padap, (u16 *)temp_buff.data, NULL);
1190 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
1191 }
1192
cudbg_collect_pm_stats(struct cudbg_init * pdbg_init,struct cudbg_buffer * dbg_buff,struct cudbg_error * cudbg_err)1193 int cudbg_collect_pm_stats(struct cudbg_init *pdbg_init,
1194 struct cudbg_buffer *dbg_buff,
1195 struct cudbg_error *cudbg_err)
1196 {
1197 struct adapter *padap = pdbg_init->adap;
1198 struct cudbg_buffer temp_buff = { 0 };
1199 struct cudbg_pm_stats *pm_stats_buff;
1200 int rc;
1201
1202 rc = cudbg_get_buff(pdbg_init, dbg_buff, sizeof(struct cudbg_pm_stats),
1203 &temp_buff);
1204 if (rc)
1205 return rc;
1206
1207 pm_stats_buff = (struct cudbg_pm_stats *)temp_buff.data;
1208 t4_pmtx_get_stats(padap, pm_stats_buff->tx_cnt, pm_stats_buff->tx_cyc);
1209 t4_pmrx_get_stats(padap, pm_stats_buff->rx_cnt, pm_stats_buff->rx_cyc);
1210 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
1211 }
1212
cudbg_collect_hw_sched(struct cudbg_init * pdbg_init,struct cudbg_buffer * dbg_buff,struct cudbg_error * cudbg_err)1213 int cudbg_collect_hw_sched(struct cudbg_init *pdbg_init,
1214 struct cudbg_buffer *dbg_buff,
1215 struct cudbg_error *cudbg_err)
1216 {
1217 struct adapter *padap = pdbg_init->adap;
1218 struct cudbg_buffer temp_buff = { 0 };
1219 struct cudbg_hw_sched *hw_sched_buff;
1220 int i, rc = 0;
1221
1222 if (!padap->params.vpd.cclk)
1223 return CUDBG_STATUS_CCLK_NOT_DEFINED;
1224
1225 rc = cudbg_get_buff(pdbg_init, dbg_buff, sizeof(struct cudbg_hw_sched),
1226 &temp_buff);
1227
1228 if (rc)
1229 return rc;
1230
1231 hw_sched_buff = (struct cudbg_hw_sched *)temp_buff.data;
1232 hw_sched_buff->map = t4_read_reg(padap, TP_TX_MOD_QUEUE_REQ_MAP_A);
1233 hw_sched_buff->mode = TIMERMODE_G(t4_read_reg(padap, TP_MOD_CONFIG_A));
1234 t4_read_pace_tbl(padap, hw_sched_buff->pace_tab);
1235 for (i = 0; i < NTX_SCHED; ++i)
1236 t4_get_tx_sched(padap, i, &hw_sched_buff->kbps[i],
1237 &hw_sched_buff->ipg[i], true);
1238 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
1239 }
1240
cudbg_collect_tp_indirect(struct cudbg_init * pdbg_init,struct cudbg_buffer * dbg_buff,struct cudbg_error * cudbg_err)1241 int cudbg_collect_tp_indirect(struct cudbg_init *pdbg_init,
1242 struct cudbg_buffer *dbg_buff,
1243 struct cudbg_error *cudbg_err)
1244 {
1245 struct adapter *padap = pdbg_init->adap;
1246 struct cudbg_buffer temp_buff = { 0 };
1247 struct ireg_buf *ch_tp_pio;
1248 int i, rc, n = 0;
1249 u32 size;
1250
1251 if (is_t5(padap->params.chip))
1252 n = sizeof(t5_tp_pio_array) +
1253 sizeof(t5_tp_tm_pio_array) +
1254 sizeof(t5_tp_mib_index_array);
1255 else
1256 n = sizeof(t6_tp_pio_array) +
1257 sizeof(t6_tp_tm_pio_array) +
1258 sizeof(t6_tp_mib_index_array);
1259
1260 n = n / (IREG_NUM_ELEM * sizeof(u32));
1261 size = sizeof(struct ireg_buf) * n;
1262 rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff);
1263 if (rc)
1264 return rc;
1265
1266 ch_tp_pio = (struct ireg_buf *)temp_buff.data;
1267
1268 /* TP_PIO */
1269 if (is_t5(padap->params.chip))
1270 n = sizeof(t5_tp_pio_array) / (IREG_NUM_ELEM * sizeof(u32));
1271 else if (is_t6(padap->params.chip))
1272 n = sizeof(t6_tp_pio_array) / (IREG_NUM_ELEM * sizeof(u32));
1273
1274 for (i = 0; i < n; i++) {
1275 struct ireg_field *tp_pio = &ch_tp_pio->tp_pio;
1276 u32 *buff = ch_tp_pio->outbuf;
1277
1278 if (is_t5(padap->params.chip)) {
1279 tp_pio->ireg_addr = t5_tp_pio_array[i][0];
1280 tp_pio->ireg_data = t5_tp_pio_array[i][1];
1281 tp_pio->ireg_local_offset = t5_tp_pio_array[i][2];
1282 tp_pio->ireg_offset_range = t5_tp_pio_array[i][3];
1283 } else if (is_t6(padap->params.chip)) {
1284 tp_pio->ireg_addr = t6_tp_pio_array[i][0];
1285 tp_pio->ireg_data = t6_tp_pio_array[i][1];
1286 tp_pio->ireg_local_offset = t6_tp_pio_array[i][2];
1287 tp_pio->ireg_offset_range = t6_tp_pio_array[i][3];
1288 }
1289 t4_tp_pio_read(padap, buff, tp_pio->ireg_offset_range,
1290 tp_pio->ireg_local_offset, true);
1291 ch_tp_pio++;
1292 }
1293
1294 /* TP_TM_PIO */
1295 if (is_t5(padap->params.chip))
1296 n = sizeof(t5_tp_tm_pio_array) / (IREG_NUM_ELEM * sizeof(u32));
1297 else if (is_t6(padap->params.chip))
1298 n = sizeof(t6_tp_tm_pio_array) / (IREG_NUM_ELEM * sizeof(u32));
1299
1300 for (i = 0; i < n; i++) {
1301 struct ireg_field *tp_pio = &ch_tp_pio->tp_pio;
1302 u32 *buff = ch_tp_pio->outbuf;
1303
1304 if (is_t5(padap->params.chip)) {
1305 tp_pio->ireg_addr = t5_tp_tm_pio_array[i][0];
1306 tp_pio->ireg_data = t5_tp_tm_pio_array[i][1];
1307 tp_pio->ireg_local_offset = t5_tp_tm_pio_array[i][2];
1308 tp_pio->ireg_offset_range = t5_tp_tm_pio_array[i][3];
1309 } else if (is_t6(padap->params.chip)) {
1310 tp_pio->ireg_addr = t6_tp_tm_pio_array[i][0];
1311 tp_pio->ireg_data = t6_tp_tm_pio_array[i][1];
1312 tp_pio->ireg_local_offset = t6_tp_tm_pio_array[i][2];
1313 tp_pio->ireg_offset_range = t6_tp_tm_pio_array[i][3];
1314 }
1315 t4_tp_tm_pio_read(padap, buff, tp_pio->ireg_offset_range,
1316 tp_pio->ireg_local_offset, true);
1317 ch_tp_pio++;
1318 }
1319
1320 /* TP_MIB_INDEX */
1321 if (is_t5(padap->params.chip))
1322 n = sizeof(t5_tp_mib_index_array) /
1323 (IREG_NUM_ELEM * sizeof(u32));
1324 else if (is_t6(padap->params.chip))
1325 n = sizeof(t6_tp_mib_index_array) /
1326 (IREG_NUM_ELEM * sizeof(u32));
1327
1328 for (i = 0; i < n ; i++) {
1329 struct ireg_field *tp_pio = &ch_tp_pio->tp_pio;
1330 u32 *buff = ch_tp_pio->outbuf;
1331
1332 if (is_t5(padap->params.chip)) {
1333 tp_pio->ireg_addr = t5_tp_mib_index_array[i][0];
1334 tp_pio->ireg_data = t5_tp_mib_index_array[i][1];
1335 tp_pio->ireg_local_offset =
1336 t5_tp_mib_index_array[i][2];
1337 tp_pio->ireg_offset_range =
1338 t5_tp_mib_index_array[i][3];
1339 } else if (is_t6(padap->params.chip)) {
1340 tp_pio->ireg_addr = t6_tp_mib_index_array[i][0];
1341 tp_pio->ireg_data = t6_tp_mib_index_array[i][1];
1342 tp_pio->ireg_local_offset =
1343 t6_tp_mib_index_array[i][2];
1344 tp_pio->ireg_offset_range =
1345 t6_tp_mib_index_array[i][3];
1346 }
1347 t4_tp_mib_read(padap, buff, tp_pio->ireg_offset_range,
1348 tp_pio->ireg_local_offset, true);
1349 ch_tp_pio++;
1350 }
1351 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
1352 }
1353
cudbg_read_sge_qbase_indirect_reg(struct adapter * padap,struct sge_qbase_reg_field * qbase,u32 func,bool is_pf)1354 static void cudbg_read_sge_qbase_indirect_reg(struct adapter *padap,
1355 struct sge_qbase_reg_field *qbase,
1356 u32 func, bool is_pf)
1357 {
1358 u32 *buff, i;
1359
1360 if (is_pf) {
1361 buff = qbase->pf_data_value[func];
1362 } else {
1363 buff = qbase->vf_data_value[func];
1364 /* In SGE_QBASE_INDEX,
1365 * Entries 0->7 are PF0->7, Entries 8->263 are VFID0->256.
1366 */
1367 func += 8;
1368 }
1369
1370 t4_write_reg(padap, qbase->reg_addr, func);
1371 for (i = 0; i < SGE_QBASE_DATA_REG_NUM; i++, buff++)
1372 *buff = t4_read_reg(padap, qbase->reg_data[i]);
1373 }
1374
cudbg_collect_sge_indirect(struct cudbg_init * pdbg_init,struct cudbg_buffer * dbg_buff,struct cudbg_error * cudbg_err)1375 int cudbg_collect_sge_indirect(struct cudbg_init *pdbg_init,
1376 struct cudbg_buffer *dbg_buff,
1377 struct cudbg_error *cudbg_err)
1378 {
1379 struct adapter *padap = pdbg_init->adap;
1380 struct cudbg_buffer temp_buff = { 0 };
1381 struct sge_qbase_reg_field *sge_qbase;
1382 struct ireg_buf *ch_sge_dbg;
1383 int i, rc;
1384
1385 rc = cudbg_get_buff(pdbg_init, dbg_buff,
1386 sizeof(*ch_sge_dbg) * 2 + sizeof(*sge_qbase),
1387 &temp_buff);
1388 if (rc)
1389 return rc;
1390
1391 ch_sge_dbg = (struct ireg_buf *)temp_buff.data;
1392 for (i = 0; i < 2; i++) {
1393 struct ireg_field *sge_pio = &ch_sge_dbg->tp_pio;
1394 u32 *buff = ch_sge_dbg->outbuf;
1395
1396 sge_pio->ireg_addr = t5_sge_dbg_index_array[i][0];
1397 sge_pio->ireg_data = t5_sge_dbg_index_array[i][1];
1398 sge_pio->ireg_local_offset = t5_sge_dbg_index_array[i][2];
1399 sge_pio->ireg_offset_range = t5_sge_dbg_index_array[i][3];
1400 t4_read_indirect(padap,
1401 sge_pio->ireg_addr,
1402 sge_pio->ireg_data,
1403 buff,
1404 sge_pio->ireg_offset_range,
1405 sge_pio->ireg_local_offset);
1406 ch_sge_dbg++;
1407 }
1408
1409 if (CHELSIO_CHIP_VERSION(padap->params.chip) > CHELSIO_T5) {
1410 sge_qbase = (struct sge_qbase_reg_field *)ch_sge_dbg;
1411 /* 1 addr reg SGE_QBASE_INDEX and 4 data reg
1412 * SGE_QBASE_MAP[0-3]
1413 */
1414 sge_qbase->reg_addr = t6_sge_qbase_index_array[0];
1415 for (i = 0; i < SGE_QBASE_DATA_REG_NUM; i++)
1416 sge_qbase->reg_data[i] =
1417 t6_sge_qbase_index_array[i + 1];
1418
1419 for (i = 0; i <= PCIE_FW_MASTER_M; i++)
1420 cudbg_read_sge_qbase_indirect_reg(padap, sge_qbase,
1421 i, true);
1422
1423 for (i = 0; i < padap->params.arch.vfcount; i++)
1424 cudbg_read_sge_qbase_indirect_reg(padap, sge_qbase,
1425 i, false);
1426
1427 sge_qbase->vfcount = padap->params.arch.vfcount;
1428 }
1429
1430 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
1431 }
1432
cudbg_collect_ulprx_la(struct cudbg_init * pdbg_init,struct cudbg_buffer * dbg_buff,struct cudbg_error * cudbg_err)1433 int cudbg_collect_ulprx_la(struct cudbg_init *pdbg_init,
1434 struct cudbg_buffer *dbg_buff,
1435 struct cudbg_error *cudbg_err)
1436 {
1437 struct adapter *padap = pdbg_init->adap;
1438 struct cudbg_buffer temp_buff = { 0 };
1439 struct cudbg_ulprx_la *ulprx_la_buff;
1440 int rc;
1441
1442 rc = cudbg_get_buff(pdbg_init, dbg_buff, sizeof(struct cudbg_ulprx_la),
1443 &temp_buff);
1444 if (rc)
1445 return rc;
1446
1447 ulprx_la_buff = (struct cudbg_ulprx_la *)temp_buff.data;
1448 t4_ulprx_read_la(padap, (u32 *)ulprx_la_buff->data);
1449 ulprx_la_buff->size = ULPRX_LA_SIZE;
1450 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
1451 }
1452
cudbg_collect_tp_la(struct cudbg_init * pdbg_init,struct cudbg_buffer * dbg_buff,struct cudbg_error * cudbg_err)1453 int cudbg_collect_tp_la(struct cudbg_init *pdbg_init,
1454 struct cudbg_buffer *dbg_buff,
1455 struct cudbg_error *cudbg_err)
1456 {
1457 struct adapter *padap = pdbg_init->adap;
1458 struct cudbg_buffer temp_buff = { 0 };
1459 struct cudbg_tp_la *tp_la_buff;
1460 int size, rc;
1461
1462 size = sizeof(struct cudbg_tp_la) + TPLA_SIZE * sizeof(u64);
1463 rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff);
1464 if (rc)
1465 return rc;
1466
1467 tp_la_buff = (struct cudbg_tp_la *)temp_buff.data;
1468 tp_la_buff->mode = DBGLAMODE_G(t4_read_reg(padap, TP_DBG_LA_CONFIG_A));
1469 t4_tp_read_la(padap, (u64 *)tp_la_buff->data, NULL);
1470 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
1471 }
1472
cudbg_collect_meminfo(struct cudbg_init * pdbg_init,struct cudbg_buffer * dbg_buff,struct cudbg_error * cudbg_err)1473 int cudbg_collect_meminfo(struct cudbg_init *pdbg_init,
1474 struct cudbg_buffer *dbg_buff,
1475 struct cudbg_error *cudbg_err)
1476 {
1477 struct adapter *padap = pdbg_init->adap;
1478 struct cudbg_buffer temp_buff = { 0 };
1479 struct cudbg_meminfo *meminfo_buff;
1480 struct cudbg_ver_hdr *ver_hdr;
1481 int rc;
1482
1483 rc = cudbg_get_buff(pdbg_init, dbg_buff,
1484 sizeof(struct cudbg_ver_hdr) +
1485 sizeof(struct cudbg_meminfo),
1486 &temp_buff);
1487 if (rc)
1488 return rc;
1489
1490 ver_hdr = (struct cudbg_ver_hdr *)temp_buff.data;
1491 ver_hdr->signature = CUDBG_ENTITY_SIGNATURE;
1492 ver_hdr->revision = CUDBG_MEMINFO_REV;
1493 ver_hdr->size = sizeof(struct cudbg_meminfo);
1494
1495 meminfo_buff = (struct cudbg_meminfo *)(temp_buff.data +
1496 sizeof(*ver_hdr));
1497 rc = cudbg_fill_meminfo(padap, meminfo_buff);
1498 if (rc) {
1499 cudbg_err->sys_err = rc;
1500 cudbg_put_buff(pdbg_init, &temp_buff);
1501 return rc;
1502 }
1503
1504 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
1505 }
1506
cudbg_collect_cim_pif_la(struct cudbg_init * pdbg_init,struct cudbg_buffer * dbg_buff,struct cudbg_error * cudbg_err)1507 int cudbg_collect_cim_pif_la(struct cudbg_init *pdbg_init,
1508 struct cudbg_buffer *dbg_buff,
1509 struct cudbg_error *cudbg_err)
1510 {
1511 struct cudbg_cim_pif_la *cim_pif_la_buff;
1512 struct adapter *padap = pdbg_init->adap;
1513 struct cudbg_buffer temp_buff = { 0 };
1514 int size, rc;
1515
1516 size = sizeof(struct cudbg_cim_pif_la) +
1517 2 * CIM_PIFLA_SIZE * 6 * sizeof(u32);
1518 rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff);
1519 if (rc)
1520 return rc;
1521
1522 cim_pif_la_buff = (struct cudbg_cim_pif_la *)temp_buff.data;
1523 cim_pif_la_buff->size = CIM_PIFLA_SIZE;
1524 t4_cim_read_pif_la(padap, (u32 *)cim_pif_la_buff->data,
1525 (u32 *)cim_pif_la_buff->data + 6 * CIM_PIFLA_SIZE,
1526 NULL, NULL);
1527 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
1528 }
1529
cudbg_collect_clk_info(struct cudbg_init * pdbg_init,struct cudbg_buffer * dbg_buff,struct cudbg_error * cudbg_err)1530 int cudbg_collect_clk_info(struct cudbg_init *pdbg_init,
1531 struct cudbg_buffer *dbg_buff,
1532 struct cudbg_error *cudbg_err)
1533 {
1534 struct adapter *padap = pdbg_init->adap;
1535 struct cudbg_buffer temp_buff = { 0 };
1536 struct cudbg_clk_info *clk_info_buff;
1537 u64 tp_tick_us;
1538 int rc;
1539
1540 if (!padap->params.vpd.cclk)
1541 return CUDBG_STATUS_CCLK_NOT_DEFINED;
1542
1543 rc = cudbg_get_buff(pdbg_init, dbg_buff, sizeof(struct cudbg_clk_info),
1544 &temp_buff);
1545 if (rc)
1546 return rc;
1547
1548 clk_info_buff = (struct cudbg_clk_info *)temp_buff.data;
1549 clk_info_buff->cclk_ps = 1000000000 / padap->params.vpd.cclk; /* psec */
1550 clk_info_buff->res = t4_read_reg(padap, TP_TIMER_RESOLUTION_A);
1551 clk_info_buff->tre = TIMERRESOLUTION_G(clk_info_buff->res);
1552 clk_info_buff->dack_re = DELAYEDACKRESOLUTION_G(clk_info_buff->res);
1553 tp_tick_us = (clk_info_buff->cclk_ps << clk_info_buff->tre) / 1000000;
1554
1555 clk_info_buff->dack_timer =
1556 (clk_info_buff->cclk_ps << clk_info_buff->dack_re) / 1000000 *
1557 t4_read_reg(padap, TP_DACK_TIMER_A);
1558 clk_info_buff->retransmit_min =
1559 tp_tick_us * t4_read_reg(padap, TP_RXT_MIN_A);
1560 clk_info_buff->retransmit_max =
1561 tp_tick_us * t4_read_reg(padap, TP_RXT_MAX_A);
1562 clk_info_buff->persist_timer_min =
1563 tp_tick_us * t4_read_reg(padap, TP_PERS_MIN_A);
1564 clk_info_buff->persist_timer_max =
1565 tp_tick_us * t4_read_reg(padap, TP_PERS_MAX_A);
1566 clk_info_buff->keepalive_idle_timer =
1567 tp_tick_us * t4_read_reg(padap, TP_KEEP_IDLE_A);
1568 clk_info_buff->keepalive_interval =
1569 tp_tick_us * t4_read_reg(padap, TP_KEEP_INTVL_A);
1570 clk_info_buff->initial_srtt =
1571 tp_tick_us * INITSRTT_G(t4_read_reg(padap, TP_INIT_SRTT_A));
1572 clk_info_buff->finwait2_timer =
1573 tp_tick_us * t4_read_reg(padap, TP_FINWAIT2_TIMER_A);
1574
1575 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
1576 }
1577
cudbg_collect_pcie_indirect(struct cudbg_init * pdbg_init,struct cudbg_buffer * dbg_buff,struct cudbg_error * cudbg_err)1578 int cudbg_collect_pcie_indirect(struct cudbg_init *pdbg_init,
1579 struct cudbg_buffer *dbg_buff,
1580 struct cudbg_error *cudbg_err)
1581 {
1582 struct adapter *padap = pdbg_init->adap;
1583 struct cudbg_buffer temp_buff = { 0 };
1584 struct ireg_buf *ch_pcie;
1585 int i, rc, n;
1586 u32 size;
1587
1588 n = sizeof(t5_pcie_pdbg_array) / (IREG_NUM_ELEM * sizeof(u32));
1589 size = sizeof(struct ireg_buf) * n * 2;
1590 rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff);
1591 if (rc)
1592 return rc;
1593
1594 ch_pcie = (struct ireg_buf *)temp_buff.data;
1595 /* PCIE_PDBG */
1596 for (i = 0; i < n; i++) {
1597 struct ireg_field *pcie_pio = &ch_pcie->tp_pio;
1598 u32 *buff = ch_pcie->outbuf;
1599
1600 pcie_pio->ireg_addr = t5_pcie_pdbg_array[i][0];
1601 pcie_pio->ireg_data = t5_pcie_pdbg_array[i][1];
1602 pcie_pio->ireg_local_offset = t5_pcie_pdbg_array[i][2];
1603 pcie_pio->ireg_offset_range = t5_pcie_pdbg_array[i][3];
1604 t4_read_indirect(padap,
1605 pcie_pio->ireg_addr,
1606 pcie_pio->ireg_data,
1607 buff,
1608 pcie_pio->ireg_offset_range,
1609 pcie_pio->ireg_local_offset);
1610 ch_pcie++;
1611 }
1612
1613 /* PCIE_CDBG */
1614 n = sizeof(t5_pcie_cdbg_array) / (IREG_NUM_ELEM * sizeof(u32));
1615 for (i = 0; i < n; i++) {
1616 struct ireg_field *pcie_pio = &ch_pcie->tp_pio;
1617 u32 *buff = ch_pcie->outbuf;
1618
1619 pcie_pio->ireg_addr = t5_pcie_cdbg_array[i][0];
1620 pcie_pio->ireg_data = t5_pcie_cdbg_array[i][1];
1621 pcie_pio->ireg_local_offset = t5_pcie_cdbg_array[i][2];
1622 pcie_pio->ireg_offset_range = t5_pcie_cdbg_array[i][3];
1623 t4_read_indirect(padap,
1624 pcie_pio->ireg_addr,
1625 pcie_pio->ireg_data,
1626 buff,
1627 pcie_pio->ireg_offset_range,
1628 pcie_pio->ireg_local_offset);
1629 ch_pcie++;
1630 }
1631 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
1632 }
1633
cudbg_collect_pm_indirect(struct cudbg_init * pdbg_init,struct cudbg_buffer * dbg_buff,struct cudbg_error * cudbg_err)1634 int cudbg_collect_pm_indirect(struct cudbg_init *pdbg_init,
1635 struct cudbg_buffer *dbg_buff,
1636 struct cudbg_error *cudbg_err)
1637 {
1638 struct adapter *padap = pdbg_init->adap;
1639 struct cudbg_buffer temp_buff = { 0 };
1640 struct ireg_buf *ch_pm;
1641 int i, rc, n;
1642 u32 size;
1643
1644 n = sizeof(t5_pm_rx_array) / (IREG_NUM_ELEM * sizeof(u32));
1645 size = sizeof(struct ireg_buf) * n * 2;
1646 rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff);
1647 if (rc)
1648 return rc;
1649
1650 ch_pm = (struct ireg_buf *)temp_buff.data;
1651 /* PM_RX */
1652 for (i = 0; i < n; i++) {
1653 struct ireg_field *pm_pio = &ch_pm->tp_pio;
1654 u32 *buff = ch_pm->outbuf;
1655
1656 pm_pio->ireg_addr = t5_pm_rx_array[i][0];
1657 pm_pio->ireg_data = t5_pm_rx_array[i][1];
1658 pm_pio->ireg_local_offset = t5_pm_rx_array[i][2];
1659 pm_pio->ireg_offset_range = t5_pm_rx_array[i][3];
1660 t4_read_indirect(padap,
1661 pm_pio->ireg_addr,
1662 pm_pio->ireg_data,
1663 buff,
1664 pm_pio->ireg_offset_range,
1665 pm_pio->ireg_local_offset);
1666 ch_pm++;
1667 }
1668
1669 /* PM_TX */
1670 n = sizeof(t5_pm_tx_array) / (IREG_NUM_ELEM * sizeof(u32));
1671 for (i = 0; i < n; i++) {
1672 struct ireg_field *pm_pio = &ch_pm->tp_pio;
1673 u32 *buff = ch_pm->outbuf;
1674
1675 pm_pio->ireg_addr = t5_pm_tx_array[i][0];
1676 pm_pio->ireg_data = t5_pm_tx_array[i][1];
1677 pm_pio->ireg_local_offset = t5_pm_tx_array[i][2];
1678 pm_pio->ireg_offset_range = t5_pm_tx_array[i][3];
1679 t4_read_indirect(padap,
1680 pm_pio->ireg_addr,
1681 pm_pio->ireg_data,
1682 buff,
1683 pm_pio->ireg_offset_range,
1684 pm_pio->ireg_local_offset);
1685 ch_pm++;
1686 }
1687 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
1688 }
1689
cudbg_collect_tid(struct cudbg_init * pdbg_init,struct cudbg_buffer * dbg_buff,struct cudbg_error * cudbg_err)1690 int cudbg_collect_tid(struct cudbg_init *pdbg_init,
1691 struct cudbg_buffer *dbg_buff,
1692 struct cudbg_error *cudbg_err)
1693 {
1694 struct adapter *padap = pdbg_init->adap;
1695 struct cudbg_tid_info_region_rev1 *tid1;
1696 struct cudbg_buffer temp_buff = { 0 };
1697 struct cudbg_tid_info_region *tid;
1698 u32 para[2], val[2];
1699 int rc;
1700
1701 rc = cudbg_get_buff(pdbg_init, dbg_buff,
1702 sizeof(struct cudbg_tid_info_region_rev1),
1703 &temp_buff);
1704 if (rc)
1705 return rc;
1706
1707 tid1 = (struct cudbg_tid_info_region_rev1 *)temp_buff.data;
1708 tid = &tid1->tid;
1709 tid1->ver_hdr.signature = CUDBG_ENTITY_SIGNATURE;
1710 tid1->ver_hdr.revision = CUDBG_TID_INFO_REV;
1711 tid1->ver_hdr.size = sizeof(struct cudbg_tid_info_region_rev1) -
1712 sizeof(struct cudbg_ver_hdr);
1713
1714 /* If firmware is not attached/alive, use backdoor register
1715 * access to collect dump.
1716 */
1717 if (!is_fw_attached(pdbg_init))
1718 goto fill_tid;
1719
1720 #define FW_PARAM_PFVF_A(param) \
1721 (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) | \
1722 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_##param) | \
1723 FW_PARAMS_PARAM_Y_V(0) | \
1724 FW_PARAMS_PARAM_Z_V(0))
1725
1726 para[0] = FW_PARAM_PFVF_A(ETHOFLD_START);
1727 para[1] = FW_PARAM_PFVF_A(ETHOFLD_END);
1728 rc = t4_query_params(padap, padap->mbox, padap->pf, 0, 2, para, val);
1729 if (rc < 0) {
1730 cudbg_err->sys_err = rc;
1731 cudbg_put_buff(pdbg_init, &temp_buff);
1732 return rc;
1733 }
1734 tid->uotid_base = val[0];
1735 tid->nuotids = val[1] - val[0] + 1;
1736
1737 if (is_t5(padap->params.chip)) {
1738 tid->sb = t4_read_reg(padap, LE_DB_SERVER_INDEX_A) / 4;
1739 } else if (is_t6(padap->params.chip)) {
1740 tid1->tid_start =
1741 t4_read_reg(padap, LE_DB_ACTIVE_TABLE_START_INDEX_A);
1742 tid->sb = t4_read_reg(padap, LE_DB_SRVR_START_INDEX_A);
1743
1744 para[0] = FW_PARAM_PFVF_A(HPFILTER_START);
1745 para[1] = FW_PARAM_PFVF_A(HPFILTER_END);
1746 rc = t4_query_params(padap, padap->mbox, padap->pf, 0, 2,
1747 para, val);
1748 if (rc < 0) {
1749 cudbg_err->sys_err = rc;
1750 cudbg_put_buff(pdbg_init, &temp_buff);
1751 return rc;
1752 }
1753 tid->hpftid_base = val[0];
1754 tid->nhpftids = val[1] - val[0] + 1;
1755 }
1756
1757 #undef FW_PARAM_PFVF_A
1758
1759 fill_tid:
1760 tid->ntids = padap->tids.ntids;
1761 tid->nstids = padap->tids.nstids;
1762 tid->stid_base = padap->tids.stid_base;
1763 tid->hash_base = padap->tids.hash_base;
1764
1765 tid->natids = padap->tids.natids;
1766 tid->nftids = padap->tids.nftids;
1767 tid->ftid_base = padap->tids.ftid_base;
1768 tid->aftid_base = padap->tids.aftid_base;
1769 tid->aftid_end = padap->tids.aftid_end;
1770
1771 tid->sftid_base = padap->tids.sftid_base;
1772 tid->nsftids = padap->tids.nsftids;
1773
1774 tid->flags = padap->flags;
1775 tid->le_db_conf = t4_read_reg(padap, LE_DB_CONFIG_A);
1776 tid->ip_users = t4_read_reg(padap, LE_DB_ACT_CNT_IPV4_A);
1777 tid->ipv6_users = t4_read_reg(padap, LE_DB_ACT_CNT_IPV6_A);
1778
1779 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
1780 }
1781
cudbg_collect_pcie_config(struct cudbg_init * pdbg_init,struct cudbg_buffer * dbg_buff,struct cudbg_error * cudbg_err)1782 int cudbg_collect_pcie_config(struct cudbg_init *pdbg_init,
1783 struct cudbg_buffer *dbg_buff,
1784 struct cudbg_error *cudbg_err)
1785 {
1786 struct adapter *padap = pdbg_init->adap;
1787 struct cudbg_buffer temp_buff = { 0 };
1788 u32 size, *value, j;
1789 int i, rc, n;
1790
1791 size = sizeof(u32) * CUDBG_NUM_PCIE_CONFIG_REGS;
1792 n = sizeof(t5_pcie_config_array) / (2 * sizeof(u32));
1793 rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff);
1794 if (rc)
1795 return rc;
1796
1797 value = (u32 *)temp_buff.data;
1798 for (i = 0; i < n; i++) {
1799 for (j = t5_pcie_config_array[i][0];
1800 j <= t5_pcie_config_array[i][1]; j += 4) {
1801 t4_hw_pci_read_cfg4(padap, j, value);
1802 value++;
1803 }
1804 }
1805 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
1806 }
1807
cudbg_sge_ctxt_check_valid(u32 * buf,int type)1808 static int cudbg_sge_ctxt_check_valid(u32 *buf, int type)
1809 {
1810 int index, bit, bit_pos = 0;
1811
1812 switch (type) {
1813 case CTXT_EGRESS:
1814 bit_pos = 176;
1815 break;
1816 case CTXT_INGRESS:
1817 bit_pos = 141;
1818 break;
1819 case CTXT_FLM:
1820 bit_pos = 89;
1821 break;
1822 }
1823 index = bit_pos / 32;
1824 bit = bit_pos % 32;
1825 return buf[index] & (1U << bit);
1826 }
1827
cudbg_get_ctxt_region_info(struct adapter * padap,struct cudbg_region_info * ctx_info,u8 * mem_type)1828 static int cudbg_get_ctxt_region_info(struct adapter *padap,
1829 struct cudbg_region_info *ctx_info,
1830 u8 *mem_type)
1831 {
1832 struct cudbg_mem_desc mem_desc;
1833 struct cudbg_meminfo meminfo;
1834 u32 i, j, value, found;
1835 u8 flq;
1836 int rc;
1837
1838 rc = cudbg_fill_meminfo(padap, &meminfo);
1839 if (rc)
1840 return rc;
1841
1842 /* Get EGRESS and INGRESS context region size */
1843 for (i = CTXT_EGRESS; i <= CTXT_INGRESS; i++) {
1844 found = 0;
1845 memset(&mem_desc, 0, sizeof(struct cudbg_mem_desc));
1846 for (j = 0; j < ARRAY_SIZE(meminfo.avail); j++) {
1847 rc = cudbg_get_mem_region(padap, &meminfo, j,
1848 cudbg_region[i],
1849 &mem_desc);
1850 if (!rc) {
1851 found = 1;
1852 rc = cudbg_get_mem_relative(padap, &meminfo, j,
1853 &mem_desc.base,
1854 &mem_desc.limit);
1855 if (rc) {
1856 ctx_info[i].exist = false;
1857 break;
1858 }
1859 ctx_info[i].exist = true;
1860 ctx_info[i].start = mem_desc.base;
1861 ctx_info[i].end = mem_desc.limit;
1862 mem_type[i] = j;
1863 break;
1864 }
1865 }
1866 if (!found)
1867 ctx_info[i].exist = false;
1868 }
1869
1870 /* Get FLM and CNM max qid. */
1871 value = t4_read_reg(padap, SGE_FLM_CFG_A);
1872
1873 /* Get number of data freelist queues */
1874 flq = HDRSTARTFLQ_G(value);
1875 ctx_info[CTXT_FLM].exist = true;
1876 ctx_info[CTXT_FLM].end = (CUDBG_MAX_FL_QIDS >> flq) * SGE_CTXT_SIZE;
1877
1878 /* The number of CONM contexts are same as number of freelist
1879 * queues.
1880 */
1881 ctx_info[CTXT_CNM].exist = true;
1882 ctx_info[CTXT_CNM].end = ctx_info[CTXT_FLM].end;
1883
1884 return 0;
1885 }
1886
cudbg_dump_context_size(struct adapter * padap)1887 int cudbg_dump_context_size(struct adapter *padap)
1888 {
1889 struct cudbg_region_info region_info[CTXT_CNM + 1] = { {0} };
1890 u8 mem_type[CTXT_INGRESS + 1] = { 0 };
1891 u32 i, size = 0;
1892 int rc;
1893
1894 /* Get max valid qid for each type of queue */
1895 rc = cudbg_get_ctxt_region_info(padap, region_info, mem_type);
1896 if (rc)
1897 return rc;
1898
1899 for (i = 0; i < CTXT_CNM; i++) {
1900 if (!region_info[i].exist) {
1901 if (i == CTXT_EGRESS || i == CTXT_INGRESS)
1902 size += CUDBG_LOWMEM_MAX_CTXT_QIDS *
1903 SGE_CTXT_SIZE;
1904 continue;
1905 }
1906
1907 size += (region_info[i].end - region_info[i].start + 1) /
1908 SGE_CTXT_SIZE;
1909 }
1910 return size * sizeof(struct cudbg_ch_cntxt);
1911 }
1912
cudbg_read_sge_ctxt(struct cudbg_init * pdbg_init,u32 cid,enum ctxt_type ctype,u32 * data)1913 static void cudbg_read_sge_ctxt(struct cudbg_init *pdbg_init, u32 cid,
1914 enum ctxt_type ctype, u32 *data)
1915 {
1916 struct adapter *padap = pdbg_init->adap;
1917 int rc = -1;
1918
1919 /* Under heavy traffic, the SGE Queue contexts registers will be
1920 * frequently accessed by firmware.
1921 *
1922 * To avoid conflicts with firmware, always ask firmware to fetch
1923 * the SGE Queue contexts via mailbox. On failure, fallback to
1924 * accessing hardware registers directly.
1925 */
1926 if (is_fw_attached(pdbg_init))
1927 rc = t4_sge_ctxt_rd(padap, padap->mbox, cid, ctype, data);
1928 if (rc)
1929 t4_sge_ctxt_rd_bd(padap, cid, ctype, data);
1930 }
1931
cudbg_get_sge_ctxt_fw(struct cudbg_init * pdbg_init,u32 max_qid,u8 ctxt_type,struct cudbg_ch_cntxt ** out_buff)1932 static void cudbg_get_sge_ctxt_fw(struct cudbg_init *pdbg_init, u32 max_qid,
1933 u8 ctxt_type,
1934 struct cudbg_ch_cntxt **out_buff)
1935 {
1936 struct cudbg_ch_cntxt *buff = *out_buff;
1937 int rc;
1938 u32 j;
1939
1940 for (j = 0; j < max_qid; j++) {
1941 cudbg_read_sge_ctxt(pdbg_init, j, ctxt_type, buff->data);
1942 rc = cudbg_sge_ctxt_check_valid(buff->data, ctxt_type);
1943 if (!rc)
1944 continue;
1945
1946 buff->cntxt_type = ctxt_type;
1947 buff->cntxt_id = j;
1948 buff++;
1949 if (ctxt_type == CTXT_FLM) {
1950 cudbg_read_sge_ctxt(pdbg_init, j, CTXT_CNM, buff->data);
1951 buff->cntxt_type = CTXT_CNM;
1952 buff->cntxt_id = j;
1953 buff++;
1954 }
1955 }
1956
1957 *out_buff = buff;
1958 }
1959
cudbg_collect_dump_context(struct cudbg_init * pdbg_init,struct cudbg_buffer * dbg_buff,struct cudbg_error * cudbg_err)1960 int cudbg_collect_dump_context(struct cudbg_init *pdbg_init,
1961 struct cudbg_buffer *dbg_buff,
1962 struct cudbg_error *cudbg_err)
1963 {
1964 struct cudbg_region_info region_info[CTXT_CNM + 1] = { {0} };
1965 struct adapter *padap = pdbg_init->adap;
1966 u32 j, size, max_ctx_size, max_ctx_qid;
1967 u8 mem_type[CTXT_INGRESS + 1] = { 0 };
1968 struct cudbg_buffer temp_buff = { 0 };
1969 struct cudbg_ch_cntxt *buff;
1970 u64 *dst_off, *src_off;
1971 u8 *ctx_buf;
1972 u8 i, k;
1973 int rc;
1974
1975 /* Get max valid qid for each type of queue */
1976 rc = cudbg_get_ctxt_region_info(padap, region_info, mem_type);
1977 if (rc)
1978 return rc;
1979
1980 rc = cudbg_dump_context_size(padap);
1981 if (rc <= 0)
1982 return CUDBG_STATUS_ENTITY_NOT_FOUND;
1983
1984 size = rc;
1985 rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff);
1986 if (rc)
1987 return rc;
1988
1989 /* Get buffer with enough space to read the biggest context
1990 * region in memory.
1991 */
1992 max_ctx_size = max(region_info[CTXT_EGRESS].end -
1993 region_info[CTXT_EGRESS].start + 1,
1994 region_info[CTXT_INGRESS].end -
1995 region_info[CTXT_INGRESS].start + 1);
1996
1997 ctx_buf = kvzalloc(max_ctx_size, GFP_KERNEL);
1998 if (!ctx_buf) {
1999 cudbg_put_buff(pdbg_init, &temp_buff);
2000 return -ENOMEM;
2001 }
2002
2003 buff = (struct cudbg_ch_cntxt *)temp_buff.data;
2004
2005 /* Collect EGRESS and INGRESS context data.
2006 * In case of failures, fallback to collecting via FW or
2007 * backdoor access.
2008 */
2009 for (i = CTXT_EGRESS; i <= CTXT_INGRESS; i++) {
2010 if (!region_info[i].exist) {
2011 max_ctx_qid = CUDBG_LOWMEM_MAX_CTXT_QIDS;
2012 cudbg_get_sge_ctxt_fw(pdbg_init, max_ctx_qid, i,
2013 &buff);
2014 continue;
2015 }
2016
2017 max_ctx_size = region_info[i].end - region_info[i].start + 1;
2018 max_ctx_qid = max_ctx_size / SGE_CTXT_SIZE;
2019
2020 /* If firmware is not attached/alive, use backdoor register
2021 * access to collect dump.
2022 */
2023 if (is_fw_attached(pdbg_init)) {
2024 t4_sge_ctxt_flush(padap, padap->mbox, i);
2025
2026 rc = t4_memory_rw(padap, MEMWIN_NIC, mem_type[i],
2027 region_info[i].start, max_ctx_size,
2028 (__be32 *)ctx_buf, 1);
2029 }
2030
2031 if (rc || !is_fw_attached(pdbg_init)) {
2032 max_ctx_qid = CUDBG_LOWMEM_MAX_CTXT_QIDS;
2033 cudbg_get_sge_ctxt_fw(pdbg_init, max_ctx_qid, i,
2034 &buff);
2035 continue;
2036 }
2037
2038 for (j = 0; j < max_ctx_qid; j++) {
2039 src_off = (u64 *)(ctx_buf + j * SGE_CTXT_SIZE);
2040 dst_off = (u64 *)buff->data;
2041
2042 /* The data is stored in 64-bit cpu order. Convert it
2043 * to big endian before parsing.
2044 */
2045 for (k = 0; k < SGE_CTXT_SIZE / sizeof(u64); k++)
2046 dst_off[k] = cpu_to_be64(src_off[k]);
2047
2048 rc = cudbg_sge_ctxt_check_valid(buff->data, i);
2049 if (!rc)
2050 continue;
2051
2052 buff->cntxt_type = i;
2053 buff->cntxt_id = j;
2054 buff++;
2055 }
2056 }
2057
2058 kvfree(ctx_buf);
2059
2060 /* Collect FREELIST and CONGESTION MANAGER contexts */
2061 max_ctx_size = region_info[CTXT_FLM].end -
2062 region_info[CTXT_FLM].start + 1;
2063 max_ctx_qid = max_ctx_size / SGE_CTXT_SIZE;
2064 /* Since FLM and CONM are 1-to-1 mapped, the below function
2065 * will fetch both FLM and CONM contexts.
2066 */
2067 cudbg_get_sge_ctxt_fw(pdbg_init, max_ctx_qid, CTXT_FLM, &buff);
2068
2069 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
2070 }
2071
cudbg_tcamxy2valmask(u64 x,u64 y,u8 * addr,u64 * mask)2072 static inline void cudbg_tcamxy2valmask(u64 x, u64 y, u8 *addr, u64 *mask)
2073 {
2074 *mask = x | y;
2075 y = (__force u64)cpu_to_be64(y);
2076 memcpy(addr, (char *)&y + 2, ETH_ALEN);
2077 }
2078
cudbg_mps_rpl_backdoor(struct adapter * padap,struct fw_ldst_mps_rplc * mps_rplc)2079 static void cudbg_mps_rpl_backdoor(struct adapter *padap,
2080 struct fw_ldst_mps_rplc *mps_rplc)
2081 {
2082 if (is_t5(padap->params.chip)) {
2083 mps_rplc->rplc255_224 = htonl(t4_read_reg(padap,
2084 MPS_VF_RPLCT_MAP3_A));
2085 mps_rplc->rplc223_192 = htonl(t4_read_reg(padap,
2086 MPS_VF_RPLCT_MAP2_A));
2087 mps_rplc->rplc191_160 = htonl(t4_read_reg(padap,
2088 MPS_VF_RPLCT_MAP1_A));
2089 mps_rplc->rplc159_128 = htonl(t4_read_reg(padap,
2090 MPS_VF_RPLCT_MAP0_A));
2091 } else {
2092 mps_rplc->rplc255_224 = htonl(t4_read_reg(padap,
2093 MPS_VF_RPLCT_MAP7_A));
2094 mps_rplc->rplc223_192 = htonl(t4_read_reg(padap,
2095 MPS_VF_RPLCT_MAP6_A));
2096 mps_rplc->rplc191_160 = htonl(t4_read_reg(padap,
2097 MPS_VF_RPLCT_MAP5_A));
2098 mps_rplc->rplc159_128 = htonl(t4_read_reg(padap,
2099 MPS_VF_RPLCT_MAP4_A));
2100 }
2101 mps_rplc->rplc127_96 = htonl(t4_read_reg(padap, MPS_VF_RPLCT_MAP3_A));
2102 mps_rplc->rplc95_64 = htonl(t4_read_reg(padap, MPS_VF_RPLCT_MAP2_A));
2103 mps_rplc->rplc63_32 = htonl(t4_read_reg(padap, MPS_VF_RPLCT_MAP1_A));
2104 mps_rplc->rplc31_0 = htonl(t4_read_reg(padap, MPS_VF_RPLCT_MAP0_A));
2105 }
2106
cudbg_collect_tcam_index(struct cudbg_init * pdbg_init,struct cudbg_mps_tcam * tcam,u32 idx)2107 static int cudbg_collect_tcam_index(struct cudbg_init *pdbg_init,
2108 struct cudbg_mps_tcam *tcam, u32 idx)
2109 {
2110 struct adapter *padap = pdbg_init->adap;
2111 u64 tcamy, tcamx, val;
2112 u32 ctl, data2;
2113 int rc = 0;
2114
2115 if (CHELSIO_CHIP_VERSION(padap->params.chip) >= CHELSIO_T6) {
2116 /* CtlReqID - 1: use Host Driver Requester ID
2117 * CtlCmdType - 0: Read, 1: Write
2118 * CtlTcamSel - 0: TCAM0, 1: TCAM1
2119 * CtlXYBitSel- 0: Y bit, 1: X bit
2120 */
2121
2122 /* Read tcamy */
2123 ctl = CTLREQID_V(1) | CTLCMDTYPE_V(0) | CTLXYBITSEL_V(0);
2124 if (idx < 256)
2125 ctl |= CTLTCAMINDEX_V(idx) | CTLTCAMSEL_V(0);
2126 else
2127 ctl |= CTLTCAMINDEX_V(idx - 256) | CTLTCAMSEL_V(1);
2128
2129 t4_write_reg(padap, MPS_CLS_TCAM_DATA2_CTL_A, ctl);
2130 val = t4_read_reg(padap, MPS_CLS_TCAM_RDATA1_REQ_ID1_A);
2131 tcamy = DMACH_G(val) << 32;
2132 tcamy |= t4_read_reg(padap, MPS_CLS_TCAM_RDATA0_REQ_ID1_A);
2133 data2 = t4_read_reg(padap, MPS_CLS_TCAM_RDATA2_REQ_ID1_A);
2134 tcam->lookup_type = DATALKPTYPE_G(data2);
2135
2136 /* 0 - Outer header, 1 - Inner header
2137 * [71:48] bit locations are overloaded for
2138 * outer vs. inner lookup types.
2139 */
2140 if (tcam->lookup_type && tcam->lookup_type != DATALKPTYPE_M) {
2141 /* Inner header VNI */
2142 tcam->vniy = (data2 & DATAVIDH2_F) | DATAVIDH1_G(data2);
2143 tcam->vniy = (tcam->vniy << 16) | VIDL_G(val);
2144 tcam->dip_hit = data2 & DATADIPHIT_F;
2145 } else {
2146 tcam->vlan_vld = data2 & DATAVIDH2_F;
2147 tcam->ivlan = VIDL_G(val);
2148 }
2149
2150 tcam->port_num = DATAPORTNUM_G(data2);
2151
2152 /* Read tcamx. Change the control param */
2153 ctl |= CTLXYBITSEL_V(1);
2154 t4_write_reg(padap, MPS_CLS_TCAM_DATA2_CTL_A, ctl);
2155 val = t4_read_reg(padap, MPS_CLS_TCAM_RDATA1_REQ_ID1_A);
2156 tcamx = DMACH_G(val) << 32;
2157 tcamx |= t4_read_reg(padap, MPS_CLS_TCAM_RDATA0_REQ_ID1_A);
2158 data2 = t4_read_reg(padap, MPS_CLS_TCAM_RDATA2_REQ_ID1_A);
2159 if (tcam->lookup_type && tcam->lookup_type != DATALKPTYPE_M) {
2160 /* Inner header VNI mask */
2161 tcam->vnix = (data2 & DATAVIDH2_F) | DATAVIDH1_G(data2);
2162 tcam->vnix = (tcam->vnix << 16) | VIDL_G(val);
2163 }
2164 } else {
2165 tcamy = t4_read_reg64(padap, MPS_CLS_TCAM_Y_L(idx));
2166 tcamx = t4_read_reg64(padap, MPS_CLS_TCAM_X_L(idx));
2167 }
2168
2169 /* If no entry, return */
2170 if (tcamx & tcamy)
2171 return rc;
2172
2173 tcam->cls_lo = t4_read_reg(padap, MPS_CLS_SRAM_L(idx));
2174 tcam->cls_hi = t4_read_reg(padap, MPS_CLS_SRAM_H(idx));
2175
2176 if (is_t5(padap->params.chip))
2177 tcam->repli = (tcam->cls_lo & REPLICATE_F);
2178 else if (is_t6(padap->params.chip))
2179 tcam->repli = (tcam->cls_lo & T6_REPLICATE_F);
2180
2181 if (tcam->repli) {
2182 struct fw_ldst_cmd ldst_cmd;
2183 struct fw_ldst_mps_rplc mps_rplc;
2184
2185 memset(&ldst_cmd, 0, sizeof(ldst_cmd));
2186 ldst_cmd.op_to_addrspace =
2187 htonl(FW_CMD_OP_V(FW_LDST_CMD) |
2188 FW_CMD_REQUEST_F | FW_CMD_READ_F |
2189 FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_MPS));
2190 ldst_cmd.cycles_to_len16 = htonl(FW_LEN16(ldst_cmd));
2191 ldst_cmd.u.mps.rplc.fid_idx =
2192 htons(FW_LDST_CMD_FID_V(FW_LDST_MPS_RPLC) |
2193 FW_LDST_CMD_IDX_V(idx));
2194
2195 /* If firmware is not attached/alive, use backdoor register
2196 * access to collect dump.
2197 */
2198 if (is_fw_attached(pdbg_init))
2199 rc = t4_wr_mbox(padap, padap->mbox, &ldst_cmd,
2200 sizeof(ldst_cmd), &ldst_cmd);
2201
2202 if (rc || !is_fw_attached(pdbg_init)) {
2203 cudbg_mps_rpl_backdoor(padap, &mps_rplc);
2204 /* Ignore error since we collected directly from
2205 * reading registers.
2206 */
2207 rc = 0;
2208 } else {
2209 mps_rplc = ldst_cmd.u.mps.rplc;
2210 }
2211
2212 tcam->rplc[0] = ntohl(mps_rplc.rplc31_0);
2213 tcam->rplc[1] = ntohl(mps_rplc.rplc63_32);
2214 tcam->rplc[2] = ntohl(mps_rplc.rplc95_64);
2215 tcam->rplc[3] = ntohl(mps_rplc.rplc127_96);
2216 if (padap->params.arch.mps_rplc_size > CUDBG_MAX_RPLC_SIZE) {
2217 tcam->rplc[4] = ntohl(mps_rplc.rplc159_128);
2218 tcam->rplc[5] = ntohl(mps_rplc.rplc191_160);
2219 tcam->rplc[6] = ntohl(mps_rplc.rplc223_192);
2220 tcam->rplc[7] = ntohl(mps_rplc.rplc255_224);
2221 }
2222 }
2223 cudbg_tcamxy2valmask(tcamx, tcamy, tcam->addr, &tcam->mask);
2224 tcam->idx = idx;
2225 tcam->rplc_size = padap->params.arch.mps_rplc_size;
2226 return rc;
2227 }
2228
cudbg_collect_mps_tcam(struct cudbg_init * pdbg_init,struct cudbg_buffer * dbg_buff,struct cudbg_error * cudbg_err)2229 int cudbg_collect_mps_tcam(struct cudbg_init *pdbg_init,
2230 struct cudbg_buffer *dbg_buff,
2231 struct cudbg_error *cudbg_err)
2232 {
2233 struct adapter *padap = pdbg_init->adap;
2234 struct cudbg_buffer temp_buff = { 0 };
2235 u32 size = 0, i, n, total_size = 0;
2236 struct cudbg_mps_tcam *tcam;
2237 int rc;
2238
2239 n = padap->params.arch.mps_tcam_size;
2240 size = sizeof(struct cudbg_mps_tcam) * n;
2241 rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff);
2242 if (rc)
2243 return rc;
2244
2245 tcam = (struct cudbg_mps_tcam *)temp_buff.data;
2246 for (i = 0; i < n; i++) {
2247 rc = cudbg_collect_tcam_index(pdbg_init, tcam, i);
2248 if (rc) {
2249 cudbg_err->sys_err = rc;
2250 cudbg_put_buff(pdbg_init, &temp_buff);
2251 return rc;
2252 }
2253 total_size += sizeof(struct cudbg_mps_tcam);
2254 tcam++;
2255 }
2256
2257 if (!total_size) {
2258 rc = CUDBG_SYSTEM_ERROR;
2259 cudbg_err->sys_err = rc;
2260 cudbg_put_buff(pdbg_init, &temp_buff);
2261 return rc;
2262 }
2263 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
2264 }
2265
cudbg_collect_vpd_data(struct cudbg_init * pdbg_init,struct cudbg_buffer * dbg_buff,struct cudbg_error * cudbg_err)2266 int cudbg_collect_vpd_data(struct cudbg_init *pdbg_init,
2267 struct cudbg_buffer *dbg_buff,
2268 struct cudbg_error *cudbg_err)
2269 {
2270 struct adapter *padap = pdbg_init->adap;
2271 struct cudbg_buffer temp_buff = { 0 };
2272 char vpd_str[CUDBG_VPD_VER_LEN + 1];
2273 u32 scfg_vers, vpd_vers, fw_vers;
2274 struct cudbg_vpd_data *vpd_data;
2275 struct vpd_params vpd = { 0 };
2276 int rc, ret;
2277
2278 rc = t4_get_raw_vpd_params(padap, &vpd);
2279 if (rc)
2280 return rc;
2281
2282 rc = t4_get_fw_version(padap, &fw_vers);
2283 if (rc)
2284 return rc;
2285
2286 /* Serial Configuration Version is located beyond the PF's vpd size.
2287 * Temporarily give access to entire EEPROM to get it.
2288 */
2289 rc = pci_set_vpd_size(padap->pdev, EEPROMVSIZE);
2290 if (rc < 0)
2291 return rc;
2292
2293 ret = cudbg_read_vpd_reg(padap, CUDBG_SCFG_VER_ADDR, CUDBG_SCFG_VER_LEN,
2294 &scfg_vers);
2295
2296 /* Restore back to original PF's vpd size */
2297 rc = pci_set_vpd_size(padap->pdev, CUDBG_VPD_PF_SIZE);
2298 if (rc < 0)
2299 return rc;
2300
2301 if (ret)
2302 return ret;
2303
2304 rc = cudbg_read_vpd_reg(padap, CUDBG_VPD_VER_ADDR, CUDBG_VPD_VER_LEN,
2305 vpd_str);
2306 if (rc)
2307 return rc;
2308
2309 vpd_str[CUDBG_VPD_VER_LEN] = '\0';
2310 rc = kstrtouint(vpd_str, 0, &vpd_vers);
2311 if (rc)
2312 return rc;
2313
2314 rc = cudbg_get_buff(pdbg_init, dbg_buff, sizeof(struct cudbg_vpd_data),
2315 &temp_buff);
2316 if (rc)
2317 return rc;
2318
2319 vpd_data = (struct cudbg_vpd_data *)temp_buff.data;
2320 memcpy(vpd_data->sn, vpd.sn, SERNUM_LEN + 1);
2321 memcpy(vpd_data->bn, vpd.pn, PN_LEN + 1);
2322 memcpy(vpd_data->na, vpd.na, MACADDR_LEN + 1);
2323 memcpy(vpd_data->mn, vpd.id, ID_LEN + 1);
2324 vpd_data->scfg_vers = scfg_vers;
2325 vpd_data->vpd_vers = vpd_vers;
2326 vpd_data->fw_major = FW_HDR_FW_VER_MAJOR_G(fw_vers);
2327 vpd_data->fw_minor = FW_HDR_FW_VER_MINOR_G(fw_vers);
2328 vpd_data->fw_micro = FW_HDR_FW_VER_MICRO_G(fw_vers);
2329 vpd_data->fw_build = FW_HDR_FW_VER_BUILD_G(fw_vers);
2330 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
2331 }
2332
cudbg_read_tid(struct cudbg_init * pdbg_init,u32 tid,struct cudbg_tid_data * tid_data)2333 static int cudbg_read_tid(struct cudbg_init *pdbg_init, u32 tid,
2334 struct cudbg_tid_data *tid_data)
2335 {
2336 struct adapter *padap = pdbg_init->adap;
2337 int i, cmd_retry = 8;
2338 u32 val;
2339
2340 /* Fill REQ_DATA regs with 0's */
2341 for (i = 0; i < NUM_LE_DB_DBGI_REQ_DATA_INSTANCES; i++)
2342 t4_write_reg(padap, LE_DB_DBGI_REQ_DATA_A + (i << 2), 0);
2343
2344 /* Write DBIG command */
2345 val = DBGICMD_V(4) | DBGITID_V(tid);
2346 t4_write_reg(padap, LE_DB_DBGI_REQ_TCAM_CMD_A, val);
2347 tid_data->dbig_cmd = val;
2348
2349 val = DBGICMDSTRT_F | DBGICMDMODE_V(1); /* LE mode */
2350 t4_write_reg(padap, LE_DB_DBGI_CONFIG_A, val);
2351 tid_data->dbig_conf = val;
2352
2353 /* Poll the DBGICMDBUSY bit */
2354 val = 1;
2355 while (val) {
2356 val = t4_read_reg(padap, LE_DB_DBGI_CONFIG_A);
2357 val = val & DBGICMDBUSY_F;
2358 cmd_retry--;
2359 if (!cmd_retry)
2360 return CUDBG_SYSTEM_ERROR;
2361 }
2362
2363 /* Check RESP status */
2364 val = t4_read_reg(padap, LE_DB_DBGI_RSP_STATUS_A);
2365 tid_data->dbig_rsp_stat = val;
2366 if (!(val & 1))
2367 return CUDBG_SYSTEM_ERROR;
2368
2369 /* Read RESP data */
2370 for (i = 0; i < NUM_LE_DB_DBGI_RSP_DATA_INSTANCES; i++)
2371 tid_data->data[i] = t4_read_reg(padap,
2372 LE_DB_DBGI_RSP_DATA_A +
2373 (i << 2));
2374 tid_data->tid = tid;
2375 return 0;
2376 }
2377
cudbg_get_le_type(u32 tid,struct cudbg_tcam tcam_region)2378 static int cudbg_get_le_type(u32 tid, struct cudbg_tcam tcam_region)
2379 {
2380 int type = LE_ET_UNKNOWN;
2381
2382 if (tid < tcam_region.server_start)
2383 type = LE_ET_TCAM_CON;
2384 else if (tid < tcam_region.filter_start)
2385 type = LE_ET_TCAM_SERVER;
2386 else if (tid < tcam_region.clip_start)
2387 type = LE_ET_TCAM_FILTER;
2388 else if (tid < tcam_region.routing_start)
2389 type = LE_ET_TCAM_CLIP;
2390 else if (tid < tcam_region.tid_hash_base)
2391 type = LE_ET_TCAM_ROUTING;
2392 else if (tid < tcam_region.max_tid)
2393 type = LE_ET_HASH_CON;
2394 else
2395 type = LE_ET_INVALID_TID;
2396
2397 return type;
2398 }
2399
cudbg_is_ipv6_entry(struct cudbg_tid_data * tid_data,struct cudbg_tcam tcam_region)2400 static int cudbg_is_ipv6_entry(struct cudbg_tid_data *tid_data,
2401 struct cudbg_tcam tcam_region)
2402 {
2403 int ipv6 = 0;
2404 int le_type;
2405
2406 le_type = cudbg_get_le_type(tid_data->tid, tcam_region);
2407 if (tid_data->tid & 1)
2408 return 0;
2409
2410 if (le_type == LE_ET_HASH_CON) {
2411 ipv6 = tid_data->data[16] & 0x8000;
2412 } else if (le_type == LE_ET_TCAM_CON) {
2413 ipv6 = tid_data->data[16] & 0x8000;
2414 if (ipv6)
2415 ipv6 = tid_data->data[9] == 0x00C00000;
2416 } else {
2417 ipv6 = 0;
2418 }
2419 return ipv6;
2420 }
2421
cudbg_fill_le_tcam_info(struct adapter * padap,struct cudbg_tcam * tcam_region)2422 void cudbg_fill_le_tcam_info(struct adapter *padap,
2423 struct cudbg_tcam *tcam_region)
2424 {
2425 u32 value;
2426
2427 /* Get the LE regions */
2428 value = t4_read_reg(padap, LE_DB_TID_HASHBASE_A); /* hash base index */
2429 tcam_region->tid_hash_base = value;
2430
2431 /* Get routing table index */
2432 value = t4_read_reg(padap, LE_DB_ROUTING_TABLE_INDEX_A);
2433 tcam_region->routing_start = value;
2434
2435 /* Get clip table index. For T6 there is separate CLIP TCAM */
2436 if (is_t6(padap->params.chip))
2437 value = t4_read_reg(padap, LE_DB_CLCAM_TID_BASE_A);
2438 else
2439 value = t4_read_reg(padap, LE_DB_CLIP_TABLE_INDEX_A);
2440 tcam_region->clip_start = value;
2441
2442 /* Get filter table index */
2443 value = t4_read_reg(padap, LE_DB_FILTER_TABLE_INDEX_A);
2444 tcam_region->filter_start = value;
2445
2446 /* Get server table index */
2447 value = t4_read_reg(padap, LE_DB_SERVER_INDEX_A);
2448 tcam_region->server_start = value;
2449
2450 /* Check whether hash is enabled and calculate the max tids */
2451 value = t4_read_reg(padap, LE_DB_CONFIG_A);
2452 if ((value >> HASHEN_S) & 1) {
2453 value = t4_read_reg(padap, LE_DB_HASH_CONFIG_A);
2454 if (CHELSIO_CHIP_VERSION(padap->params.chip) > CHELSIO_T5) {
2455 tcam_region->max_tid = (value & 0xFFFFF) +
2456 tcam_region->tid_hash_base;
2457 } else {
2458 value = HASHTIDSIZE_G(value);
2459 value = 1 << value;
2460 tcam_region->max_tid = value +
2461 tcam_region->tid_hash_base;
2462 }
2463 } else { /* hash not enabled */
2464 if (is_t6(padap->params.chip))
2465 tcam_region->max_tid = (value & ASLIPCOMPEN_F) ?
2466 CUDBG_MAX_TID_COMP_EN :
2467 CUDBG_MAX_TID_COMP_DIS;
2468 else
2469 tcam_region->max_tid = CUDBG_MAX_TCAM_TID;
2470 }
2471
2472 if (is_t6(padap->params.chip))
2473 tcam_region->max_tid += CUDBG_T6_CLIP;
2474 }
2475
cudbg_collect_le_tcam(struct cudbg_init * pdbg_init,struct cudbg_buffer * dbg_buff,struct cudbg_error * cudbg_err)2476 int cudbg_collect_le_tcam(struct cudbg_init *pdbg_init,
2477 struct cudbg_buffer *dbg_buff,
2478 struct cudbg_error *cudbg_err)
2479 {
2480 struct adapter *padap = pdbg_init->adap;
2481 struct cudbg_buffer temp_buff = { 0 };
2482 struct cudbg_tcam tcam_region = { 0 };
2483 struct cudbg_tid_data *tid_data;
2484 u32 bytes = 0;
2485 int rc, size;
2486 u32 i;
2487
2488 cudbg_fill_le_tcam_info(padap, &tcam_region);
2489
2490 size = sizeof(struct cudbg_tid_data) * tcam_region.max_tid;
2491 size += sizeof(struct cudbg_tcam);
2492 rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff);
2493 if (rc)
2494 return rc;
2495
2496 memcpy(temp_buff.data, &tcam_region, sizeof(struct cudbg_tcam));
2497 bytes = sizeof(struct cudbg_tcam);
2498 tid_data = (struct cudbg_tid_data *)(temp_buff.data + bytes);
2499 /* read all tid */
2500 for (i = 0; i < tcam_region.max_tid; ) {
2501 rc = cudbg_read_tid(pdbg_init, i, tid_data);
2502 if (rc) {
2503 cudbg_err->sys_warn = CUDBG_STATUS_PARTIAL_DATA;
2504 /* Update tcam header and exit */
2505 tcam_region.max_tid = i;
2506 memcpy(temp_buff.data, &tcam_region,
2507 sizeof(struct cudbg_tcam));
2508 goto out;
2509 }
2510
2511 if (cudbg_is_ipv6_entry(tid_data, tcam_region)) {
2512 /* T6 CLIP TCAM: ipv6 takes 4 entries */
2513 if (is_t6(padap->params.chip) &&
2514 i >= tcam_region.clip_start &&
2515 i < tcam_region.clip_start + CUDBG_T6_CLIP)
2516 i += 4;
2517 else /* Main TCAM: ipv6 takes two tids */
2518 i += 2;
2519 } else {
2520 i++;
2521 }
2522
2523 tid_data++;
2524 bytes += sizeof(struct cudbg_tid_data);
2525 }
2526
2527 out:
2528 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
2529 }
2530
cudbg_collect_cctrl(struct cudbg_init * pdbg_init,struct cudbg_buffer * dbg_buff,struct cudbg_error * cudbg_err)2531 int cudbg_collect_cctrl(struct cudbg_init *pdbg_init,
2532 struct cudbg_buffer *dbg_buff,
2533 struct cudbg_error *cudbg_err)
2534 {
2535 struct adapter *padap = pdbg_init->adap;
2536 struct cudbg_buffer temp_buff = { 0 };
2537 u32 size;
2538 int rc;
2539
2540 size = sizeof(u16) * NMTUS * NCCTRL_WIN;
2541 rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff);
2542 if (rc)
2543 return rc;
2544
2545 t4_read_cong_tbl(padap, (void *)temp_buff.data);
2546 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
2547 }
2548
cudbg_collect_ma_indirect(struct cudbg_init * pdbg_init,struct cudbg_buffer * dbg_buff,struct cudbg_error * cudbg_err)2549 int cudbg_collect_ma_indirect(struct cudbg_init *pdbg_init,
2550 struct cudbg_buffer *dbg_buff,
2551 struct cudbg_error *cudbg_err)
2552 {
2553 struct adapter *padap = pdbg_init->adap;
2554 struct cudbg_buffer temp_buff = { 0 };
2555 struct ireg_buf *ma_indr;
2556 int i, rc, n;
2557 u32 size, j;
2558
2559 if (CHELSIO_CHIP_VERSION(padap->params.chip) < CHELSIO_T6)
2560 return CUDBG_STATUS_ENTITY_NOT_FOUND;
2561
2562 n = sizeof(t6_ma_ireg_array) / (IREG_NUM_ELEM * sizeof(u32));
2563 size = sizeof(struct ireg_buf) * n * 2;
2564 rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff);
2565 if (rc)
2566 return rc;
2567
2568 ma_indr = (struct ireg_buf *)temp_buff.data;
2569 for (i = 0; i < n; i++) {
2570 struct ireg_field *ma_fli = &ma_indr->tp_pio;
2571 u32 *buff = ma_indr->outbuf;
2572
2573 ma_fli->ireg_addr = t6_ma_ireg_array[i][0];
2574 ma_fli->ireg_data = t6_ma_ireg_array[i][1];
2575 ma_fli->ireg_local_offset = t6_ma_ireg_array[i][2];
2576 ma_fli->ireg_offset_range = t6_ma_ireg_array[i][3];
2577 t4_read_indirect(padap, ma_fli->ireg_addr, ma_fli->ireg_data,
2578 buff, ma_fli->ireg_offset_range,
2579 ma_fli->ireg_local_offset);
2580 ma_indr++;
2581 }
2582
2583 n = sizeof(t6_ma_ireg_array2) / (IREG_NUM_ELEM * sizeof(u32));
2584 for (i = 0; i < n; i++) {
2585 struct ireg_field *ma_fli = &ma_indr->tp_pio;
2586 u32 *buff = ma_indr->outbuf;
2587
2588 ma_fli->ireg_addr = t6_ma_ireg_array2[i][0];
2589 ma_fli->ireg_data = t6_ma_ireg_array2[i][1];
2590 ma_fli->ireg_local_offset = t6_ma_ireg_array2[i][2];
2591 for (j = 0; j < t6_ma_ireg_array2[i][3]; j++) {
2592 t4_read_indirect(padap, ma_fli->ireg_addr,
2593 ma_fli->ireg_data, buff, 1,
2594 ma_fli->ireg_local_offset);
2595 buff++;
2596 ma_fli->ireg_local_offset += 0x20;
2597 }
2598 ma_indr++;
2599 }
2600 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
2601 }
2602
cudbg_collect_ulptx_la(struct cudbg_init * pdbg_init,struct cudbg_buffer * dbg_buff,struct cudbg_error * cudbg_err)2603 int cudbg_collect_ulptx_la(struct cudbg_init *pdbg_init,
2604 struct cudbg_buffer *dbg_buff,
2605 struct cudbg_error *cudbg_err)
2606 {
2607 struct adapter *padap = pdbg_init->adap;
2608 struct cudbg_buffer temp_buff = { 0 };
2609 struct cudbg_ulptx_la *ulptx_la_buff;
2610 struct cudbg_ver_hdr *ver_hdr;
2611 u32 i, j;
2612 int rc;
2613
2614 rc = cudbg_get_buff(pdbg_init, dbg_buff,
2615 sizeof(struct cudbg_ver_hdr) +
2616 sizeof(struct cudbg_ulptx_la),
2617 &temp_buff);
2618 if (rc)
2619 return rc;
2620
2621 ver_hdr = (struct cudbg_ver_hdr *)temp_buff.data;
2622 ver_hdr->signature = CUDBG_ENTITY_SIGNATURE;
2623 ver_hdr->revision = CUDBG_ULPTX_LA_REV;
2624 ver_hdr->size = sizeof(struct cudbg_ulptx_la);
2625
2626 ulptx_la_buff = (struct cudbg_ulptx_la *)(temp_buff.data +
2627 sizeof(*ver_hdr));
2628 for (i = 0; i < CUDBG_NUM_ULPTX; i++) {
2629 ulptx_la_buff->rdptr[i] = t4_read_reg(padap,
2630 ULP_TX_LA_RDPTR_0_A +
2631 0x10 * i);
2632 ulptx_la_buff->wrptr[i] = t4_read_reg(padap,
2633 ULP_TX_LA_WRPTR_0_A +
2634 0x10 * i);
2635 ulptx_la_buff->rddata[i] = t4_read_reg(padap,
2636 ULP_TX_LA_RDDATA_0_A +
2637 0x10 * i);
2638 for (j = 0; j < CUDBG_NUM_ULPTX_READ; j++)
2639 ulptx_la_buff->rd_data[i][j] =
2640 t4_read_reg(padap,
2641 ULP_TX_LA_RDDATA_0_A + 0x10 * i);
2642 }
2643
2644 for (i = 0; i < CUDBG_NUM_ULPTX_ASIC_READ; i++) {
2645 t4_write_reg(padap, ULP_TX_ASIC_DEBUG_CTRL_A, 0x1);
2646 ulptx_la_buff->rdptr_asic[i] =
2647 t4_read_reg(padap, ULP_TX_ASIC_DEBUG_CTRL_A);
2648 ulptx_la_buff->rddata_asic[i][0] =
2649 t4_read_reg(padap, ULP_TX_ASIC_DEBUG_0_A);
2650 ulptx_la_buff->rddata_asic[i][1] =
2651 t4_read_reg(padap, ULP_TX_ASIC_DEBUG_1_A);
2652 ulptx_la_buff->rddata_asic[i][2] =
2653 t4_read_reg(padap, ULP_TX_ASIC_DEBUG_2_A);
2654 ulptx_la_buff->rddata_asic[i][3] =
2655 t4_read_reg(padap, ULP_TX_ASIC_DEBUG_3_A);
2656 ulptx_la_buff->rddata_asic[i][4] =
2657 t4_read_reg(padap, ULP_TX_ASIC_DEBUG_4_A);
2658 ulptx_la_buff->rddata_asic[i][5] =
2659 t4_read_reg(padap, PM_RX_BASE_ADDR);
2660 }
2661
2662 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
2663 }
2664
cudbg_collect_up_cim_indirect(struct cudbg_init * pdbg_init,struct cudbg_buffer * dbg_buff,struct cudbg_error * cudbg_err)2665 int cudbg_collect_up_cim_indirect(struct cudbg_init *pdbg_init,
2666 struct cudbg_buffer *dbg_buff,
2667 struct cudbg_error *cudbg_err)
2668 {
2669 struct adapter *padap = pdbg_init->adap;
2670 struct cudbg_buffer temp_buff = { 0 };
2671 u32 local_offset, local_range;
2672 struct ireg_buf *up_cim;
2673 u32 size, j, iter;
2674 u32 instance = 0;
2675 int i, rc, n;
2676
2677 if (is_t5(padap->params.chip))
2678 n = sizeof(t5_up_cim_reg_array) /
2679 ((IREG_NUM_ELEM + 1) * sizeof(u32));
2680 else if (is_t6(padap->params.chip))
2681 n = sizeof(t6_up_cim_reg_array) /
2682 ((IREG_NUM_ELEM + 1) * sizeof(u32));
2683 else
2684 return CUDBG_STATUS_NOT_IMPLEMENTED;
2685
2686 size = sizeof(struct ireg_buf) * n;
2687 rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff);
2688 if (rc)
2689 return rc;
2690
2691 up_cim = (struct ireg_buf *)temp_buff.data;
2692 for (i = 0; i < n; i++) {
2693 struct ireg_field *up_cim_reg = &up_cim->tp_pio;
2694 u32 *buff = up_cim->outbuf;
2695
2696 if (is_t5(padap->params.chip)) {
2697 up_cim_reg->ireg_addr = t5_up_cim_reg_array[i][0];
2698 up_cim_reg->ireg_data = t5_up_cim_reg_array[i][1];
2699 up_cim_reg->ireg_local_offset =
2700 t5_up_cim_reg_array[i][2];
2701 up_cim_reg->ireg_offset_range =
2702 t5_up_cim_reg_array[i][3];
2703 instance = t5_up_cim_reg_array[i][4];
2704 } else if (is_t6(padap->params.chip)) {
2705 up_cim_reg->ireg_addr = t6_up_cim_reg_array[i][0];
2706 up_cim_reg->ireg_data = t6_up_cim_reg_array[i][1];
2707 up_cim_reg->ireg_local_offset =
2708 t6_up_cim_reg_array[i][2];
2709 up_cim_reg->ireg_offset_range =
2710 t6_up_cim_reg_array[i][3];
2711 instance = t6_up_cim_reg_array[i][4];
2712 }
2713
2714 switch (instance) {
2715 case NUM_CIM_CTL_TSCH_CHANNEL_INSTANCES:
2716 iter = up_cim_reg->ireg_offset_range;
2717 local_offset = 0x120;
2718 local_range = 1;
2719 break;
2720 case NUM_CIM_CTL_TSCH_CHANNEL_TSCH_CLASS_INSTANCES:
2721 iter = up_cim_reg->ireg_offset_range;
2722 local_offset = 0x10;
2723 local_range = 1;
2724 break;
2725 default:
2726 iter = 1;
2727 local_offset = 0;
2728 local_range = up_cim_reg->ireg_offset_range;
2729 break;
2730 }
2731
2732 for (j = 0; j < iter; j++, buff++) {
2733 rc = t4_cim_read(padap,
2734 up_cim_reg->ireg_local_offset +
2735 (j * local_offset), local_range, buff);
2736 if (rc) {
2737 cudbg_put_buff(pdbg_init, &temp_buff);
2738 return rc;
2739 }
2740 }
2741 up_cim++;
2742 }
2743 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
2744 }
2745
cudbg_collect_pbt_tables(struct cudbg_init * pdbg_init,struct cudbg_buffer * dbg_buff,struct cudbg_error * cudbg_err)2746 int cudbg_collect_pbt_tables(struct cudbg_init *pdbg_init,
2747 struct cudbg_buffer *dbg_buff,
2748 struct cudbg_error *cudbg_err)
2749 {
2750 struct adapter *padap = pdbg_init->adap;
2751 struct cudbg_buffer temp_buff = { 0 };
2752 struct cudbg_pbt_tables *pbt;
2753 int i, rc;
2754 u32 addr;
2755
2756 rc = cudbg_get_buff(pdbg_init, dbg_buff,
2757 sizeof(struct cudbg_pbt_tables),
2758 &temp_buff);
2759 if (rc)
2760 return rc;
2761
2762 pbt = (struct cudbg_pbt_tables *)temp_buff.data;
2763 /* PBT dynamic entries */
2764 addr = CUDBG_CHAC_PBT_ADDR;
2765 for (i = 0; i < CUDBG_PBT_DYNAMIC_ENTRIES; i++) {
2766 rc = t4_cim_read(padap, addr + (i * 4), 1,
2767 &pbt->pbt_dynamic[i]);
2768 if (rc) {
2769 cudbg_err->sys_err = rc;
2770 cudbg_put_buff(pdbg_init, &temp_buff);
2771 return rc;
2772 }
2773 }
2774
2775 /* PBT static entries */
2776 /* static entries start when bit 6 is set */
2777 addr = CUDBG_CHAC_PBT_ADDR + (1 << 6);
2778 for (i = 0; i < CUDBG_PBT_STATIC_ENTRIES; i++) {
2779 rc = t4_cim_read(padap, addr + (i * 4), 1,
2780 &pbt->pbt_static[i]);
2781 if (rc) {
2782 cudbg_err->sys_err = rc;
2783 cudbg_put_buff(pdbg_init, &temp_buff);
2784 return rc;
2785 }
2786 }
2787
2788 /* LRF entries */
2789 addr = CUDBG_CHAC_PBT_LRF;
2790 for (i = 0; i < CUDBG_LRF_ENTRIES; i++) {
2791 rc = t4_cim_read(padap, addr + (i * 4), 1,
2792 &pbt->lrf_table[i]);
2793 if (rc) {
2794 cudbg_err->sys_err = rc;
2795 cudbg_put_buff(pdbg_init, &temp_buff);
2796 return rc;
2797 }
2798 }
2799
2800 /* PBT data entries */
2801 addr = CUDBG_CHAC_PBT_DATA;
2802 for (i = 0; i < CUDBG_PBT_DATA_ENTRIES; i++) {
2803 rc = t4_cim_read(padap, addr + (i * 4), 1,
2804 &pbt->pbt_data[i]);
2805 if (rc) {
2806 cudbg_err->sys_err = rc;
2807 cudbg_put_buff(pdbg_init, &temp_buff);
2808 return rc;
2809 }
2810 }
2811 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
2812 }
2813
cudbg_collect_mbox_log(struct cudbg_init * pdbg_init,struct cudbg_buffer * dbg_buff,struct cudbg_error * cudbg_err)2814 int cudbg_collect_mbox_log(struct cudbg_init *pdbg_init,
2815 struct cudbg_buffer *dbg_buff,
2816 struct cudbg_error *cudbg_err)
2817 {
2818 struct adapter *padap = pdbg_init->adap;
2819 struct cudbg_mbox_log *mboxlog = NULL;
2820 struct cudbg_buffer temp_buff = { 0 };
2821 struct mbox_cmd_log *log = NULL;
2822 struct mbox_cmd *entry;
2823 unsigned int entry_idx;
2824 u16 mbox_cmds;
2825 int i, k, rc;
2826 u64 flit;
2827 u32 size;
2828
2829 log = padap->mbox_log;
2830 mbox_cmds = padap->mbox_log->size;
2831 size = sizeof(struct cudbg_mbox_log) * mbox_cmds;
2832 rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff);
2833 if (rc)
2834 return rc;
2835
2836 mboxlog = (struct cudbg_mbox_log *)temp_buff.data;
2837 for (k = 0; k < mbox_cmds; k++) {
2838 entry_idx = log->cursor + k;
2839 if (entry_idx >= log->size)
2840 entry_idx -= log->size;
2841
2842 entry = mbox_cmd_log_entry(log, entry_idx);
2843 /* skip over unused entries */
2844 if (entry->timestamp == 0)
2845 continue;
2846
2847 memcpy(&mboxlog->entry, entry, sizeof(struct mbox_cmd));
2848 for (i = 0; i < MBOX_LEN / 8; i++) {
2849 flit = entry->cmd[i];
2850 mboxlog->hi[i] = (u32)(flit >> 32);
2851 mboxlog->lo[i] = (u32)flit;
2852 }
2853 mboxlog++;
2854 }
2855 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
2856 }
2857
cudbg_collect_hma_indirect(struct cudbg_init * pdbg_init,struct cudbg_buffer * dbg_buff,struct cudbg_error * cudbg_err)2858 int cudbg_collect_hma_indirect(struct cudbg_init *pdbg_init,
2859 struct cudbg_buffer *dbg_buff,
2860 struct cudbg_error *cudbg_err)
2861 {
2862 struct adapter *padap = pdbg_init->adap;
2863 struct cudbg_buffer temp_buff = { 0 };
2864 struct ireg_buf *hma_indr;
2865 int i, rc, n;
2866 u32 size;
2867
2868 if (CHELSIO_CHIP_VERSION(padap->params.chip) < CHELSIO_T6)
2869 return CUDBG_STATUS_ENTITY_NOT_FOUND;
2870
2871 n = sizeof(t6_hma_ireg_array) / (IREG_NUM_ELEM * sizeof(u32));
2872 size = sizeof(struct ireg_buf) * n;
2873 rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff);
2874 if (rc)
2875 return rc;
2876
2877 hma_indr = (struct ireg_buf *)temp_buff.data;
2878 for (i = 0; i < n; i++) {
2879 struct ireg_field *hma_fli = &hma_indr->tp_pio;
2880 u32 *buff = hma_indr->outbuf;
2881
2882 hma_fli->ireg_addr = t6_hma_ireg_array[i][0];
2883 hma_fli->ireg_data = t6_hma_ireg_array[i][1];
2884 hma_fli->ireg_local_offset = t6_hma_ireg_array[i][2];
2885 hma_fli->ireg_offset_range = t6_hma_ireg_array[i][3];
2886 t4_read_indirect(padap, hma_fli->ireg_addr, hma_fli->ireg_data,
2887 buff, hma_fli->ireg_offset_range,
2888 hma_fli->ireg_local_offset);
2889 hma_indr++;
2890 }
2891 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
2892 }
2893
cudbg_fill_qdesc_num_and_size(const struct adapter * padap,u32 * num,u32 * size)2894 void cudbg_fill_qdesc_num_and_size(const struct adapter *padap,
2895 u32 *num, u32 *size)
2896 {
2897 u32 tot_entries = 0, tot_size = 0;
2898
2899 /* NIC TXQ, RXQ, FLQ, and CTRLQ */
2900 tot_entries += MAX_ETH_QSETS * 3;
2901 tot_entries += MAX_CTRL_QUEUES;
2902
2903 tot_size += MAX_ETH_QSETS * MAX_TXQ_ENTRIES * MAX_TXQ_DESC_SIZE;
2904 tot_size += MAX_ETH_QSETS * MAX_RSPQ_ENTRIES * MAX_RXQ_DESC_SIZE;
2905 tot_size += MAX_ETH_QSETS * MAX_RX_BUFFERS * MAX_FL_DESC_SIZE;
2906 tot_size += MAX_CTRL_QUEUES * MAX_CTRL_TXQ_ENTRIES *
2907 MAX_CTRL_TXQ_DESC_SIZE;
2908
2909 /* FW_EVTQ and INTRQ */
2910 tot_entries += INGQ_EXTRAS;
2911 tot_size += INGQ_EXTRAS * MAX_RSPQ_ENTRIES * MAX_RXQ_DESC_SIZE;
2912
2913 /* PTP_TXQ */
2914 tot_entries += 1;
2915 tot_size += MAX_TXQ_ENTRIES * MAX_TXQ_DESC_SIZE;
2916
2917 /* ULD TXQ, RXQ, and FLQ */
2918 tot_entries += CXGB4_TX_MAX * MAX_OFLD_QSETS;
2919 tot_entries += CXGB4_ULD_MAX * MAX_ULD_QSETS * 2;
2920
2921 tot_size += CXGB4_TX_MAX * MAX_OFLD_QSETS * MAX_TXQ_ENTRIES *
2922 MAX_TXQ_DESC_SIZE;
2923 tot_size += CXGB4_ULD_MAX * MAX_ULD_QSETS * MAX_RSPQ_ENTRIES *
2924 MAX_RXQ_DESC_SIZE;
2925 tot_size += CXGB4_ULD_MAX * MAX_ULD_QSETS * MAX_RX_BUFFERS *
2926 MAX_FL_DESC_SIZE;
2927
2928 /* ULD CIQ */
2929 tot_entries += CXGB4_ULD_MAX * MAX_ULD_QSETS;
2930 tot_size += CXGB4_ULD_MAX * MAX_ULD_QSETS * SGE_MAX_IQ_SIZE *
2931 MAX_RXQ_DESC_SIZE;
2932
2933 tot_size += sizeof(struct cudbg_ver_hdr) +
2934 sizeof(struct cudbg_qdesc_info) +
2935 sizeof(struct cudbg_qdesc_entry) * tot_entries;
2936
2937 if (num)
2938 *num = tot_entries;
2939
2940 if (size)
2941 *size = tot_size;
2942 }
2943
cudbg_collect_qdesc(struct cudbg_init * pdbg_init,struct cudbg_buffer * dbg_buff,struct cudbg_error * cudbg_err)2944 int cudbg_collect_qdesc(struct cudbg_init *pdbg_init,
2945 struct cudbg_buffer *dbg_buff,
2946 struct cudbg_error *cudbg_err)
2947 {
2948 u32 num_queues = 0, tot_entries = 0, size = 0;
2949 struct adapter *padap = pdbg_init->adap;
2950 struct cudbg_buffer temp_buff = { 0 };
2951 struct cudbg_qdesc_entry *qdesc_entry;
2952 struct cudbg_qdesc_info *qdesc_info;
2953 struct cudbg_ver_hdr *ver_hdr;
2954 struct sge *s = &padap->sge;
2955 u32 i, j, cur_off, tot_len;
2956 u8 *data;
2957 int rc;
2958
2959 cudbg_fill_qdesc_num_and_size(padap, &tot_entries, &size);
2960 size = min_t(u32, size, CUDBG_DUMP_BUFF_SIZE);
2961 tot_len = size;
2962 data = kvzalloc(size, GFP_KERNEL);
2963 if (!data)
2964 return -ENOMEM;
2965
2966 ver_hdr = (struct cudbg_ver_hdr *)data;
2967 ver_hdr->signature = CUDBG_ENTITY_SIGNATURE;
2968 ver_hdr->revision = CUDBG_QDESC_REV;
2969 ver_hdr->size = sizeof(struct cudbg_qdesc_info);
2970 size -= sizeof(*ver_hdr);
2971
2972 qdesc_info = (struct cudbg_qdesc_info *)(data +
2973 sizeof(*ver_hdr));
2974 size -= sizeof(*qdesc_info);
2975 qdesc_entry = (struct cudbg_qdesc_entry *)qdesc_info->data;
2976
2977 #define QDESC_GET(q, desc, type, label) do { \
2978 if (size <= 0) { \
2979 goto label; \
2980 } \
2981 if (desc) { \
2982 cudbg_fill_qdesc_##q(q, type, qdesc_entry); \
2983 size -= sizeof(*qdesc_entry) + qdesc_entry->data_size; \
2984 num_queues++; \
2985 qdesc_entry = cudbg_next_qdesc(qdesc_entry); \
2986 } \
2987 } while (0)
2988
2989 #define QDESC_GET_TXQ(q, type, label) do { \
2990 struct sge_txq *txq = (struct sge_txq *)q; \
2991 QDESC_GET(txq, txq->desc, type, label); \
2992 } while (0)
2993
2994 #define QDESC_GET_RXQ(q, type, label) do { \
2995 struct sge_rspq *rxq = (struct sge_rspq *)q; \
2996 QDESC_GET(rxq, rxq->desc, type, label); \
2997 } while (0)
2998
2999 #define QDESC_GET_FLQ(q, type, label) do { \
3000 struct sge_fl *flq = (struct sge_fl *)q; \
3001 QDESC_GET(flq, flq->desc, type, label); \
3002 } while (0)
3003
3004 /* NIC TXQ */
3005 for (i = 0; i < s->ethqsets; i++)
3006 QDESC_GET_TXQ(&s->ethtxq[i].q, CUDBG_QTYPE_NIC_TXQ, out);
3007
3008 /* NIC RXQ */
3009 for (i = 0; i < s->ethqsets; i++)
3010 QDESC_GET_RXQ(&s->ethrxq[i].rspq, CUDBG_QTYPE_NIC_RXQ, out);
3011
3012 /* NIC FLQ */
3013 for (i = 0; i < s->ethqsets; i++)
3014 QDESC_GET_FLQ(&s->ethrxq[i].fl, CUDBG_QTYPE_NIC_FLQ, out);
3015
3016 /* NIC CTRLQ */
3017 for (i = 0; i < padap->params.nports; i++)
3018 QDESC_GET_TXQ(&s->ctrlq[i].q, CUDBG_QTYPE_CTRLQ, out);
3019
3020 /* FW_EVTQ */
3021 QDESC_GET_RXQ(&s->fw_evtq, CUDBG_QTYPE_FWEVTQ, out);
3022
3023 /* INTRQ */
3024 QDESC_GET_RXQ(&s->intrq, CUDBG_QTYPE_INTRQ, out);
3025
3026 /* PTP_TXQ */
3027 QDESC_GET_TXQ(&s->ptptxq.q, CUDBG_QTYPE_PTP_TXQ, out);
3028
3029 /* ULD Queues */
3030 mutex_lock(&uld_mutex);
3031
3032 if (s->uld_txq_info) {
3033 struct sge_uld_txq_info *utxq;
3034
3035 /* ULD TXQ */
3036 for (j = 0; j < CXGB4_TX_MAX; j++) {
3037 if (!s->uld_txq_info[j])
3038 continue;
3039
3040 utxq = s->uld_txq_info[j];
3041 for (i = 0; i < utxq->ntxq; i++)
3042 QDESC_GET_TXQ(&utxq->uldtxq[i].q,
3043 cudbg_uld_txq_to_qtype(j),
3044 out_unlock);
3045 }
3046 }
3047
3048 if (s->uld_rxq_info) {
3049 struct sge_uld_rxq_info *urxq;
3050 u32 base;
3051
3052 /* ULD RXQ */
3053 for (j = 0; j < CXGB4_ULD_MAX; j++) {
3054 if (!s->uld_rxq_info[j])
3055 continue;
3056
3057 urxq = s->uld_rxq_info[j];
3058 for (i = 0; i < urxq->nrxq; i++)
3059 QDESC_GET_RXQ(&urxq->uldrxq[i].rspq,
3060 cudbg_uld_rxq_to_qtype(j),
3061 out_unlock);
3062 }
3063
3064 /* ULD FLQ */
3065 for (j = 0; j < CXGB4_ULD_MAX; j++) {
3066 if (!s->uld_rxq_info[j])
3067 continue;
3068
3069 urxq = s->uld_rxq_info[j];
3070 for (i = 0; i < urxq->nrxq; i++)
3071 QDESC_GET_FLQ(&urxq->uldrxq[i].fl,
3072 cudbg_uld_flq_to_qtype(j),
3073 out_unlock);
3074 }
3075
3076 /* ULD CIQ */
3077 for (j = 0; j < CXGB4_ULD_MAX; j++) {
3078 if (!s->uld_rxq_info[j])
3079 continue;
3080
3081 urxq = s->uld_rxq_info[j];
3082 base = urxq->nrxq;
3083 for (i = 0; i < urxq->nciq; i++)
3084 QDESC_GET_RXQ(&urxq->uldrxq[base + i].rspq,
3085 cudbg_uld_ciq_to_qtype(j),
3086 out_unlock);
3087 }
3088 }
3089
3090 out_unlock:
3091 mutex_unlock(&uld_mutex);
3092
3093 out:
3094 qdesc_info->qdesc_entry_size = sizeof(*qdesc_entry);
3095 qdesc_info->num_queues = num_queues;
3096 cur_off = 0;
3097 while (tot_len) {
3098 u32 chunk_size = min_t(u32, tot_len, CUDBG_CHUNK_SIZE);
3099
3100 rc = cudbg_get_buff(pdbg_init, dbg_buff, chunk_size,
3101 &temp_buff);
3102 if (rc) {
3103 cudbg_err->sys_warn = CUDBG_STATUS_PARTIAL_DATA;
3104 goto out_free;
3105 }
3106
3107 memcpy(temp_buff.data, data + cur_off, chunk_size);
3108 tot_len -= chunk_size;
3109 cur_off += chunk_size;
3110 rc = cudbg_write_and_release_buff(pdbg_init, &temp_buff,
3111 dbg_buff);
3112 if (rc) {
3113 cudbg_put_buff(pdbg_init, &temp_buff);
3114 cudbg_err->sys_warn = CUDBG_STATUS_PARTIAL_DATA;
3115 goto out_free;
3116 }
3117 }
3118
3119 out_free:
3120 if (data)
3121 kvfree(data);
3122
3123 #undef QDESC_GET_FLQ
3124 #undef QDESC_GET_RXQ
3125 #undef QDESC_GET_TXQ
3126 #undef QDESC_GET
3127
3128 return rc;
3129 }
3130
